WO2016160656A1

WO2016160656A1 - Diluted drift layer with variable stripe widths for power transistors

Info

Publication number: WO2016160656A1
Application number: PCT/US2016/024431
Authority: WO
Inventors: Yongxi Zhang; Sameer P. Pendharkar; Scott G. BALSTER
Original assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Current assignee: Texas Instruments Japan Ltd; Texas Instruments Inc
Priority date: 2015-03-27
Filing date: 2016-03-28
Publication date: 2016-10-06
Anticipated expiration: 2017-09-27
Also published as: JP2018509781A; US9431480B1; US9985028B2; US20170221896A1; CN107534055A; CN107534055B; US20160336427A1; US9653577B2; JP6789281B2

Abstract

In described examples, a multi-finger lateral high voltage transistors (MFLHVT) (100) includes a substrate (105) doped a first dopant type, a well (102) doped a second dopant type, and a buried drift layer (BDL) (132) doped first type having a diluted BDL portion (DBDL) (132a) including dilution stripes. A semiconductor surface (138) doped the second type is on the BDL. Dielectric isolation regions (162) have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT, each doped the second dopant type. The DBDL is within a fingertip drift region associated with drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

Description

DILUTED DRIFT LAYER WITH VARIABLE STRIPE WIDTHS

FOR POWER TRANSISTORS

[0001] This relates to lateral high voltage metal oxide semiconductor (MOS) power transistors having diluted drift layers, including LDMOS and DEMOS transistors.

BACKGROUND

[0002] Modern digital very-large-scale integration (VLSI) circuits commonly operate at supply voltages of around 2.5 volts or below. However, certain integrated circuits (ICs) call for additional on-chip circuits operating at higher voltages. Example circuits are input/output (IO) interface circuits with various off-chip system components, such as power management switches, analog input circuits conditioning transducer signals, or output analog drive functions for speakers or other actuators.

[0003] One solution to this problem is to use multiple different gate oxide thicknesses and to build both low voltage transistors and high voltage transistors on the same IC chip. This method increases process complexity and cost. An alternative solution is to use lateral asymmetric source and drain MOS transistors having a lightly doped n-type gap between the drain and gate (for n-type devices) to enable use of higher drain to source voltages, such as laterally diffused metal-oxide-semiconductor (LDMOS) or drain-extended MOS (DEMOS), which have drain structures capable of operating at higher voltages as compared to conventional symmetric MOS transistors.

[0004] In an LDMOS transistor, a lightly doped lateral diffused drain region is constructed between the heavily doped drain contact and the transistor channel region. As the LDMOS name implies, a lateral current is created between drain and source. A depletion region forms in this lightly doped lateral diffused region, resulting in a voltage drop between the drain contact and the transistor gate. With proper design, sufficient voltage may be dropped between the drain contact and the gate dielectric to allow use of a low gate voltage transistor as a switch for the high voltage.

[0005] Some lateral power transistors include "RESURF" regions, which are reduced surface electric field regions. For purposes of this patent application, the term "RESURF" refers to a material that reduces an electric field in an adjacent surface semiconductor region. For example, a RESURF region may be a buried semiconductor region (or layer) with an opposite conductivity type from the adjacent semiconductor region (or layer). RESURF structures are described in Appels, et.al., "Thin Layer High Voltage Devices" Philips J, Res. 35 1-13, 1980. The RESURF region(s) for lateral power transistors are generally referred to as buried drift regions.

[0006] To raise the breakdown voltage of the lateral power transistor, a diluted buried drift layer may be used in the drift region at one end of the transistor, which can be formed by a masked implant that enables implanting dilution stripes separated by masked (non-implanted) stripes. One or more high temperature annealing processes follow, which results in dopant from the implanted stripes diffusing into the non-implanted stripes that create more heavily doped stripes alternating with less heavily doped stripes.

[0007] The DEMOS or LDMOS transistor can have: a multi-finger layout with multiple source and drain fingers generally interdigitated with one another; or a racetrack layout, which is (in essence) a single finger design with an enclosed source or an enclosed drain. The diluted buried drift layer for diluted buried drift layer designs generally sets the drain-to- source breakdown voltage (BVDSS) for the lateral power transistor, with the racetrack layout generally providing a higher breakdown voltage that is near the ideal (planar) junction breakdown voltage due to less junction curvature, as compared to a lower BVDSS for the multi-finger layout having higher curvature at the fingertip regions. Fingertip regions correspond to the curved distal end of the fingers that extend from linear (un-curved) regions of the fingertip Advantages of multi-finger lateral power transistors (e.g., DEMOS or LDMOS transistors) include decreased parasitics effects and the ability to change width (W), length (L), number of fingers, and number of contacts, which helps speed the transistor layout process.

SUMMARY

[0008] In described examples, a multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT, each doped the second dopant type. The DBDL is within a fingertip drift region associated with drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 A is a cross sectional view of an example IC having an n-channel MFLHVT with an example DBDL portion and multiple horizontal current channels, according to an example embodiment.

[0011] FIG. IB is a top down view of the IC of FIG. 1 A.

[0012] FIG. 2A depicts a portion of a disclosed MFLHVT showing a source finger having a source fingertip between a first drain finger and a second drain finger having a drain fingertip, respectively, according to an example embodiment.

[0013] FIG. 2B is a top view depiction of the DBDL of a MFLHVT after BDL implant having a MIOD dilution stripe width design, with the dilution stripes corresponding to implanted regions with fifteen (15) example dilution stripes designed based on disclosed scaling in the FDR, according to an example embodiment.

[0014] FIGS. 3A and 3B show a finger including a fingertip and a ½ of a fingertip portion, respectively, used to show parameters in disclosed DBDL designs, according to an example embodiment.

[0015] FIG. 4 shows comparative NLDMOS BVDSS data, including data from a disclosed multi-finger NLDMOS device having a disclosed DBDL design having a MIOD, such as shown in FIG. 2B, and a control racetrack NLDMOS device having a conventional DBDL having a fixed stripe overdesign dimension.

DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S

[0016] The figures are not necessarily drawn to scale. In this disclosure, some acts or events may occur in different orders and/or concurrently with other acts or events, and some illustrated acts or events are optional.

[0017] In example embodiments, multi-finger lateral high voltage transistors (MFLHVTs) include drain extended MOS (DEMOS) and laterally diffused MOS (LDMOS) transistors having a conventional diluted buried drift layer between the source and drain fingertips of the fingers, referred to herein as the fingertip drift region "FDR." In such embodiments, the use of a fixed overdesign dimension (scaling, such as 200%) for the dilution stripe width (e.g., at the drain end for n-channel metal-oxide-semiconductor (NMOS)) of the FDR can limit the drain-to-source breakdown voltage (BVDSS) of these transistors. This reduced BVDSS is due to the significant curvature induced electric field crowding at the FDR, particularly at the highest junction curvature portions, which has been verified by emission microscopy imaging (EMMI) that detects and localizes certain integrated circuit (IC) failures. For example, the BVDSS of a multi-finger LDMOS can be about 100V lower at -700V, as compared to the otherwise equivalent racetrack version that has a BVDSS of -800V, which is the ideal BVDSS due to a large endcap radius.

[0018] Also, example embodiments provide a calculation (formula)-based diluted buried drift layer (DBDL) design in the FDR for MFLHVTs, which provides a monotonically increasing overdesign dimension (MIOD) for the dilution stripe width along at least a portion of the DBDL, which is within the FDR associated with source fingertips and/or drain fingertips. The dilution stripe width corresponds to implanted buried drift layer regions. Disclosed DBDL designs have been found to improve the BVDSS of such transistors by relieving electric field crowding in the highest junction curvature portions of the FDR. Disclosed integrated circuits (ICs) can combine both n-type dilution for p-channel MOS (PMOS) MFLHVTs and p-type dilution for NMOS MFLHVTs.

[0019] Example embodiments include MFLHVTs that have a DBDL design in the FDR having an MIOD, which has been found to improve the BVDSS by relieving electric field crowding. Disclosed MFLHVTs also provide high current at high voltage with reduced area by having multiple current channels between the source and drain. Because current in disclosed MFLHVTs may flow through multiple channels when disclosed transistors are turned ON, disclosed transistors provide high current with a reduced area. The multiple current channels feature significantly reduces the area required for MFLHVTs that include LDMOS or DEMOS transistors, thereby significantly reducing cost.

[0020] In this description, the term "current channel" refers to a region of the semiconductor substrate through which current flows. One current channel is isolated from another current channel by a diffusion of an opposite dopant type. One current channel may be shorted to the other current channel at the ends of the diffusion of opposite dopant type, which separates the two current channels. [0021] As shown in the cross sectional view of FIG. 1A, an example IC 150 has an n-channel MFLHVT (MFLHVT 100) with a p-type BDL 132, including DBDL portion 132a at the drain end near the common drain 218 in the FDR adjacent to fingertips between interdigitated source and drain finger, with multiple horizontal current channels shown with dashed lines as upper current channel 226 and lower current channel 228. Fingertip regions correspond to the curved distal end of the fingers that extend from linear (un-curved) regions of the fingertip. A p-channel MFLHVT on the same IC, such as IC 150 or another IC having n-type dilution, may be realized by a reverse-tone device relative to MFLHVT 100.

[0022] FIG. IB shows a top down view of the IC 150. Referring to FIG. IB, upper current channel 226 is in the semiconductor surface 138 (doped n-type) between a top p-type surface layer 174 and BDL 132 (which is p-type), while lower current channel 228 is in an nwell 102 between the BDL 132 and the substrate 105. Substrate 105 is doped a first dopant type (being p-type), and the semiconductor surface 138 is doped with the second dopant type (being n-type). The vertical layer stack for MFLHVT has a pnpnp structure, which provides 4 reduced surface electric field (RESURF) regions. However, because the top p-type surface layer 174 (FIG. 1A) is optional, the top p-type surface layer 174 can be removed (skipped in the process) to provide a disclosed MFLHVT having a pnpn structure, which provides 3 RESURF regions.

[0023] The substrate 105 can include silicon, silicon-germanium, or other semiconductor material. One particular arrangement is an epitaxial silicon/germanium (SiGe) semiconductor surface on a silicon substrate 105.

[0024] A symmetric S/D core logic PMOS transistor 50 has an nwell 146, source/drain diffusions 224 and a transistor gate 202. A symmetric S/D core logic NMOS transistor 60 has a p-type epi layer 130, source/drain diffusions 214 and a transistor gate 204. The MFLHVT 100 has two gates electrodes 206 and 208, and upper current channel 226 and lower current channel 228, both between its common drain (drain) 218 and common source (source) 216. More than two horizontal current paths may be provided if desired. The gate electrodes 206 and 208 can include poly silicon, or alternatively metal.

[0025] When the gate including gate electrode 206 of the MFLHVT 100 is turned ON, current flows through the upper current channel 226 between the top p-type surface layer 174 and the BDL 132. When the gate including the gate electrode 208 of the MFLHVT 100 is turned ON, current flows through the upper current channel 226 and lower current channel 228. However, for power switching applications, the gate electrodes 206 and 208 may be shorted together to maximize the transistor ON-state current. Although two gates are shown in FIG. 1A, a single gate may support both the upper current channel 226 and the lower current channel 228, so that disclosed MFLHVTs need only one gate.

[0026] Dielectric isolation regions 162 are shown at least partially in the semiconductor surface as trench isolation (e.g., shallow trench isolation (STI)), which can alternatively be field oxidation (FOX), including over the semiconductor surface 138, p-type epi layer 130 and nwell 146 of the IC 150 having gaps in the dielectric defining: a first active area in a first dielectric gap region (hereafter source MOAT) 110 where a common source 216 is formed; and a second active area in a second dielectric gap region (hereafter drain MOAT) 115 where the drain 218 is formed. The current channels 226, 228 are both shown as sharing source 216 and drain 218. The current channels 226, 228 are tapered and are narrower and more lightly doped near the common drain 218, as compared to their doping and width near the common source 216.

[0027] When gates including gate electrode 206 and 208 are both turned OFF and high voltage is applied to the common drain 218, an expanded depletion region forms between the upper current channel 226 (which is n-type) and the p-type surface layer 174 and BDL 132, and an expanded depletion region forms between the lower current channel 228 (which is n-type) and the BDL 132 and the substrate 105, so that upper current channel 226 and lower current channel 228 cease providing a continuous current path from the common source 216 to common drain 218. Sufficient voltage is dropped across these depletion regions, so that the transistor gates stacks including gate electrodes 206 and 208 may use the same low voltage gate dielectric as the logic transistors 50 and 60 to switch the high voltage.

[0028] FIG. 2A depicts a portion 200 of a disclosed MFLHVT showing an interdigitated fingertip arrangement, including a source finger 216a having a source fingertip 216a' between: a first drain finger 218a having a drain fingertip 218a'; and a second drain finger 218b having a drain fingertip 218b'. The MFLHVT will have multiple repetitions of the interdigitated finger arrangement shown. The source fingertip 216a' is associated with the source FDR 210, which is between an outer edge of the drain moat 115 and an outer edge of the source moat 110 (including the DBDL portion 132a of FIG. 1A). Similarly, respective drain FDRs 215 are associated with drain fingertips 218a' and 218b' between the outer edge of the drain moat 115 and the outer edge of the source moat 110, which can also include a disclosed DBDL portion such as DBDL 132a (FIG. 1A). The dilution is heavier on the side near the drain 218 (equating to closer pitched discernable dilution stripes in FIG. 2A), as compared to a lesser degree of dilution on the side near the source 216 (equating to non-discernable dilution stripes in FIG. 2A).

[0029] FIG. 2B is a top view depiction 250 of the source FDR 210 (FIG. 2A), showing an example DBDL portion 132a after BDL implant having a DBDL stripe widths corresponding to implanted regions, which monotonically increase in size as a function of the drift length (DL) at their location, according to an example embodiment. The fingertip center at the beginning of the source fingertip 216a' is identified and shown as 285, the linear drift region 290 is shown above the horizontal dashed line boundary shown as 295, and the source FDR 210 is shown below the horizontal dashed line 295.

[0030] As used herein, DL (which is a constant shown as L in FIG. 2B) is defined as the minimum spacing between the drain MOAT 115 and source MOAT 110 in the linear drift region, which is the shortest distance between source moat 110 and drain moat 1 15 (from source moat edge 110' to drain moat edge 115'). In the source FDR 210, DL is defined as the distance between source moat edge 110' and drain moat edge 115' at the particular angle Θ in the source FDR 210 (see FIGS. 3A and 3B showing Θ). DBDL portion 132a includes fifteen (15) example diluted DBDL stripes, including stripes 132ai, 132a₂ and 132a₃ that will be BDL implanted regions, alternating with non-implanted stripes 132a' i, 132a'₂ and 132a'₃ (which are non-implanted regions) that are masked during the BDL implant.

[0031] The parameter Lf (FIG. 2B) is the over design dimension for the dilution stripes, where Lf is a fixed parameter (constant) for a conventional fixed layout design that determines the overall size of the source FDR 210, and Le is a variable in the FDR (see Le shown in FIG. 3B described below) that sets the stripe width. For the particular layout shown in FIG. 2B, Lf is a fixed parameter, while Le varies with Θ ranging from 0 degrees to 90 or 180 degrees. The parameter L (FIG. 2B) is the distance from the edge of the source MOAT 110 to center of the finger (see L shown in FIG. 3B described below). As described in the examples, for an n-channel MFLHVT having a DBDL portion design (such as shown in FIG. 2B), the BVDSS difference between multi-finger and racetrack (single finger) layouts has be found to be reduced from about 100 V to less than 40V.

[0032] When the MFLHVT includes an MOS device, for a constant distance from the fingertip center 285, the respective stripe widths of DBDLs 132a are shown in FIG. 2B to increase with an increasing angle Θ relative to the horizontal dashed line boundary 295 of the source FDR 210 with the linear drift region 290, having a maximum width at 90 degrees. However, the stripe width change with Θ is opposite for the FDR associated with the drain fingertip, such as the drain FDR 215 shown in FIG. 2 A, where the respective stripe widths for the DBDL will decrease instead with an increasing angle Θ. This asymmetry reflects the disclosed dilution concept in the linear region, such as for an MOS MFLHVT where the p-type DBDL 132a is diluted more on drain side near drain 218, while the p-type DBDL 132a is diluted less on the source side near the source 216 as shown in FIG. 1 A as described above.

[0033] Also, for a fixed Θ, as the distance from the fingertip center 285 increases, the width of the DBDLs 132a shown in FIG. 2B decreases, which (as with the stripe width change with Θ) is opposite for the FDR associated with the drain fingertip. However, some adjacent dilution stripes can be the same stripe width due to a process limit, such as the stripes close to drain in linear drift region. Similarly the dilution stripe spacing can be the same for some adjacent stripes due to a process limit, such as the dilution stripe spacing close to the source in the linear drift region. When the MFLHVT includes a PMOS device, the dilution will be provided by an n-type buried layer, and (analogous to the NMOS device described above) there will be less n-type buried layer dilution for the PMOS source side and more relative n-type buried layer dilution for the PMOS drain side.

[0034] Although NMOS MFLHVTs are generally described above, this information is also useful for PMOS MFLHVTs by substituting the n-doped regions with p-doping and vice versa. As used herein, if a diffused region is referred to as being doped with a particular dopant type (e.g., n-type), then such region in the semiconductor surface is where doping concentration of the particular dopant type is higher than the doping concentration of dopants of another type (e.g., p-type).

[0035] General aspects that make MFLHVTs including LDMO S/DEMO S transistors and processing to form the same can be found in a variety of references, including Patent No. US 8,470,675 entitled "thick gate oxide for LDMOS and DEMOS" to Sridhar et al., which is incorporated herein by reference. A DEMOS transistor has an extended drain by adding a drain drift region between the drain and the channel of the device, trapping the majority of the electric field in this region instead of the channel region, and (as used herein) also includes a variant called double-diffused drain MOS (DDDMOS). An LDMOS transistor uses a drain drift region created by an extra doping, similar to the DEMOS transistor structure.

[0036] Regarding processing to form a disclosed DBDL, a DBDL layer mask is used having multiple stripes, such as to print a photoresist pattern having exposed stripe shaped regions that are striped. Implantation follows to form diluted buried drift layer stripes, followed by annealing. A drain including multiple drain fingers is formed interdigitated with multiple source fingers, each doped the second dopant type. At least a first gate stack is formed on the semiconductor surface between the source and drain.

[0037] Advantages of disclosed embodiments include relieving field crowding for triple RESURF HV transistors (which lack the top surface layer 174) or quadruple RESURF HV transistors (such as MFLHVT 100 shown in FIG. 1A), without compromising the current contribution from the fingertip region resulting from known removal of current conduction path(s). Another advantage is that disclosed DBDL designs are equation-based, enabling use for auto-design without the need for any human layout activity. Other advantages include low cost of implementation, because implementation only involves mask change(s), and extra fabrication steps are unnecessary.

EXAMPLES

[0038] Disclosed embodiments are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.

[0039] FIG. 3 A shows a source or drain finger, including a linear finger portion 310 with an associated linear drift region 290, and a fingertip 31 1 with an associated source FDR 210, with a BDL stripe 320 shown in the linear drift region 290. In FIG. 3B, one-half of the fingertip 31 1 (FIG. 3 A) is shown as 31 1a, and one-half of the source FDR 210 is shown as 210a, to show parameters in disclosed DBDL designs according to an example embodiment. FIGS. 3A and 3B show Θ, which is the angle to the location of interest in the FDR. FIG. 3B shows Lg, which is the distance (length) from the outer edge of the drain MOAT 1 15 to fingertip center 285. FIG. 3 A shows rGnl, which is the trajectory of xnl within the source FDR 210, and xnl is one edge of the BDL stripe 320 in the linear drift region 290. rGnl lines up with xnl at 0=0. rs,d is the radius of the fingertip 31 1 half circle, depicted as a solid line as shown in FIG. 3 A drawn from the fingertip center 285.

[0040] For example Le calculations within the FDR, when Θ < arc tangent (arctg) (Lf/L):

L_g = L I cos Θ and when π/2 > Θ > arctg (Lf/L)

[0041] An exam le drift length scaling equation is:

One then can solve for L_e, and then solve for r0 (shown as Γ_ΘΠΙ) from the above scaling equation, where re defines how to draw (layout) the edge of each DBDL stripe in the FDR associated with the fingertips for source or drain fingers, such as source FDR 210 described above associated with the source fingertip. As Le increases, re_ni increases, which increases the width of the DBDL stripes. The width of non-implanted regions (gaps) between the DBDL stripes also increases with L_e. L = DL+ rs,d; DL=L-rs,d is the constant drift length in the linear drift region. The drift region in the FDR is Le=DLe+ rs,d, DLe=Le - rs,d.

[0042] In FIG. 2B, which shows the case of a source FDR 210 for an MOS device, each of the fifteen DBDL stripes shown as DBDL 132a within the source FDR 210 has a width that varies with Θ, specifically increasing in width with increasing Θ, having a maximum width at 90 degrees, and being symmetric in width pattern relative to the 90 degree line. The equations above generate such a distribution, because Le increases as Θ increases, which increases re_ni that increases the width of the DBDL stripes.

[0043] FIG. 4 shows comparative LDMOS BVDSS data, including the BVDSS from a multi-finger NLDMOS device that has a disclosed DBDL having a variable stripe width overdesign dimension in the FDR, such as shown in FIG. 2B, and a control racetrack NLDMOS device that has a conventional DBDL having a fixed stripe width overdesign dimension. The BVDSS difference between multi-finger and racetrack (single finger) NLDMOS device layouts is only ~40V, versus in excess of over 100V reduction for the multi-finger NLDMOS device that has a DBDL design having a fixed stripe overdesign dimension.

[0044] Disclosed embodiments are useful to form semiconductor die that may be integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements, such as source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines and conductive vias. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

[0045] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

CLAIMS What is claimed is:

1. A multi-finger lateral high voltage transistor (MFLHVT), comprising:

a stack on a substrate doped a first dopant type including a well doped a second dopant type, a buried drift layer (BDL) doped the first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, a semiconductor surface on the BDL doped the second dopant type;

dielectric isolation regions at least partially in the semiconductor surface having gaps defining a first active area in a first dielectric gap region (first MOAT) and a second active area in a second dielectric gap region (second MOAT);

a drain including a plurality of drain fingers having drain fingertips in the second MOAT interdigitated with a source including a plurality of source fingers having source fingertips in the first MOAT, each doped the second dopant type;

a fingertip drift region (FDR) associated with at least one of the drain fingertips (drain FDR) and the source fingertips (source FDR) between the first MOAT and the second MOAT that the DBDL is within;

an upper current channel in the semiconductor surface and lower current channel in the well, both between the source and the drain; and

at least a first gate stack on the semiconductor surface between the source and the drain; wherein the plurality of dilution stripes have respective stripe widths that increase monotonically with a drift length at their respective positions.

2. The MFLHVT of claim 1, wherein the respective stripe widths for the source FDR increase monotonically with an increasing angle Θ relative to a boundary of the source FDR with a linear drift region having a maximum width at 90 degrees, and wherein the respective stripe widths for the drain FDR decrease monotonically with an increasing angle Θ relative to a boundary of the drain FDR with a linear drift region having a minimum width at 90 degrees.

3. The MFLHVT of claim 1, wherein the FDR includes the source FDR and the drain FDR.

4. The MFLHVT of claim 1, further comprising a top surface layer in the semiconductor surface doped the first dopant type.

5. The MFLHVT of claim 1, wherein the first gate stack includes a split-gate including a first gate stack and a second gate stack lateral to the first gate stack.

6. The MFLHVT of claim 1, wherein the MFLHVT includes a drain-extended MOS (DEMOS) transistor.

7. The MFLHVT of claim 1, wherein the MFLHVT includes laterally diffused MOS (LDMOS) transistor.

8. The MFLHVT of claim 1, wherein the substrate includes silicon and a gate electrode of the first gate stack includes polysilicon.

9. An integrated circuit (IC), comprising:

a substrate doped a first dopant type;

a multi-finger lateral high voltage transistor (MFLHVT), including:

a stack on the substrate including a well doped a second dopant type, a buried drift layer (BDL) doped the first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, a semiconductor surface on the BDL doped the second dopant type;

an upper current channel in the semiconductor surface and lower current channel in the well, both between the source and the drain;

at least a first gate stack on the semiconductor surface between the source and the drain;

wherein the plurality of dilution stripes have respective stripe widths that increase monotonically with a drift length at their respective positions, and

a symmetric p-channel metal oxide semiconductor (PMOS) transistor and symmetric n-channel MOS ( MOS) transistor formed in the substrate.

10. The IC of claim 9, wherein the respective stripe widths for the source FDR increase monotonically with an increasing angle Θ relative to a boundary of the source FDR with a linear drift region having a maximum width at 90 degrees, and wherein the respective stripe widths for the drain FDR decrease monotonically with an increasing angle Θ relative to a boundary of the drain FDR with a linear drift region having a minimum width at 90 degrees.

11. The IC of claim 9, wherein the FDR includes the source FDR and the drain FDR.

12. The IC of claim 9, wherein the MFLHVT further includes a top surface layer in the semiconductor surface doped the first dopant type.

13. The IC of claim 9, wherein the first gate stack includes a split-gate including a first gate stack and a second gate stack lateral to the first gate stack.

14. A method of forming a lateral power MOS transistor, comprising

providing a substrate doped with a first dopant type having a well thereon doped a second dopant type, with a semiconductor surface doped the second dopant type on the well;

forming dielectric isolation regions at least partially in the semiconductor surface having gaps defining a first active area in a first dielectric gap region (first MOAT) and a second active area in a second dielectric gap region (second MOAT);

forming a buried drift layer (BDL) doped the first dopant type having a diluted BDL portion (DBDL) including a plurality of dilution stripes, including: forming a masking pattern using a diluted BDL mask having the plurality of dilution stripes with respective stripe widths that increase monotonically with a drift length at their respective positions; and implanting using the masking pattern;

forming a drain including a plurality of drain fingers having drain fingertips in the second MOAT interdigitated with a source including a plurality of source fingers having source fingertips in the first MOAT, each doped the second dopant type;

wherein the DBDL is within a fingertip drift region (FDR) associated with at least one of the drain fingertips (drain FDR) and the source fingertips (source FDR) between the first MOAT and the second MOAT; and

forming at least a first gate stack on the semiconductor surface between the source and the drain.

15. The method of claim 14, wherein the respective stripe widths increase with an increasing angle Θ relative to a boundary of the FDR, with a linear drift region having a maximum width at 90 degrees.

16. The method of claim 14, wherein the FDR includes the source FDR and the drain FDR.

17. The method of claim 14, further comprising forming a top surface layer in the semiconductor surface doped the first dopant type.

18. The method of claim 14, wherein the first gate stack includes a split-gate including a first gate stack and a second gate stack lateral to the first gate stack.