WO2016155323A1

WO2016155323A1 - Model and storage method for resistive random access memory having reset function

Info

Publication number: WO2016155323A1
Application number: PCT/CN2015/094866
Authority: WO
Inventors: 王小光
Original assignee: 山东华芯半导体有限公司
Priority date: 2015-03-27
Filing date: 2015-11-18
Publication date: 2016-10-06
Also published as: CN104794261A

Abstract

A model and a storage method for a resistive random access memory having a reset function. The model comprises a resistive storage unit, a bit end b1, a word end w1, and a source end sl, and further comprises a reset module. A reset end is arranged on the resistive storage unit. The reset module is used for resetting the storage unit in a storage array into a preset initial resistance value state by means of the reset end before the resistive storage unit is operated. The model and the storage method solve the technical problems of long simulation time, heavy simulation load and large generated simulation files of an existing simulation model, can truly reflect the characteristics of memory or storage information of a variable resistor under different working conditions, and can be reliably applied to the simulation work in the design of the resistive memory.

Description

Resistance variable random access memory model with reset function and storage method

Technical field

The invention relates to a resistive random access memory model and a storage method with a reset function.

Background technique

Resistive Random Access Memory (RRAM) is a new type of non-volatile data storage technology characterized by the use of a metal oxide that can undergo resistance changes under special conditions as a memory cell, such as HfOx, WOx, TiOx, NiOx. Wait.

In the design of resistive memory, in order to accurately and realistically simulate the design of the internal circuit of the chip, the model of the resistive memory cell is generally established, that is, according to the working principle of the variable resistor itself and the working conditions of different conditions, and The data related to the electrical characteristics of the resistive change unit obtained in the class test establishes a simulation model that can truly reflect the working state of the resistive memory cell under different conditions and can realize data storage and reading. Using the simulation model, the designer can effectively verify various control circuits and analog circuits that are shuttled to the periphery of the memory cell in the chip-level simulation to ensure the correctness and feasibility of all circuit designs, thus ensuring the successful development and production of the memory chip.

For the establishment of memory cell model in resistive memory design, the existing model building method has a description of the narrative paper, academic paper: "Hspice model design of a resistive memory cell"; Chen Yi et al; Journal of Fudan University (Natural Science Edition) , August 2011, Vol. 50, No. 4, as shown in Figure 1a, Figure 1b, Figure 2 is its schematic diagram and current-voltage relationship curve. Figure 1a is the state transition circuit, including the resistor Rset, Rreset and switch S0, S1; Figure 1b is a state transition control circuit including switches S1/SB1, S2/S2B, resistors and capacitors R1/C1, R2/C2, comparator CMP1/CMP2, reference excitation source VSET/VREST, and RS latch (2 NOR gate and 1 NOT gate).

This paper builds the peripheral circuit of the resistive change unit for the working principle of the variable resistance unit. The principle is as follows:

When the voltage across the variable resistor is Vin>VSET, the output of the comparator CMP1 causes the Q terminal (ie, signal A) and the QB terminal (ie, signal B) of the RS latch to be high and low, respectively, to open the SET path (Note: The switch control signal of the state transition circuit is reversed, that is, the signal A should control the switch S1 in series with the resistor Rset, and the signal B should control the switch S0) in series with the resistor Rreset; at this time, the resistance of the variable resistor is equal to the Rset. Resistance value

When Vin>VRESET, the output of the comparator CMP2 causes the Q terminal (ie, signal A) and the QB terminal (ie, signal B) of the SR latch to be low and high, respectively, to turn on the RESET path; at this time, the resistance of the variable resistor is equal to The resistance of Rreset.

Although the method in the above document can more accurately fit the electrical characteristics of the variable resistor, it reflects the characteristics of the memory or stored information of the variable resistor under different working conditions. However, there are the following disadvantages: 1) The number of circuit unit devices required in the model is large, and the circuit is only a peripheral required circuit of a memory cell. For large-capacity memory design simulation, more devices (capacitors, Resistor, MOS tube, etc.) and circuit nodes can affect the simulation time, which makes the emulator load increase during chip-level simulation, the simulation time is long and the efficiency is low; thus greatly extending the chip development cycle and increasing the chip development cost; Multi-device and circuit node simulation makes the simulation result file data large and occupies disk resources; 2) This model does not specify the implementation of the comparator; if implemented with MOS tube, the number of discrete devices of this model will be further increased; This model is a circuit construction method. If the resistance value needs to be changed in the future, it still needs to be modified for the circuit, and any function improvement needs to be changed to the circuit, and the steps are complicated; 4) This model does not have the state control switch S1/ The working principle of S1B and S2/S2B is explained, and it is not clear whether an auxiliary circuit is still needed.

Summary of the invention

In order to solve the problem that the existing simulation model has long simulation time and heavy simulation load, the simulation file is generated. The invention provides a resistive random access memory model and a storage method with a reset function.

Technical solution of the invention:

A resistive random access memory model with a reset function, comprising a resistive memory cell, a bit terminal bl, a word terminal w1 and a source terminal sl, further comprising a reset module, wherein the resistive memory unit is provided with a reset terminal, the reset A module is configured to reset a memory cell in the memory array to a predetermined initial resistance state through the reset terminal before the resistive memory cell is operated.

Further, the resistive random access memory model with a reset function further includes a state monitoring module, wherein the resistive memory unit is provided with a state port, and the state monitoring module reflects the current state of the resistive memory cell in real time through the state port. And output a signal representing the current resistance state.

A storage method of a resistive random access memory with a reset function, comprising:

Step 1. Idle state: the variable resistance of the resistive memory cell is in an initial resistance state;

Step 2: reset: the reset module passes the reset end, and sets the initial resistance value state of the resistive memory unit according to the user requirement;

Step 3: Storage: when the terminal voltage V(bl) and the source voltage V(sl) of the resistive memory cell satisfy: V(bl)>V(sl) and V(bl,sl)>V _threshold , V _threshold In order to resist the threshold, the variable resistor will jump to the low-resistance state, that is, realize the operation of the resistive memory cell to write data 1; the absolute voltage difference of the terminal voltage and the source voltage of the resistive memory cell |V(bl, sl ) | < V _threshold , the variable resistor will always be in the current low-resistance state, that is, to maintain the state of storing data 1; when the terminal voltage V(bl) and the source voltage V(sl) of the resistive memory cell satisfy: V ( Sl)>V(bl) and V(sl, bl)>V _threshold , the variable resistor will jump to the high-impedance state, that is, the operation of writing data 0 to the resistive memory cell; the bit end of the resistive memory cell The absolute voltage difference between the voltage and the source voltage |V(bl,sl)|<V _threshold , the variable resistor will always be in the current high-impedance state, that is, the state in which the data 0 is stored;

Step 4: Verify that the write operation of step 3 is correct.

Further, the foregoing step 4 is specifically implemented as: the status monitoring module reflects in real time through the status port. The current state of the memory cell is resisted and a signal representing the current state is output.

The advantages of the invention:

1. The invention can reflect the characteristics of the memory or the stored information of the variable resistor under different working conditions more realistically, and can be reliably applied to the simulation work of the resistive memory design.

2. The memory cell model of the present invention provides an initial resistance reset function. With this function, the initial resistance of the memory cell can be flexibly designed in the simulation, so that the test sequence can be simplified in different simulation test sequences, and the simulation and test time can be reduced.

3. The storage unit model of the present invention provides a storage unit status monitoring interface, and the interface can be used to directly monitor the current variable resistance working state in the simulation, thereby facilitating simulation verification work and speeding up simulation efficiency.

4. The memory cell model in the present invention uses the Verilog-a language to design and implement the model, and the simulation verification ensures the feasibility and reliability of the simulation model.

DRAWINGS

1a is a schematic diagram of a state transition circuit in a conventional modeling method;

FIG. 1b is a schematic diagram of a state transition control circuit in a conventional modeling method;

2 is a graph showing a current-voltage relationship of a conventional method;

3 is a schematic structural diagram of a memory cell of a resistive random access memory model of the present invention;

4 is a working curve of a resistive random access memory of the present invention;

5 is a schematic diagram of a storage method of a resistive random access memory according to the present invention;

Figure 6 is a schematic view of an embodiment of the present invention;

FIG. 7a is a waveform diagram of a write data 0 operation of the resistive random access memory; FIG.

Figure 7b is a waveform diagram of the read data 0 operation of the resistive random access memory;

Figure 7c is a waveform diagram of the operation of writing data 1 to the resistive random access memory;

Fig. 7d is a waveform diagram of the read data 1 operation of the resistive random access memory.

detailed description

In order to clearly illustrate the technical features of the present solution, the present embodiment will be described below through a specific embodiment and in conjunction with the accompanying drawings.

Figure 3 and Figure 4 are schematic diagrams and model working curves of the resistive memory cell, where: V(bl,sl)=V(bl)-V(sl) is the voltage difference across the variable resistor, when the memory cells are absolutely absolute when the voltage difference V (BL, SL) is greater than the threshold value V resistive _threshold (assuming a threshold of 1V), its resistance will change in low resistance (SET state, 10K ohms), when the phase voltage V (sl, bl) is greater than 1v When it is, its resistance will change to high resistance (RESET state, 100K ohms). If the voltage at both ends is less than 1V, the resistance will maintain the current resistance state. The memory cells will be in different resistance states depending on the conditions. The resistance threshold is determined based on the material of the variable resistor.

Figure 5 is a flow chart of the operation of the resistive memory cell. In the idle state, the resistance value in the model will be in the initial resistance value state. With the reset terminal function, when the model is reset, its resistance value will be in the initial resistance value state set by the user according to the demand (such as low resistance value 10KΩ). Or high resistance value 100KΩ). When the external condition of the memory cell satisfies the low-resistance state change condition (V(bl)>V(sl) and V(bl,sl)>1V), the model will jump to the low-impedance state (10KΩ), and then if the absolute voltage is at both ends Poor|V(bl,sl)|<1V, the resistor will always be in the current low-resistance state, that is, the operation of writing data 1 to the memory cell (SET operation) is realized. If the external condition of the memory cell satisfies the condition of high resistance change (V(sl)>V(bl) and V(sl, bl)>1V), the memory model will jump to the high-impedance state (100KΩ), after which if both ends are absolute The voltage difference |V(bl,sl)|<1V, the model will always be in the current high-impedance state, that is, the operation of writing data 0 to the memory cell (RESET operation) is realized. Regardless of whether the model is in a high-impedance or low-resistance state, as long as the resistance change condition is satisfied, the model will generate a corresponding resistance state jump, thereby simulating the migration of the working state of the real resistive memory cell, and realizing the data storage. For read operations, because the memory cells have different self-resistance values when they are in different states, when the appropriate read data voltage is applied to both ends of the memory cell, according to the principle of Ohm's law, I=U/R, there will be a large A current of I(bl,sl)=V(bl,sl)/R flows out of bl, and then the operation of reading the corresponding

data

0 or 1 can be realized by detecting and amplifying the outflow current in combination with the peripheral circuit.

A state monitoring port is added to the simulation model of the present invention, and the port can output a real-time signal reflecting the state of the current memory cell as a low resistance state (10KΩ) and a high resistance state (100KΩ), so that the chip is simulated. At any time, the current state of the storage unit can be monitored directly by the determination of the status port. For example, if the write 1 operation is performed, if it is necessary to confirm whether the write 1 operation is successful, it is necessary to perform a read operation on the current storage unit to determine whether the data stored in the unit is 1, thereby determining whether the previous write 1 operation is Success, while reading the data operation itself takes time. If the storage model of the present invention is utilized, the state monitoring terminal can be used to directly check whether the state end of the model is 0. If it is 0, it indicates that the write operation has successfully converted the memory cell to a low resistance (10KΩ) state. That is, data 1 is successfully written, otherwise the operation fails, and then the operation mode is further improved. To a certain extent, the process of verifying the internal function in the chip simulation is simplified, and the simulation efficiency is improved.

The reset function added in the present invention means that the memory cell in the memory array can be reset to a preset initial resistance state (high resistance/low resistance) by using the function before the memory cell array is operated. Function, in the simulation process, the artificial initial value of the data in the storage can be flexibly set, so that a certain test sequence and simulation time can be saved in the large-scale chip simulation. Figure 6 shows an application example in the simulation. If the operation to test the read data sequence is "01010101..." in the simulation, the following operation modes are explained:

The original operation: firstly, the memory unit needs to be erased to implement the full write 1 operation, and then the memory is programmed to realize the operation of writing 0 to the partial memory unit, thereby rewriting the data stored in the array to 0101... Format, and finally read operation;

Optimization operation 1: After using the model of the present invention, the initial resistance can be directly set to a full low resistance value (10KΩ) by using the reset function, thereby skipping the erase operation and directly performing the programming operation to realize partial storage. Write 0 operation of the unit, and finally complete the reading;

Optimization operation 2: After using the model of the invention, the initial resistance of the memory cell in the array is directly set to low resistance according to the demand portion, and the portion is set to high resistance, so that the data format in the array is set after resetting. The sequence of "1010..." can be directly executed during simulation, and the simulation verification of the read data can be completed, and the execution of the erase and program operations is directly omitted, which greatly simplifies the test sequence and saves the simulation. time. Taking the 64MB RRAM as an example, the chip execution time saved when the above operation sequence is implemented is as shown in Table 1.

Table 1 shows the simulation model optimization and time saving for the simulation model.

In order to better verify the reliability and authenticity of the resistive memory cell model of the present invention, the present invention utilizes the Verilog-a language to simulate and verify the memory cell model of the present invention. The technical parameters related to resistive storage are parameterized, such as high and low resistance variable threshold Vset/Vreset, high and low resistance value R_set/R_reset, memory cell initial resistance initial_res, etc., so that the memory design can be based on the process conditions. The changes or the development of technology will improve and upgrade the model in the future, ensuring the sustainable applicability of the model of the invention.

According to the working principle of the resistive memory, the model is simulated, and the resistance of the model is calculated by the voltage V(bl,sl) at both ends of the memory cell and the current value I(bl,sl) flowing out from the BL terminal, as shown in Fig. 7a, Fig. 7b, Fig. 7c and Figure 7d is the reset (write 0) operation, the read data 0 operation, the set (write 1) operation, and the read data 1 operation simulation result. It can be seen that the simulation model can be successfully converted to the corresponding one when performing the related operation. The resistance state, that is, the function of storing the data information can be completed, and the functional correctness of the storage model of the present invention is proved, and can be reliably applied to the design and development of the resistive memory.

Claims

A resistive random access memory model with a reset function, comprising a resistive memory cell, a bit terminal bl, a word terminal w1 and a source terminal sl, further comprising: a reset module, wherein the resistive memory unit is provided with a reset terminal The reset module is configured to reset the memory cells in the memory array to a preset initial resistance state through the reset terminal before the resistive memory cells are operated.
The resistive random access memory model with reset function according to claim 1, further comprising a state monitoring module, wherein the resistive memory unit is provided with a state port, and the state monitoring module reflects the resistance in real time through the state port. The current state of the memory cell is changed, and a signal representing the current resistive state is output.
A storage method of a resistive random access memory with a reset function, comprising:

Step 1. Idle state: the variable resistance of the resistive memory cell is in an initial resistance state;

Step 2: reset: the reset module passes the reset end, and sets the initial resistance value state of the resistive memory unit according to the user requirement;

Step 3: Storage: when the terminal voltage V(bl) and the source voltage V(sl) of the resistive memory cell satisfy: V(bl)>V(sl) and V(bl,sl)>V threshold , V threshold In order to resist the threshold, the variable resistor will jump to the low-resistance state, that is, realize the operation of the resistive memory cell to write data 1; the absolute voltage difference of the terminal voltage and the source voltage of the resistive memory cell |V(bl, sl ) | < V threshold , the variable resistor will always be in the current low-resistance state, that is, to maintain the state of storing data 1; when the terminal voltage V(bl) and the source voltage V(sl) of the resistive memory cell satisfy: V ( Sl)>V(bl) and V(sl, bl)>V threshold , the variable resistor will jump to the high-impedance state, that is, the operation of writing data 0 to the resistive memory cell; the bit end of the resistive memory cell The absolute voltage difference between the voltage and the source voltage |V(bl,sl)|<V threshold , the variable resistor will always be in the current high-impedance state, that is, the state in which the data 0 is stored;

Step 4: Verify that the write operation of step 3 is correct.
A storage method of a resistive random access memory having a reset function according to claim 3, The method is characterized in that: the step 4 is implemented by: the status monitoring module reflects the current state of the resistive memory unit in real time through the status port, and outputs a signal representing the current status.