WO2016147729A1 - Direct digital synthesizer, reference signal generation device, and signal output method - Google Patents

Direct digital synthesizer, reference signal generation device, and signal output method Download PDF

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Publication number
WO2016147729A1
WO2016147729A1 PCT/JP2016/053190 JP2016053190W WO2016147729A1 WO 2016147729 A1 WO2016147729 A1 WO 2016147729A1 JP 2016053190 W JP2016053190 W JP 2016053190W WO 2016147729 A1 WO2016147729 A1 WO 2016147729A1
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Prior art keywords
signal
reference signal
unit
output
sine wave
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PCT/JP2016/053190
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French (fr)
Japanese (ja)
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一典 宮原
克久 山階
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古野電気株式会社
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Priority to JP2017506135A priority Critical patent/JP6538823B2/en
Publication of WO2016147729A1 publication Critical patent/WO2016147729A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B28/00—Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the present invention mainly relates to a direct digital synthesizer capable of outputting a signal of a predetermined frequency.
  • DDS Direct Digital Synthesizer
  • NCO Numerically Controlled Oscillator
  • ROM Read Only Memory
  • LPF Low Pass Filter
  • the NCO outputs a sawtooth wave with a predetermined frequency.
  • the ROM stores the output value of the NCO (the phase of the sawtooth wave) and the amplitude of the sine wave set in association with this output value as a spear table.
  • the ROM can convert a sawtooth wave into a sine wave by performing signal conversion based on this table.
  • the sine wave is output after the high frequency component is removed by the LPF.
  • Patent Document 1 includes an integration circuit unit, a multiplication circuit unit, and an error correction unit.
  • the integrating circuit unit has the same configuration as the NCO.
  • the multiplication circuit unit converts the sawtooth wave into a parabolic signal by performing a predetermined calculation on the sawtooth wave output from the integration circuit unit.
  • the error correction unit corrects the parabolic signal obtained from the multiplication circuit unit based on the ideal waveform of the sine wave stored in advance in the storage device. Thereby, a sine wave can be generated.
  • Patent Documents 2 and 3 disclose clock generation circuits. These clock generation circuits disclose a configuration for modulating a generated clock in order to reduce EMI (electromagnetic interference). Patent Documents 2 and 3 disclose that a triangular wave oscillation circuit, a ⁇ modulator, or the like is used for this modulation.
  • the reference signal generation device including the above-described DDS is installed in a base station such as a mobile phone or WiMAX.
  • a base station such as a mobile phone or WiMAX.
  • many base stations have been provided in order to cope with an increase in the amount of communication data such as cellular phones. Therefore, there is a need for a reference signal generator having a compact and inexpensive configuration.
  • the generated signal is converted into an analog signal by a D / A converter.
  • a D / A converter it is difficult to make a D / A converter into a chip.
  • the D / A converter function is mounted on the board without being formed into a chip, many analog parts are included, which hinders the realization of a compact configuration.
  • the conventional D / A converter has room for improvement in that the resolution of resolution is low when the bit is low and the cost is high when the bit is high.
  • the present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a DDS including a large number of digital parts and having improved resolution.
  • the direct digital synthesizer includes a numerically controlled oscillator, a ⁇ modulator, and a filter.
  • the numerically controlled oscillator outputs a digital signal.
  • the ⁇ modulation unit ⁇ modulates a signal output from the numerically controlled oscillator or a signal based on the signal.
  • the filter unit outputs the signal that is ⁇ modulated by the ⁇ modulation unit as an analog signal.
  • the ⁇ modulation unit by providing the ⁇ modulation unit, most of the D / A converters that have conventionally been configured with analog components can be realized with digital circuits. Therefore, it is possible to realize a compact configuration by making most of the DDS into a chip. Further, by performing ⁇ modulation, it is possible to suppress quantization errors by noise shaving (details will be described later), so that the resolution of the signal after D / A conversion can be improved.
  • the direct digital synthesizer may include a conversion information storage unit that converts an input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator. preferable.
  • the filter unit extracts a sine wave signal having a predetermined frequency by passing a signal in a predetermined range from a signal output from the numerically controlled oscillator or a signal based on the signal. It is preferable to do.
  • the direct digital synthesizer preferably has the following configuration. That is, this direct digital synthesizer includes a conversion information storage unit that converts an input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator. . One of the sine wave signal converted by the conversion information storage unit and the sine wave signal extracted by the filter unit is output to the outside.
  • a reference signal generator having the following configuration. That is, the reference signal generator includes the direct digital synthesizer, a control unit, and an output unit.
  • the control unit compares the phase or frequency of a signal output from the numerically controlled oscillator or a signal based thereon with a reference signal, and controls the numerically controlled oscillator based on a comparison result.
  • the output unit outputs a signal output from the direct digital synthesizer or a signal based on the signal as a reference signal.
  • the reference signal generator includes a self-running control unit that generates a self-running control signal for generating the reference signal when it is determined that the appropriate reference signal cannot be used.
  • the reference signal generator preferably includes at least a power control unit that performs control to reduce power consumption of the numerically controlled oscillator.
  • the power consumption of the reference signal generator can be reduced by stopping the clock, reducing the supplied voltage, or making it zero.
  • the reference signal generator described above preferably has the following configuration. That is, the reference signal generator includes a GNSS receiver that acquires position information based on radio waves from a GNSS satellite.
  • the power supply control unit performs control to reduce the power consumption of the signal generation unit.
  • the power consumption of the reference signal generator is greatly reduced by reducing the power consumption of the signal generator. be able to.
  • the reference signal generator described above preferably has the following configuration. That is, the reference signal generator includes a GNSS antenna and a GNSS receiver.
  • the GNSS antenna is attached to the same board as the control unit, and receives a positioning signal from a GNSS satellite.
  • the GNSS receiving unit is attached to the same substrate as the control unit, and generates a reference signal based on a positioning signal received by the GNSS antenna.
  • this signal output method includes a digital signal output step, a modulation step, and an analog signal output step IV.
  • a digital signal is output by a numerically controlled oscillator.
  • the modulation step the signal ⁇ output in the digital signal output step is ⁇ modulated.
  • the analog signal output step the signal output in the modulation step is output as an analog signal by performing filter processing.
  • the block diagram which shows the structure of the reference signal generator which concerns on one Embodiment of this invention. The figure explaining the mechanism converted from a sawtooth wave to a triangular wave.
  • the block diagram which shows the structure of a delta-sigma modulation part.
  • the block diagram of the reference signal generator provided with the structure which can directly input the signal which NCO outputs into a frequency-dividing part.
  • the block diagram of the reference signal generator provided with the structure in which self-running control is possible.
  • the block diagram of the reference signal generator provided with the structure which can adjust the power supply to a signal generation part.
  • the block diagram of the reference signal generator provided with the structure which can adjust the clock used by a signal generation part.
  • FIG. 1 is a block diagram showing a configuration of a reference signal generator 10 according to an embodiment of the present invention.
  • the reference signal generator 10 is for providing a reference signal and the like to the connected user equipment.
  • Examples of the reference signal generator 10 to which the reference signal is supplied include a mobile phone base station, a terrestrial digital broadcast transmitter, and a WiMAX (Worldwide Interoperability for Microwave Access) communication facility.
  • the reference signal generator 10 of the present embodiment includes a GPS receiving unit 21, a PLL (Phase Locked Loop) circuit 51, and a DDS (Direct Digital Synthesizer) 52 as main components.
  • PLL Phase Locked Loop
  • DDS Direct Digital Synthesizer
  • a GPS antenna (GNSS antenna) 11 is connected to the signal input unit 41 of the reference signal generator 10.
  • a positioning signal received by the GPS antenna 11 from a GPS satellite (GNSS satellite) ⁇ ⁇ is input to the GPS receiving unit 21 via the signal input unit 41.
  • the GPS receiving unit 21 generates a reference signal (one pulse signal per second) by performing positioning calculation based on the positioning signal. This reference signal is appropriately calibrated to be accurately synchronized to 1 second of Coordinated Universal Time (UTC).
  • UTC Coordinated Universal Time
  • the PLL circuit 51 includes a control unit 22, an NCO (numerically controlled oscillator) 23, and a frequency dividing unit 24.
  • a phase comparison is performed between the reference signal output from the GPS receiving unit 21 and a signal obtained by dividing the signal output from the NCO 23, and the frequency of the signal output from the NCO 23 is adjusted based on the comparison result. Is done.
  • each device constituting the PLL circuit 51 will be described in detail.
  • the control unit 22 receives the reference signal and a signal obtained by dividing the signal output from the NCO 23.
  • the control unit 22 compares the phases of these signals to obtain a phase difference, and generates a signal (phase difference signal, frequency control amount) based on the phase difference.
  • the control unit 22 outputs the frequency control amount to the NCO 23 after blocking the high frequency component of the frequency power control amount and removing noise.
  • the control unit 22 may be configured to output a comparison result of both signals, and the signal processing method is arbitrary.
  • the NCO 23 is a digitally controlled oscillator for outputting a signal that is the basis of a reference signal.
  • the NCO 23 includes an unillustrated register and an adder.
  • the NCO 23 outputs a signal (sawtooth wave, see FIG. 2B) in which the output value gradually increases and the output threshold value returns to 0 in a predetermined cycle by the adder and the register.
  • the output value of the NCO 23 may be particularly referred to as “the phase of the sawtooth wave” by paying attention to the periodic change.
  • a frequency control amount is input to the NCO 23 from the control unit 22.
  • the NCO 23 generates a sawtooth wave so as to eliminate a phase difference between the reference signal and a signal obtained by dividing the signal output from the NCO 23 based on the frequency control amount.
  • the sawtooth wave is appropriately converted by each unit included in the DDS 52 and then output to the frequency dividing unit 24.
  • the frequency divider 24 divides the signal output from the DDS 52 and converts it from a high frequency to a low frequency, and outputs the obtained signal (phase comparison signal) to the control unit 22.
  • the frequency divider 24 divides the 10 MHz signal by a frequency division ratio of 1 / 10,000,000 to generate a 1 Hz phase comparison signal.
  • the phase comparison signal is output from the output unit 44 to the external user system as a reference timing signal.
  • a loop of the PLL circuit 51 is configured by the configuration described above. For example, it is assumed that the timing at which the adder of the NCO 23 performs integration has changed due to changes over time, ambient temperature changes, power supply voltage, and the like. In this case, the phase of the sawtooth wave output from the NCO 23 changes, and a stable reference signal cannot be output. However, the PLL loop circuit 51 digitally controls the NCO 23 based on the accurate 1PPS signal input from the GPS receiver 21 so that the phase shift of the sawtooth wave is eliminated. Therefore, even when the timing at which the adder performs integration changes as described above, the reference signal output from the reference signal generator 10 can be maintained with high accuracy.
  • the DDS 52 includes an NCO 23, a sine wave conversion ROM (conversion information storage unit) 25, a triangular wave conversion circuit 26, a selection unit 27, a ⁇ modulation unit 28, and a BPF (bandpass filter, Filter section) 29.
  • NCO sine wave conversion ROM
  • triangular wave conversion circuit 26 a selection unit 27, a ⁇ modulation unit 28, and a BPF (bandpass filter, Filter section) 29.
  • BPF bandpass filter, Filter section
  • the sine wave conversion ROM 25 stores the output value (sawtooth phase) of the NCO 23 and the amplitude of the sine wave set in association with this output value as a table.
  • the sine wave conversion ROM 25 can convert a sawtooth wave into a sine wave by performing signal conversion based on this table.
  • the signal converted by the sine wave conversion ROM 25 is output to the selection unit 27.
  • the triangular wave conversion circuit 26 is a circuit that converts a sawtooth wave into a triangular wave by inverting the latter half of the sawtooth wave generated by the NCO 23.
  • the triangular wave conversion circuit 26 will be described in detail with reference to FIG.
  • the phase change of the sawtooth wave output from the NCO 23 is described in a 3-bit binary number.
  • the sawtooth wave shows a waveform that increases the output value by 1 (see the graph on the left side of FIG. 2B).
  • the triangular wave conversion circuit 26 is configured to obtain an exclusive OR with “000” with respect to the first half part (d1 to d4) of the sawtooth wave and to the second half part (d5 to d8) of the sawtooth wave.
  • the logic circuit is configured to take an exclusive OR with “111”. By taking the exclusive logical sum, the output value of the latter half is bit-inverted as described in the column “After Conversion” on the right side of FIG.
  • a triangular wave signal can be obtained in which the output value of the first half portion (d1 to d4) gradually increases and the output value of the second half portion (d5 to d8) gradually decreases (FIG. 2B). (See graph on the right side of).
  • the triangular wave signal output from the triangular wave conversion circuit 26 is output to the selection unit 27.
  • the selection unit 27 outputs either the sine wave signal output from the sine wave conversion ROM 25 or the triangular wave signal output from the triangular wave conversion circuit 26 to the ⁇ modulation unit 28.
  • the signal output from the selection unit 27 is determined by initial setting or user operation.
  • the ⁇ modulation unit 28 modulates the signal output from the selection unit 27.
  • the ⁇ modulation unit 28 includes a subtraction unit (differentiator) 61, an addition unit (integrator) 62, a storage unit 63, and a quantization unit 64.
  • the adder 62 and the storage 63 integrate the input signal and output it to the quantizer 64.
  • the quantizing unit 64 quantizes the output of the adding unit 62 and delays the output by a predetermined time, and then outputs the quantized signal to the subtracting unit 61.
  • the subtractor 61 subtracts the quantized signal from the input signal and outputs the result to the adder 62.
  • the ⁇ modulation unit 28 may be a primary ⁇ modulation unit as shown in FIG. 3 or may be a secondary or higher-order ⁇ modulation unit.
  • the ⁇ modulator 28 can be configured by a digital circuit. Accordingly, the DDS 52 according to the present embodiment is largely composed of digital components (from the NCO 23 to the ⁇ modulation unit 28), so that these functions can be easily realized on the semiconductor chip. Therefore, a compact and inexpensive configuration can be realized.
  • the BPF 29 is an analog filter configured to pass only signals in a predetermined frequency band (pass band) and not pass signals of other frequencies. By passing this filter, the signal output from the ⁇ modulator 28 can be output as an analog signal.
  • a high frequency component or the like of the signal is removed.
  • the triangular wave signal converted by the triangular wave conversion circuit 26 ⁇ passes through the BPF 29, the triangular wave is a wave obtained by superimposing the sine wave and its odd overtone, and thus a sine wave signal having a predetermined frequency is extracted.
  • the sine wave signal generated as described above is output from the output unit 42 to an external user side system as a sine wave reference frequency signal.
  • the sine wave signal is converted into a rectangular wave signal by the hard limiter 31.
  • the signal converted by the hard limiter 31 is output from the output unit 43 to the external user system as a rectangular reference frequency signal.
  • the rectangular wave signal is output to the frequency divider 24 described above. As described above, the frequency divider 24 divides the rectangular wave signal to generate a comparison signal.
  • the sine wave conversion ROM 25 when used to output a sine wave signal, the sine wave conversion ROM 25 has many correspondence relations between the phase of the sawtooth wave and the displacement of the sine wave in order to exhibit the performance of the NCO 23 sufficiently. It is necessary to memorize. Therefore, in order to improve the resolution, a ROM having a large storage capacity is required, which increases the circuit scale and hinders downsizing of the apparatus.
  • the sine wave signal when a sine wave signal is output using the triangular wave conversion circuit 26, the sine wave signal can be generated without requiring the ROM. Therefore, high resolution can be achieved while realizing miniaturization of the apparatus.
  • the selection unit 27 can select which of the sine wave conversion ROM 25 and the triangular wave conversion circuit 26 is used, the sine wave conversion ROM 25 is used when importance is attached to the speed of wrinkles until synchronization with the reference signal.
  • the reference signal generating apparatus 10 can be used in such a manner that the triangular wave conversion circuit 26 is used.
  • the configuration can remove jitter by allowing the BPF 29 to pass through.
  • the configuration may be as shown in FIG. 4, which includes an adjustment unit 37 and a selection unit 38 as an output destination of the NCO 23.
  • the adjustment unit 37 extracts MSB (Most Significant Bit) and the like from the output of the NCO, and binarizes the output of the NCO 23.
  • the selection unit 38 receives the signal input from the adjustment rod unit 37 and the signal input from the hard limiter 31. The selection unit 38 outputs any one of the input signals to the frequency division unit 24. The signal output from the selection unit 27 is determined by initial setting or user operation.
  • the reference signal generator 10 has a function of transmitting the reference signal while maintaining a predetermined accuracy even when the reference signal cannot be acquired due to a lightning strike or interference radio wave.
  • the reference signal generation device 10 includes a self-running control unit 33 and a self-running selection unit 34 as a configuration for realizing this function.
  • the signals output from the free-running selection unit 34, the sine wave conversion ROM 25, and the triangular wave conversion circuit 26 are input to the selection unit 27.
  • a VCXO or the like can be arranged after the ⁇ modulator 28, or the NCO 23 or the like can be used as an oscillator.
  • heel selection unit 27 outputs the signal output from free-running selection unit 34 to ⁇ modulation unit 28.
  • the selection unit 27 outputs the signal output from the sine wave conversion ROM 25 or the triangular wave conversion circuit 26 to the ⁇ modulation unit 28.
  • the self-running control unit 33 receives the frequency control amount output from the control unit 22.
  • the self-running control unit 33 stores a correspondence relationship between the temperature detected by a temperature sensor (not shown) and the frequency of the signal output from the VCXO. This correspondence may be obtained before the product is shipped, or the value obtained before the product is shipped may be used after being corrected. Further, the self-running control unit 33 corrects the frequency control amount in consideration of the current temperature detected by the soot temperature sensor and the temperature characteristic obtained above.
  • the self-running selection unit 34 receives the frequency control amount output by the control unit 22 and the frequency control amount corrected by the self-running control unit 33.
  • the self-running selection unit 34 outputs the frequency control amount of the control unit 22 when an appropriate reference signal is available, and outputs the frequency control amount of the self-running control unit 33 when an appropriate reference signal is not available. To do.
  • the frequency control amount output by the self-running control unit 33 is determined in consideration of environmental changes (specifically, temperature changes). An accurate reference signal can be continuously output. Further, by using an OCXO having a high frequency stability as an oscillator arranged at the subsequent stage of the ⁇ modulation unit 28, it is possible to maintain a high frequency stability for a long time.
  • the configuration in which the VCXO or the like is not arranged in the subsequent stage of the ⁇ modulation unit 28 is the same as the configuration of the above-described embodiment, and thus description thereof is omitted.
  • this configuration by not arranging the VCXO or the like, the cost can be reduced as compared with the configuration in which the VCXO or the like is arranged.
  • reducing power consumption is to reduce power consumption compared to normal times, and is a concept including a case where power consumption is reduced to zero.
  • the reference signal generator 10 configured to reduce power consumption by performing control to switch whether or not to supply power will be described with reference to FIG.
  • the reference signal generation device 10 according to the present modification includes a power source 71 and a power source control unit 72.
  • the power source 71 and the power control unit 72 are electrically connected by a cable or the like. Further, the power control unit 72 is connected to the GPS receiving rod unit 21, the signal generating unit 53, and the like using a cable or the like for supplying power. The power controller 72 can switch whether to supply power to the GPS receiver 21 and whether to supply power to the signal generator 53 in response to an instruction from an external signal or an internal processing device. It is.
  • the signal generator 53 is a part that generates a reference signal based on the input reference signal, and includes the PLL circuit 51 and the DDS 52 described above.
  • the reference signal generator 10 having a large number of digital parts as in the present application can be realized on a semiconductor chip, it can be configured compactly and inexpensively. Therefore, even if only the positioning result output from the GPS receiving unit 21 is necessary, the chip-based reference signal generator 10 may be used. In this case, the power consumption of the reference signal generator 10 can be reduced by instructing the power supply controller 72 not to supply power to the signal generator 53 (or to reduce the supplied power).
  • the reference signal generation device 10 of the present modification includes a clock generation unit 73.
  • the clock generation unit 73 is a device that generates a clock mainly used by devices in the signal generation unit 53.
  • the clock generation unit 73 can change the frequency of the clock supplied to the devices in the signal generation unit 53 in response to an instruction from an external signal, an internal processing device, or the like.
  • the power consumption of the devices in the signal generating unit 53 is reduced by reducing (or setting to zero) the frequency of the clock generated by the clock generating unit 73. Can be reduced.
  • the power supply and the clock frequency are changed for all the devices in the signal generator 53, but only for a specific device (for example, the NCO 23).
  • the power supply or the clock frequency may be changed.
  • a clock gating circuit is provided between the clock generator 73 and the NCO 23, etc., and the clock supplied to the NCO 23, etc. is reduced (or made zero) only when an external signal is input to the clock gating circuit.
  • the DDS 52 of the present invention includes the NCO 23, the ⁇ modulator 28, and the BPF 29.
  • the NCO 23 outputs a digital signal.
  • the ⁇ modulation unit 28 modulates a sine wave signal or a triangular wave signal based on the signal output from the NCO 23.
  • the BPF 29 outputs the signal output from the ⁇ modulator 28 as an analog signal.
  • the ⁇ modulation unit 28 By providing the ⁇ modulation unit 28, most of the D / A converters that have been conventionally constituted by analog parts can be realized by a digital circuit. Therefore, most of the DDS 52 can be made into a chip to realize a compact configuration. Further, by providing the ⁇ modulator 28, the resolution of the signal after the D / A conversion can be improved.
  • the configuration can be appropriately changed as long as the configuration uses GNSS (Global Navigation Satellite System).
  • GNSS Global Navigation Satellite System
  • the configuration can be changed to a configuration in which a reference signal is generated based on a signal from a GLONASS satellite or a GALILEO satellite. Further, it may be configured to acquire a reference signal from an external device.
  • the GPS receiving unit 21 can be changed to a configuration that generates a signal other than 1 Hz such as PP2S as a reference signal instead of 1PPS. Further, the GPS receiver 21 may be arranged outside the reference signal generator 10 instead of inside.
  • the triangular wave conversion circuit is not limited to the above configuration using exclusive OR, and may be realized by a circuit having an arbitrary configuration. Further, a plurality of triangular wave conversion circuits are provided, and a part of the triangular wave shown above (two in the center when divided into four) is inverted to obtain a triangular wave for two cycles from a triangular wave for one cycle. be able to. In addition, it can change to the structure by which the sawtooth wave which NCO23 outputs is converted into a sine wave signal by BPF29, without providing a triangular wave conversion circuit.
  • the PLL circuit 51 that compares the phase difference is used, but an FLL circuit that compares the frequency difference can also be used.
  • the GPS antenna 11 is connected to a substrate on which the PLL circuit 51 and the like are formed via a predetermined cable.
  • the GPS antenna 11 may be directly attached to this board. In this case, since a cable is not necessary, the installation cost of the reference signal generator can be reduced.
  • the power consumption is reduced by reducing the power to be supplied or the clock to be supplied, but the power consumption is reduced by other configurations (such as not operating the software that controls the signal generator 53).
  • the configuration can be changed to be reduced.
  • the units included in the reference signal generation device 10 can be configured by software instead of being configured by hardware.

Abstract

[Problem] To provide a DDS that is configured by including many digital components and has improved resolution. [Solution] A DDS 52 is provided with an NCO 23, a ΔΣ modulation unit 28, and a BPF 29. The NCO 23 outputs a digital signal. The ΔΣ modulation unit 28 ΔΣ-modulates a signal based on the signal outputted by the NCO 23 (specifically, a sine wave signal converted by a sine wave conversion ROM 25, or a triangular wave signal converted by a triangular wave conversion circuit 26). The BPF 29 outputs the signal outputted by the ΔΣ modulation unit 28, as an analog signal. Unlike conventional D/A converters, the ΔΣ modulation unit 28 can be achieved using a digital circuit.

Description

ダイレクトデジタルシンセサイザ、基準信号発生装置、及び信号出力方法Direct digital synthesizer, reference signal generator, and signal output method
　本発明は、主要には、所定の周波数の信号を出力可能なダイレクトデジタルシンセサイザに関する。 The present invention mainly relates to a direct digital synthesizer capable of outputting a signal of a predetermined frequency.
　従来から、ＮＣＯ（数値制御発振器）と、ＲＯＭと、ＬＰＦ（ローパスフィルタ）と、を備えたＤＤＳ（ダイレクトデジタルシンセサイザ）が知られている。 Conventionally, a DDS (Direct Digital Synthesizer) including an NCO (Numerically Controlled Oscillator), a ROM, and an LPF (Low Pass Filter) is known.
　 ＮＣＯは、所定の周波数のノコギリ波を出力する。ＲＯＭは、ＮＣＯの出力値（ノコギリ波の位相）と、この出力値に対応付けて設定された正弦波の振幅と、を テーブルとして記憶している。ＲＯＭは、このテーブルに基づいて信号の変換を行うことにより、ノコギリ波を正弦波に変換することができる。そして、この正 弦波は、ＬＰＦにより高周波成分が取り除かれた後に出力される。 The NCO outputs a sawtooth wave with a predetermined frequency. The ROM stores the output value of the NCO (the phase of the sawtooth wave) and the amplitude of the sine wave set in association with this output value as a spear table. The ROM can convert a sawtooth wave into a sine wave by performing signal conversion based on this table. The sine wave is output after the high frequency component is removed by the LPF.
　特許文献１は、積算回路部と、乗算回路部と、誤差補正部 と、を備える。積算回路部は、上記ＮＣＯと同等の構成である。乗算回路部は、積算回路部が出力するノコギリ波に所定の演算を行うことにより、このノコギリ 波を放物線状の信号に変換する。誤差補正部は、予め記憶装置に記憶された正弦波の理想的な波形に基づいて、乗算回路部から得られた放物線状の信号を補正す る。これにより、正弦波を生成することができる。 Patent Document 1 includes an integration circuit unit, a multiplication circuit unit, and an error correction unit. The integrating circuit unit has the same configuration as the NCO. The multiplication circuit unit converts the sawtooth wave into a parabolic signal by performing a predetermined calculation on the sawtooth wave output from the integration circuit unit. The error correction unit corrects the parabolic signal obtained from the multiplication circuit unit based on the ideal waveform of the sine wave stored in advance in the storage device. Thereby, a sine wave can be generated.
　特許文献２及び３は、クロック発生回路を開示する。これらのクロック発生回路は、ＥＭＩ（電磁妨害）を低減するために、発生させるクロックを変調させる構成を開示する。特許文献２及び３では、この変調のために、三角波発振回路やΔΣ変調器等を用いる点が開示されている。 Patent Documents 2 and 3 disclose clock generation circuits. These clock generation circuits disclose a configuration for modulating a generated clock in order to reduce EMI (electromagnetic interference). Patent Documents 2 and 3 disclose that a triangular wave oscillation circuit, a ΔΣ modulator, or the like is used for this modulation.
特開２００５－４５６７４号公報JP 2005-45674 A 特開２０１１－１７６４１３号公報JP 2011-176413 A 特開２００５－２３６５３６号公報JP 2005-236536 A
　 ところで、上記のＤＤＳ等を備える基準信号発生装置は、例えば、携帯電話やＷｉＭＡＸ等の基地局に設置される。近年では、携帯電話等の通信データ量の増加 に対応するために、この基地局を多数設けることが行われている。従って、コンパクトかつ安価な構成の基準信号発生装置が求められている。 By the way, the reference signal generation device including the above-described DDS is installed in a base station such as a mobile phone or WiMAX. In recent years, many base stations have been provided in order to cope with an increase in the amount of communication data such as cellular phones. Therefore, there is a need for a reference signal generator having a compact and inexpensive configuration.
　 電子部品をコンパクトかつ安価にする方法として、例えば、必要な機能を半導体チップ上で実現する方法が考えられる。しかし、上記特許文献の構成は、チャー ジポンプ等のアナログ部品を多く含んでいる。アナログ部品で構成される部分をチップ化し、コンパクトな構成の実現をするには、設計や検証に時間が掛かり、 開発費用も高価になる等、実現が困難な場合が多い。 As a method for making electronic components compact and inexpensive, for example, a method for realizing necessary functions on a semiconductor chip is conceivable. However, the configuration of the above-mentioned patent document includes many analog parts such as a charge pump. In order to realize a compact configuration by making a part composed of analog parts into a chip, it is often difficult to realize such as it takes time for design and verification, and the cost of developing a kite is high.
　また、従来のＤＤＳでは、生成された信号はＤ／Ａコンバータによって アナログ信号に変換される。しかし、Ｄ／Ａコンバータをチップ化することは上述のように困難である。しかし、チップ化せずにＤ／Ａコンバータ機能を基板上 に実装する場合は、アナログ部品を多く含むこととなり、コンパクトな構成の実現の妨げとなっていた。更に、従来のＤ／Ａコンバータは、低ビットの場合は分 解能が低くなってしまい、高ビットの場合はコストが高くなるという点でも改善の余地があった。 Also, in the conventional DDS, the generated signal is converted into an analog signal by a D / A converter. However, as mentioned above, it is difficult to make a D / A converter into a chip. However, in the case where the D / A converter function is mounted on the board without being formed into a chip, many analog parts are included, which hinders the realization of a compact configuration. Furthermore, the conventional D / A converter has room for improvement in that the resolution of resolution is low when the bit is low and the cost is high when the bit is high.
　本発明は以上の事情に鑑みてされたものであり、その主要な目的は、多くのデジタル部品を含んで構成されるとともに分解能を向上させたＤＤＳを提供することにある。 The present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a DDS including a large number of digital parts and having improved resolution.
課題を解決するための手段及び効果Means and effects for solving the problems
　本発明の解決しようとする課題は以上の如くであり、次にこの課題を解決するための手段とその効果を説明する。 The problems to be solved by the present invention are as described above. Next, means for solving the problems and the effects thereof will be described.
　 本発明の第１の観点によれば、以下の構成のダイレクトデジタルシンセサイザが提供される。即ち、このダイレクトデジタルシンセサイザは、数値制御発振器 と、ΔΣ変調部と、フィルタ部と、を備える。前記数値制御発振器は、デジタル信号を出力する。前記ΔΣ変調部は、前記数値制御発振器が出力する信号又は当 該信号に基づく信号をΔΣ変調する。前記フィルタ部は、前記ΔΣ変調部がΔΣ変調した信号をアナログ信号として出力する。 According to the first aspect of the present invention, a direct digital synthesizer having the following configuration is provided. That is, the direct digital synthesizer includes a numerically controlled oscillator, a ΔΣ modulator, and a filter. The numerically controlled oscillator outputs a digital signal. The ΔΣ modulation unit ΔΣ modulates a signal output from the numerically controlled oscillator or a signal based on the signal. The filter unit outputs the signal that is ΔΣ modulated by the ΔΣ modulation unit as an analog signal.
　 これにより、ΔΣ変調部を備えることで、従来はアナログ部品で構成されていたＤ／Ａコンバータの大部分をデジタル回路で実現できる。従って、ＤＤＳの大部 分をチップ化してコンパクトな構成を実現することができる。また、ΔΣ変調を行うことによりノイズシェービング（詳細は後述）により量子化誤差を抑えるこ とができるので、Ｄ／Ａ変換後の信号の分解能を向上させることができる。 Thus, by providing the ΔΣ modulation unit, most of the D / A converters that have conventionally been configured with analog components can be realized with digital circuits. Therefore, it is possible to realize a compact configuration by making most of the DDS into a chip. Further, by performing ΔΣ modulation, it is possible to suppress quantization errors by noise shaving (details will be described later), so that the resolution of the signal after D / A conversion can be improved.
　前記のダイレクトデジタルシンセサイザにおいては、前記数値制御発振器から入力された信号の位相に応じた振幅の信号を出力することで、入力された信号を正弦波信号に変換する変換情報記憶部を備えることが好ましい。 The direct digital synthesizer may include a conversion information storage unit that converts an input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator. preferable.
　 これにより、ＤＤＳに一般的に採用される構成を活かしつつ、ＤＤＳのデジタル化を実現することができる。また、このＤＤＳを備えるＰＬＬ回路を作成した場 合、フィルタ部で正弦波信号を抽出する構成と異なり、フィルタ部の帯域幅を広くしても高調波が出力されないので、リファレンス信号に同期するまでの時間を 短くすることができる。 This makes it possible to realize DDS digitization while taking advantage of the configuration generally adopted for DDS. In addition, when a PLL circuit having this DDS is created, unlike the configuration in which a sine wave signal is extracted by the filter unit, harmonics are not output even if the bandwidth of the filter unit is widened. Can be shortened.
　前記のダイレクトデジタルシンセサイザにおいては、前記フィルタ部は、前記数値制御発振器が出力する信号又は当該信号に基づく信号から、一定範囲の周波数の信号を通過させることで、所定の周波数の正弦波信号を抽出することが好ましい。 In the direct digital synthesizer, the filter unit extracts a sine wave signal having a predetermined frequency by passing a signal in a predetermined range from a signal output from the numerically controlled oscillator or a signal based on the signal. It is preferable to do.
　 これにより、変換情報記憶部（ＲＯＭテーブル）が不要となるので、高容量のＲＯＭを用いることなく分解能を向上させることができる。従って、よりコンパク トかつ高分解能なＤＤＳが実現できる。また、通過させる周波数帯（通過領域）が異なるフィルタ部を使い分けることにより、基本波の整数倍の周波数の正弦波 を出力することができる。 This eliminates the need for a conversion information storage unit (ROM table), so that the resolution can be improved without using a high-capacity ROM. Therefore, a more compact and high resolution DDS can be realized. In addition, a sine wave having a frequency that is an integral multiple of the fundamental wave can be output by properly using filter units having different frequency bands (pass regions) to pass.
　前記のダイレクトデジタルシンセサイザにおいては、以下の構成とすることが好ましい。即ち、こ のダイレクトデジタルシンセサイザは、前記数値制御発振器から入力された信号の位相に応じた振幅の信号を出力することで、入力された信号を正弦波信号に変 換する変換情報記憶部を備える。前記変換情報記憶部が変換した正弦波信号、及び、前記フィルタ部が抽出した正弦波信号のうち、一方の信号が外部へ出力され る。 The direct digital synthesizer preferably has the following configuration. That is, this direct digital synthesizer includes a conversion information storage unit that converts an input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator. . One of the sine wave signal converted by the conversion information storage unit and the sine wave signal extracted by the filter unit is output to the outside.
　これにより、ユーザの要望や使用環境に適した方の信号を利用可能なＤＤＳが実現できる。 This makes it possible to realize a DDS that can use the signal suitable for the user's request and usage environment.
　 本発明の第２の観点によれば、以下の構成の基準信号発生装置が提供される。即ち、この基準信号発生装置は、前記ダイレクトデジタルシンセサイザと、制御部 と、出力部と、を備える。前記制御部は、前記数値制御発振器が出力した信号又はそれに基づく信号と、リファレンス信号と、の位相又は周波数を比較し、比較 結果に基づいて前記数値制御発振器を制御する。前記出力部は、前記ダイレクトデジタルシンセサイザが出力する信号又は当該信号に基づく信号を基準信号とし て出力する。 According to a second aspect of the present invention, a reference signal generator having the following configuration is provided. That is, the reference signal generator includes the direct digital synthesizer, a control unit, and an output unit. The control unit compares the phase or frequency of a signal output from the numerically controlled oscillator or a signal based thereon with a reference signal, and controls the numerically controlled oscillator based on a comparison result. The output unit outputs a signal output from the direct digital synthesizer or a signal based on the signal as a reference signal.
　これにより、デジタル部品の割合が多く、コンパクトな構成が実現可能な基準信号発生装置が実現できる。 This makes it possible to realize a reference signal generator that has a large proportion of digital components and can realize a compact configuration.
　前記の基準信号発生装置においては、適切な前記リファレンス信号を利用できないと判断したときに、前記基準信号を生成するための自走用制御信号を生成する自走制御部を備えることが好ましい。 Preferably, the reference signal generator includes a self-running control unit that generates a self-running control signal for generating the reference signal when it is determined that the appropriate reference signal cannot be used.
　これにより、障害物や妨害電波等により適切なリファレンス信号が利用できなくなった場合であっても、高精度な基準信号を出力し続けることができる。 Thus, even when an appropriate reference signal cannot be used due to an obstacle or jamming radio wave, it is possible to continue outputting a highly accurate reference signal.
　前記の基準信号発生装置においては、少なくとも前記数値制御発振器の消費電力を低減させる制御を行う電力制御部を備えることが好ましい。 The reference signal generator preferably includes at least a power control unit that performs control to reduce power consumption of the numerically controlled oscillator.
　これにより、数値制御発振器を利用しないときは、クロックを停止したり、供給する電圧を低減又はゼロにしたりすることで、基準信号発生装置の消費電力を低減することができる。 Thus, when the numerically controlled oscillator is not used, the power consumption of the reference signal generator can be reduced by stopping the clock, reducing the supplied voltage, or making it zero.
　 前記の基準信号発生装置においては、以下の構成とすることが好ましい。即ち、この基準信号発生装置は、ＧＮＳＳ衛星からの電波に基づいて、位置情報を取得 するＧＮＳＳ受信部を備える。前記ダイレクトデジタルシンセサイザ及び前記制御部を含み、基準信号を発生させる部分を信号発生部と称したときに、前記電力 制御部は、当該信号発生部の消費電力を低減させる制御を行う。 The reference signal generator described above preferably has the following configuration. That is, the reference signal generator includes a GNSS receiver that acquires position information based on radio waves from a GNSS satellite. When the portion that includes the direct digital synthesizer and the control unit and generates the reference signal is referred to as a signal generation unit, the power supply control unit performs control to reduce the power consumption of the signal generation unit.
　これにより、ＧＮＳＳ部が出力する位置情報のみが必要であって基準信号の出力が不要な場合は、信号発生部の消費電力を低減することで、基準信号発生装置の消費電力を大幅に低減することができる。 As a result, when only the position information output by the GNSS unit is necessary and the output of the reference signal is not necessary, the power consumption of the reference signal generator is greatly reduced by reducing the power consumption of the signal generator. be able to.
　 前記の基準信号発生装置においては、以下の構成とすることが好ましい。即ち、この基準信号発生装置は、ＧＮＳＳアンテナと、ＧＮＳＳ受信部と、を備える。 前記ＧＮＳＳアンテナは、前記制御部と同じ基板に取り付けられ、ＧＮＳＳ衛星からの測位信号を受信する。前記ＧＮＳＳ受信部は、前記制御部と同じ基板に取 り付けられ、前記ＧＮＳＳアンテナが受信した測位信号に基づいてリファレンス信号を生成する。 The reference signal generator described above preferably has the following configuration. That is, the reference signal generator includes a GNSS antenna and a GNSS receiver. The GNSS antenna is attached to the same board as the control unit, and receives a positioning signal from a GNSS satellite. The GNSS receiving unit is attached to the same substrate as the control unit, and generates a reference signal based on a positioning signal received by the GNSS antenna.
　これにより、ＧＮＳＳアンテナと基板とを接続するケーブルを配設する必要がなくなるため、基準信号発生装置の設置コストを低減することができる。 This eliminates the need to provide a cable for connecting the GNSS antenna and the substrate, thereby reducing the installation cost of the reference signal generator.
　 本発明の第３の観点によれば、以下の信号出力方法が提供される。即ち、この信号出力方法は、デジタル信号出力工程と、変調工程と、アナログ信号出力工程 と、を含む。前記デジタル信号出力工程では、数値制御発振器によりデジタル信号を出力する。前記変調工程では、前記デジタル信号出力工程で出力された信号 をΔΣ変調する。前記アナログ信号出力工程では、フィルタ処理を行うことにより、前記変調工程で出力された信号をアナログ信号として出力する。 According to the third aspect of the present invention, the following signal output method is provided. That is, this signal output method includes a digital signal output step, a modulation step, and an analog signal output step IV. In the digital signal output step, a digital signal is output by a numerically controlled oscillator. In the modulation step, the signal 出力 output in the digital signal output step is ΔΣ modulated. In the analog signal output step, the signal output in the modulation step is output as an analog signal by performing filter processing.
　 これにより、ΔΣ変調を行うΔΣ変調部を備えることで、従来はアナログ部品で構成されていたＤ／Ａコンバータの大部分をデジタル回路で実現できる。従っ て、ＤＤＳの大部分をチップ化してコンパクトな構成を実現することができる。また、ΔΣ変調部を備えることで、Ｄ／Ａ変換後の信号の分解能を向上させるこ とができる。 Thus, by including a ΔΣ modulation unit that performs ΔΣ modulation, most of the D / A converters conventionally configured with analog components can be realized with digital circuits. Therefore, most of the DDS can be made into chips and a compact configuration can be realized. In addition, by providing the ΔΣ modulator, it is possible to improve the resolution of the signal after D / A conversion.
本発明の一実施形態に係る基準信号発生装置の構成を示すブロック図。The block diagram which shows the structure of the reference signal generator which concerns on one Embodiment of this invention. ノコギリ波から三角波へ変換される仕組みを説明する図。The figure explaining the mechanism converted from a sawtooth wave to a triangular wave. ΔΣ変調部の構成を示すブロック図。The block diagram which shows the structure of a delta-sigma modulation part. ＮＣＯが出力する信号を直接的に分周部に入力可能な構成を備えた基準信号発生装置のブロック図。The block diagram of the reference signal generator provided with the structure which can directly input the signal which NCO outputs into a frequency-dividing part. 自走制御が可能な構成を備えた基準信号発生装置のブロック図。The block diagram of the reference signal generator provided with the structure in which self-running control is possible. 信号発生部への電源を調整可能な構成を備えた基準信号発生装置のブロック図。The block diagram of the reference signal generator provided with the structure which can adjust the power supply to a signal generation part. 信号発生部で使用されるクロックを調整可能な構成を備えた基準信号発生装置のブロック図。The block diagram of the reference signal generator provided with the structure which can adjust the clock used by a signal generation part.
　次に発明の実施の形態について説明する。図１は、本発明の一実施形態に係る基準信号発生装置１０の構成を示すブロック図である。 Next, embodiments of the invention will be described. FIG. 1 is a block diagram showing a configuration of a reference signal generator 10 according to an embodiment of the present invention.
　 基準信号発生装置１０は、接続されるユーザ側の機器に基準信号等を提供するためのものである。基準信号発生装置１０が基準信号を供給する対象としては、例 えば、携帯電話の基地局、地上デジタル放送の送信局及びＷｉＭＡＸ（Ｗｏｒｌｄｗｉｄｅ　Ｉｎｔｅｒｏｐｅｒａｂｉｌｉｔｙ　ｆｏｒ　Ｍｉｃｒｏｗａｖｅ 　Ａｃｃｅｓｓ）通信設備等がある。 The reference signal generator 10 is for providing a reference signal and the like to the connected user equipment. Examples of the reference signal generator 10 to which the reference signal is supplied include a mobile phone base station, a terrestrial digital broadcast transmitter, and a WiMAX (Worldwide Interoperability for Microwave Access) communication facility.
　本実施形態の基準信号発生装置１０は、ＧＰＳ受信部２１と、ＰＬＬ（Ｐｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ）回路５１と、ＤＤＳ（ダイレクトデジタルシンセサイザ）５２と、を主要な構成として備えている。 The reference signal generator 10 of the present embodiment includes a GPS receiving unit 21, a PLL (Phase Locked Loop) circuit 51, and a DDS (Direct Digital Synthesizer) 52 as main components.
　 基準信号発生装置１０の信号入力部４１には、ＧＰＳアンテナ（ＧＮＳＳアンテナ）１１が接続されている。ＧＰＳアンテナ１１がＧＰＳ衛星（ＧＮＳＳ衛星） から受信した測位用信号は、この信号入力部４１を介して、ＧＰＳ受信部２１へ入力される。ＧＰＳ受信部２１は、この測位用信号に基づいて測位計算を行うこ とで、リファレンス信号（１秒に１回のパルス信号）を生成する。このリファレンス信号は、協定世界時（ＵＴＣ）の１秒に正確に同期するように適宜較正され ている。 A GPS antenna (GNSS antenna) 11 is connected to the signal input unit 41 of the reference signal generator 10. A positioning signal received by the GPS antenna 11 from a GPS satellite (GNSS satellite) 入 力 is input to the GPS receiving unit 21 via the signal input unit 41. The GPS receiving unit 21 generates a reference signal (one pulse signal per second) by performing positioning calculation based on the positioning signal. This reference signal is appropriately calibrated to be accurately synchronized to 1 second of Coordinated Universal Time (UTC).
　次に、ＰＬＬ回路５１について説明する。ＰＬＬ回路５１は、図１に示すように、制御部２２と、ＮＣＯ（数値制御 発振器）２３と、分周部２４と、で構成されている。このＰＬＬ回路５１では、ＧＰＳ受信部２１が出力したリファレンス信号と、ＮＣＯ２３が出力した信号を 分周した信号と、の位相比較を行い、当該比較結果に基づいてＮＣＯ２３が出力する信号の周波数が調整される。以下、ＰＬＬ回路５１を構成する各機器につい て詳細に説明する。 Next, the PLL circuit 51 will be described. As shown in FIG. 1, the PLL circuit 51 includes a control unit 22, an NCO (numerically controlled oscillator) 23, and a frequency dividing unit 24. In this PLL circuit 51, a phase comparison is performed between the reference signal output from the GPS receiving unit 21 and a signal obtained by dividing the signal output from the NCO 23, and the frequency of the signal output from the NCO 23 is adjusted based on the comparison result. Is done. Hereinafter, each device constituting the PLL circuit 51 will be described in detail.
　制御部２２には、前記リファレンス信号と、ＮＣＯ２３が出力した信号を分周した信号と、が入力され る。制御部２２は、これらの信号の位相を比較して位相差を求め、その位相差に基づく信号（位相差信号、周波数制御量）を生成する。制御部２２は、この周波 数制御量の高周波成分の遮断及び雑音の除去を行った後に、周波数制御量をＮＣＯ２３へ出力する。なお、制御部２２は、両信号の比較結果を出力する構成であ れば良く、信号の処理方法は任意である。 The control unit 22 receives the reference signal and a signal obtained by dividing the signal output from the NCO 23. The control unit 22 compares the phases of these signals to obtain a phase difference, and generates a signal (phase difference signal, frequency control amount) based on the phase difference. The control unit 22 outputs the frequency control amount to the NCO 23 after blocking the high frequency component of the frequency power control amount and removing noise. The control unit 22 may be configured to output a comparison result of both signals, and the signal processing method is arbitrary.
　ＮＣＯ２３は、基準信号の基となる信号を出力するためのデジタル制御発振器であ る。ＮＣＯ２３は、図略のレジスタと加算器とを備えている。ＮＣＯ２３は、加算器及びレジスタにより、出力値が徐々に増大するとともに、所定の周期で出力 値が０に戻る信号（ノコギリ波、図２（ｂ）を参照）を出力する。なお、以下の説明ではＮＣＯ２３の出力値を、その周期的な変化に着目して、特に「ノコギリ 波の位相」と呼ぶことがある。 The NCO 23 is a digitally controlled oscillator for outputting a signal that is the basis of a reference signal. The NCO 23 includes an unillustrated register and an adder. The NCO 23 outputs a signal (sawtooth wave, see FIG. 2B) in which the output value gradually increases and the output threshold value returns to 0 in a predetermined cycle by the adder and the register. In the following description, the output value of the NCO 23 may be particularly referred to as “the phase of the sawtooth wave” by paying attention to the periodic change.
　また、ＮＣＯ２３には、制御部２２から周波数制御量が入力されている。ＮＣＯ２３は、この 周波数制御量に基づいて、リファレンス信号と、ＮＣＯ２３が出力する信号を分周した信号と、の間の位相差を無くすようにノコギリ波を生成する。ノコギリ波 は、ＤＤＳ５２が備える各部によって適宜変換された後に、分周部２４へ出力される。 Further, a frequency control amount is input to the NCO 23 from the control unit 22. The NCO 23 generates a sawtooth wave so as to eliminate a phase difference between the reference signal and a signal obtained by dividing the signal output from the NCO 23 based on the frequency control amount. The sawtooth wave is appropriately converted by each unit included in the DDS 52 and then output to the frequency dividing unit 24.
　分周部２４は、ＤＤＳ５２から出力さ れた信号を分周して高い周波数から低い周波数に変換し、得られた信号（位相比較用信号）を制御部２２へ出力するように構成されている。例えば、基準周波数 信号が１０ＭＨｚである場合、分周部２４は、この１０ＭＨｚの信号を分周比１／１０００００００で分周して、１Ｈｚの位相比較用信号を生成する。そして、 この位相比較用信号は、基準タイミング信号として出力部４４から外部のユーザ側のシステムへと出力される。 The frequency divider 24 divides the signal output from the DDS 52 and converts it from a high frequency to a low frequency, and outputs the obtained signal (phase comparison signal) to the control unit 22. . For example, when the reference frequency signal is 10 MHz, the frequency divider 24 divides the 10 MHz signal by a frequency division ratio of 1 / 10,000,000 to generate a 1 Hz phase comparison signal. The phase comparison signal is output from the output unit 44 to the external user system as a reference timing signal.
　以上に説明し た構成によって、ＰＬＬ回路５１のループが構成される。例えば、経時変化や周囲の温度変化及び電源電圧等に起因して、ＮＣＯ２３の加算器が積算を行うタイ ミングが変わってしまったとする。この場合、ＮＣＯ２３の出力するノコギリ波の位相が変化し、安定した基準信号が出力できなくなる。しかしながら、ＰＬＬ 回路５１は、ＧＰＳ受信部２１から入力される正確な１ＰＰＳ信号に基づいて、ノコギリ波の位相のズレがなくなるようにＮＣＯ２３をデジタル制御している。 従って、上記のように加算器が積算を行うタイミングが変わった場合であっても、基準信号発生装置１０のから出力される基準信号を高精度に保つことができ る。 A loop of the PLL circuit 51 is configured by the configuration described above. For example, it is assumed that the timing at which the adder of the NCO 23 performs integration has changed due to changes over time, ambient temperature changes, power supply voltage, and the like. In this case, the phase of the sawtooth wave output from the NCO 23 changes, and a stable reference signal cannot be output. However, the PLL loop circuit 51 digitally controls the NCO 23 based on the accurate 1PPS signal input from the GPS receiver 21 so that the phase shift of the sawtooth wave is eliminated. Therefore, even when the timing at which the adder performs integration changes as described above, the reference signal output from the reference signal generator 10 can be maintained with high accuracy.
　次に、ＤＤＳ５２について説明する。ＤＤＳ５２は、図１に示すように、ＮＣＯ２３と、正弦波変換ＲＯＭ（変換情報記 憶部）２５と、三角波変換回路２６と、選択部２７と、ΔΣ変調部２８と、ＢＰＦ（バンドパスフィルタ、フィルタ部）２９と、から構成されている。なお、 フィルタ部としては、ＢＰＦに代えてＬＰＦ（ローパスフィルタ）を利用することもできる。 Next, the DDS 52 will be described. As shown in FIG. 1, the DDS 52 includes an NCO 23, a sine wave conversion ROM (conversion information storage unit) 25, a triangular wave conversion circuit 26, a selection unit 27, a ΔΣ modulation unit 28, and a BPF (bandpass filter, Filter section) 29. In addition, as a soot filter part, it can replace with BPF and can also use LPF (low-pass filter).
　正弦波変換ＲＯＭ２５は、 ＮＣＯ２３の出力値（ノコギリ波の位相）と、この出力値に対応付けて設定された正弦波の振幅と、をテーブルとして記憶している。正弦波変換ＲＯＭ２５は、 このテーブルに基づいて信号の変換を行うことにより、ノコギリ波を正弦波に変換することができる。正弦波変換ＲＯＭ２５が変換した信号は、選択部２７へ出 力される。 The sine wave conversion ROM 25 stores the output value (sawtooth phase) of the NCO 23 and the amplitude of the sine wave set in association with this output value as a table. The sine wave conversion ROM 25 can convert a sawtooth wave into a sine wave by performing signal conversion based on this table. The signal converted by the sine wave conversion ROM 25 is output to the selection unit 27.
　三角波変換回路２６は、ＮＣＯ２３が生成したノコギリ波の後半の半周期分を反転させることにより、ノコギリ波 を三角波に変換する回路である。以下、図２を参照して、この三角波変換回路２６について具体的に説明する。図２（ａ）に示す表の「変換前」の列には、 ＮＣＯ２３が出力するノコギリ波の位相の変化が３ビットの２進数で記されている。この表に示すように、ノコギリ波は出力値を１ずつ増加させる波形を示すこ とが分かる（図２（ｂ）の左側のグラフを参照）。三角波変換回路２６は、ノコギリ波の前半部分（ｄ１～ｄ４）に対して「０００」との排他的論理和をとるよ うに構成されるとともに、このノコギリ波の後半部分（ｄ５～ｄ８）に対して「１１１」との排他的論理和をとるように構成された論理回路である。排他的論理 和をとることにより、図２（ａ）の右側の「変換後」の列に記されているように、後半部分の出力値がビット反転する。以上のようにして、前半部分 （ｄ１～ｄ４）は徐々に出力値が大きくなり、後半部分（ｄ５～ｄ８）は徐々に出力値が小さくなる三角波信号を得ることができる（図２（ｂ）の右側のグラフ を参照）。三角波変換回路２６が出力した三角波信号は、選択部２７へ出力される。 The triangular wave conversion circuit 26 is a circuit that converts a sawtooth wave into a triangular wave by inverting the latter half of the sawtooth wave generated by the NCO 23. Hereinafter, the triangular wave conversion circuit 26 will be described in detail with reference to FIG. In the column “before conversion” of the table shown in FIG. 2A, the phase change of the sawtooth wave output from the NCO 23 is described in a 3-bit binary number. As shown in this table, it can be seen that the sawtooth wave shows a waveform that increases the output value by 1 (see the graph on the left side of FIG. 2B). The triangular wave conversion circuit 26 is configured to obtain an exclusive OR with “000” with respect to the first half part (d1 to d4) of the sawtooth wave and to the second half part (d5 to d8) of the sawtooth wave. The logic circuit is configured to take an exclusive OR with “111”. By taking the exclusive logical sum, the output value of the latter half is bit-inverted as described in the column “After Conversion” on the right side of FIG. As described above, a triangular wave signal can be obtained in which the output value of the first half portion (d1 to d4) gradually increases and the output value of the second half portion (d5 to d8) gradually decreases (FIG. 2B). (See graph on the right side of). The triangular wave signal output from the triangular wave conversion circuit 26 is output to the selection unit 27.
　選択部２７は、正弦波変換ＲＯＭ２５が出力した正弦波信号、及び、三角波変換回路２６が出力した三角波信号のうち何れか一方をΔΣ変調部２８へ出力する。選択部２７が出力する信号は、初期設定又はユーザの操作等により決定される。 The selection unit 27 outputs either the sine wave signal output from the sine wave conversion ROM 25 or the triangular wave signal output from the triangular wave conversion circuit 26 to the ΔΣ modulation unit 28. The signal output from the selection unit 27 is determined by initial setting or user operation.
　ΔΣ変調部２８は、選択部２７が出力した信号を変調する。ΔΣ変調部２８は、図３に示すように、減算部（微分器）６１と、加算部（積分器）６２と、記憶部６３と、量子化部６４と、を備えている。 The ΔΣ modulation unit 28 modulates the signal output from the selection unit 27. As shown in FIG. 3, the ΔΣ modulation unit 28 includes a subtraction unit (differentiator) 61, an addition unit (integrator) 62, a storage unit 63, and a quantization unit 64.
　 加算部６２及び記憶部６３は、入力される信号を積分して量子化部６４へ出力する。量子化部６４は、加算部６２の出力を量子化して、所定時間だけ遅延させた 後に、量子化した信号を減算部６１へ出力する。減算部６１は、入力信号から、この量子化された信号を減算して、加算部６２へ出力する。 The adder 62 and the storage 63 integrate the input signal and output it to the quantizer 64. The quantizing unit 64 quantizes the output of the adding unit 62 and delays the output by a predetermined time, and then outputs the quantized signal to the subtracting unit 61. The subtractor 61 subtracts the quantized signal from the input signal and outputs the result to the adder 62.
　 このように、量子化雑音を含む量子化された入力信号をフィードバックすることにより、量子化部６４では、量子化雑音の低周波成分を抑えることができる（ノ イズシェービング）。そのため、量子化部６４のビット数を高くすることなく高い分解能を実現することができる。従って、従来の多ビットのＤ／Ａコンバータ よりも部品コストを低減することができる。なお、ΔΣ変調部２８は、図３に示したような一次のΔΣ変調部であっても良いし、２次以上としたΔΣ変調部で あっても良い。 As described above, by feeding back the quantized input signal including the quantization noise, the quantization unit 64 can suppress the low frequency component of the quantization noise (noise shaving). Therefore, high resolution can be realized without increasing the number of bits of the quantization unit 64. Therefore, the component cost can be reduced as compared with the conventional multi-bit D / A converter. The ΔΣ modulation unit 28 may be a primary ΔΣ modulation unit as shown in FIG. 3 or may be a secondary or higher-order ΔΣ modulation unit.
　また、ΔΣ変調部２８は、デジタル回路で構成することができる。従って、本実施形態のＤＤＳ５２は、大部 分（ＮＣＯ２３からΔΣ変調部２８まで）がデジタル部品で構成されるため、これらの機能を半導体チップ上で容易に実現することができる。従って、コンパク トかつ安価な構成が実現できる。 Further, the ΔΣ modulator 28 can be configured by a digital circuit. Accordingly, the DDS 52 according to the present embodiment is largely composed of digital components (from the NCO 23 to the ΔΣ modulation unit 28), so that these functions can be easily realized on the semiconductor chip. Therefore, a compact and inexpensive configuration can be realized.
　ＢＰＦ２９は、所定の周波数帯（通過帯域）の信号のみを通過させ、それ以外の周波数の信 号を通過させない構成のアナログフィルタである。このフィルタを通過させることにより、ΔΣ変調部２８の出力する信号をアナログ信号として出力することが できる。また、正弦波変換ＲＯＭ２５が変換した正弦波信号がＢＰＦ２９を通過することで、当該信号の高周波成分等が除去される。一方、三角波変換回路２６ が変換した三角波信号がＢＰＦ２９を通過することで、三角波は正弦波とその奇数倍音を重ね合わせた波であるため、所定の周波数の正弦波信号が抽出される。 The BPF 29 is an analog filter configured to pass only signals in a predetermined frequency band (pass band) and not pass signals of other frequencies. By passing this filter, the signal output from the ΔΣ modulator 28 can be output as an analog signal. In addition, when the sine wave signal converted by the sine wave conversion ROM 25 passes through the BPF 29, a high frequency component or the like of the signal is removed. On the other hand, since the triangular wave signal converted by the triangular wave conversion circuit 26 を passes through the BPF 29, the triangular wave is a wave obtained by superimposing the sine wave and its odd overtone, and thus a sine wave signal having a predetermined frequency is extracted.
　以上のようにして生成された正弦波信号は、正弦波の基準周波数信号として出力部４２から外部のユーザ側のシステムへと出力される。また、この正弦波信号は、ハードリミッタ３１によって矩形波信号に変換される。 The sine wave signal generated as described above is output from the output unit 42 to an external user side system as a sine wave reference frequency signal. The sine wave signal is converted into a rectangular wave signal by the hard limiter 31.
　 ハードリミッタ３１によって変換された信号は、矩形波の基準周波数信号として、出力部４３から外部のユーザ側のシステムへと出力される。また、この矩形波 信号は、上述の分周部２４へ出力される。分周部２４は、上述のように、この矩形波信号を分周することで、比較用信号を生成する。 The signal converted by the hard limiter 31 is output from the output unit 43 to the external user system as a rectangular reference frequency signal. The rectangular wave signal is output to the frequency divider 24 described above. As described above, the frequency divider 24 divides the rectangular wave signal to generate a comparison signal.
　次に、正弦波変換ＲＯＭ２５を利用して正弦波信号を出力する場合と、三角波変換回路２６を利用して正弦波信号出力する場合と、の違いについて説明する。 Next, a difference between a case where a sine wave signal is output using the sine wave conversion ROM 25 and a case where a sine wave signal is output using the triangular wave conversion circuit 26 will be described.
　 正弦波変換ＲＯＭ２５を利用して正弦波信号を出力する場合、ＢＰＦ２９の帯域幅をある程度広くしても、除去される周波数の範囲が変化するだけであり、さほ ど問題は生じない。従って、ＢＰＦ２９の帯域幅を広くしてＮＣＯ２３の周波数制御範囲を広くすることで、リファレンス信号に同期するまでの時間を短くする ことができる。 When a sine wave signal is output using the sine wave conversion ROM 25, even if the bandwidth of the BPF 29 is widened to some extent, only the range of the frequency to be removed changes, so that there is almost no problem. Therefore, by widening the bandwidth of the BPF 29 and widening the frequency control range of the NCO 23, the time until synchronization with the reference signal can be shortened.
　これに対し、三角波変換回路２６を利用して正弦波信号出力する場合、ＢＰＦ２９の帯域幅を広くしてしまう と、抽出対象の正弦波だけでなく、その高調波も抽出されてしまう。従って、ＢＰＦ２９の帯域幅を狭くせざるを得ないため、リファレンス信号に同期するまで の時間が長くなってしまう。 On the other hand, when the sine wave signal is output using the triangular wave conversion circuit 26, not only the sine wave to be extracted but also its harmonics are extracted when the bandwidth of the BPF 29 is widened. Therefore, since the bandwidth of the BPF 29 must be narrowed, the time required for the trap is long until the BPF 29 is synchronized with the reference signal.
　つまり、リファレンス信号に同期するまでの早さという観点では、正弦波変換ＲＯＭ２５を利用した方が優れている。 That is, it is better to use the sine wave conversion ROM 25 from the viewpoint of speed of synchronization with the reference signal.
　 また、正弦波変換ＲＯＭ２５を利用して正弦波信号を出力する場合、ＮＣＯ２３の性能を十分に発揮させるためには、ノコギリ波の位相と正弦波の変位との対応 関係を正弦波変換ＲＯＭ２５に多数記憶させる必要がある。従って、分解能を向上させるためには、記憶容量の大きなＲＯＭが必要となるので、回路規模が大き くなり、装置の小型化の妨げとなってしまう。 Further, when the sine wave conversion ROM 25 is used to output a sine wave signal, the sine wave conversion ROM 25 has many correspondence relations between the phase of the sawtooth wave and the displacement of the sine wave in order to exhibit the performance of the NCO 23 sufficiently. It is necessary to memorize. Therefore, in order to improve the resolution, a ROM having a large storage capacity is required, which increases the circuit scale and hinders downsizing of the apparatus.
　これに対し、三角波変換回路２６を利用して正弦波信号を出力する場合、上記のＲＯＭを必要とせずに正弦波信号を生成することができる。従って、装置の小型化を実現しつつ、高い分解能を達成することができる。 On the other hand, when a sine wave signal is output using the triangular wave conversion circuit 26, the sine wave signal can be generated without requiring the ROM. Therefore, high resolution can be achieved while realizing miniaturization of the apparatus.
　つまり、分解能の高さ及び装置の小型化という観点では、三角波変換回路２６を利用した方が優れている。 In other words, it is better to use the triangular wave conversion circuit 26 from the viewpoint of high resolution and downsizing of the apparatus.
　 本実施形態では、正弦波変換ＲＯＭ２５及び三角波変換回路２６の何れを利用するかを選択部２７により選択可能であるため、リファレンス信号に同期するまで の早さを重視する場合は正弦波変換ＲＯＭ２５を利用し、分解能の高さ及び装置の小型化を重視する場合は三角波変換回路２６を利用するといった態様で基準信 号発生装置１０を使用できる。 In this embodiment, since the selection unit 27 can select which of the sine wave conversion ROM 25 and the triangular wave conversion circuit 26 is used, the sine wave conversion ROM 25 is used when importance is attached to the speed of wrinkles until synchronization with the reference signal. When the high resolution and the downsizing of the apparatus are emphasized, the reference signal generating apparatus 10 can be used in such a manner that the triangular wave conversion circuit 26 is used.
　なお、上記の構成はＢＰＦ２９を通過させること等により、ジッタを除去することができる。しかし、ジッタを問題としない場合は、図４のように構成しても良い、図４は、ＮＣＯ２３の出力先として調整部３７と選択部３８とを備える。 Note that the above configuration can remove jitter by allowing the BPF 29 to pass through. However, when jitter is not a problem, the configuration may be as shown in FIG. 4, which includes an adjustment unit 37 and a selection unit 38 as an output destination of the NCO 23.
　 調整部３７は、ＮＣＯの出力のうちＭＳＢ（Ｍｏｓｔ　Ｓｉｇｎｉｆｉｃａｎｔ　Ｂｉｔ）等を抽出し、ＮＣＯ２３の出力を２値化する。選択部３８には、調整 部３７から入力された信号と、ハードリミッタ３１から入力された信号と、が入力される。選択部３８は、入力された信号のうち何れか一方を分周部２４へ出力 する。選択部２７が出力する信号は、初期設定又はユーザの操作等により決定される。 The adjustment unit 37 extracts MSB (Most Significant Bit) and the like from the output of the NCO, and binarizes the output of the NCO 23. The selection unit 38 receives the signal input from the adjustment rod unit 37 and the signal input from the hard limiter 31. The selection unit 38 outputs any one of the input signals to the frequency division unit 24. The signal output from the selection unit 27 is determined by initial setting or user operation.
　選択部３８によって選択部２７が出力 する信号が選択された場合、この信号はＢＰＦ２９を経由しないため、周波数制御範囲を広くすることができる。従って、リファレンス信号に同期するまでの早 さをより向上させることができる。一方で、調整部３７はＮＣＯ２３が出力するデジタル信号を２値化しているため、量子化誤差が大きくなってしまい、分解能 が低下してしまう。 When the signal output from the selection unit 27 is selected by the selection unit 38, this signal does not pass through the BPF 29, so that the frequency control range can be widened. Therefore, it is possible to further improve the speed until synchronization with the reference signal. On the other hand, since the adjustment unit 37 binarizes the digital signal output from the NCO 23, the quantization error increases and the resolution decreases.
　次に、基準信号発生装置１０の変形例について説明する。なお、以下に説明する変形例においては、上記実施形態と同一又は類似するものには同一の符号を付し、その説明を省略する。 Next, a modification of the reference signal generator 10 will be described. In addition, in the modified example demonstrated below, the same code | symbol is attached | subjected to the same or similar thing as the said embodiment, and the description is abbreviate | omitted.
　 本変形例の基準信号発生装置１０は、落雷や妨害電波等によってリファレンス信号を取得できなくなった場合であっても、所定の精度を維持しながら基準信号を 送信する機能を有している。基準信号発生装置１０は、この機能を実現するための構成として、自走制御部３３と、自走選択部３４と、を備えている。 The reference signal generator 10 according to the present modification has a function of transmitting the reference signal while maintaining a predetermined accuracy even when the reference signal cannot be acquired due to a lightning strike or interference radio wave. The reference signal generation device 10 includes a self-running control unit 33 and a self-running selection unit 34 as a configuration for realizing this function.
　 本変形例では、選択部２７には、自走選択部３４、正弦波変換ＲＯＭ２５、及び三角波変換回路２６が出力した信号が入力されている。変形例の基準信号発生装 置１０は、ΔΣ変調部２８の後段にＶＣＸＯ等を配置することもできるし、ＮＣＯ２３等を発振器として利用することもできる。ＶＣＸＯ等が配置される場合、 選択部２７は、自走選択部３４が出力した信号をΔΣ変調部２８へ出力する。一方、ＮＣＯ２３等を発振器として利用する場合、選択部２７は、正弦波変換 ＲＯＭ２５又は三角波変換回路２６が出力した信号をΔΣ変調部２８へ出力する。 In this modification, the signals output from the free-running selection unit 34, the sine wave conversion ROM 25, and the triangular wave conversion circuit 26 are input to the selection unit 27. In the reference signal generating apparatus 10 according to the modification, a VCXO or the like can be arranged after the ΔΣ modulator 28, or the NCO 23 or the like can be used as an oscillator. When VCXO or the like is arranged, heel selection unit 27 outputs the signal output from free-running selection unit 34 to ΔΣ modulation unit 28. On the other hand, when the NCO 23 or the like is used as an oscillator, the selection unit 27 outputs the signal output from the sine wave conversion ROM 25 or the triangular wave conversion circuit 26 to the ΔΣ modulation unit 28.
　自走制御部３３には、制御部２２が出力す る周波数制御量が入力される。自走制御部３３は、同期状態である場合は、図略の温度センサが検出した温度と、上記のＶＣＸＯが出力した信号の周波数と、の 対応関係を記憶する。なお、この対応関係は、製品の出荷前に求めても良いし、製品の出荷前に求めた値を修正して使用しても良い。また、自走制御部３３は、 温度センサが検出した現在の温度と、上記で求めた温度特性と、を考慮して、周波数制御量を補正する。 The self-running control unit 33 receives the frequency control amount output from the control unit 22. When the self-running control unit 33 is in a synchronized state, the self-running control unit 33 stores a correspondence relationship between the temperature detected by a temperature sensor (not shown) and the frequency of the signal output from the VCXO. This correspondence may be obtained before the product is shipped, or the value obtained before the product is shipped may be used after being corrected. Further, the self-running control unit 33 corrects the frequency control amount in consideration of the current temperature detected by the soot temperature sensor and the temperature characteristic obtained above.
　自走選択部３４に は、制御部２２が出力した周波数制御量と、自走制御部３３が補正した周波数制御量と、が入力される。自走選択部３４は、適切なリファレンス信号が利用でき るときは、制御部２２の周波数制御量を出力し、適切なリファレンス信号が利用できないときは、自走制御部３３の周波数制御量を出力する。 The self-running selection unit 34 receives the frequency control amount output by the control unit 22 and the frequency control amount corrected by the self-running control unit 33. The self-running selection unit 34 outputs the frequency control amount of the control unit 22 when an appropriate reference signal is available, and outputs the frequency control amount of the self-running control unit 33 when an appropriate reference signal is not available. To do.
　 自走制御部３３が出力する周波数制御量は、環境の変化（具体的には温度の変化）を考慮して定められているので、自走状態において環境が変化した場合であっ ても、高精度な基準信号を出力し続けることができる。また、ΔΣ変調部２８の後段に配置される発振器として周波数安定度の高いＯＣＸＯを用いることで、長 い時間高い周波数安定度を維持することができる。 The frequency control amount output by the self-running control unit 33 is determined in consideration of environmental changes (specifically, temperature changes). An accurate reference signal can be continuously output. Further, by using an OCXO having a high frequency stability as an oscillator arranged at the subsequent stage of the ΔΣ modulation unit 28, it is possible to maintain a high frequency stability for a long time.
　なお、ΔΣ変調部２８の後段にＶＣＸＯ等が配置されない構成は、上記実施形態の構成と同様なので、説明を省略する。この構成は、ＶＣＸＯ等を配置しないことにより、ＶＣＸＯ等を配置する構成と比較して、コストを削減することができる。 Note that the configuration in which the VCXO or the like is not arranged in the subsequent stage of the ΔΣ modulation unit 28 is the same as the configuration of the above-described embodiment, and thus description thereof is omitted. In this configuration, by not arranging the VCXO or the like, the cost can be reduced as compared with the configuration in which the VCXO or the like is arranged.
　次に、基準信号発生装置１０で消費電力を低減させる制御を行う変形例について説明する。なお、本明細書において、「消費電力を低減」とは、消費電力を通常時よりも小さくすることであり、消費電力をゼロにする場合も含む概念である。 Next, a modified example in which control for reducing power consumption is performed by the reference signal generation device 10 will be described. In the present specification, “reducing power consumption” is to reduce power consumption compared to normal times, and is a concept including a case where power consumption is reduced to zero.
　初めに図６を参照して、電力を供給するか否かを切り替える制御を行うことで、消費電力を低減する構成の基準信号発生装置１０について説明する。本変形例の基準信号発生装置１０は、電源７１と、電源制御部７２と、を備えている。 First, the reference signal generator 10 configured to reduce power consumption by performing control to switch whether or not to supply power will be described with reference to FIG. The reference signal generation device 10 according to the present modification includes a power source 71 and a power source control unit 72.
　 電源７１と電源制御部７２とはケーブル等によって電気的に接続されている。また、電源制御部７２は、電力を供給するためのケーブル等を用いて、ＧＰＳ受信 部２１及び信号発生部５３等に接続されている。電源制御部７２は、外部信号や内部の処理装置等から指示を受けて、ＧＰＳ受信部２１に電力を供給するか否 か、及び、信号発生部５３に電力を供給するか否かを切替可能である。 The power source 71 and the power control unit 72 are electrically connected by a cable or the like. Further, the power control unit 72 is connected to the GPS receiving rod unit 21, the signal generating unit 53, and the like using a cable or the like for supplying power. The power controller 72 can switch whether to supply power to the GPS receiver 21 and whether to supply power to the signal generator 53 in response to an instruction from an external signal or an internal processing device. It is.
　なお、信号発生部５３は、入力されたリファレンス信号に基づいて基準信号を発生させる部分であり、上述のＰＬＬ回路５１及びＤＤＳ５２等を含む部分である。 The signal generator 53 is a part that generates a reference signal based on the input reference signal, and includes the PLL circuit 51 and the DDS 52 described above.
　 ところで、本願のようにデジタル部品が多い基準信号発生装置１０は、大部分を半導体チップ上に実現できるので、コンパクトかつ安価に構成することができ る。従って、ＧＰＳ受信部２１が出力する測位結果のみが必要であっても、チップ化した基準信号発生装置１０が用いられる場合がある。この場合、信号発生部 ５３へ電力を供給しないように（又は供給する電力を減らすように）電源制御部７２に指示することで、基準信号発生装置１０の消費電力を低減することができ る。 By the way, since the reference signal generator 10 having a large number of digital parts as in the present application can be realized on a semiconductor chip, it can be configured compactly and inexpensively. Therefore, even if only the positioning result output from the GPS receiving unit 21 is necessary, the chip-based reference signal generator 10 may be used. In this case, the power consumption of the reference signal generator 10 can be reduced by instructing the power supply controller 72 not to supply power to the signal generator 53 (or to reduce the supplied power).
　次に、図７を参照して、供給するクロックを低減することで基準信号発生装置１０の消費電力を低減する構成について説明する。図７に示すように、本変形例の基準信号発生装置１０は、クロック生成部７３を備えている。 Next, a configuration for reducing the power consumption of the reference signal generator 10 by reducing the clock to be supplied will be described with reference to FIG. As shown in FIG. 7, the reference signal generation device 10 of the present modification includes a clock generation unit 73.
　クロック生成部７３は、主に信号発生部５３内の機器で使用されるクロックを生成する機器である。また、クロック生成部７３は、外部信号や内部の処理装置等から指示を受けて、信号発生部５３内の機器へ供給するクロックの周波数を変化させることができる。 The clock generation unit 73 is a device that generates a clock mainly used by devices in the signal generation unit 53. The clock generation unit 73 can change the frequency of the clock supplied to the devices in the signal generation unit 53 in response to an instruction from an external signal, an internal processing device, or the like.
　従って、例えばＧＰＳ受信部２１が出力する測位結果のみが必要な場合、クロック生成部７３が生成するクロックの周波数を低減する（又はゼロにする）ことで、信号発生部５３内の機器の消費電力を低減することができる。 Therefore, for example, when only the positioning result output from the GPS receiving unit 21 is necessary, the power consumption of the devices in the signal generating unit 53 is reduced by reducing (or setting to zero) the frequency of the clock generated by the clock generating unit 73. Can be reduced.
　なお、図６及び図７で示した変形例では、信号発生部５３内の全ての機器に対して、電力の供給及びクロックの周波数を変化させる構成だが、特定の機器（例えばＮＣＯ２３）についてのみ、電力の供給又はクロックの周波数を変化させる構成であっても良い。 In the modification shown in FIGS. 6 and 7, the power supply and the clock frequency are changed for all the devices in the signal generator 53, but only for a specific device (for example, the NCO 23). The power supply or the clock frequency may be changed.
　また、クロック生成部７３と、ＮＣＯ２３等の間にクロックゲーティング回路を設け、クロックゲーティング回路に外部信号が入力されたときのみＮＣＯ２３等に供給するクロックを低減する（又はゼロにする）構成にすることもできる。 In addition, a clock gating circuit is provided between the clock generator 73 and the NCO 23, etc., and the clock supplied to the NCO 23, etc. is reduced (or made zero) only when an external signal is input to the clock gating circuit. You can also
　 以上に説明したように、本発明のＤＤＳ５２は、ＮＣＯ２３と、ΔΣ変調部２８と、ＢＰＦ２９と、を備える。ＮＣＯ２３は、デジタル信号を出力する。ΔΣ変 調部２８は、ＮＣＯ２３が出力する信号に基づく正弦波信号又は三角波信号を変調する。ＢＰＦ２９は、ΔΣ変調部２８が出力した信号をアナログ信号として出 力する。 As described above, the DDS 52 of the present invention includes the NCO 23, the ΔΣ modulator 28, and the BPF 29. The NCO 23 outputs a digital signal. The ΔΣ modulation unit 28 modulates a sine wave signal or a triangular wave signal based on the signal output from the NCO 23. The BPF 29 outputs the signal output from the ΔΣ modulator 28 as an analog signal.
　これにより、ΔΣ変調部２８を備えることで、従来はアナログ部品で構成されていたＤ／Ａコンバータの大部分をデ ジタル回路で実現できる。従って、ＤＤＳ５２の大部分をチップ化してコンパクトな構成を実現することができる。また、ΔΣ変調部２８を備えることで、 Ｄ／Ａ変換後の信号の分解能を向上させることができる。 Thus, by providing the ΔΣ modulation unit 28, most of the D / A converters that have been conventionally constituted by analog parts can be realized by a digital circuit. Therefore, most of the DDS 52 can be made into a chip to realize a compact configuration. Further, by providing the ΔΣ modulator 28, the resolution of the signal after the D / A conversion can be improved.
　以上に本発明の好適な実施の形態を説明したが、上記の構成は例えば以下のように変更することができる。 Although a preferred embodiment of the present invention has been described above, the above configuration can be modified as follows, for example.
　 上記実施形態及び変形例では、正弦波変換ＲＯＭ２５及び三角波変換回路２６の両方を備える構成を開示しているが、正弦波変換ＲＯＭ２５のみ又は三角波変換 回路２６のみを備える構成であっても、ＤＤＳ５２の大部分をデジタル化できるという本発明の効果を実現することができる。 In the above-described embodiment and the modification, the configuration including both the sine wave conversion ROM 25 and the triangular wave conversion circuit 26 is disclosed. However, even in the configuration including only the sine wave conversion ROM 25 or only the triangular wave conversion circuit 26, the DDS 52 The effect of the present invention that most can be digitized can be realized.
　 上記実施形態及び変形例は、ＧＰＳ衛星からの信号に基づいてリファレンス信号を生成する構成であるが、ＧＮＳＳ（Ｇｌｏｂａｌ　Ｎａｖｉｇａｔｉｏｎ　 Ｓａｔｅｌｌｉｔｅ　Ｓｙｓｔｅｍ）を利用する構成であれば、適宜変更することができる。例えば、ＧＬＯＮＡＳＳ衛星やＧＡＬＩＬＥＯ衛星からの信号に基 づいてリファレンス信号を生成する構成に変更することができる。また、外部装置からのリファレンス信号を取得する構成としても良い。 Although the above embodiment and the modification are configured to generate a reference signal based on a signal from a GPS satellite, the configuration can be appropriately changed as long as the configuration uses GNSS (Global Navigation Satellite System). For example, the configuration can be changed to a configuration in which a reference signal is generated based on a signal from a GLONASS satellite or a GALILEO satellite. Further, it may be configured to acquire a reference signal from an external device.
　ＧＰＳ受信部２１は、１ＰＰＳに代えて、ＰＰ２Ｓ等の１Ｈｚ以外の信号をリファレンス信号として生成する構成に変更することができる。また、ＧＰＳ受信部２１は、基準信号発生装置１０の内部ではなく外部に配置されていても良い。 The GPS receiving unit 21 can be changed to a configuration that generates a signal other than 1 Hz such as PP2S as a reference signal instead of 1PPS. Further, the GPS receiver 21 may be arranged outside the reference signal generator 10 instead of inside.
　 三角波変換回路は、排他的論理和を用いる上記の構成に限られず、任意の構成の回路によって実現されていても良い。また、三角波変換回路を複数備え、上記で 示した三角波の一部（４分割したときの中央の２つ）を反転させて、１周期分の三角波から２周期分の三角波が得られる構成とすることができる。なお、三角波 変換回路を設けずに、ＮＣＯ２３が出力するノコギリ波がＢＰＦ２９によって正弦波信号に変換される構成に変更することができる。 The triangular wave conversion circuit is not limited to the above configuration using exclusive OR, and may be realized by a circuit having an arbitrary configuration. Further, a plurality of triangular wave conversion circuits are provided, and a part of the triangular wave shown above (two in the center when divided into four) is inverted to obtain a triangular wave for two cycles from a triangular wave for one cycle. be able to. In addition, it can change to the structure by which the sawtooth wave which NCO23 outputs is converted into a sine wave signal by BPF29, without providing a triangular wave conversion circuit.
　上記実施形態及び変形例では、位相差を比較するＰＬＬ回路５１を用いているが、周波数差を比較するＦＬＬ回路を用いることもできる。 In the above embodiment and the modification, the PLL circuit 51 that compares the phase difference is used, but an FLL circuit that compares the frequency difference can also be used.
　 上記実施形態及び変形例では、ＧＰＳアンテナ１１は、所定のケーブルを介して、ＰＬＬ回路５１等が形成された基板と接続される構成である。これに代えて、 この基板にＧＰＳアンテナ１１が直接的に取り付けられる構成であっても良い。この場合、ケーブルが不要となるので、基準信号発生装置の設置コストを低減で きる。 In the embodiment and the modification described above, the GPS antenna 11 is connected to a substrate on which the PLL circuit 51 and the like are formed via a predetermined cable. Alternatively, the GPS antenna 11 may be directly attached to this board. In this case, since a cable is not necessary, the installation cost of the reference signal generator can be reduced.
　上記の変形例は、供給する電力の低減又は供給するクロックの低減により、消費電力を低減させる構成であるが、その他の構成（信号発生部５３を制御するソフトウェアを動作させない等）によって消費電力を低減させる構成に変更することができる。 In the above modification, the power consumption is reduced by reducing the power to be supplied or the clock to be supplied, but the power consumption is reduced by other configurations (such as not operating the software that controls the signal generator 53). The configuration can be changed to be reduced.
　基準信号発生装置１０が備える各部は、ハードウェアとして構成することに代えて、ソフトウェアにより構成することもできる。 The units included in the reference signal generation device 10 can be configured by software instead of being configured by hardware.
　１０　基準信号発生装置
　１１　ＧＰＳアンテナ
　２１　ＧＰＳ受信部（ＧＮＳＳ受信部）
　２２　制御部
　２３　ＮＣＯ（数値制御発振器）
　２４　分周部
　２５　正弦波変換ＲＯＭ（変換情報記憶部）
　２６　三角波変換回路
　２７　選択部
　２８　ΔΣ変調部
　２９　ＢＰＦ（フィルタ部）
　５１　ＰＬＬ回路
　５２　ＤＤＳ（ダイレクトデジタルシンセサイザ） 10 reference signal generator 11 GPS antenna 21 GPS receiver (GNSS receiver)
22 Control Unit 23 NCO (Numerically Controlled Oscillator)
24 frequency dividing unit 25 sine wave conversion ROM (conversion information storage unit)
26 Triangular Wave Conversion Circuit 27 Selection Unit 28 ΔΣ Modulation Unit 29 BPF (Filter Unit)
51 PLL circuit 52 DDS (Direct Digital Synthesizer)

Claims (10)

  1. 　デジタル信号を出力する数値制御発振器と、
    　前記数値制御発振器が出力する信号又は当該信号に基づく信号をΔΣ変調するΔΣ変調部と、
    　前記ΔΣ変調部がΔΣ変調した信号をアナログ信号として出力するフィルタ部と、
    を備えることを特徴とするダイレクトデジタルシンセサイザ。     A numerically controlled oscillator that outputs digital signals;
    A ΔΣ modulator that ΔΣ modulates a signal output from the numerically controlled oscillator or a signal based on the signal;
    A filter unit that outputs a signal obtained by ΔΣ modulation by the ΔΣ modulation unit as an analog signal;
    A direct digital synthesizer characterized by comprising:
  2. 　請求項１に記載のダイレクトデジタルシンセサイザであって、
    　前記数値制御発振器から入力された信号の位相に応じた振幅の信号を出力することで、入力された信号を正弦波信号に変換する変換情報記憶部を備えることを特徴とするダイレクトデジタルシンセサイザ。     A direct digital synthesizer according to claim 1,
    A direct digital synthesizer comprising a conversion information storage unit for converting an input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator.
  3. 　請求項１に記載のダイレクトデジタルシンセサイザであって、
    　前記フィルタ部は、前記数値制御発振器が出力する信号又は当該信号に基づく信号から、一定範囲の周波数の信号を通過させることで、所定の周波数の正弦波信号を抽出することを特徴とするダイレクトデジタルシンセサイザ。     A direct digital synthesizer according to claim 1,
    The filter unit extracts a sine wave signal having a predetermined frequency by passing a signal having a predetermined frequency range from a signal output from the numerically controlled oscillator or a signal based on the signal. Synthesizer.
  4. 　請求項３に記載のダイレクトデジタルシンセサイザであって、
    　前記数値制御発振器から入力された信号の位相に応じた振幅の信号を出力することで、入力された信号を正弦波信号に変換する変換情報記憶部を備え、
    　前記変換情報記憶部が変換した正弦波信号、及び、前記フィルタ部が抽出した正弦波信号のうち、一方の信号が外部へ出力されることを特徴とするダイレクトデジタルシンセサイザ。     A direct digital synthesizer according to claim 3,
    A conversion information storage unit that converts the input signal into a sine wave signal by outputting a signal having an amplitude corresponding to the phase of the signal input from the numerically controlled oscillator;
    One of the sine wave signal converted by the conversion information storage unit and the sine wave signal extracted by the filter unit is output to the outside.
  5. 　請求項１から４までの何れか一項に記載のダイレクトデジタルシンセサイザと、
    　前記数値制御発振器が出力した信号又はそれに基づく信号と、リファレンス信号と、の位相又は周波数を比較し、比較結果に基づいて前記数値制御発振器を制御する制御部と、
    　前記ダイレクトデジタルシンセサイザが出力する信号又は当該信号に基づく信号を基準信号として出力する出力部と、
    を備えることを特徴とする基準信号発生装置。     A direct digital synthesizer according to any one of claims 1 to 4,
    A control unit that compares the phase or frequency of a signal output from the numerically controlled oscillator or a signal based thereon and a reference signal, and controls the numerically controlled oscillator based on a comparison result;
    An output unit that outputs a signal output from the direct digital synthesizer or a signal based on the signal as a reference signal;
    A reference signal generation device comprising:
  6. 　請求項５に記載の基準信号発生装置であって、
    　適切な前記リファレンス信号を利用できないと判断したときに、前記基準信号を生成するための自走用制御信号を生成する自走制御部を備えることを特徴とする基準信号発生装置。     The reference signal generator according to claim 5, wherein
    A reference signal generation device comprising: a self-running control unit that generates a self-running control signal for generating the reference signal when it is determined that the appropriate reference signal cannot be used.
  7. 　請求項５又は６に記載の基準信号発生装置であって、
    　少なくとも前記数値制御発振器の消費電力を低減させる制御を行う電力制御部を備えることを特徴とする基準信号発生装置。     The reference signal generator according to claim 5 or 6,
    A reference signal generator comprising a power control unit that performs control to reduce power consumption of at least the numerically controlled oscillator.
  8. 　請求項７に記載の基準信号発生装置であって、
    　ＧＮＳＳ衛星からの電波に基づいて、位置情報を取得するＧＮＳＳ受信部を備え、
    　前記ダイレクトデジタルシンセサイザ及び前記制御部を含み、基準信号を発生させる部分を信号発生部と称したときに、前記電力制御部は、当該信号発生部の消費電力を低減させる制御を行うことを特徴とする基準信号発生装置。     The reference signal generator according to claim 7,
    A GNSS receiver that acquires position information based on radio waves from a GNSS satellite;
    When the portion that includes the direct digital synthesizer and the control unit and generates a reference signal is referred to as a signal generation unit, the power control unit performs control to reduce power consumption of the signal generation unit. A reference signal generator.
  9. 　請求項５から８までの何れか一項に記載の基準信号発生装置であって、
    　前記制御部と同じ基板に取り付けられ、ＧＮＳＳ衛星からの測位信号を受信するＧＮＳＳアンテナと、
    　前記制御部と同じ基板に取り付けられ、前記ＧＮＳＳアンテナが受信した測位信号に基づいてリファレンス信号を生成するＧＮＳＳ受信部と、
    を備えることを特徴とする基準信号発生装置。     The reference signal generator according to any one of claims 5 to 8,
    A GNSS antenna attached to the same substrate as the control unit and receiving a positioning signal from a GNSS satellite;
    A GNSS receiver that is attached to the same substrate as the controller and generates a reference signal based on a positioning signal received by the GNSS antenna;
    A reference signal generation device comprising:
  10. 　数値制御発振器によりデジタル信号を出力するデジタル信号出力工程と、
    　前記デジタル信号出力工程で出力された信号をΔΣ変調する変調工程と、
    　フィルタ処理を行うことにより、前記変調工程で出力された信号をアナログ信号として出力するアナログ信号出力工程と、
    を含むことを特徴とする信号出力方法。     A digital signal output process for outputting a digital signal by a numerically controlled oscillator;
    A modulation step of ΔΣ modulating the signal output in the digital signal output step;
    An analog signal output step of outputting the signal output in the modulation step as an analog signal by performing filter processing;
    A signal output method comprising:
PCT/JP2016/053190 2015-03-16 2016-02-03 Direct digital synthesizer, reference signal generation device, and signal output method WO2016147729A1 (en)

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Citations (5)

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JPH06338784A (en) * 1993-05-28 1994-12-06 Kenwood Corp Phase locked circuit
US20020008588A1 (en) * 2000-06-21 2002-01-24 Nasserullah Khan Direct digital frequency synthesizer and a hybrid frequency synthesizer combining a direct digital frequency synthesizer and a phase locked loop
JP2004236139A (en) * 2003-01-31 2004-08-19 Icom Inc Phase locked loop circuit
US7557661B1 (en) * 2006-09-25 2009-07-07 Cirrus Logic, Inc. Direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization
WO2010137419A1 (en) * 2009-05-25 2010-12-02 古野電気株式会社 Reference frequency generator device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06338784A (en) * 1993-05-28 1994-12-06 Kenwood Corp Phase locked circuit
US20020008588A1 (en) * 2000-06-21 2002-01-24 Nasserullah Khan Direct digital frequency synthesizer and a hybrid frequency synthesizer combining a direct digital frequency synthesizer and a phase locked loop
JP2004236139A (en) * 2003-01-31 2004-08-19 Icom Inc Phase locked loop circuit
US7557661B1 (en) * 2006-09-25 2009-07-07 Cirrus Logic, Inc. Direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization
WO2010137419A1 (en) * 2009-05-25 2010-12-02 古野電気株式会社 Reference frequency generator device

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