WO2016143229A1 - Method for manufacturing nitride semiconductor laminated body, and nitride semiconductor laminated body - Google Patents

Method for manufacturing nitride semiconductor laminated body, and nitride semiconductor laminated body Download PDF

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WO2016143229A1
WO2016143229A1 PCT/JP2015/085824 JP2015085824W WO2016143229A1 WO 2016143229 A1 WO2016143229 A1 WO 2016143229A1 JP 2015085824 W JP2015085824 W JP 2015085824W WO 2016143229 A1 WO2016143229 A1 WO 2016143229A1
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layer
nitride semiconductor
gan
gan layer
substrate
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藤倉　序章
今野　泰一郎
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住友化学株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments

Definitions

  • the present invention relates to a method for manufacturing a nitride semiconductor multilayer body and a nitride semiconductor multilayer body.
  • a gallium nitride (GaN) substrate as a self-supporting substrate, for example, a VAS method (Void-assisted Method) is sometimes used.
  • a self-standing substrate is formed by forming a GaN layer as a self-supporting substrate on a base substrate and peeling the base substrate and the GaN layer.
  • a first GaN layer provided on the substrate As the base substrate, a first GaN layer provided on the substrate, an aluminum gallium nitride (AlGaN) layer provided on the first GaN layer, and a second GaN layer provided on the AlGaN layer, And a metal film (for example, a TiN film) provided on the second GaN layer, and the second GaN layer and the metal film are made porous by forming voids.
  • a physical semiconductor laminate may be used (see, for example, Patent Document 1).
  • the first GaN layer, the AlGaN layer, and the second GaN layer are each formed (film formation, growth) by a MOVPE (Metal Organic Vapor Phase Epitaxy) method.
  • MOVPE Metal Organic Vapor Phase Epitaxy
  • each layer included in the nitride semiconductor multilayer body By forming each layer included in the nitride semiconductor multilayer body by the MOVPE method, pits appearing on the surface of the second GaN layer, for example, even if the thickness of the first GaN layer is reduced to about 2 to 3 ⁇ m. Macro defects can be sufficiently reduced.
  • the growth rate of the nitride semiconductor by the MOVPE method is as low as several ⁇ m / hour at most, there is a problem that when each layer is formed by the MOVPE method, the productivity of the nitride semiconductor stacked body becomes very low. As a result, the productivity of free standing substrates by the VAS method may be reduced.
  • the present invention uses a HVPE (Hydride Vapor Phase Epitaxy) method with a growth rate of several to several tens of mm / hour, which is higher than the MOVPE method, to form a free-standing substrate by the VAS method.
  • An object of the present invention is to provide a technique for improving the productivity of a nitride semiconductor laminated body used as a base substrate and the productivity of a free-standing substrate.
  • a nitride semiconductor stacked body in which a force is applied to the first gallium nitride layer so that the warp generated in the first gallium nitride layer is canceled by the warp generated in the aluminum nitride layer.
  • the present invention it is possible to provide a technique for improving the productivity of a nitride semiconductor stacked body used as a base substrate when forming a freestanding substrate by the VAS method, and the productivity of a freestanding substrate.
  • the longitudinal cross-sectional schematic of the nitride semiconductor laminated body concerning one Embodiment of this invention is shown. It is a figure which shows an example of the manufacturing process of the nitride semiconductor laminated body concerning one Embodiment of this invention, and a GaN self-supporting substrate.
  • each layer of the nitride semiconductor laminate is not grown by the MOVPE method, which is slower than the MOVPE method. It is considered to form (film formation) by a high growth rate, for example, HVPE.
  • HVPE high growth rate
  • the HVPE method is inferior in crystal growth controllability compared to the MOVPE method. Therefore, for example, when the first GaN layer having a thickness of about 2 to 3 ⁇ m as described above is formed by the HVPE method, a pit having a diameter of slightly less than 1 ⁇ m to several ⁇ m appears on the surface (upper surface) of the second GaN layer. In some cases, it is not possible to sufficiently reduce such macro defects. As a result, the metal film provided on the second GaN layer may be peeled off. For example, the metal film may be peeled off when the metal film is formed by vapor deposition, or the metal film may be peeled off during the process of modifying the metal film into a porous film.
  • the yield of the nitride semiconductor substrate may be lowered. That is, even when each layer of the nitride semiconductor multilayer body is formed by the HVPE method, the productivity of the nitride semiconductor multilayer body may be reduced.
  • the thickness of the first GaN layer is made thicker than when the GaN layer is formed by the MOVPE method.
  • the thickness of the first GaN layer may be 4 ⁇ m or more.
  • a nitride semiconductor multilayer body having a substrate and a predetermined nitride semiconductor (nitride semiconductor layer) including the first GaN layer may be greatly warped.
  • a nitride semiconductor laminate formed by providing a predetermined nitride semiconductor on a 2 inch substrate typically has a warpage amount at room temperature when the thickness of the first GaN layer is 4 ⁇ m. Becomes 60 ⁇ m or more. The origin of this warp is due to the difference between the thermal expansion coefficient of the nitride semiconductor and the thermal expansion coefficient of sapphire as the substrate.
  • the amount of warpage is almost zero at around 1000 ° C., which is the temperature (growth temperature) for growing each layer constituting the nitride semiconductor multilayer body. .
  • a nitride semiconductor laminate having a large warp at room temperature is used as the base substrate, for example, a GaN layer (hereinafter referred to as “GaN layer” to be a self-supporting substrate on the base substrate.
  • the base substrate (nitride semiconductor laminate) may be cracked when forming (film formation)). Most of the cracks in the base substrate occur during the temperature rising process from room temperature to 1000 ° C. which is the growth temperature.
  • a nitride semiconductor multilayer body including a nitride semiconductor having a large strain, that is, a nitride semiconductor multilayer body greatly warped at room temperature tends to be easily broken.
  • the crack is also taken over by the GaN free-standing substrate formed on the base substrate, so that the growth yield of the GaN free-standing substrate layer is reduced, that is, the productivity of the GaN free-standing substrate is reduced. .
  • the present inventors have provided a nitride semiconductor stack with a layer that warps in a direction opposite to the direction of warpage that occurs in the first GaN layer, so that the nitride semiconductor can be used even when the HVPE method is used. It has been found that the warpage occurring in the entire laminate can be reduced.
  • the present invention is based on the above findings found by the inventors.
  • the nitride semiconductor multilayer body 1 includes a substrate 2.
  • a substrate made of sapphire, silicon, SiC, langasite, zirconium diboride, or gallium arsenide (GaAs) can be used.
  • GaAs gallium arsenide
  • a sapphire substrate is more preferably used as the substrate 2 from the viewpoint of lattice constants of an AlN layer 3 and a GaN layer (first GaN layer 4 and second GaN layer 6) described later.
  • An AlN layer 3 is provided on any main surface of the substrate 2.
  • the AlN layer 3 is warped.
  • the AlN layer 3 is warped such that the center (center portion) is the lowest. That is, the AlN layer 3 warps, for example, a concave shape (a bowl shape).
  • the thickness of the AlN layer 3 is a thickness that can sufficiently warp the AlN layer 3.
  • the thickness of the AlN layer 3 is preferably 10 nm or more and 500 nm or less, for example.
  • the AlN layer 3 may not be sufficiently warped. By making the thickness of the AlN layer 3 10 nm or more, the AlN layer 3 can be sufficiently warped.
  • the thickness of the AlN layer 3 exceeds 500 nm, it takes time to form the AlN layer 3 even when the AlN layer 3 is formed by the HVPE method. May decrease.
  • the thickness of the AlN layer 3 500 nm or less this can be solved, and the decrease in productivity of the nitride semiconductor multilayer body 1 can be suppressed.
  • the AlN layer 3 also functions as a buffer layer that buffers a mismatch in lattice constant between the sapphire substrate and the first GaN layer 4 described later.
  • the first GaN layer 4 is provided on the AlN layer 3.
  • the first GaN layer 4 functions as an underlayer for the second GaN layer 6 described later, and the dislocation of the second GaN layer 6 can be reduced.
  • the first GaN layer 4 is warped.
  • the first GaN layer 4 is warped such that the center (center portion) is the highest. That is, the first GaN layer 4 is warped to have a convex shape (dome shape), for example.
  • the first GaN layer 4 is warped in the opposite direction to the warp generated in the AlN layer 3.
  • the thickness of the first GaN layer 4 is preferably 4 ⁇ m or more, for example.
  • the first GaN layer 4 is formed by, for example, the HVPE method
  • if the thickness of the first GaN layer 4 is less than 4 ⁇ m macros such as pits appearing on the surface (upper surface) of the second GaN layer 6 described later. Defects may not be reduced sufficiently.
  • the macro defect density on the surface of the second GaN layer 6 may not be sufficiently reduced.
  • the first GaN layer 4 is warped in the opposite direction to the warp generated in the AlN layer 3. Accordingly, the warping of the AlN layer 3 can apply a force to the first GaN layer 4 so as to cancel the warp generated in the first GaN layer 4. That is, a force in a direction opposite to the direction of warpage generated in the first GaN layer 4, for example, a force that flattens the first GaN layer 4 can be applied to the first GaN layer. Further, when the first GaN layer 4 is warped, a force can be applied to the AlN layer 3 so as to cancel the warp generated in the AlN layer 3.
  • a force in a direction opposite to the direction of warping generated in the AlN layer 3, for example, a force that flattens the AlN layer 3 can be applied to the AlN layer 3.
  • the AlN layer 3 and the first GaN layer 4 are warped, so that a force that cancels the warpage generated in each layer can be applied to each layer.
  • the warp generated in the first GaN layer 4 by the warp generated in the AlN layer 3 can be offset. As a result, the amount of warpage (stress) in the entire nitride semiconductor multilayer body 1 can be reduced.
  • a group III nitride semiconductor layer 5 containing aluminum (Al) is provided on the first GaN layer 4.
  • the group III nitride semiconductor layer 5 has voids in the first GaN layer 4 when a process for modifying the metal film 7 described later into a porous film (hereinafter also simply referred to as “modification process”) is performed. It functions as a layer (void formation preventing layer) that prevents (void) from being formed.
  • the group III nitride semiconductor layer 5 functions as a layer that suppresses desorption of N (nitrogen element) from the first GaN layer 4 due to the modification treatment.
  • the group III nitride semiconductor layer 5 also functions as a layer that suppresses the enlargement of voids formed in the second GaN layer 6 described later.
  • group III nitride semiconductor layer 5 containing Al for example, a layer having a composition of Al x Ga 1-x N (0.01 ⁇ x ⁇ 1) is preferably provided.
  • Voids are also formed in the group III nitride semiconductor layer 5 by the modification process described later.
  • a void penetrating in the thickness direction may be formed in the group III nitride semiconductor layer 5 in some cases. That is, a through hole may be formed in the group III nitride semiconductor layer 5.
  • the group III nitride semiconductor layer 5 may not function as a void formation suppression layer. That is, during the modification process described later, the first GaN layer 4 is also exposed to the first GaN layer 4 through the portion of the first GaN layer 4 exposed from the through hole formed in the group III nitride semiconductor layer 5. Voids may be formed.
  • the value of x may be 1. That is, an AlN layer may be provided as the group III nitride semiconductor layer 5. However, from the viewpoint of reducing the difference in lattice constant between the group III nitride semiconductor layer 5, the first GaN layer 4, and the second GaN layer 6 described later, the group III nitride semiconductor layer 5 is x More preferably, an AlGaN layer having a value of less than 1 is provided.
  • the thickness of the group III nitride semiconductor layer 5 is preferably formed to a thickness at which no through hole is formed in the group III nitride semiconductor layer 5 by a modification process described later.
  • the thickness of the group III nitride semiconductor layer 5 is preferably 3 nm or more.
  • the thickness of the group III nitride semiconductor layer 5 is less than 3 nm, through holes may be formed in the group III nitride semiconductor layer 5 by a modification process described later.
  • the thickness of group III nitride semiconductor layer 5 is set to 3 nm or more, formation of a through hole in group III nitride semiconductor layer 5 can be more reliably suppressed by a modification process described later.
  • the upper limit of the thickness of the group III nitride semiconductor layer 5 is not particularly limited. However, as the thickness of the group III nitride semiconductor layer 5 increases, strain due to lattice mismatch between the group III nitride semiconductor layer 5 containing Al and the first GaN layer 4 increases, and the group III nitride semiconductor layer When growing 5, the group III nitride semiconductor layer 5 may be cracked. Therefore, the thickness of group III nitride semiconductor layer 5 is preferably set to a thickness (critical film thickness) or less that does not cause a crack corresponding to the composition of group III nitride semiconductor layer 5.
  • a second GaN layer 6 having a predetermined thickness (for example, several 100 nm) is provided. Voids are formed in the second GaN layer 6 by a modification process described later. That is, the second GaN layer 6 is a porous layer.
  • a metal film 7 is provided on the second GaN layer 6. Voids are formed in the metal film 7. That is, the metal film 7 is a porous film.
  • the metal contained in the metal film 7 include titanium, vanadium, chromium, manganese, iron, cobalt, nickel, copper, yttrium, zirconium, niobium, molybdenum, tellurium, ruthenium, rhodium, palladium, hafnium, tantalum, and tungsten. , Rhenium, osmium, iridium, platinum, gold and the like can be used.
  • a titanium nitride (TiN) film is provided as the metal film 7, for example.
  • the thickness of the metal film 7 is preferably 100 nm or less, for example, and more preferably 30 nm or less. If the thickness of the metal film 7 exceeds 100 nm, it takes time to modify the metal film 7 into a porous film, and the productivity of the nitride semiconductor multilayer body 1 may be reduced. By setting the thickness of the metal film 7 to 100 nm or less, this can be solved, and the decrease in productivity of the nitride semiconductor multilayer body 1 can be further suppressed. By reducing the thickness of the metal film 7 to 30 nm or less, it is possible to further suppress a decrease in productivity of the nitride semiconductor multilayer body 1.
  • the lower limit of the thickness of the metal film 7 is not particularly limited, but is preferably 1 nm or more, for example.
  • First step A first step of forming the AlN layer 3 on the substrate 2 (for example, on the sapphire substrate) is performed.
  • the AlN layer 3 is formed by the HVPE method using a hydride vapor phase epitaxy (HVPE) apparatus.
  • HVPE hydride vapor phase epitaxy
  • the formation temperature (growth temperature) of the AlN layer 3 is preferably set to a temperature at which the dense AlN layer 3 can be formed.
  • the growth temperature of the AlN layer 3 is preferably 800 ° C. or higher and 1200 ° C. or lower, and more preferably about 1000 ° C.
  • the AlN layer 3 may not be a dense layer. As a result, when the temperature of the AlN layer 3 drops, the AlN layer 3 may not be sufficiently warped.
  • the AlN layer 3 By setting the growth temperature of the AlN layer 3 to 800 ° C. or higher, the AlN layer 3 can be made sufficiently dense. As a result, the AlN layer 3 can be sufficiently warped.
  • the growth temperature of the AlN layer 3 exceeds 1200 ° C., the surface of the sapphire substrate becomes rough before the AlN layer 3 grows. For this reason, the crystal orientation of the AlN layer grown on the surface of the sapphire substrate may be lowered.
  • the growth temperature of the AlN layer 3 By setting the growth temperature of the AlN layer 3 to 1200 ° C. or less, it is possible to prevent the crystal orientation of the AlN layer 3 from being lowered.
  • the thickness of the AlN layer 3 is, for example, not less than 10 nm and not more than 500 nm.
  • a second step of forming the first GaN layer 4 on the AlN layer 3 is performed.
  • the first GaN layer 4 is formed by HVPE using an HVPE apparatus.
  • the thickness of the first GaN layer 4 is preferably 4 ⁇ m or more.
  • the thickness of the first GaN layer 4 can be adjusted, for example, by adjusting the film formation time of the first GaN layer 4.
  • a third step of forming a group III nitride semiconductor layer 5 containing Al on the first GaN layer 4 is performed.
  • group III nitride semiconductor layer 5 is formed by HVPE using an HVPE apparatus.
  • the group III nitride semiconductor layer 5 for example, a layer having a composition of Al x Ga 1-x N (0.01 ⁇ x ⁇ 1) is preferably formed.
  • the thickness of the group III nitride semiconductor layer 5 is preferably 3 nm or more. The thickness of group III nitride semiconductor layer 5 can be adjusted, for example, by adjusting the film formation time of group III nitride semiconductor layer 5.
  • a fourth step of forming the second GaN layer 6 having a predetermined thickness on the group III nitride semiconductor layer 5 is performed.
  • the second GaN layer 6 is formed by HVPE using an HVPE apparatus.
  • a fifth step of forming a metal film 7 having a predetermined thickness on the second GaN layer 6 is performed.
  • a Ti film as the metal film 7 is formed by vapor deposition, for example. Thereby, for example, a stacked body 1A shown in FIG. 2A is formed.
  • a sixth step of modifying the second GaN layer 6 and the metal film 7 to be porous is performed.
  • heat treatment is performed on the second GaN layer 6 and the metal film 7.
  • a void is formed in the second GaN layer 6 to be modified into a porous layer
  • a void is formed in the metal film 7 (metal nitride film) by modifying the metal film 7 into a metal nitride film.
  • the metal film 7 is modified into a porous film.
  • the nitride semiconductor multilayer body 1 shown in FIG. 2B is formed.
  • a seventh step of forming a free-standing substrate by the VAS method is performed. That is, in the seventh step, as shown in FIG. 2C, after the sixth step is finished, the nitride semiconductor multilayer body 1 is used as a base substrate, and a GaN layer that becomes a free-standing substrate on the base substrate. 10 (GaN free-standing substrate layer 10) is formed, and a GaN free-standing substrate is formed. Specifically, first, in the seventh step, the substrate 2, the AlN layer 3, the first GaN layer 4, the group III nitride semiconductor layer 5, the second GaN layer 6, and the metal film 7.
  • a GaN free-standing substrate layer 10 is formed on a base substrate (porous metal film 7 (metal nitride film)) using a nitride semiconductor laminate 1 having Thereafter, the GaN free-standing substrate layer 10 is peeled from the base substrate. Note that the GaN free-standing substrate layer 10 is naturally peeled from the underlying substrate when the stacked body of the underlying substrate and the GaN free-standing substrate layer 10 is cooled to a predetermined temperature (for example, about room temperature). The peeled GaN free-standing substrate layer 10 becomes a GaN free-standing substrate.
  • the seventh step it is preferable to adjust the growth time of the GaN layer so that the GaN free-standing substrate layer 10 has a predetermined thickness (for example, 800 ⁇ m).
  • the GaN free-standing substrate layer 10 separated from the base substrate may be sliced to a predetermined thickness. That is, a plurality of GaN free-standing substrates may be formed from one GaN free-standing substrate layer 10.
  • AlN layer 3 that generates a warp in a direction opposite to the direction of the warp that occurs in the first GaN layer 4 is provided, and the AlN layer 3 and the first GaN layer 4 are warped, respectively. Even when each of the GaN layer 4, the group III nitride semiconductor layer 5, and the second GaN layer 6 is formed by the HVPE method, the amount of warpage can be reduced in the entire nitride semiconductor multilayer body 1. it can. As a result, the productivity of the nitride semiconductor multilayer body 1 and the productivity of the GaN free-standing substrate can be improved.
  • each of the AlN layer 3, the first GaN layer 4, the group III nitride semiconductor layer 5, and the second GaN layer 6 is formed by the HVPE method, so that the growth rate of each layer is increased. Can be made 10 to 100 times faster than when formed by the MOVPE method, for example.
  • the nitride semiconductor multilayer body 1 can be formed in a time of 1 hour or less including the time until the reactor cleaning after growing the above-described layers. Therefore, the productivity of the nitride semiconductor multilayer body 1 can be improved as compared with the case where the above-described layers are formed by the MOVPE method.
  • the nitride semiconductor multilayer body 1 in which a predetermined layer is formed by the HVPE method is used as the base substrate. Even when it is used as a substrate, it is possible to prevent the base substrate (nitride semiconductor multilayer body 1) from being broken (cracked) during the formation of the GaN layer (GaN free-standing substrate layer 10) serving as a free-standing substrate. can do. Thereby, the yield (growth yield) of the GaN free-standing substrate layer 10 can be improved. As a result, the productivity of the GaN free-standing substrate can be improved.
  • the dense AlN layer 3 can be formed by forming the AlN layer 3 in an atmosphere of high temperature (for example, 800 ° C. or more and 1200 ° C. or less). Thereby, when the temperature of the AlN layer 3 falls, the AlN layer 3 can be warped more sufficiently. Therefore, even when the thickness of the first GaN layer 4 is increased and the amount of warpage generated in the first GaN layer 4 is increased, the amount of warpage in the entire nitride semiconductor multilayer body 1 is reliably reduced. be able to. As a result, the effects (c) and (d) can be obtained more.
  • high temperature for example, 800 ° C. or more and 1200 ° C. or less
  • the growth temperature of the AlN layer 3 can be brought close to the growth temperature of the first GaN layer 4.
  • the growth temperature of the AlN layer 3 and the growth temperature of the first GaN layer 4 can be made comparable.
  • time until it starts a 2nd process can be shortened.
  • the waiting time until the temperature of the processing chamber provided in the HVPE apparatus is raised (or lowered) to a predetermined temperature at which the first GaN layer 4 can be formed is shortened. be able to.
  • the formation of the first GaN layer 4 can be started immediately after the formation of the AlN layer 3 is completed. Therefore, the productivity of the nitride semiconductor multilayer body 1 can be further improved.
  • the macro defects can be sufficiently reduced.
  • the macro defect density on the surface of the second GaN layer 6 can be less than 2 cm ⁇ 2 , preferably 0 cm ⁇ 2 .
  • the nitride semiconductor multilayer body 1 forms a base substrate when a GaN free-standing substrate is formed by, for example, the VAS method.
  • the nitride semiconductor multilayer body 1 can function as a good base substrate. Thereby, the productivity of the GaN free-standing substrate can be further improved.
  • a GaN free-standing substrate with good reproducibility that is, a high-quality GaN free-standing substrate can be formed by the VAS method.
  • the invention according to this embodiment is particularly effective when the thickness of the first GaN layer 4 cannot be reduced, that is, when the thickness of the first GaN layer 4 needs to be increased. is there.
  • the amount of warpage generated in the first GaN layer 4 increases.
  • the AlN layer 3 as in the present embodiment, even when the amount of warpage generated in the first GaN layer 4 is large, the amount of warpage in the entire nitride semiconductor multilayer body 1 is reduced. be able to.
  • the entire nitride semiconductor multilayer body 1 can have a warp amount of less than 60 ⁇ m. Thereby, the effects (c) and (d) can be further obtained.
  • the first GaN layer is formed by, for example, the MOVPE method.
  • the thickness of the first GaN layer is about 2 to 3 ⁇ m, macro defects appearing on the surface of the second GaN layer can be sufficiently reduced. That is, the thickness of the first GaN layer can be made thinner than when the first GaN layer is formed by the HVPE method. As a result, the amount of warpage generated in the first GaN layer is also reduced. Therefore, when the first GaN layer is formed by the MOVPE method, the amount of warpage in the entire nitride semiconductor multilayer body is provided without providing the AlN layer 3 that causes warpage in the opposite direction to the warpage generated in the first GaN layer.
  • the productivity of the nitride semiconductor stacked body becomes very poor.
  • the time until reactor cleaning after growing each layer including the first GaN layer it may take about 10 hours to form the nitride semiconductor stacked body.
  • a predetermined layer such as the first GaN layer 4 is formed by the HVPE method, so that the time required for forming the nitride semiconductor multilayer body 1 is about 1 hour.
  • the productivity of the nitride semiconductor multilayer body 1 can be greatly improved.
  • the seventh step of forming the GaN free-standing substrate is considered to be included in the manufacturing process of the nitride semiconductor multilayer body 1 is described, but the present invention is not limited to this. That is, in the seventh step, the first to sixth steps may be manufacturing steps of the nitride semiconductor multilayer body 1, and the seventh step may be a manufacturing step of the GaN free-standing substrate.
  • the present invention is not limited to this.
  • the slice process may not be performed. That is, one self-standing substrate may be formed from one GaN free-standing substrate layer 10.
  • Samples 8 to 14 are nitride semiconductor laminates formed in the same manner as Samples 1 to 7, respectively, except that the AlN layer was not provided.
  • a thickness of 20 nm is grown between the sapphire substrate and the first GaN layer 4 under a low temperature (550 ° C.) condition instead of the AlN layer.
  • GaN layer low temperature growth GaN layer
  • the thicknesses of the first GaN layers of the samples 8 to 14 are as shown in Table 2 below.
  • the warpage amount was measured for each of the nitride semiconductor laminates of Samples 1 to 14. The results are shown in Table 1 and Table 2, respectively.
  • the yield was calculated for each nitride semiconductor multilayer body of Samples 1 to 14. This yield is the yield when a GaN free-standing substrate is formed using the nitride semiconductor laminate as a base substrate. We also observed the main causes of defects that caused the yield to decrease. These results are shown in Table 1 and Table 2, respectively.
  • “TiN peeling” indicates that the TiN film, which is a metal film, has been peeled off.
  • “cracking” means that when the GaN free-standing substrate layer is formed on the nitride semiconductor multilayer body, the nitride semiconductor multilayer body is cracked and the GaN free-standing substrate itself is defective. ing.
  • the amount of warpage generated in the nitride semiconductor multilayer body can be reduced by providing the film.
  • the amount of warpage of the nitride semiconductor stacked body of sample 4 provided with the AlN layer is 33 ⁇ m.
  • the amount of warpage of the nitride semiconductor multilayer body of Sample 11 in which the AlN layer was not provided was 60 ⁇ m.
  • the nitride semiconductor multilayer structure is provided by providing an AlN layer that warps in a direction opposite to the direction of warpage generated in the first GaN layer. It was confirmed that the amount of warpage can be reduced in the whole body. For example, it was confirmed that the amount of warpage can be less than 60 ⁇ m in the entire nitride semiconductor multilayer body.
  • the yield can be improved by reducing the amount of warpage of the entire nitride semiconductor multilayer body.
  • the yield of the sample 5 having a smaller warpage amount in the entire nitride semiconductor multilayer body is higher. Confirmed that it was high. That is, it was confirmed that a decrease in productivity of the nitride semiconductor multilayer body can be suppressed.
  • the thickness of the first GaN layer is 4 ⁇ m or more, the macro defect density appearing on the surface of the second GaN layer can be sufficiently reduced. It was confirmed. For example, when the thickness of the first GaN layer is 4 ⁇ m or more from each of Samples 4 to 7 and Samples 11 to 14, the macro defect density on the surface of the second GaN layer can be reduced to 0 cm ⁇ 2. confirmed.
  • Appendix 2 The method for producing a nitride semiconductor multilayer body according to appendix 1, preferably, In the first step, the temperature for forming the aluminum nitride layer is set to 800 ° C. or more and 1200 ° C. or less.
  • Appendix 3 The method for producing a nitride semiconductor stacked body according to appendix 1 or 2, preferably, In the first step, the thickness of the aluminum nitride layer is set to 10 nm or more and 500 nm or less.
  • Appendix 4 A method for producing a nitride semiconductor multilayer structure according to any one of appendices 1 to 3, preferably, In the second step, the first gallium nitride layer is set to 4 ⁇ m or more.
  • Appendix 5 A method for manufacturing a nitride semiconductor multilayer structure according to any one of appendices 1 to 4, preferably, A sapphire substrate is used as the substrate.
  • Appendix 6 A method for manufacturing a nitride semiconductor multilayer structure according to any one of appendices 1 to 5, preferably, A seventh step of forming a gallium nitride layer serving as a self-supporting substrate on the metal film modified to be porous;
  • Appendix 7 The method for manufacturing a nitride semiconductor multilayer body according to appendix 6, preferably, In the seventh step, the gallium nitride layer to be the self-supporting substrate is peeled from the metal film to form the self-supporting substrate.
  • Appendix 8 The method for manufacturing a nitride semiconductor multilayer body according to appendix 7, preferably, In the seventh step, a plurality of the self-supporting substrates are formed from one gallium nitride layer serving as the self-standing substrate by performing a slicing process on the separated gallium nitride layer serving as the self-supporting substrate.
  • a nitride semiconductor stacked body in which a force is applied to the first gallium nitride layer so that the warp generated in the first gallium nitride layer is canceled by the warp generated in the aluminum nitride layer.
  • Appendix 10 The nitride semiconductor stacked body according to appendix 9, preferably, The thickness of the first gallium nitride layer is 4 ⁇ m or more.
  • Appendix 12 The nitride semiconductor stacked body according to any one of appendices 9 to 11, preferably, The substrate is a sapphire substrate.

Abstract

The present invention has: a first step for forming an AlN layer on a substrate; a second step for forming a first GaN layer on the AlN layer; a third step for forming an Al-containing III nitride semiconductor layer on the first GaN layer; a fourth step for forming a second GaN layer on the III nitride semiconductor layer; a fifth step for forming a metal film on the second GaN layer; and a sixth step for performing treatment for modifying the second GaN layer and the metal film to be porous. Each of the first to fourth steps is performed by means of an HVPE method.

Description

窒化物半導体積層体の製造方法及び窒化物半導体積層体Nitride semiconductor laminate manufacturing method and nitride semiconductor laminate
　本発明は、窒化物半導体積層体の製造方法及び窒化物半導体積層体に関する。 The present invention relates to a method for manufacturing a nitride semiconductor multilayer body and a nitride semiconductor multilayer body.
　従来より、自立基板としての窒化ガリウム（ＧａＮ）基板の形成方法として、例えばＶＡＳ法（Ｖｏｉｄ－ａｓｓｉｓｔｅｄ　Ｍｅｔｈｏｄ）が用いられることがある。ＶＡＳ法では、下地基板上に自立基板となるＧａＮ層を形成し、下地基板とＧａＮ層とを剥離することで自立基板が形成される。この下地基板として、基板上に設けられた第１のＧａＮ層と、第１のＧａＮ層上に設けられた窒化アルミニウムガリウム（ＡｌＧａＮ）層と、ＡｌＧａＮ層上に設けられた第２のＧａＮ層と、第２のＧａＮ層上に設けられた金属膜（例えばＴｉＮ膜）と、を備え、第２のＧａＮ層及び金属膜が、空隙（ボイド）が形成されることで多孔質になっている窒化物半導体積層体が用いられることがある（例えば特許文献１参照）。この窒化物半導体積層体では、第１のＧａＮ層、ＡｌＧａＮ層及び第２のＧａＮ層はそれぞれ、ＭＯＶＰＥ（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｖａｐｏｒ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）法により形成（成膜、成長）されている。 Conventionally, as a method for forming a gallium nitride (GaN) substrate as a self-supporting substrate, for example, a VAS method (Void-assisted Method) is sometimes used. In the VAS method, a self-standing substrate is formed by forming a GaN layer as a self-supporting substrate on a base substrate and peeling the base substrate and the GaN layer. As the base substrate, a first GaN layer provided on the substrate, an aluminum gallium nitride (AlGaN) layer provided on the first GaN layer, and a second GaN layer provided on the AlGaN layer, And a metal film (for example, a TiN film) provided on the second GaN layer, and the second GaN layer and the metal film are made porous by forming voids. A physical semiconductor laminate may be used (see, for example, Patent Document 1). In this nitride semiconductor multilayer body, the first GaN layer, the AlGaN layer, and the second GaN layer are each formed (film formation, growth) by a MOVPE (Metal Organic Vapor Phase Epitaxy) method.
特開２００４－３１９７１１号公報JP 2004-319711 A
　窒化物半導体積層体が備える各層をそれぞれＭＯＶＰＥ法により形成することで、例えば第１のＧａＮ層の厚さを２～３μｍ程度と薄くしても、第２のＧａＮ層の表面に現れるピット等のマクロ欠陥を十分に低減させることができる。しかしながら、ＭＯＶＰＥ法による窒化物半導体の成長速度はせいぜい数μｍ／時と遅いため、各層をＭＯＶＰＥ法により形成すると、窒化物半導体積層体の生産性が非常に低くなるという課題がある。その結果、ＶＡＳ法による自立基板の生産性が低下することがある。 By forming each layer included in the nitride semiconductor multilayer body by the MOVPE method, pits appearing on the surface of the second GaN layer, for example, even if the thickness of the first GaN layer is reduced to about 2 to 3 μm. Macro defects can be sufficiently reduced. However, since the growth rate of the nitride semiconductor by the MOVPE method is as low as several μm / hour at most, there is a problem that when each layer is formed by the MOVPE method, the productivity of the nitride semiconductor stacked body becomes very low. As a result, the productivity of free standing substrates by the VAS method may be reduced.
　本発明は、上記課題を解決するために、成長速度が数～数１０ｍｍ／時とＭＯＶＰＥ法よりも高いＨＶＰＥ（Ｈｙｄｒｉｄｅ　Ｖａｐｏｒ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）法を用いることで、ＶＡＳ法により自立基板を形成する際に下地基板として用いられる窒化物半導体積層体の生産性、自立基板の生産性を向上させる技術を提供することを目的とする。 In order to solve the above-mentioned problems, the present invention uses a HVPE (Hydride Vapor Phase Epitaxy) method with a growth rate of several to several tens of mm / hour, which is higher than the MOVPE method, to form a free-standing substrate by the VAS method. An object of the present invention is to provide a technique for improving the productivity of a nitride semiconductor laminated body used as a base substrate and the productivity of a free-standing substrate.
　本発明の一態様によれば、
　基板上に窒化アルミニウム層を形成する第１の工程と、
　前記窒化アルミニウム層上に第１の窒化ガリウム層を形成する第２の工程と、
　前記第１の窒化ガリウム層上に、アルミニウムを含むＩＩＩ族窒化物半導体層を形成する第３の工程と、
　前記ＩＩＩ族窒化物半導体層上に、第２の窒化ガリウム層を形成する第４の工程と、
　前記第２の窒化ガリウム層上に、金属膜を形成する第５の工程と、
　前記第２の窒化ガリウム層及び前記金属膜を多孔質に改質する処理を行う第６の工程と、を有し、
　前記第１～第４の各工程をそれぞれ、ＨＶＰＥ法により行う窒化物半導体積層体の製造方法が提供される。 According to one aspect of the invention,
A first step of forming an aluminum nitride layer on the substrate;
A second step of forming a first gallium nitride layer on the aluminum nitride layer;
A third step of forming a group III nitride semiconductor layer containing aluminum on the first gallium nitride layer;
A fourth step of forming a second gallium nitride layer on the group III nitride semiconductor layer;
A fifth step of forming a metal film on the second gallium nitride layer;
A sixth step of performing a treatment for modifying the second gallium nitride layer and the metal film to be porous,
There is provided a method for manufacturing a nitride semiconductor multilayer body in which the first to fourth steps are each performed by an HVPE method.
　本発明の他の態様によれば、
　基板上に設けられた窒化アルミニウム層と、
　前記窒化アルミニウム層上に設けられた第１の窒化ガリウム層と、
　前記第１の窒化ガリウム層上に設けられたアルミニウムを含むＩＩＩ族窒化物半導体層と、
　前記ＩＩＩ族窒化物半導体層上に設けられ、多孔質な第２の窒化ガリウム層と、
　前記第２の窒化ガリウム層上に設けられ、多孔質な金属膜と、を備え、
　前記窒化アルミニウム層に生じた反りによって、前記第１の窒化ガリウム層に生じた反りが打ち消されるような力が前記第１の窒化ガリウム層に加えられている窒化物半導体積層体が提供される。 According to another aspect of the invention,
An aluminum nitride layer provided on the substrate;
A first gallium nitride layer provided on the aluminum nitride layer;
A group III nitride semiconductor layer containing aluminum provided on the first gallium nitride layer;
A porous second gallium nitride layer provided on the group III nitride semiconductor layer; and
A porous metal film provided on the second gallium nitride layer,
There is provided a nitride semiconductor stacked body in which a force is applied to the first gallium nitride layer so that the warp generated in the first gallium nitride layer is canceled by the warp generated in the aluminum nitride layer.
　本発明によれば、ＶＡＳ法により自立基板を形成する際に下地基板として用いられる窒化物半導体積層体の生産性、自立基板の生産性を向上させる技術を提供することができる。 According to the present invention, it is possible to provide a technique for improving the productivity of a nitride semiconductor stacked body used as a base substrate when forming a freestanding substrate by the VAS method, and the productivity of a freestanding substrate.
本発明の一実施形態にかかる窒化物半導体積層体の縦断面概略図を示す。The longitudinal cross-sectional schematic of the nitride semiconductor laminated body concerning one Embodiment of this invention is shown. 本発明の一実施形態にかかる窒化物半導体積層体及びＧａＮ自立基板の製造工程の一例を示す図である。It is a figure which shows an example of the manufacturing process of the nitride semiconductor laminated body concerning one Embodiment of this invention, and a GaN self-supporting substrate.
（発明者等が得た知見）
　本発明の実施形態の説明に先立ち、本発明者等が得た知見について説明する。ＶＡＳ法により自立基板を形成する際に下地基板として用いられる窒化物半導体積層体の生産性を向上させるために、窒化物半導体積層体の各層を成長速度の遅いＭＯＶＰＥ法ではなく、ＭＯＶＰＥ法よりも成長速度が速い、例えばＨＶＰＥ法により形成（成膜）することが考えられている。しかしながら、窒化物半導体積層体の各層の成膜方法を、ＭＯＶＰＥ法からＨＶＰＥ法に単純に変更するだけでは、窒化物半導体積層体の生産性を向上させることが難しいことがある。 (Knowledge obtained by the inventors)
Prior to the description of the embodiments of the present invention, the knowledge obtained by the present inventors will be described. In order to improve the productivity of the nitride semiconductor laminate used as a base substrate when forming a free-standing substrate by the VAS method, each layer of the nitride semiconductor laminate is not grown by the MOVPE method, which is slower than the MOVPE method. It is considered to form (film formation) by a high growth rate, for example, HVPE. However, it may be difficult to improve the productivity of the nitride semiconductor multilayer body by simply changing the method of forming each layer of the nitride semiconductor multilayer body from the MOVPE method to the HVPE method.
　具体的には、ＨＶＰＥ法はＭＯＶＰＥ法に比べて結晶成長の制御性に劣る。このため、例えば、ＨＶＰＥ法により、上述のような厚さが２～３μｍ程度の第１のＧａＮ層を形成すると、第２のＧａＮ層の表面（上面）に現れる１μｍ弱～数μｍ径のピット等のマクロ欠陥を十分に低減させることができないことがある。その結果、第２のＧａＮ層上に設けられる金属膜が剥がれることがある。例えば、蒸着により金属膜を形成している際に、金属膜が剥がれてしまったり、金属膜を多孔質な膜に改質する処理を行っている際に金属膜が剥がれてしまうことがある。その結果、窒化物半導体基板の歩留りが低くなることがある。つまり、窒化物半導体積層体の各層をＨＶＰＥ法により形成した場合であっても、窒化物半導体積層体の生産性が低下してしまうことがある。 Specifically, the HVPE method is inferior in crystal growth controllability compared to the MOVPE method. Therefore, for example, when the first GaN layer having a thickness of about 2 to 3 μm as described above is formed by the HVPE method, a pit having a diameter of slightly less than 1 μm to several μm appears on the surface (upper surface) of the second GaN layer. In some cases, it is not possible to sufficiently reduce such macro defects. As a result, the metal film provided on the second GaN layer may be peeled off. For example, the metal film may be peeled off when the metal film is formed by vapor deposition, or the metal film may be peeled off during the process of modifying the metal film into a porous film. As a result, the yield of the nitride semiconductor substrate may be lowered. That is, even when each layer of the nitride semiconductor multilayer body is formed by the HVPE method, the productivity of the nitride semiconductor multilayer body may be reduced.
　このようなマクロ欠陥を低減するためには、ＨＶＰＥ法で第１のＧａＮ層を形成する際に、第１のＧａＮ層の厚さを、ＭＯＶＰＥ法で形成する場合よりも厚くすることが考えられる。例えば、第１のＧａＮ層の厚さを４μｍ以上にすることが考えられる。これにより、第１のＧａＮ層をＨＶＰＥ法により形成した場合であっても、第２のＧａＮ層の表面に現れるマクロ欠陥を十分に低減させることができる。例えば、第１のＧａＮ層を、ＭＯＶＰＥ法で形成した場合と同程度まで、第２のＧａＮ層の表面に現れるマクロ欠陥を低減させることができる。 In order to reduce such macro defects, it can be considered that when the first GaN layer is formed by the HVPE method, the thickness of the first GaN layer is made thicker than when the GaN layer is formed by the MOVPE method. . For example, the thickness of the first GaN layer may be 4 μm or more. Thereby, even when the first GaN layer is formed by the HVPE method, the macro defects appearing on the surface of the second GaN layer can be sufficiently reduced. For example, macro defects appearing on the surface of the second GaN layer can be reduced to the same extent as when the first GaN layer is formed by the MOVPE method.
　しかしながら、第１のＧａＮ層の厚さが厚くなるほど、第１のＧａＮ層中において歪が増大する傾向にある。このため、基板と第１のＧａＮ層を含む所定の窒化物半導体（窒化物半導体層）とを有する窒化物半導体積層体が大きく反ることがある。例えば、２インチの基板上に所定の窒化物半導体を設けることで形成された窒化物半導体積層体は、第１のＧａＮ層の厚さが４μｍの場合で、室温での反り量が典型的には６０μｍ以上になる。この反りの起源は、窒化物半導体の熱膨張率と基板であるサファイアの熱膨張率との差に起因する。このため、室温では大きな反り量を持つ窒化物半導体積層体であっても、窒化物半導体積層体を構成する各層を成長させる温度（成長温度）である１０００℃付近では反り量はほぼ０になる。 However, as the thickness of the first GaN layer increases, the strain in the first GaN layer tends to increase. For this reason, a nitride semiconductor multilayer body having a substrate and a predetermined nitride semiconductor (nitride semiconductor layer) including the first GaN layer may be greatly warped. For example, a nitride semiconductor laminate formed by providing a predetermined nitride semiconductor on a 2 inch substrate typically has a warpage amount at room temperature when the thickness of the first GaN layer is 4 μm. Becomes 60 μm or more. The origin of this warp is due to the difference between the thermal expansion coefficient of the nitride semiconductor and the thermal expansion coefficient of sapphire as the substrate. For this reason, even if the nitride semiconductor multilayer body has a large amount of warpage at room temperature, the amount of warpage is almost zero at around 1000 ° C., which is the temperature (growth temperature) for growing each layer constituting the nitride semiconductor multilayer body. .
　ＶＡＳ法により自立基板を形成する際に、下地基板として、室温で大きな反りが生じている窒化物半導体積層体が用いられた場合、下地基板上に例えば自立基板となるＧａＮ層（以下、「ＧａＮ自立基板層」とも言う。）を形成（成膜）する際に、下地基板（窒化物半導体積層体）が割れることがある。下地基板の割れのほとんどは、室温から成長温度である１０００℃までの昇温過程で生じる。大きな歪を有する窒化物半導体を有する窒化物半導体積層体、つまり室温で大きく反っている窒化物半導体積層体ほど、割れやすい傾向にある。昇温過程で下地基板が割れた場合、下地基板上に形成されるＧａＮ自立基板にも割れが引き継がれるため、ＧａＮ自立基板層の成長歩留りが低下する、つまりＧａＮ自立基板の生産性が低下する。 When forming a self-supporting substrate by the VAS method, if a nitride semiconductor laminate having a large warp at room temperature is used as the base substrate, for example, a GaN layer (hereinafter referred to as “GaN layer” to be a self-supporting substrate on the base substrate. The base substrate (nitride semiconductor laminate) may be cracked when forming (film formation)). Most of the cracks in the base substrate occur during the temperature rising process from room temperature to 1000 ° C. which is the growth temperature. A nitride semiconductor multilayer body including a nitride semiconductor having a large strain, that is, a nitride semiconductor multilayer body greatly warped at room temperature tends to be easily broken. If the base substrate is cracked during the temperature rising process, the crack is also taken over by the GaN free-standing substrate formed on the base substrate, so that the growth yield of the GaN free-standing substrate layer is reduced, that is, the productivity of the GaN free-standing substrate is reduced. .
　そこで、本発明者等は、窒化物半導体積層体に第１のＧａＮ層に生じる反りの方向と反対方向に反る層を設けることで、ＨＶＰＥ法を用いた場合であっても、窒化物半導体積層体全体に生じる反りを低減することができることを見出した。本発明は、発明者等が見出した上記知見に基づくものである。 Therefore, the present inventors have provided a nitride semiconductor stack with a layer that warps in a direction opposite to the direction of warpage that occurs in the first GaN layer, so that the nitride semiconductor can be used even when the HVPE method is used. It has been found that the warpage occurring in the entire laminate can be reduced. The present invention is based on the above findings found by the inventors.
＜本発明の一実施形態＞
（１）窒化物半導体積層体の構成
　以下に、本発明の一実施形態にかかる窒化物半導体積層体について、図１を参照しながら説明する。 <One Embodiment of the Present Invention>
(1) Configuration of Nitride Semiconductor Stack A nitride semiconductor stack according to an embodiment of the present invention will be described below with reference to FIG.
　図１に示すように、窒化物半導体積層体１は、基板２を備えている。基板２としては、例えばサファイア、シリコン、ＳｉＣ、ランガサイト、二ホウ化ジルコニウム、ヒ化ガリウム（ＧａＡｓ）からなる基板を用いることができる。これらの中でも、基板２として、後述のＡｌＮ層３とＧａＮ層（第１のＧａＮ層４、第２のＧａＮ層６）との格子定数の観点から、サファイア基板が用いられることがより好ましい。 As shown in FIG. 1, the nitride semiconductor multilayer body 1 includes a substrate 2. As the substrate 2, for example, a substrate made of sapphire, silicon, SiC, langasite, zirconium diboride, or gallium arsenide (GaAs) can be used. Among these, a sapphire substrate is more preferably used as the substrate 2 from the viewpoint of lattice constants of an AlN layer 3 and a GaN layer (first GaN layer 4 and second GaN layer 6) described later.
　基板２のいずれかの主面上には、ＡｌＮ層３が設けられている。ＡｌＮ層３には反りが生じている。例えば、ＡｌＮ層３には、中心（中心部）が最も低くなるような反りが生じている。つまり、ＡｌＮ層３は例えば凹形状（お椀型）に反っている。 An AlN layer 3 is provided on any main surface of the substrate 2. The AlN layer 3 is warped. For example, the AlN layer 3 is warped such that the center (center portion) is the lowest. That is, the AlN layer 3 warps, for example, a concave shape (a bowl shape).
　ＡｌＮ層３の厚さは、ＡｌＮ層３を十分に反らせることができる厚さであることが好ましい。ＡｌＮ層３の厚さは、例えば１０ｎｍ以上５００ｎｍ以下であることが好ましい。 It is preferable that the thickness of the AlN layer 3 is a thickness that can sufficiently warp the AlN layer 3. The thickness of the AlN layer 3 is preferably 10 nm or more and 500 nm or less, for example.
　ＡｌＮ層３の厚さが１０ｎｍ未満であると、ＡｌＮ層３を十分に反らせることができないことがある。ＡｌＮ層３の厚さを１０ｎｍ以上にすることで、ＡｌＮ層３を十分に反らせることができる。 If the thickness of the AlN layer 3 is less than 10 nm, the AlN layer 3 may not be sufficiently warped. By making the thickness of the AlN layer 3 10 nm or more, the AlN layer 3 can be sufficiently warped.
　しかしながら、ＡｌＮ層３の厚さが５００ｎｍを超えると、ＨＶＰＥ法によりＡｌＮ層３を形成した場合であっても、ＡｌＮ層３の形成に時間がかかるため、窒化物半導体積層体１の生産性が低下することがある。ＡｌＮ層３の厚さを５００ｎｍ以下にすることで、これを解決し、窒化物半導体積層体１の生産性の低下を抑制することができる。 However, if the thickness of the AlN layer 3 exceeds 500 nm, it takes time to form the AlN layer 3 even when the AlN layer 3 is formed by the HVPE method. May decrease. By making the thickness of the AlN layer 3 500 nm or less, this can be solved, and the decrease in productivity of the nitride semiconductor multilayer body 1 can be suppressed.
　なお、ＡｌＮ層３は、サファイア基板と後述の第１のＧａＮ層４との間の格子定数の不整合を緩衝するバッファ層としても機能する。 The AlN layer 3 also functions as a buffer layer that buffers a mismatch in lattice constant between the sapphire substrate and the first GaN layer 4 described later.
　ＡｌＮ層３上には、第１のＧａＮ層４が設けられている。第１のＧａＮ層４は、後述の第２のＧａＮ層６の下地層として機能し、第２のＧａＮ層６の低転位化を図ることができる。第１のＧａＮ層４には、反りが生じている。例えば、第１のＧａＮ層４には、中心（中心部）が最も高くなるような反りが生じている。つまり、第１のＧａＮ層４は例えば凸形状（ドーム型）になるように反っている。このように、第１のＧａＮ層４には、ＡｌＮ層３に生じた反りとは反対方向の反りが生じている。 The first GaN layer 4 is provided on the AlN layer 3. The first GaN layer 4 functions as an underlayer for the second GaN layer 6 described later, and the dislocation of the second GaN layer 6 can be reduced. The first GaN layer 4 is warped. For example, the first GaN layer 4 is warped such that the center (center portion) is the highest. That is, the first GaN layer 4 is warped to have a convex shape (dome shape), for example. Thus, the first GaN layer 4 is warped in the opposite direction to the warp generated in the AlN layer 3.
　第１のＧａＮ層４の厚さは、例えば４μｍ以上であることが好ましい。第１のＧａＮ層４を例えばＨＶＰＥ法により形成した場合、第１のＧａＮ層４の厚さが４μｍ未満であると、後述の第２のＧａＮ層６の表面（上面）に現れるピット等のマクロ欠陥を十分に低減させることができないことがある。例えば、第２のＧａＮ層６の表面におけるマクロ欠陥密度を十分に低減することができないことがある。第１のＧａＮ層４の厚さを４μｍ以上にすることで、第１のＧａＮ層４を例えばＨＶＰＥ法により形成した場合であっても、第２のＧａＮ層６の表面に現れるマクロ欠陥を十分に低減させることができる。 The thickness of the first GaN layer 4 is preferably 4 μm or more, for example. When the first GaN layer 4 is formed by, for example, the HVPE method, if the thickness of the first GaN layer 4 is less than 4 μm, macros such as pits appearing on the surface (upper surface) of the second GaN layer 6 described later. Defects may not be reduced sufficiently. For example, the macro defect density on the surface of the second GaN layer 6 may not be sufficiently reduced. By setting the thickness of the first GaN layer 4 to 4 μm or more, macro defects appearing on the surface of the second GaN layer 6 are sufficiently obtained even when the first GaN layer 4 is formed by, for example, the HVPE method. Can be reduced.
　上述したように、第１のＧａＮ層４には、ＡｌＮ層３に生じた反りとは反対方向の反りが生じている。従って、ＡｌＮ層３が反ることで、第１のＧａＮ層４に生じた反りを打ち消すような力を第１のＧａＮ層４に加えることができる。つまり、第１のＧａＮ層４に生じた反りの方向とは反対方向の力、例えば第１のＧａＮ層４が平坦になるような力を、第１のＧａＮ層に加えることができる。また、第１のＧａＮ層４が反ることで、ＡｌＮ層３に生じた反りを打ち消すような力をＡｌＮ層３に加えることができる。つまり、ＡｌＮ層３に生じた反りの方向とは反対方向の力、例えばＡｌＮ層３が平坦になるような力を、ＡｌＮ層３に加えることができる。このように、ＡｌＮ層３及び第１のＧａＮ層４がそれぞれ反ることで、互いの層にそれぞれ生じた反りを打ち消すような力を互いの層に加えることができる。例えば、ＡｌＮ層３に生じた反りによって第１のＧａＮ層４に生じた反りを相殺することができる。その結果、窒化物半導体積層体１全体での反り量（応力）を低減することができる。 As described above, the first GaN layer 4 is warped in the opposite direction to the warp generated in the AlN layer 3. Accordingly, the warping of the AlN layer 3 can apply a force to the first GaN layer 4 so as to cancel the warp generated in the first GaN layer 4. That is, a force in a direction opposite to the direction of warpage generated in the first GaN layer 4, for example, a force that flattens the first GaN layer 4 can be applied to the first GaN layer. Further, when the first GaN layer 4 is warped, a force can be applied to the AlN layer 3 so as to cancel the warp generated in the AlN layer 3. That is, a force in a direction opposite to the direction of warping generated in the AlN layer 3, for example, a force that flattens the AlN layer 3 can be applied to the AlN layer 3. As described above, the AlN layer 3 and the first GaN layer 4 are warped, so that a force that cancels the warpage generated in each layer can be applied to each layer. For example, the warp generated in the first GaN layer 4 by the warp generated in the AlN layer 3 can be offset. As a result, the amount of warpage (stress) in the entire nitride semiconductor multilayer body 1 can be reduced.
　第１のＧａＮ層４上には、アルミニウム（Ａｌ）を含むＩＩＩ族窒化物半導体層５が設けられている。ＩＩＩ族窒化物半導体層５は、後述の金属膜７を多孔質な膜に改質する処理（以下では、単に「改質処理」とも言う。）を行う際に第１のＧａＮ層４に空隙（ボイド）が形成されることを阻止する層（空隙形成阻止層）として機能する。例えば、ＩＩＩ族窒化物半導体層５は、改質処理によって第１のＧａＮ層４からＮ（窒素元素）が脱離することを抑制する層として機能する。また、ＩＩＩ族窒化物半導体層５は、後述の第２のＧａＮ層６に形成されるボイドの肥大化を抑制する層としても機能する。 A group III nitride semiconductor layer 5 containing aluminum (Al) is provided on the first GaN layer 4. The group III nitride semiconductor layer 5 has voids in the first GaN layer 4 when a process for modifying the metal film 7 described later into a porous film (hereinafter also simply referred to as “modification process”) is performed. It functions as a layer (void formation preventing layer) that prevents (void) from being formed. For example, the group III nitride semiconductor layer 5 functions as a layer that suppresses desorption of N (nitrogen element) from the first GaN layer 4 due to the modification treatment. The group III nitride semiconductor layer 5 also functions as a layer that suppresses the enlargement of voids formed in the second GaN layer 6 described later.
　Ａｌを含むＩＩＩ族窒化物半導体層５として、例えば組成がＡｌｘＧａ１－ｘＮ（０．０１≦ｘ≦１）からなる層が設けられていることが好ましい。 As the group III nitride semiconductor layer 5 containing Al, for example, a layer having a composition of Al x Ga 1-x N (0.01 ≦ x ≦ 1) is preferably provided.
　後述の改質処理によって、ＩＩＩ族窒化物半導体層５中にもボイドが形成される。この際、ｘの値が０．０１未満であると、ＩＩＩ族窒化物半導体層５中に、その厚さ方向に貫通するボイドが形成されることがある。つまり、ＩＩＩ族窒化物半導体層５に、貫通孔が形成されることがある。その結果、ＩＩＩ族窒化物半導体層５が空隙形成抑制層として機能しないことがある。つまり、後述の改質処理を行っている際、ＩＩＩ族窒化物半導体層５に形成された貫通孔から露出した第１のＧａＮ層４の箇所を介して、第１のＧａＮ層４中にもボイドが形成されてしまうことがある。 Voids are also formed in the group III nitride semiconductor layer 5 by the modification process described later. At this time, if the value of x is less than 0.01, a void penetrating in the thickness direction may be formed in the group III nitride semiconductor layer 5 in some cases. That is, a through hole may be formed in the group III nitride semiconductor layer 5. As a result, the group III nitride semiconductor layer 5 may not function as a void formation suppression layer. That is, during the modification process described later, the first GaN layer 4 is also exposed to the first GaN layer 4 through the portion of the first GaN layer 4 exposed from the through hole formed in the group III nitride semiconductor layer 5. Voids may be formed.
　ｘの値を０．０１以上にすることで、後述の改質処理により、ＩＩＩ族窒化物半導体層５に貫通孔が形成されることを抑制することができる。 By setting the value of x to 0.01 or more, it is possible to suppress the formation of through holes in the group III nitride semiconductor layer 5 by the modification process described later.
　なお、ｘの値は１であっても良い。つまり、ＩＩＩ族窒化物半導体層５としてＡｌＮ層が設けられていてもよい。しかしながら、ＩＩＩ族窒化物半導体層５と、第１のＧａＮ層４、後述の第２のＧａＮ層６と、の間の格子定数の差を小さくする観点から、ＩＩＩ族窒化物半導体層５としてｘの値が１未満であるＡｌＧａＮ層が設けられていることがより好ましい。 Note that the value of x may be 1. That is, an AlN layer may be provided as the group III nitride semiconductor layer 5. However, from the viewpoint of reducing the difference in lattice constant between the group III nitride semiconductor layer 5, the first GaN layer 4, and the second GaN layer 6 described later, the group III nitride semiconductor layer 5 is x More preferably, an AlGaN layer having a value of less than 1 is provided.
　ＩＩＩ族窒化物半導体層５の厚さは、後述の改質処理によって、ＩＩＩ族窒化物半導体層５に貫通孔が形成されない厚さに形成されていることが好ましい。例えば、ＩＩＩ族窒化物半導体層５の厚さが３ｎｍ以上であることが好ましい。 The thickness of the group III nitride semiconductor layer 5 is preferably formed to a thickness at which no through hole is formed in the group III nitride semiconductor layer 5 by a modification process described later. For example, the thickness of the group III nitride semiconductor layer 5 is preferably 3 nm or more.
　ＩＩＩ族窒化物半導体層５の厚さが３ｎｍ未満であると、後述の改質処理によって、ＩＩＩ族窒化物半導体層５に貫通孔が形成されることがある。ＩＩＩ族窒化物半導体層５の厚さを３ｎｍ以上にすることで、後述の改質処理によって、ＩＩＩ族窒化物半導体層５に貫通孔が形成されることをより確実に抑制することができる。 If the thickness of the group III nitride semiconductor layer 5 is less than 3 nm, through holes may be formed in the group III nitride semiconductor layer 5 by a modification process described later. By setting the thickness of group III nitride semiconductor layer 5 to 3 nm or more, formation of a through hole in group III nitride semiconductor layer 5 can be more reliably suppressed by a modification process described later.
　なお、ＩＩＩ族窒化物半導体層５の厚さの上限値は、特に限定されない。しかしながら、ＩＩＩ族窒化物半導体層５の厚さが厚くなるほど、Ａｌを含むＩＩＩ族窒化物半導体層５と第１のＧａＮ層４との格子不整合による歪が大きくなり、ＩＩＩ族窒化物半導体層５を成長させている際にＩＩＩ族窒化物半導体層５にクラック（割れ）が生じる場合がある。このため、ＩＩＩ族窒化物半導体層５の厚さは、ＩＩＩ族窒化物半導体層５の組成に対応したクラックを生じない厚さ（臨界膜厚）以下とすることが好ましい。 Note that the upper limit of the thickness of the group III nitride semiconductor layer 5 is not particularly limited. However, as the thickness of the group III nitride semiconductor layer 5 increases, strain due to lattice mismatch between the group III nitride semiconductor layer 5 containing Al and the first GaN layer 4 increases, and the group III nitride semiconductor layer When growing 5, the group III nitride semiconductor layer 5 may be cracked. Therefore, the thickness of group III nitride semiconductor layer 5 is preferably set to a thickness (critical film thickness) or less that does not cause a crack corresponding to the composition of group III nitride semiconductor layer 5.
　ＩＩＩ族窒化物半導体層５上には、所定厚さ（例えば数１００ｎｍ）の第２のＧａＮ層６が設けられている。第２のＧａＮ層６には、後述の改質処理によってボイドが形成されている。つまり、第２のＧａＮ層６は多孔質な層になっている。 On the group III nitride semiconductor layer 5, a second GaN layer 6 having a predetermined thickness (for example, several 100 nm) is provided. Voids are formed in the second GaN layer 6 by a modification process described later. That is, the second GaN layer 6 is a porous layer.
　第２のＧａＮ層６上には、金属膜７が設けられている。金属膜７にはボイドが形成されている。つまり、金属膜７は多孔質な膜になっている。金属膜７中に含まれる金属としては、例えば、チタン、バナジウム、クロム、マンガン、鉄、コバルト、ニッケル、銅、イットリウム、ジルコニウム、ニオブ、モリブデン、テルル、ルテニウム、ロジウム、パラジウム、ハフニウム、タンタル、タングステン、レニウム、オスミウム、イリジウム、白金、金等を用いることができる。金属膜７として、例えば窒化チタン（ＴｉＮ）膜が設けられている。 A metal film 7 is provided on the second GaN layer 6. Voids are formed in the metal film 7. That is, the metal film 7 is a porous film. Examples of the metal contained in the metal film 7 include titanium, vanadium, chromium, manganese, iron, cobalt, nickel, copper, yttrium, zirconium, niobium, molybdenum, tellurium, ruthenium, rhodium, palladium, hafnium, tantalum, and tungsten. , Rhenium, osmium, iridium, platinum, gold and the like can be used. As the metal film 7, for example, a titanium nitride (TiN) film is provided.
　金属膜７の厚さは例えば１００ｎｍ以下であることが好ましく、３０ｎｍ以下であることがより好ましい。金属膜７の厚さが１００ｎｍを超えると、金属膜７を多孔質な膜に改質する処理に時間がかかり、窒化物半導体積層体１の生産性が低下することがある。金属膜７の厚さを１００ｎｍ以下にすることで、これを解決でき、窒化物半導体積層体１の生産性の低下をより抑制することができる。金属膜７の厚さを３０ｎｍ以下にすることで、窒化物半導体積層体１の生産性の低下をさらに抑制することができる。なお、金属膜７の厚さの下限値は特に限定されないが、例えば１ｎｍ以上であることが好ましい。 The thickness of the metal film 7 is preferably 100 nm or less, for example, and more preferably 30 nm or less. If the thickness of the metal film 7 exceeds 100 nm, it takes time to modify the metal film 7 into a porous film, and the productivity of the nitride semiconductor multilayer body 1 may be reduced. By setting the thickness of the metal film 7 to 100 nm or less, this can be solved, and the decrease in productivity of the nitride semiconductor multilayer body 1 can be further suppressed. By reducing the thickness of the metal film 7 to 30 nm or less, it is possible to further suppress a decrease in productivity of the nitride semiconductor multilayer body 1. The lower limit of the thickness of the metal film 7 is not particularly limited, but is preferably 1 nm or more, for example.
（２）窒化物半導体積層体の製造方法
　次に、本実施形態にかかる窒化物半導体積層体１及びＧａＮ自立基板の製造方法の一実施形態について、図２を用いて説明する。 (2) Method for Manufacturing Nitride Semiconductor Stack Next, an embodiment of a method for manufacturing the nitride semiconductor stack 1 and the GaN free-standing substrate according to the present embodiment will be described with reference to FIG.
（第１の工程）
　基板２（例えばサファイア基板上）に、ＡｌＮ層３を形成する第１の工程を行う。第１の工程では、ハイドライド気相成長（ＨＶＰＥ：Ｈｙｄｒｉｄｅ　Ｖａｐｏｒ　Ｐｈａｓｅ　Ｅｐｉｔａｘｙ）装置を用い、ＨＶＰＥ法によりＡｌＮ層３を形成する。 (First step)
A first step of forming the AlN layer 3 on the substrate 2 (for example, on the sapphire substrate) is performed. In the first step, the AlN layer 3 is formed by the HVPE method using a hydride vapor phase epitaxy (HVPE) apparatus.
　第１の工程では、高温の雰囲気下でＡｌＮ層３を形成することが好ましい。具体的には、ＡｌＮ層３の形成温度（成長温度）を、緻密なＡｌＮ層３を形成することができる温度にすることが好ましい。例えば、ＡｌＮ層３の成長温度を８００℃以上１２００℃以下にすることが好ましく、１０００℃程度にすることがより好ましい。 In the first step, it is preferable to form the AlN layer 3 in a high temperature atmosphere. Specifically, the formation temperature (growth temperature) of the AlN layer 3 is preferably set to a temperature at which the dense AlN layer 3 can be formed. For example, the growth temperature of the AlN layer 3 is preferably 800 ° C. or higher and 1200 ° C. or lower, and more preferably about 1000 ° C.
　ＡｌＮ層３の成長温度が８００℃未満であると、ＡｌＮ層３を緻密な層にできない場合がある。その結果、ＡｌＮ層３が降温した際に、ＡｌＮ層３を十分に反らせることができないことがある。ＡｌＮ層３の成長温度を８００℃以上にすることで、ＡｌＮ層３を十分に緻密な層にすることができる。その結果、ＡｌＮ層３を十分に反らせることができる。ＡｌＮ層３の成長温度が１２００℃を超えると、ＡｌＮ層３が成長する前にサファイア基板の表面が荒れてしまう。このため、サファイア基板の表面上に成長するＡｌＮ層の結晶配向性が低下することがある。ＡｌＮ層３の成長温度を１２００℃以下にすることで、ＡｌＮ層３の結晶配向性の低下を防止することができる。 If the growth temperature of the AlN layer 3 is less than 800 ° C., the AlN layer 3 may not be a dense layer. As a result, when the temperature of the AlN layer 3 drops, the AlN layer 3 may not be sufficiently warped. By setting the growth temperature of the AlN layer 3 to 800 ° C. or higher, the AlN layer 3 can be made sufficiently dense. As a result, the AlN layer 3 can be sufficiently warped. When the growth temperature of the AlN layer 3 exceeds 1200 ° C., the surface of the sapphire substrate becomes rough before the AlN layer 3 grows. For this reason, the crystal orientation of the AlN layer grown on the surface of the sapphire substrate may be lowered. By setting the growth temperature of the AlN layer 3 to 1200 ° C. or less, it is possible to prevent the crystal orientation of the AlN layer 3 from being lowered.
　また、第１の工程では、ＡｌＮ層３の厚さを例えば１０ｎｍ以上５００ｎｍ以下にすることが好ましい。ＡｌＮ層３の厚さの調整は、例えばＡｌ（例えばＡｌ融液）とＨＣｌガスとを反応させて生成した塩化アルミニウム（ＡｌＣｌ３）ガスを用いてＡｌＮ層３を成長させる際に用いられるＨＣｌガスを流用してＡｌＮ層３をエッチングすることで行うことができる。また、ＡｌＮ層３の成膜時間を調整することでＡｌＮ層３の厚さの調整を行ってもよい。 In the first step, it is preferable that the thickness of the AlN layer 3 is, for example, not less than 10 nm and not more than 500 nm. For adjusting the thickness of the AlN layer 3, for example, HCl gas used when the AlN layer 3 is grown by using aluminum chloride (AlCl 3 ) gas generated by reacting Al (for example, Al melt) and HCl gas. This can be performed by etching the AlN layer 3 by diverting the above. Further, the thickness of the AlN layer 3 may be adjusted by adjusting the deposition time of the AlN layer 3.
（第２の工程）
　第１の工程が終了した後、ＡｌＮ層３上に、第１のＧａＮ層４を形成する第２の工程を行う。第２の工程では、ＨＶＰＥ装置を用い、ＨＶＰＥ法により第１のＧａＮ層４を形成する。 (Second step)
After the first step is completed, a second step of forming the first GaN layer 4 on the AlN layer 3 is performed. In the second step, the first GaN layer 4 is formed by HVPE using an HVPE apparatus.
　第２の工程では、第１のＧａＮ層４の厚さを４μｍ以上にすることが好ましい。なお、第１のＧａＮ層４の厚さの調整は、例えば第１のＧａＮ層４の成膜時間を調整することで行うことができる。また、第２の工程では、所定温度（例えば１０００℃程度）の雰囲気下で第１のＧａＮ層４を形成することが好ましい。 In the second step, the thickness of the first GaN layer 4 is preferably 4 μm or more. The thickness of the first GaN layer 4 can be adjusted, for example, by adjusting the film formation time of the first GaN layer 4. In the second step, it is preferable to form the first GaN layer 4 in an atmosphere at a predetermined temperature (for example, about 1000 ° C.).
（第３の工程）
　第２の工程が終了した後、第１のＧａＮ層４上に、Ａｌを含むＩＩＩ族窒化物半導体層５を形成する第３の工程を行う。第３の工程では、ＨＶＰＥ装置を用い、ＨＶＰＥ法によりＩＩＩ族窒化物半導体層５を形成する。第３の工程では、ＩＩＩ族窒化物半導体層５として、例えば組成がＡｌｘＧａ１－ｘＮ（０．０１≦ｘ≦１）からなる層を形成することが好ましい。また、第３の工程では、ＩＩＩ族窒化物半導体層５の厚さを３ｎｍ以上にすることが好ましい。なお、ＩＩＩ族窒化物半導体層５の厚さの調整は、例えばＩＩＩ族窒化物半導体層５の成膜時間を調整することで行うことができる。 (Third step)
After the completion of the second step, a third step of forming a group III nitride semiconductor layer 5 containing Al on the first GaN layer 4 is performed. In the third step, group III nitride semiconductor layer 5 is formed by HVPE using an HVPE apparatus. In the third step, as the group III nitride semiconductor layer 5, for example, a layer having a composition of Al x Ga 1-x N (0.01 ≦ x ≦ 1) is preferably formed. In the third step, the thickness of the group III nitride semiconductor layer 5 is preferably 3 nm or more. The thickness of group III nitride semiconductor layer 5 can be adjusted, for example, by adjusting the film formation time of group III nitride semiconductor layer 5.
（第４の工程）
　第３の工程が終了した後、ＩＩＩ族窒化物半導体層５上に、所定厚さの第２のＧａＮ層６を形成する第４の工程を行う。第４の工程では、ＨＶＰＥ装置を用い、ＨＶＰＥ法により第２のＧａＮ層６を形成する。 (Fourth process)
After the completion of the third step, a fourth step of forming the second GaN layer 6 having a predetermined thickness on the group III nitride semiconductor layer 5 is performed. In the fourth step, the second GaN layer 6 is formed by HVPE using an HVPE apparatus.
（第５の工程）
　第４の工程が終了した後、第２のＧａＮ層６上に、所定厚さの金属膜７を形成する第５の工程を行う。第５の工程では、例えば蒸着により金属膜７としてのＴｉ膜を形成する。これにより、例えば図２（ａ）に示す積層体１Ａが形成される。 (Fifth step)
After the fourth step is completed, a fifth step of forming a metal film 7 having a predetermined thickness on the second GaN layer 6 is performed. In the fifth step, a Ti film as the metal film 7 is formed by vapor deposition, for example. Thereby, for example, a stacked body 1A shown in FIG. 2A is formed.
（第６の工程）
　第５の工程が終了した後、第２のＧａＮ層６及び金属膜７を多孔質に改質する第６の工程を行う。第６の工程では、第２のＧａＮ層６及び金属膜７に対して熱処理を行う。これにより、第２のＧａＮ層６にボイドを形成して多孔質な層に改質するとともに、金属膜７を金属窒化膜に改質することで金属膜７（金属窒化膜）にボイドを形成し、金属膜７を多孔質な膜に改質する。これにより、例えば図２（ｂ）に示す窒化物半導体積層体１が形成される。 (Sixth step)
After the fifth step is completed, a sixth step of modifying the second GaN layer 6 and the metal film 7 to be porous is performed. In the sixth step, heat treatment is performed on the second GaN layer 6 and the metal film 7. As a result, a void is formed in the second GaN layer 6 to be modified into a porous layer, and a void is formed in the metal film 7 (metal nitride film) by modifying the metal film 7 into a metal nitride film. Then, the metal film 7 is modified into a porous film. Thereby, for example, the nitride semiconductor multilayer body 1 shown in FIG. 2B is formed.
（第７の工程）
　第６の工程が終了した後、ＶＡＳ法により自立基板を形成する第７の工程を行う。つまり、第７の工程では、図２（ｃ）に示すように、第６の工程が終了した後、窒化物半導体積層体１を下地基板として用い、下地基板上に、自立基板になるＧａＮ層１０（ＧａＮ自立基板層１０）を形成し、ＧａＮ自立基板を形成する。具体的には、まず、第７の工程では、基板２と、ＡｌＮ層３と、第１のＧａＮ層４と、ＩＩＩ族窒化物半導体層５と、第２のＧａＮ層６と、金属膜７と、を有する窒化物半導体積層体１を下地基板とし、下地基板（多孔質な金属膜７（金属窒化膜））上にＧａＮ自立基板層１０を形成する。その後、下地基板からＧａＮ自立基板層１０を剥離する。なお、ＧａＮ自立基板層１０は、下地基板とＧａＮ自立基板層１０との積層体が所定温度（例えば室温程度）まで降温することで、下地基板から自然に剥離する。この剥離したＧａＮ自立基板層１０がＧａＮ自立基板になる。 (Seventh step)
After the sixth step is completed, a seventh step of forming a free-standing substrate by the VAS method is performed. That is, in the seventh step, as shown in FIG. 2C, after the sixth step is finished, the nitride semiconductor multilayer body 1 is used as a base substrate, and a GaN layer that becomes a free-standing substrate on the base substrate. 10 (GaN free-standing substrate layer 10) is formed, and a GaN free-standing substrate is formed. Specifically, first, in the seventh step, the substrate 2, the AlN layer 3, the first GaN layer 4, the group III nitride semiconductor layer 5, the second GaN layer 6, and the metal film 7. A GaN free-standing substrate layer 10 is formed on a base substrate (porous metal film 7 (metal nitride film)) using a nitride semiconductor laminate 1 having Thereafter, the GaN free-standing substrate layer 10 is peeled from the base substrate. Note that the GaN free-standing substrate layer 10 is naturally peeled from the underlying substrate when the stacked body of the underlying substrate and the GaN free-standing substrate layer 10 is cooled to a predetermined temperature (for example, about room temperature). The peeled GaN free-standing substrate layer 10 becomes a GaN free-standing substrate.
　第７の工程では、ＧａＮ自立基板層１０が所定厚さ（例えば８００μｍ）になるように、ＧａＮ層の成長時間を調整することが好ましい。 In the seventh step, it is preferable to adjust the growth time of the GaN layer so that the GaN free-standing substrate layer 10 has a predetermined thickness (for example, 800 μm).
　また、第７の工程では、下地基板から剥離したＧａＮ自立基板層１０を所定厚さにスライスする処理を行ってもよい。つまり、１つのＧａＮ自立基板層１０から複数枚のＧａＮ自立基板を形成してもよい。 In the seventh step, the GaN free-standing substrate layer 10 separated from the base substrate may be sliced to a predetermined thickness. That is, a plurality of GaN free-standing substrates may be formed from one GaN free-standing substrate layer 10.
（３）本実施形態にかかる効果
　本実施形態によれば、以下に示す１つまたは複数の効果を奏する。 (3) Effects According to the Present Embodiment According to the present embodiment, one or a plurality of effects described below are exhibited.
（ａ）第１のＧａＮ層４に生じる反りの方向と反対方向の反りを生じるＡｌＮ層３を設け、ＡｌＮ層３及び第１のＧａＮ層４をそれぞれ反らせることで、ＡｌＮ層３、第１のＧａＮ層４、ＩＩＩ族窒化物半導体層５、第２のＧａＮ層６の各層をそれぞれ、ＨＶＰＥ法で形成した場合であっても、窒化物半導体積層体１全体では、反り量を低減することができる。その結果、窒化物半導体積層体１の生産性、ＧａＮ自立基板の生産性を向上させることができる。 (A) An AlN layer 3 that generates a warp in a direction opposite to the direction of the warp that occurs in the first GaN layer 4 is provided, and the AlN layer 3 and the first GaN layer 4 are warped, respectively. Even when each of the GaN layer 4, the group III nitride semiconductor layer 5, and the second GaN layer 6 is formed by the HVPE method, the amount of warpage can be reduced in the entire nitride semiconductor multilayer body 1. it can. As a result, the productivity of the nitride semiconductor multilayer body 1 and the productivity of the GaN free-standing substrate can be improved.
（ｂ）具体的には、ＡｌＮ層３、第１のＧａＮ層４、ＩＩＩ族窒化物半導体層５、第２のＧａＮ層６の各層をそれぞれ、ＨＶＰＥ法で形成することで、各層の成長速度を、例えばＭＯＶＰＥ法で形成した場合の１０～１００倍程度速くすることができる。例えば、上述の各層を成長した後のリアクタクリーニングまでの時間を含めて、１時間以下の時間で窒化物半導体積層体１を形成することができる。従って、上述の各層をＭＯＶＰＥ法で形成した場合よりも、窒化物半導体積層体１の生産性を向上させることができる。 (B) Specifically, each of the AlN layer 3, the first GaN layer 4, the group III nitride semiconductor layer 5, and the second GaN layer 6 is formed by the HVPE method, so that the growth rate of each layer is increased. Can be made 10 to 100 times faster than when formed by the MOVPE method, for example. For example, the nitride semiconductor multilayer body 1 can be formed in a time of 1 hour or less including the time until the reactor cleaning after growing the above-described layers. Therefore, the productivity of the nitride semiconductor multilayer body 1 can be improved as compared with the case where the above-described layers are formed by the MOVPE method.
（ｃ）また、上述の各層をＨＶＰＥ法で形成した場合であっても、第１のＧａＮ層４に生じる反りの方向と反対方向の反りを生じるＡｌＮ層３を設け、ＡｌＮ層３及び第１のＧａＮ層４をそれぞれ反らせることで、窒化物半導体積層体１全体での反り量を低減することができる。 (C) Further, even when each of the above-described layers is formed by the HVPE method, an AlN layer 3 that generates a warp in a direction opposite to the direction of the warp generated in the first GaN layer 4 is provided. By warping each of the GaN layers 4, the amount of warpage in the entire nitride semiconductor multilayer body 1 can be reduced.
（ｄ）窒化物半導体積層体１全体での反り量が低減されることで、例えばＶＡＳ法によるＧａＮ自立基板の形成において、所定の層をＨＶＰＥ法により形成した窒化物半導体積層体１を下地基板として用いた場合であっても、自立基板となるＧａＮ層（ＧａＮ自立基板層１０）を形成している最中に、下地基板（窒化物半導体積層体１）が破損する（割れる）ことを抑制することができる。これにより、ＧａＮ自立基板層１０の歩留り（成長歩留り）を向上させることができる。その結果、ＧａＮ自立基板の生産性を向上させることができる。 (D) Since the amount of warpage of the entire nitride semiconductor multilayer body 1 is reduced, for example, in forming a GaN free-standing substrate by the VAS method, the nitride semiconductor multilayer body 1 in which a predetermined layer is formed by the HVPE method is used as the base substrate. Even when it is used as a substrate, it is possible to prevent the base substrate (nitride semiconductor multilayer body 1) from being broken (cracked) during the formation of the GaN layer (GaN free-standing substrate layer 10) serving as a free-standing substrate. can do. Thereby, the yield (growth yield) of the GaN free-standing substrate layer 10 can be improved. As a result, the productivity of the GaN free-standing substrate can be improved.
（ｅ）ＡｌＮ層３を高温（例えば８００℃以上１２００℃以下）の雰囲気下で形成することで、緻密なＡｌＮ層３を形成することができる。これにより、ＡｌＮ層３が降温した際に、ＡｌＮ層３をより十分に反らせることができる。従って、第１のＧａＮ層４の厚さが厚くなり、第１のＧａＮ層４に生じる反り量が大きくなる場合であっても、窒化物半導体積層体１全体での反り量を確実に低減することができる。その結果、上記（ｃ）（ｄ）の効果をより得ることができる。 (E) The dense AlN layer 3 can be formed by forming the AlN layer 3 in an atmosphere of high temperature (for example, 800 ° C. or more and 1200 ° C. or less). Thereby, when the temperature of the AlN layer 3 falls, the AlN layer 3 can be warped more sufficiently. Therefore, even when the thickness of the first GaN layer 4 is increased and the amount of warpage generated in the first GaN layer 4 is increased, the amount of warpage in the entire nitride semiconductor multilayer body 1 is reliably reduced. be able to. As a result, the effects (c) and (d) can be obtained more.
（ｆ）第１の工程で、ＡｌＮ層３を高温の雰囲下で形成することで、ＡｌＮ層３の成長温度を、第１のＧａＮ層４の成長温度に近付けることができる。例えば、ＡｌＮ層３の成長温度と第１のＧａＮ層４の成長温度とを同程度にできる。これにより、第１の工程が終了した後、第２の工程を開始するまでの時間を短くすることができる。具体的には、ＡｌＮ層３の形成が終了した後、例えばＨＶＰＥ装置が備える処理室内が第１のＧａＮ層４を形成可能な所定温度まで昇温（又は降温）するまでの待機時間を短くすることができる。例えば、ＡｌＮ層３の形成が終了した後すぐに、第１のＧａＮ層４の形成を開始することができる。従って、窒化物半導体積層体１の生産性をより向上させることができる。 (F) By forming the AlN layer 3 in a high temperature atmosphere in the first step, the growth temperature of the AlN layer 3 can be brought close to the growth temperature of the first GaN layer 4. For example, the growth temperature of the AlN layer 3 and the growth temperature of the first GaN layer 4 can be made comparable. Thereby, after the 1st process is complete | finished, time until it starts a 2nd process can be shortened. Specifically, after the formation of the AlN layer 3 is finished, for example, the waiting time until the temperature of the processing chamber provided in the HVPE apparatus is raised (or lowered) to a predetermined temperature at which the first GaN layer 4 can be formed is shortened. be able to. For example, the formation of the first GaN layer 4 can be started immediately after the formation of the AlN layer 3 is completed. Therefore, the productivity of the nitride semiconductor multilayer body 1 can be further improved.
（ｇ）第１の工程で、ＡｌＮ層３の厚さを１０ｎｍ以上５００ｎｍ以下にすることで、ＡｌＮ層３をより確実に反らせつつ、窒化物半導体積層体１の生産性の低下を抑制することができる。従って、上記（ａ）～（ｄ）の効果をより得ることができる。 (G) In the first step, by reducing the thickness of the AlN layer 3 to 10 nm or more and 500 nm or less, suppressing the decrease in productivity of the nitride semiconductor multilayer body 1 while warping the AlN layer 3 more reliably. Can do. Therefore, the effects (a) to (d) can be further obtained.
（ｈ）第１のＧａＮ層４の厚さを４μｍ以上にすることで、第１のＧａＮ層４をＨＶＰＥ法により形成した場合であっても、第２のＧａＮ層６の表面に現れるピット等のマクロ欠陥を十分に低減させることができる。例えば、第２のＧａＮ層６の表面のマクロ欠陥密度を２ｃｍ－２未満、好ましくは０ｃｍ－２にすることができる。これにより、第２のＧａＮ層６上に金属膜７を形成する際、金属膜７が剥がれることを抑制することができる。つまり、窒化物半導体積層体１の不良品率を低減することができる。その結果、窒化物半導体積層体１の生産性をより向上させることができる。 (H) By setting the thickness of the first GaN layer 4 to 4 μm or more, pits appearing on the surface of the second GaN layer 6 even when the first GaN layer 4 is formed by the HVPE method The macro defects can be sufficiently reduced. For example, the macro defect density on the surface of the second GaN layer 6 can be less than 2 cm −2 , preferably 0 cm −2 . Thereby, when forming the metal film 7 on the 2nd GaN layer 6, it can suppress that the metal film 7 peels. That is, the defect rate of the nitride semiconductor multilayer body 1 can be reduced. As a result, the productivity of the nitride semiconductor multilayer body 1 can be further improved.
（ｉ）第２のＧａＮ層６の表面に現れるマクロ欠陥を十分に低減させることで、本実施形態にかかる窒化物半導体積層体１が、例えばＶＡＳ法によりＧａＮ自立基板を形成する際の下地基板として用いられた場合、窒化物半導体積層体１を、良好な下地基板として機能させることができる。これにより、ＧａＮ自立基板の生産性をより向上させることができる。また、ＶＡＳ法により、再現性のよいＧａＮ自立基板、つまり質の良いＧａＮ自立基板を形成することができる。 (I) By sufficiently reducing macro defects appearing on the surface of the second GaN layer 6, the nitride semiconductor multilayer body 1 according to the present embodiment forms a base substrate when a GaN free-standing substrate is formed by, for example, the VAS method. When used as, the nitride semiconductor multilayer body 1 can function as a good base substrate. Thereby, the productivity of the GaN free-standing substrate can be further improved. In addition, a GaN free-standing substrate with good reproducibility, that is, a high-quality GaN free-standing substrate can be formed by the VAS method.
（ｊ）本実施形態にかかる発明は、第１のＧａＮ層４の厚さを薄くすることができない場合、つまり第１のＧａＮ層４の厚さを厚くする必要がある場合に、特に有効である。第１のＧａＮ層４の厚さが厚くなるほど、第１のＧａＮ層４に生じる反り量が大きくなる。この際、本実施形態のように、ＡｌＮ層３を設けることで、第１のＧａＮ層４に生じる反り量が大きい場合であっても、窒化物半導体積層体１全体での反り量を低減することができる。例えば、第１のＧａＮ層４の厚さを４μｍ以上と厚くした場合であっても、窒化物半導体積層体１全体では、反り量を６０μｍ未満にすることができる。これにより、上記（ｃ）（ｄ）の効果をより得ることができる。 (J) The invention according to this embodiment is particularly effective when the thickness of the first GaN layer 4 cannot be reduced, that is, when the thickness of the first GaN layer 4 needs to be increased. is there. As the thickness of the first GaN layer 4 increases, the amount of warpage generated in the first GaN layer 4 increases. At this time, by providing the AlN layer 3 as in the present embodiment, even when the amount of warpage generated in the first GaN layer 4 is large, the amount of warpage in the entire nitride semiconductor multilayer body 1 is reduced. be able to. For example, even when the thickness of the first GaN layer 4 is increased to 4 μm or more, the entire nitride semiconductor multilayer body 1 can have a warp amount of less than 60 μm. Thereby, the effects (c) and (d) can be further obtained.
　ここで、少なくとも第１のＧａＮ層を例えばＭＯＶＰＥ法により形成した場合について説明する。この場合、第１のＧａＮ層の厚さが２～３μｍ程度であっても、第２のＧａＮ層の表面に現れるマクロ欠陥を十分に低減させることができる。つまり、第１のＧａＮ層をＨＶＰＥ法により形成する場合よりも、第１のＧａＮ層の厚さを薄くすることができる。その結果、第１のＧａＮ層に生じる反り量も小さくなる。従って、第１のＧａＮ層をＭＯＶＰＥ法により形成した場合、第１のＧａＮ層に生じる反りと反対方向の反りを生じさせるＡｌＮ層３を設けなくても、窒化物半導体積層体全体での反り量を例えば６０μｍ未満にすることができる。しかしながら、第１のＧａＮ層をＭＯＶＰＥ法により形成すると、ＨＶＰＥ法により形成した場合よりも成長速度が遅いため、窒化物半導体積層体の生産性が非常に悪くなる。例えば、第１のＧａＮ層を含む各層を成長した後のリアクタクリーニングまでの時間を含めると、窒化物半導体積層体の形成に１０時間程度を要することがある。 Here, a case where at least the first GaN layer is formed by, for example, the MOVPE method will be described. In this case, even if the thickness of the first GaN layer is about 2 to 3 μm, macro defects appearing on the surface of the second GaN layer can be sufficiently reduced. That is, the thickness of the first GaN layer can be made thinner than when the first GaN layer is formed by the HVPE method. As a result, the amount of warpage generated in the first GaN layer is also reduced. Therefore, when the first GaN layer is formed by the MOVPE method, the amount of warpage in the entire nitride semiconductor multilayer body is provided without providing the AlN layer 3 that causes warpage in the opposite direction to the warpage generated in the first GaN layer. For example, can be less than 60 μm. However, when the first GaN layer is formed by the MOVPE method, the growth rate is slower than when the first GaN layer is formed by the HVPE method, and thus the productivity of the nitride semiconductor stacked body becomes very poor. For example, when the time until reactor cleaning after growing each layer including the first GaN layer is included, it may take about 10 hours to form the nitride semiconductor stacked body.
　これに対し、上述したように、本実施形態では、第１のＧａＮ層４等の所定の層をＨＶＰＥ法で形成することで、窒化物半導体積層体１の形成に要する時間を１時間程度にすることができ、窒化物半導体積層体１の生産性を大幅に向上させることができる。また、ＡｌＮ層３を設けることで、第１のＧａＮ層４等の所定の層をＨＶＰＥ法で形成し、その厚さを厚くした場合であっても、窒化物半導体積層体１全体での反り量を低減することができる。その結果、ＶＡＳ法によるＧａＮ自立基板の形成において、ＨＶＰＥ法で形成した窒化物半導体積層体１を下地基板として用いた場合であっても、ＧａＮ自立基板の生産性の低下を抑制することができる。 On the other hand, as described above, in the present embodiment, a predetermined layer such as the first GaN layer 4 is formed by the HVPE method, so that the time required for forming the nitride semiconductor multilayer body 1 is about 1 hour. The productivity of the nitride semiconductor multilayer body 1 can be greatly improved. Further, by providing the AlN layer 3, even when a predetermined layer such as the first GaN layer 4 is formed by the HVPE method and the thickness thereof is increased, the warp of the entire nitride semiconductor multilayer body 1 is warped. The amount can be reduced. As a result, in the formation of the GaN free-standing substrate by the VAS method, even when the nitride semiconductor multilayer body 1 formed by the HVPE method is used as the base substrate, it is possible to suppress a decrease in productivity of the GaN free-standing substrate. .
＜他の実施形態＞
　以上、本発明の一実施形態を具体的に説明したが、本発明は上述の実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能である。 <Other embodiments>
As mentioned above, although one Embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, A various change is possible in the range which does not deviate from the summary.
　上述の実施形態では、ＧａＮ自立基板を形成する第７の工程を窒化物半導体積層体１の製造工程に含めて考える場合について説明したが、これに限定されない。つまり、第７の工程は、第１～第６の工程を窒化物半導体積層体１の製造工程とし、第７の工程をＧａＮ自立基板の製造工程としてもよい。 In the above-described embodiment, the case where the seventh step of forming the GaN free-standing substrate is considered to be included in the manufacturing process of the nitride semiconductor multilayer body 1 is described, but the present invention is not limited to this. That is, in the seventh step, the first to sixth steps may be manufacturing steps of the nitride semiconductor multilayer body 1, and the seventh step may be a manufacturing step of the GaN free-standing substrate.
　また、上述の実施形態では、第７の工程において、ＧａＮ自立基板層１０に対してスライス処理を行うことで、１つのＧａＮ自立基板層１０から複数枚の自立基板を形成する場合について説明したが、これに限定されない。例えば、スライス処理は行わなくてもよい。つまり、１つのＧａＮ自立基板層１０から１枚の自立基板を形成してもよい。 In the above-described embodiment, the case where a plurality of free-standing substrates are formed from one GaN free-standing substrate layer 10 by performing a slicing process on the GaN free-standing substrate layer 10 in the seventh step has been described. However, the present invention is not limited to this. For example, the slice process may not be performed. That is, one self-standing substrate may be formed from one GaN free-standing substrate layer 10.
　次に、本発明の実施例を説明するが、本発明はこれらに限定されるものではない。 Next, examples of the present invention will be described, but the present invention is not limited thereto.
＜試料１～７の作製＞
　試料１～７はそれぞれ、サファイア基板上に、サファイア基板の側から順に、ＡｌＮ層と、第１のＧａＮ層と、ＩＩＩ族窒化物半導体層と、第２のＧａＮ層と、をそれぞれＨＶＰＥ法で形成し、第２のＧａＮ層上に金属膜を蒸着により形成し、窒化物半導体積層体を形成した。なお、試料１～７にかかる窒化物半導体積層体はそれぞれ、第１のＧａＮ層の厚さを下記の表１に示す通りに変更したことを除くその他は、同一の条件で形成している。 <Preparation of samples 1 to 7>
In each of Samples 1 to 7, an AlN layer, a first GaN layer, a group III nitride semiconductor layer, and a second GaN layer are formed on the sapphire substrate in this order from the sapphire substrate side by the HVPE method. Then, a metal film was formed on the second GaN layer by vapor deposition to form a nitride semiconductor stacked body. The nitride semiconductor multilayer bodies according to Samples 1 to 7 are formed under the same conditions except that the thickness of the first GaN layer is changed as shown in Table 1 below.
Figure JPOXMLDOC01-appb-T000001
  
Figure JPOXMLDOC01-appb-T000001
  
＜試料８～１４の作製＞
　また、試料８～１４の各試料にかかる窒化物半導体積層体を形成した。試料８～１４ではそれぞれ、ＡｌＮ層を設けなかったこと以外は、試料１～７と同様に形成した窒化物半導体積層体である。この場合、ＭＯＶＰＥ法による一般的な成長方法にならい、ＡｌＮ層の代わりに、サファイア基板と第１のＧａＮ層４との間に、低温（５５０℃）の条件下で成長させた、厚さ２０ｎｍのＧａＮ層（低温成長ＧａＮ層）を形成した。なお、試料８～１４の各試料の第１のＧａＮ層の厚さはそれぞれ、下記の表２に示す通りである。 <Preparation of Samples 8 to 14>
In addition, the nitride semiconductor multilayer body according to each of the samples 8 to 14 was formed. Samples 8 to 14 are nitride semiconductor laminates formed in the same manner as Samples 1 to 7, respectively, except that the AlN layer was not provided. In this case, in accordance with a general growth method by the MOVPE method, a thickness of 20 nm is grown between the sapphire substrate and the first GaN layer 4 under a low temperature (550 ° C.) condition instead of the AlN layer. GaN layer (low temperature growth GaN layer) was formed. The thicknesses of the first GaN layers of the samples 8 to 14 are as shown in Table 2 below.
Figure JPOXMLDOC01-appb-T000002
  
Figure JPOXMLDOC01-appb-T000002
  
＜ＧａＮ自立基板の作製＞
　試料１～試料１４の窒化物半導体積層体を下地基板として用い、ＶＡＳ法によりＧａＮ自立基板を形成した。 <Production of GaN free-standing substrate>
Using the nitride semiconductor laminates of Sample 1 to Sample 14 as the base substrate, a GaN free-standing substrate was formed by the VAS method.
＜窒化物半導体積層体の評価＞
　試料１～１４の各試料についてそれぞれ、第２のＧａＮ層の表面のマクロ欠陥密度を測定した。この結果を表１及び表２にそれぞれ示す。 <Evaluation of nitride semiconductor laminate>
For each of Samples 1 to 14, the macro defect density on the surface of the second GaN layer was measured. The results are shown in Table 1 and Table 2, respectively.
　試料１～１４の各窒化物半導体積層体について、反り量を測定した。この結果を表１及び表２にそれぞれ示す。また、試料１～１４の各窒化物半導体積層体について、歩留りを算出した。なお、この歩留りは、各試料である窒化物半導体積層体を下地基板としてＧａＮ自立基板を形成した際の歩留りである。また、歩留りの低下の要因となった、主な不良原因を観察した。これらの結果を表１及び表２にそれぞれ示す。なお、表１及び表２中、「ＴｉＮ剥がれ」とは、金属膜であるＴｉＮ膜が剥がれたことを示す。また、「割れ」とは、窒化物半導体積層体上にＧａＮ自立基板層を形成している際に、窒化物半導体積層体に割れが発生し、ＧａＮ自立基板自体に欠陥が生じたことを示している。 The warpage amount was measured for each of the nitride semiconductor laminates of Samples 1 to 14. The results are shown in Table 1 and Table 2, respectively. In addition, the yield was calculated for each nitride semiconductor multilayer body of Samples 1 to 14. This yield is the yield when a GaN free-standing substrate is formed using the nitride semiconductor laminate as a base substrate. We also observed the main causes of defects that caused the yield to decrease. These results are shown in Table 1 and Table 2, respectively. In Tables 1 and 2, “TiN peeling” indicates that the TiN film, which is a metal film, has been peeled off. In addition, “cracking” means that when the GaN free-standing substrate layer is formed on the nitride semiconductor multilayer body, the nitride semiconductor multilayer body is cracked and the GaN free-standing substrate itself is defective. ing.
＜評価結果＞
　試料１～７の比較から、第１のＧａＮ層の厚さが厚くなるほど、窒化物半導体積層体に生じる反り量が大きくなることを確認した。また、同様のことが試料８～１４の比較でも確認できた。 <Evaluation results>
From comparison of Samples 1 to 7, it was confirmed that as the thickness of the first GaN layer increases, the amount of warpage generated in the nitride semiconductor multilayer body increases. The same can be confirmed by comparing Samples 8 to 14.
　また、試料１～７と試料８～１４との比較から、第１のＧａＮ層の厚さが同じ厚さである場合、第１のＧａＮ層に生じる反りの方向と反対方向に反るＡｌＮ層を設けた方が、窒化物半導体積層体に生じる反り量を低減することができることを確認した。例えば、試料４と試料１１との比較から、ＨＶＰＥ法により厚さが４μｍの第１のＧａＮ層を形成した場合、ＡｌＮ層を設けた試料４の窒化物半導体積層体の反り量は３３μｍであるのに対し、ＡｌＮ層を設けなかった試料１１の窒化物半導体積層体の反り量は６０μｍであった。 Further, from the comparison between the samples 1 to 7 and the samples 8 to 14, when the thickness of the first GaN layer is the same, the AlN layer that warps in the direction opposite to the direction of warpage generated in the first GaN layer. It was confirmed that the amount of warpage generated in the nitride semiconductor multilayer body can be reduced by providing the film. For example, from the comparison between sample 4 and sample 11, when the first GaN layer having a thickness of 4 μm is formed by the HVPE method, the amount of warpage of the nitride semiconductor stacked body of sample 4 provided with the AlN layer is 33 μm. In contrast, the amount of warpage of the nitride semiconductor multilayer body of Sample 11 in which the AlN layer was not provided was 60 μm.
　また、第１のＧａＮ層の厚さを４μｍ以上と厚くした場合であっても、第１のＧａＮ層に生じる反りの方向とは反対方向に反るＡｌＮ層を設けることで、窒化物半導体積層体全体では、反り量を低減することができることを確認した。例えば、窒化物半導体積層体全体では、反り量を６０μｍ未満にすることができることを確認した。 In addition, even when the thickness of the first GaN layer is increased to 4 μm or more, the nitride semiconductor multilayer structure is provided by providing an AlN layer that warps in a direction opposite to the direction of warpage generated in the first GaN layer. It was confirmed that the amount of warpage can be reduced in the whole body. For example, it was confirmed that the amount of warpage can be less than 60 μm in the entire nitride semiconductor multilayer body.
　窒化物半導体積層体全体の反り量が低減されることで、歩留りを向上させることができることを確認した。例えば、試料５と試料１２との比較から、第１のＧａＮ層の厚さが５μｍと同じ厚さである場合、窒化物半導体積層体全体での反り量が小さい試料５の方が、歩留りが高いことを確認した。つまり、窒化物半導体積層体の生産性の低下を抑制することができることを確認した。 It was confirmed that the yield can be improved by reducing the amount of warpage of the entire nitride semiconductor multilayer body. For example, from the comparison between the sample 5 and the sample 12, when the thickness of the first GaN layer is the same as 5 μm, the yield of the sample 5 having a smaller warpage amount in the entire nitride semiconductor multilayer body is higher. Confirmed that it was high. That is, it was confirmed that a decrease in productivity of the nitride semiconductor multilayer body can be suppressed.
　また、ＨＶＰＥ法により各層を形成した場合であっても、第１のＧａＮ層の厚さが４μｍ以上であると、第２のＧａＮ層の表面に現れるマクロ欠陥密度を十分に低下させることができることを確認した。例えば、試料４～７、試料１１～１４からそれぞれ、第１のＧａＮ層の厚さが４μｍ以上であると、第２のＧａＮ層の表面のマクロ欠陥密度を０ｃｍ－２にすることができることを確認した。 Moreover, even when each layer is formed by the HVPE method, if the thickness of the first GaN layer is 4 μm or more, the macro defect density appearing on the surface of the second GaN layer can be sufficiently reduced. It was confirmed. For example, when the thickness of the first GaN layer is 4 μm or more from each of Samples 4 to 7 and Samples 11 to 14, the macro defect density on the surface of the second GaN layer can be reduced to 0 cm −2. confirmed.
　また、試料１～３、試料８～１０から、第２のＧａＮ層の表面のマクロ欠陥密度が十分に低減されていない（例えば０ｃｍ－２になっていない）と、第２のＧａＮ層上に設けられる金属膜（ＴｉＮ膜）が第２の基板上から剥がれてしまうことがあることを確認した。その結果、歩留りが１０％以下まで低下することがあることを確認した。つまり、窒化物半導体積層体の生産性が低下することがあることを確認した。 Also, from Samples 1 to 3 and Samples 8 to 10, if the macro defect density on the surface of the second GaN layer is not sufficiently reduced (for example, not 0 cm −2 ), It was confirmed that the provided metal film (TiN film) might be peeled off from the second substrate. As a result, it was confirmed that the yield may be reduced to 10% or less. That is, it was confirmed that the productivity of the nitride semiconductor multilayer body may be lowered.
＜本発明の好ましい態様＞
　以下に、本発明の好ましい態様について付記する。 <Preferred embodiment of the present invention>
Hereinafter, preferred embodiments of the present invention will be additionally described.
［付記１］
　本発明の一態様によれば、
　基板上に窒化アルミニウム層を形成する第１の工程と、
　前記窒化アルミニウム層上に第１の窒化ガリウム層を形成する第２の工程と、
　前記第１の窒化ガリウム層上に、アルミニウムを含むＩＩＩ族窒化物半導体層を形成する第３の工程と、
　前記ＩＩＩ族窒化物半導体層上に、第２の窒化ガリウム層を形成する第４の工程と、
　前記第２の窒化ガリウム層上に、金属膜を形成する第５の工程と、
　前記第２の窒化ガリウム層及び前記金属膜を多孔質に改質する処理を行う第６の工程と、を有し、
　前記第１～第４の各工程をそれぞれ、ＨＶＰＥ法により行う窒化物半導体積層体の製造方法が提供される。 [Appendix 1]
According to one aspect of the invention,
A first step of forming an aluminum nitride layer on the substrate;
A second step of forming a first gallium nitride layer on the aluminum nitride layer;
A third step of forming a group III nitride semiconductor layer containing aluminum on the first gallium nitride layer;
A fourth step of forming a second gallium nitride layer on the group III nitride semiconductor layer;
A fifth step of forming a metal film on the second gallium nitride layer;
A sixth step of performing a treatment for modifying the second gallium nitride layer and the metal film to be porous,
There is provided a method for manufacturing a nitride semiconductor multilayer body in which the first to fourth steps are each performed by an HVPE method.
［付記２］
　付記１の窒化物半導体積層体の製造方法であって、好ましくは、
　前記第１の工程では、前記窒化アルミニウム層を形成する温度を８００℃以上１２００℃以下にする。 [Appendix 2]
The method for producing a nitride semiconductor multilayer body according to appendix 1, preferably,
In the first step, the temperature for forming the aluminum nitride layer is set to 800 ° C. or more and 1200 ° C. or less.
［付記３］
　付記１又は２の窒化物半導体積層体の製造方法であって、好ましくは、
　前記第１の工程では、前記窒化アルミニウム層の厚さを１０ｎｍ以上５００ｎｍ以下にする。 [Appendix 3]
The method for producing a nitride semiconductor stacked body according to appendix 1 or 2, preferably,
In the first step, the thickness of the aluminum nitride layer is set to 10 nm or more and 500 nm or less.
［付記４］
　付記１ないし３のいずれかの窒化物半導体積層体の製造方法であって、好ましくは、
　前記第２の工程では、前記第１の窒化ガリウム層を４μｍ以上にする。 [Appendix 4]
A method for producing a nitride semiconductor multilayer structure according to any one of appendices 1 to 3, preferably,
In the second step, the first gallium nitride layer is set to 4 μm or more.
［付記５］
　付記１ないし４のいずれかの窒化物半導体積層体の製造方法であって、好ましくは、
　前記基板としてサファイア基板を用いる。 [Appendix 5]
A method for manufacturing a nitride semiconductor multilayer structure according to any one of appendices 1 to 4, preferably,
A sapphire substrate is used as the substrate.
［付記６］
　付記１ないし５のいずれかの窒化物半導体積層体の製造方法であって、好ましくは、
　多孔質に改質された前記金属膜上に、自立基板となる窒化ガリウム層を成膜する第７の工程を有する。 [Appendix 6]
A method for manufacturing a nitride semiconductor multilayer structure according to any one of appendices 1 to 5, preferably,
A seventh step of forming a gallium nitride layer serving as a self-supporting substrate on the metal film modified to be porous;
［付記７］
　付記６の窒化物半導体積層体の製造方法であって、好ましくは、
　前記第７の工程では、前記金属膜から前記自立基板となる窒化ガリウム層を剥離し、前記自立基板を形成する。 [Appendix 7]
The method for manufacturing a nitride semiconductor multilayer body according to appendix 6, preferably,
In the seventh step, the gallium nitride layer to be the self-supporting substrate is peeled from the metal film to form the self-supporting substrate.
［付記８］
　付記７の窒化物半導体積層体の製造方法であって、好ましくは、
　前記第７の工程では、剥離した前記自立基板となる窒化ガリウム層に対してスライス処理を行うことで、１つの前記自立基板となる窒化ガリウム層から複数枚の前記自立基板を形成する。 [Appendix 8]
The method for manufacturing a nitride semiconductor multilayer body according to appendix 7, preferably,
In the seventh step, a plurality of the self-supporting substrates are formed from one gallium nitride layer serving as the self-standing substrate by performing a slicing process on the separated gallium nitride layer serving as the self-supporting substrate.
［付記９］
　本発明の他の態様によれば、
　基板上に設けられた窒化アルミニウム層と、
　前記窒化アルミニウム層上に設けられた第１の窒化ガリウム層と、
　前記第１の窒化ガリウム層上に設けられたアルミニウムを含むＩＩＩ族窒化物半導体層と、
　前記ＩＩＩ族窒化物半導体層上に設けられ、多孔質な第２の窒化ガリウム層と、
　前記第２の窒化ガリウム層上に設けられ、多孔質な金属膜と、を備え、
　前記窒化アルミニウム層に生じた反りによって、前記第１の窒化ガリウム層に生じた反りが打ち消されるような力が前記第１の窒化ガリウム層に加えられている窒化物半導体積層体が提供される。 [Appendix 9]
According to another aspect of the invention,
An aluminum nitride layer provided on the substrate;
A first gallium nitride layer provided on the aluminum nitride layer;
A group III nitride semiconductor layer containing aluminum provided on the first gallium nitride layer;
A porous second gallium nitride layer provided on the group III nitride semiconductor layer; and
A porous metal film provided on the second gallium nitride layer,
There is provided a nitride semiconductor stacked body in which a force is applied to the first gallium nitride layer so that the warp generated in the first gallium nitride layer is canceled by the warp generated in the aluminum nitride layer.
［付記１０］
　付記９の窒化物半導体積層体であって、好ましくは、
　前記第１の窒化ガリウム層の厚さが４μｍ以上である。 [Appendix 10]
The nitride semiconductor stacked body according to appendix 9, preferably,
The thickness of the first gallium nitride layer is 4 μm or more.
［付記１１］
　付記９又は１０の窒化物半導体積層体であって、好ましくは、
　前記窒化アルミニウム層の厚さが１０ｎｍ以上５００ｎｍ以下である。 [Appendix 11]
The nitride semiconductor stacked body according to appendix 9 or 10, preferably,
The aluminum nitride layer has a thickness of 10 nm to 500 nm.
［付記１２］
　付記９ないし１１のいずれかの窒化物半導体積層体であって、好ましくは、
　前記基板がサファイア基板である。 [Appendix 12]
The nitride semiconductor stacked body according to any one of appendices 9 to 11, preferably,
The substrate is a sapphire substrate.
［付記１３］
　付記９ないし１２のいずれかの窒化物半導体積層体であって、好ましくは、
　前記金属膜上には、自立基板となる窒化ガリウム層が形成されている。 [Appendix 13]
The nitride semiconductor stacked body according to any one of appendices 9 to 12, preferably,
A gallium nitride layer serving as a free-standing substrate is formed on the metal film.
１　　　　　窒化物半導体積層体
２　　　　　基板
３　　　　　ＡｌＮ層
４　　　　　第１のＧａＮ層
５　　　　　ＩＩＩ族窒化物半導体層
６　　　　　第２のＧａＮ層
７　　　　　金属膜 DESCRIPTION OF SYMBOLS 1 Nitride semiconductor laminated body 2 Substrate 3 AlN layer 4 1st GaN layer 5 Group III nitride semiconductor layer 6 2nd GaN layer 7 Metal film

Claims (7)

  1. 　基板上に窒化アルミニウム層を形成する第１の工程と、
    　前記窒化アルミニウム層上に第１の窒化ガリウム層を形成する第２の工程と、
    　前記第１の窒化ガリウム層上に、アルミニウムを含むＩＩＩ族窒化物半導体層を形成する第３の工程と、
    　前記ＩＩＩ族窒化物半導体層上に、第２の窒化ガリウム層を形成する第４の工程と、
    　前記第２の窒化ガリウム層上に、金属膜を形成する第５の工程と、
    　前記第２の窒化ガリウム層及び前記金属膜を多孔質に改質する処理を行う第６の工程と、を有し、
    　前記第１～第４の各工程をそれぞれ、ＨＶＰＥ法により行う
    窒化物半導体積層体の製造方法。     A first step of forming an aluminum nitride layer on the substrate;
    A second step of forming a first gallium nitride layer on the aluminum nitride layer;
    A third step of forming a group III nitride semiconductor layer containing aluminum on the first gallium nitride layer;
    A fourth step of forming a second gallium nitride layer on the group III nitride semiconductor layer;
    A fifth step of forming a metal film on the second gallium nitride layer;
    A sixth step of performing a treatment for modifying the second gallium nitride layer and the metal film to be porous,
    A method for manufacturing a nitride semiconductor multilayer body, wherein the first to fourth steps are each performed by an HVPE method.
  2. 　前記第１の工程では、前記窒化アルミニウム層を形成する温度を８００℃以上１２００℃以下にする
    請求項１に記載の窒化物半導体積層体の製造方法。     2. The method for manufacturing a nitride semiconductor stacked body according to claim 1, wherein in the first step, a temperature for forming the aluminum nitride layer is set to 800 ° C. or more and 1200 ° C. or less.
  3. 　前記第１の工程では、前記窒化アルミニウム層の厚さを１０ｎｍ以上５００ｎｍ以下にする
    請求項１又は２に記載の窒化物半導体積層体の製造方法。     3. The method for manufacturing a nitride semiconductor stacked body according to claim 1, wherein in the first step, the thickness of the aluminum nitride layer is set to 10 nm or more and 500 nm or less.
  4. 　前記第２の工程では、前記第１の窒化ガリウム層を４μｍ以上にする
    請求項１ないし３のいずれかに記載の窒化物半導体積層体の製造方法。     4. The method for manufacturing a nitride semiconductor stacked body according to claim 1, wherein in the second step, the first gallium nitride layer is 4 μm or more. 5.
  5. 　基板上に設けられた窒化アルミニウム層と、
    　前記窒化アルミニウム層上に設けられた第１の窒化ガリウム層と、
    　前記第１の窒化ガリウム層上に設けられたアルミニウムを含むＩＩＩ族窒化物半導体層と、
    　前記ＩＩＩ族窒化物半導体層上に設けられ、多孔質な第２の窒化ガリウム層と、
    　前記第２の窒化ガリウム層上に設けられ、多孔質な金属膜と、を備え、
    　前記窒化アルミニウム層に生じた反りによって、前記第１の窒化ガリウム層に生じた反りが打ち消されるような力が前記第１の窒化ガリウム層に加えられている
    窒化物半導体積層体。     An aluminum nitride layer provided on the substrate;
    A first gallium nitride layer provided on the aluminum nitride layer;
    A group III nitride semiconductor layer containing aluminum provided on the first gallium nitride layer;
    A porous second gallium nitride layer provided on the group III nitride semiconductor layer; and
    A porous metal film provided on the second gallium nitride layer,
    A nitride semiconductor stacked body in which a force is applied to the first gallium nitride layer so that the warp generated in the first gallium nitride layer is canceled by the warp generated in the aluminum nitride layer.
  6. 　前記第１の窒化ガリウム層の厚さが４μｍ以上である
    請求項５に記載の窒化物半導体積層体。     The nitride semiconductor multilayer body according to claim 5, wherein the first gallium nitride layer has a thickness of 4 μm or more.
  7. 　前記窒化アルミニウム層の厚さは１０ｎｍ以上５００ｎｍ以下である
    請求項５又は６に記載の窒化物半導体積層体。     The nitride semiconductor multilayer body according to claim 5 or 6, wherein the aluminum nitride layer has a thickness of 10 nm to 500 nm.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003536257A (en) * 2000-06-09 2003-12-02 セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク Method of manufacturing gallium nitride coating
JP2004319711A (en) * 2003-04-15 2004-11-11 Hitachi Cable Ltd Porous substrate for epitaxial growth and its manufacturing method, and method of manufacturing group iii nitride semiconductor substrate
JP2014527707A (en) * 2011-06-30 2014-10-16 ソイテック Method for forming a thick epitaxial layer of gallium nitride on a silicon or similar substrate and layers obtained using this method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003536257A (en) * 2000-06-09 2003-12-02 セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク Method of manufacturing gallium nitride coating
JP2004319711A (en) * 2003-04-15 2004-11-11 Hitachi Cable Ltd Porous substrate for epitaxial growth and its manufacturing method, and method of manufacturing group iii nitride semiconductor substrate
JP2014527707A (en) * 2011-06-30 2014-10-16 ソイテック Method for forming a thick epitaxial layer of gallium nitride on a silicon or similar substrate and layers obtained using this method

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