WO2016134634A1 - 报文接收方法、装置、设备、计算机存储介质及中央处理器 - Google Patents

报文接收方法、装置、设备、计算机存储介质及中央处理器 Download PDF

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WO2016134634A1
WO2016134634A1 PCT/CN2016/073369 CN2016073369W WO2016134634A1 WO 2016134634 A1 WO2016134634 A1 WO 2016134634A1 CN 2016073369 W CN2016073369 W CN 2016073369W WO 2016134634 A1 WO2016134634 A1 WO 2016134634A1
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buffer
buffer pointer
receiving
message
global
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PCT/CN2016/073369
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English (en)
French (fr)
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宋清华
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中兴通讯股份有限公司
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Publication of WO2016134634A1 publication Critical patent/WO2016134634A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • the present invention relates to the field of communications, and in particular, to a message receiving method, apparatus, device, computer storage medium, and a central processing unit (CPU).
  • CPU central processing unit
  • the CPU receives the packet, and the switch receives the packet received from the physical link from the chip cache to the system main memory.
  • the CPU acquires the content in the main memory and processes it.
  • the porting operation is generally performed by direct memory access/ Access (Direct Memory Access, DMA for short) is completed.
  • DMA Direct Memory Access
  • 1 is a schematic diagram of a CPU receiving a packet in the related art. As shown in FIG. 1 , when receiving a packet, the CPU applies for storing a buffer of the packet in the main memory, and then the CPU controls the switching chip to start DMA receiving, and when the packet is sent. When the chip cache is exchanged, the switch chip writes the message to the cache applied for in the main memory through the DMA channel. After the DMA process is completed, the switch chip generates a hardware interrupt to notify the CPU, and the CPU can process the message in the interrupt service program, or In the receiving thread, accessing the segment of memory completes packet processing, and the like.
  • FIG. 2 is a schematic diagram of the Rx DMA descriptor in the related art. As shown in FIG. 2, each descriptor chain respectively writes the address of the first descriptor into the CurrtRxDesc Ptr ⁇ n>> register of the corresponding DMA, and sets The next2Receive and next2Return of the descriptor chain are also equal to the address of the first descriptor, and the DMA channel is enabled. At this point, the message can be transmitted. After transmitting a message, the DMA CurrtRxDesc Ptr ⁇ n>> automatically points to the next descriptor. .
  • the chip manufacturer provides a ring-descriptor chain to the DMA channel when initializing. These descriptor chains are independent of each other. The correspondence with the buffer is also specified during initialization. Buffers cannot be shared between channels. In actual networking applications, it is impossible for packets from each channel to be balanced. There are many, some are small, so it is easy to see that some channels have no available buffers, causing packets to be discarded, and some channels.
  • the descriptor chain occupies the buffer and is not used.
  • the channel and the traffic class (Traffic class, TC for short) have a corresponding relationship. For example, channel 7 transmits a message with a TC of 7, and channel 6 transmits a TC of 6.
  • each chip separately allocates the descriptor chain and the buffer, the interchip buffer It is also not shared, which seriously reduces the utilization of the buffer and affects the efficiency of the collection.
  • the embodiment of the invention provides a message receiving method, device, device, computer storage medium and central processing unit CPU, so as to at least solve the problem that the buffer utilization rate is low and the receiving efficiency is low in the related art.
  • a packet receiving method including: uniformly allocating a global buffer pointer to a buffer buffer corresponding to each chip in one or more chips; determining from a uniformly allocated global buffer pointer The buffer pointer of the received packet is received by the buffer corresponding to the buffer pointer.
  • determining, by the globally allocated buffer pointer, the buffer pointer for receiving the packet includes: acquiring a traffic level TC of the packet; and obtaining, according to the acquired TC, the global buffer pointer Determining the buffer pointer for receiving the message.
  • determining, according to the obtained TC, the buffer pointer for receiving the message from the global buffer pointer comprises: determining that the number of available pointers in the global buffer pointer is less than a predetermined value; Whether the acquired TC exceeds a predetermined level; if the determination result is YES, the remaining available pointers in the global buffer pointer are allocated to the buffer pointer for receiving the message.
  • the method further includes: releasing the buffer corresponding to the buffer pointer.
  • the method further comprises: uniformly storing the uniformly allocated global buffer pointer by using a global array.
  • a message receiving apparatus including: an allocating module, configured to uniformly allocate a global buffer pointer to a buffer buffer corresponding to each chip in one or more chips; determining a module, setting The buffer pointer for receiving the message is determined from the uniformly allocated global buffer pointer, and the receiving module is configured to receive the packet by using the buffer corresponding to the determined buffer pointer.
  • the determining module includes: an obtaining unit, configured to acquire a traffic level TC of the packet; and a determining unit, configured to determine, according to the acquired TC, that the MSC is configured to receive the packet from the global buffer pointer The buffer pointer.
  • the determining unit includes: a determining subunit, configured to determine that the number of available pointers remaining in the global buffer pointer is less than a predetermined value; and determining a subunit, configured to determine whether the acquired TC exceeds a predetermined level;
  • the allocation subunit is configured to allocate the remaining available pointers in the global buffer pointer to the buffer pointer for receiving the message if the determination result of the judging subunit is YES.
  • the device further includes: a release module, configured to release the buffer corresponding to the buffer pointer.
  • a release module configured to release the buffer corresponding to the buffer pointer.
  • the device further comprises: a saving module, configured to uniformly save the uniformly allocated global buffer pointer by using a global array.
  • a central processing unit CPU comprising the apparatus of any of the above.
  • a message receiving device comprising the device of any of the above.
  • a computer storage medium storing an execution instruction for performing the method of any of the above.
  • a global buffer pointer is uniformly allocated to a buffer corresponding to each chip in one or more chips; a buffer pointer for receiving a message is determined from a uniformly allocated global buffer pointer; and the determined buffer pointer is determined.
  • the corresponding buffer receives the packet, which solves the problem that the buffer utilization rate is low and the packet collection efficiency is low in the related art, thereby improving buffer utilization and providing a basis for prioritizing high priority packets. Effect.
  • FIG. 1 is a schematic diagram of a CPU receiving a packet in the related art
  • FIG. 2 is a schematic diagram of an Rx DMA descriptor in the related art
  • FIG. 3 is a flowchart of a message receiving method according to an embodiment of the present invention.
  • FIG. 4 is a structural block diagram of a message receiving apparatus according to an embodiment of the present invention.
  • FIG. 5 is a block diagram showing a preferred structure of the determining module 44 in the message receiving apparatus according to an embodiment of the present invention
  • FIG. 6 is a block diagram showing a preferred structure of the determining unit 54 in the determining module 44 in the message receiving apparatus according to an embodiment of the present invention
  • FIG. 7 is a block diagram 1 of a preferred structure of a message receiving apparatus according to an embodiment of the present invention.
  • FIG. 8 is a block diagram 2 of a preferred structure of a message receiving apparatus according to an embodiment of the present invention.
  • FIG. 9 is a block diagram showing the structure of a CPU of a central processing unit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a linked list according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a method of acquiring/releasing a buffer in accordance with a preferred embodiment of the present invention.
  • FIG. 3 is a flowchart of a packet receiving method according to an embodiment of the present invention. As shown in FIG. 3, the process includes the following steps:
  • Step S302 uniformly allocating a global buffer pointer to a buffer buffer corresponding to each chip in one or more chips;
  • Step S304 determining a buffer pointer for receiving a message from the uniformly allocated global buffer pointer
  • Step S306 receiving a packet by using the buffer corresponding to the determined buffer pointer.
  • the buffers are uniformly allocated to the buffers corresponding to the respective chips, thereby realizing unified management of the buffers of the respective chips, solving the problem that the buffer utilization rate is low and the collection efficiency is low in the related art, thereby achieving the improvement.
  • the buffer utilization provides a basic effect for prioritizing messages with high priority.
  • the high TC can obtain the buffer priority.
  • the buffer pointer for receiving the packet is determined from the uniformly allocated global buffer pointer, the following method can be used to obtain the traffic level of the packet. TC; determining, according to the obtained TC, a buffer pointer for receiving a message from the global buffer pointer.
  • a buffer pointer for receiving a message from the global buffer pointer When determining, according to the obtained TC, a buffer pointer for receiving a message from the global buffer pointer, first determining that the number of available pointers remaining in the global buffer pointer is less than a predetermined value (that is, when the buffer is insufficient); Whether the TC exceeds a predetermined level (ie, the traffic level is high); if the judgment result is YES, the remaining available pointers in the global buffer pointer are allocated to the buffer pointer for receiving the message.
  • the method further includes: releasing the buffer corresponding to the buffer pointer. That is, the buffer that does not work is freed as much as possible, and the buffer is used efficiently.
  • the global buffer pointer is uniformly allocated to the buffer corresponding to each chip in one or more chips.
  • the method further includes: uniformly storing the global buffer pointer uniformly allocated by using a global array. Using a global array to store buffer pointers is not only fast but also simple to read.
  • a message receiving device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and has not been described again.
  • the term "module” may implement a combination of software and/or hardware of a predetermined function.
  • the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
  • FIG. 4 is a structural block diagram of a message receiving apparatus according to an embodiment of the present invention. As shown in FIG. 4, the apparatus includes: an allocating module 42, a determining module 44, and a receiving module 46. The apparatus will be described below.
  • the allocating module 42 is configured to uniformly allocate a global buffer pointer to a buffer buffer corresponding to each chip in one or more chips; the determining module 44 is connected to the foregoing allocating module 42 and configured to determine from the uniformly allocated global buffer pointer Receiving a buffer pointer of the packet; the receiving module 46 is connected to the determining module 44, and configured to receive the packet by using the buffer corresponding to the determined buffer pointer.
  • FIG. 5 is a block diagram of a preferred structure of the determining module 44 in the message receiving apparatus according to the embodiment of the present invention. As shown in FIG. 5, the determining module 44 includes: an obtaining unit 52 and a determining unit 54, and the determining module 44 is performed below. Description.
  • the obtaining unit 52 is configured to obtain the traffic level TC of the packet
  • the determining unit 54 is connected to the obtaining unit 52, and is configured to determine, according to the acquired TC, a buffer pointer for receiving the packet from the global buffer pointer.
  • FIG. 6 is a block diagram showing a preferred structure of the determining unit 54 in the determining module 44 in the message receiving apparatus according to the embodiment of the present invention.
  • the determining unit 54 includes: a determining subunit 62, a judging subunit 64, and an assigner. Unit 66, the determination unit 54 will be described below.
  • the determining subunit 62 is configured to determine that the number of available pointers remaining in the global buffer pointer is less than a predetermined value; the determining subunit 64 is coupled to the determining subunit 62, and is configured to determine whether the acquired TC exceeds a predetermined level; 66. Connect to the above-mentioned judging subunit 64, and set to allocate the remaining available pointers in the global buffer pointer to the buffer pointer for receiving the message if the judgment result of the judging unit is YES.
  • FIG. 7 is a block diagram of a preferred structure of a message receiving apparatus according to an embodiment of the present invention. As shown in FIG. 7, the apparatus includes, in addition to all the modules shown in FIG. 4, a release module 72, which is released below. Module 72 is described.
  • the release module 72 is connected to the receiving module 46 and configured to release the buffer corresponding to the buffer pointer.
  • FIG. 8 is a block diagram of a preferred structure of a message receiving apparatus according to an embodiment of the present invention. As shown in FIG. 8, the device includes: a save module 82, which is saved in the following, except for all the modules shown in FIG. Module 82 is described.
  • the saving module 82 is connected to the foregoing allocation module 42 and the determining module 44, and is configured to uniformly store the uniformly allocated global buffer pointers by using a global array.
  • FIG. 9 is a block diagram showing the structure of a CPU of a central processing unit according to an embodiment of the present invention. As shown in FIG. 9, the CPU 90 includes the message receiving apparatus 92 of any of the above.
  • a message receiving device including the device described in any of the above embodiments.
  • a computer storage medium storing an execution instruction for performing the method of any of the above embodiments.
  • the method mainly includes the following processing:
  • Step A System initialization, stacking system when initializing.
  • Use the global array to uniformly store the buffer pointer allocated by each chip, and define a global subscript variable to mark the subscript of the currently available buffer in the global array, and use the array to initialize each ring descriptor chain, for example, each chip allocation 200 buffers.
  • each ring descriptor chain for example, each chip allocation 200 buffers.
  • For a two-chip cascading system define a global array of size 200*2 to store the first address of each buffer.
  • Step B Acquire the buffer, return the currently available buffer pointer from the global array according to the channel number (ie, the TC queue), and move the subscript variable back.
  • the rule is determined according to the TC value to determine whether the buffer can be obtained, so as to ensure that only the channel of the high TC is used when the buffer is relatively small; the buffer pointer is obtained through the interface when the descriptor list is initialized; the CPU points from the descriptor chain next2Receive After the buffer read message is processed by the application, the buffer pointer is also obtained through the interface, and is assigned to the descriptor pointed to by next2Return in the description chain, and the descriptor DMA is available.
  • FIG. 10 is a schematic diagram of a linked list according to an embodiment of the present invention. For example, reference may be made to the descriptor linked list shown in FIG.
  • Step C Release the buffer, and the available buffer subscript of the global array is moved forward, and the buffer first address is stored in the global array of the subscript position.
  • the interface is called to release the buffer, and the number of available buffers is increased by one.
  • the buffer utilization is effectively improved and the high priority of high queue messages is reflected.
  • FIG. 11 is a schematic diagram of a method of acquiring/releasing a buffer according to a preferred embodiment of the present invention. As shown in FIG. 11, the method includes the following processing:
  • Step A System initialization, use the global array g_rx_buf_pool[] to uniformly save the pointer of each chip allocation buffer, and define a global subscript variable to mark the currently available buffer g_rx_buf_pos in the global array, the initialization of each descriptor chain Get the buffer address from the global array, for example, each The chip allocates 200 buffers.
  • g_rx_buf_pool[400] is defined to store the first address of each buffer.
  • Step B Acquire the buffer, return the currently available buffer pointer from the global array according to the channel number (ie, the TC queue), and subscript the variable g_rx_buf_pos++.
  • the rule is determined according to the TC value to determine whether the buffer can be obtained, so as to ensure that only the channel of the high TC is used when the buffer is relatively small; the buffer pointer is obtained through the interface when the descriptor list is initialized; the CPU points from the descriptor chain next2Receive After the buffer read message is processed by the application, the buffer pointer is also obtained through the interface, and is assigned to the descriptor pointed to by next2Return in the description chain, and the descriptor DMA is available. For example, reference may be made to the descriptor linked list shown in FIG.
  • the interface is called to release the buffer, and the number of available buffers is increased by one.
  • modules or steps of the embodiments of the present invention can be implemented by a general computing device, which can be concentrated on a single computing device or distributed in multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from The steps shown or described are performed sequentially, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.
  • the above embodiments and preferred embodiments solve the problem of low buffer utilization and low packet collection efficiency in the related art, thereby improving buffer utilization and prioritizing packets of high priority. Processing provides the underlying effect.

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Abstract

本发明公开了一种报文接收方法、装置、设备、计算机存储介质及中央处理器CPU，其中，该方法包括：对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；从统一分配的全局buffer指针中确定用于接收报文的buffer指针；采用确定的buffer指针对应的buffer接收报文，通过本发明，解决了相关技术中存在buffer的利用率低，以及收包效率低的问题，进而达到了提高buffer利用率，为高优先等级的报文得到优先处理提供了基础的效果。

Description

报文接收方法、装置、设备、计算机存储介质及中央处理器 技术领域
本发明涉及通信领域，具体而言，涉及一种报文接收方法、装置、设备、计算机存储介质及中央处理器(Central Processing Unit，简称为CPU)。
背景技术
CPU收包是指交换芯片将从物理链路上收到的报文，从芯片缓存中搬运到系统主存中，由CPU获取主存中的内容并处理，搬运工作一般由直接存储器存取/访问(Direct Memory Access，简称为DMA)完成。图1是相关技术中CPU收包的示意图，如图1所示，收包时，CPU预先在主存中申请存放报文的缓存，然后CPU控制交换芯片启动DMA收包，当报文被送到交换芯片缓存时，交换芯片将报文通过DMA通道写入主存中申请的缓存，完成了DMA过程后，交换芯片产生硬件中断通知CPU，CPU可在中断服务程序中处理报文，或在收包线程中访问该段内存完成报文处理等。
目前，marvel的专用集成电路(Application Specific Integrated Circuit，简称为ASIC)交换芯片中内置多个RxDMA通道，分别对应不同的收包队列，DMA buffer通过描述符链进行管理，每一个缓冲区buffer对应一个描述符：图2是相关技术中Rx DMA描述符的示意图，如图2示，每个描述符链分别将第一描述符的地址分别写入对应的DMA的CurrtRxDesc Ptr<n>>寄存器，设置描述符链的next2Receive和next2Return也等于第一个描述符的地址，并使能DMA通道，此时便可以传送报文，传送完一个报文后DMA CurrtRxDesc Ptr<n>>自动指向下一个描述符。
对于单芯片系统，芯片厂商提供初始化的时候给DMA通道分别分配一个环行描述符链，这几个描述符链相互独立，与buffer的对应关系也是初始化时指定的，各通道之间不能共享buffer，实际的组网应用中，不可能各通道过来的报文是均衡的，有的多，有的少，那么很容易出现有的通道没有可用的buffer，导致报文被丢弃，而有的通道的描述符链占着buffer没有被使用；另外，通道和流量等级(Traffic class，简称为TC)是有对应关系的，例如，7号通道传输TC为7的报文，6号通道传输TC为6的报文，如果各通道的buffer不能共享，那么高TC的报文的高优先权就得不到体现；对于多芯片级联的系统，每个芯片单独分配描述符链和buffer，芯片间buffer也是不共享的，这样就严重降低了buffer的利用率，并影响收包效率。
因此，在相关技术中存在buffer的利用率低，以及收包效率低的问题。
发明内容
本发明实施例提供了一种报文接收方法、装置、设备、计算机存储介质及中央处理器CPU，以至少解决相关技术中存在buffer的利用率低，以及收包效率低的问题。
根据本发明实施例的一个方面，提供了一种报文接收方法，包括：对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；从统一分配的全局buffer指针中确定用于接收报文的buffer指针；采用确定的所述buffer指针对应的buffer接收所述报文。
优选地，从统一分配的所述全局buffer指针中确定用于接收所述报文的所述buffer指针包括：获取所述报文的流量等级TC；依据获取的所述TC从所述全局buffer指针中确定用于接收所述报文的所述buffer指针。
优选地，依据获取的所述TC从所述全局buffer指针中确定用于接收所述报文的所述buffer指针包括：确定所述全局buffer指针中剩余的可用指针的数量少于预定值；判断获取的所述TC是否超过预定等级；在判断结果为是的情况下，将所述全局buffer指针中剩余的可用指针分配给用于接收所述报文的所述buffer指针。
优选地，在采用确定的所述buffer指针对应的所述buffer接收所述报文之后，还包括：释放所述buffer指针对应的所述buffer。
优选地，在对所述一个或多个芯片中各个芯片对应的buffer统一分配所述全局buffer指针之后，还包括：对统一分配的全局buffer指针采用全局数组的方式进行统一保存。
根据本发明实施例的另一方面，提供了一种报文接收装置，包括：分配模块，设置为对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；确定模块，设置为从统一分配的全局buffer指针中确定用于接收报文的buffer指针；接收模块，设置为采用确定的所述buffer指针对应的buffer接收所述报文。
优选地，所述确定模块包括：获取单元，设置为获取所述报文的流量等级TC；确定单元，设置为依据获取的所述TC从所述全局buffer指针中确定设置为接收所述报文的所述buffer指针。
优选地，所述确定单元包括：确定子单元，设置为确定所述全局buffer指针中剩余的可用指针的数量少于预定值；判断子单元，设置为判断获取的所述TC是否超过预定等级；分配子单元，设置为在所述判断子单元的判断结果为是的情况下，将所述全局buffer指针中剩余的可用指针分配给用于接收所述报文的所述buffer指针。
优选地，该装置还包括：释放模块，设置为释放所述buffer指针对应的所述buffer。
优选地，该装置还包括：保存模块，设置为对统一分配的全局buffer指针采用全局数组的方式进行统一保存。
根据本发明实施例的还一方面，提供了一种中央处理器CPU，包括上述任一项所述的装置。
根据本发明实施例的又一方面，提供了一种报文接收设备，包括上述任一项所述的装置。
根据本发明实施例的还一方面，提供了一种计算机存储介质，所述计算机存储介质存储有执行指令，所述执行指令用于执行上述任一项所述的方法。
通过本发明实施例，采用对一个或多个芯片中各个芯片对应的buffer统一分配全局buffer指针；从统一分配的全局buffer指针中确定用于接收报文的buffer指针；采用确定的所述buffer指针对应的buffer接收所述报文，解决了相关技术中存在buffer的利用率低，以及收包效率低的问题，进而达到了提高buffer利用率，为高优先等级的报文得到优先处理提供了基础的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是相关技术中CPU收包的示意图；
图2是相关技术中Rx DMA描述符的示意图；
图3是根据本发明实施例的报文接收方法的流程图；
图4是根据本发明实施例的报文接收装置的结构框图；
图5是根据本发明实施例的报文接收装置中确定模块44的优选结构框图；
图6是根据本发明实施例的报文接收装置中确定模块44中确定单元54的优选结构框图；
图7是根据本发明实施例的报文接收装置的优选结构框图一；
图8是根据本发明实施例的报文接收装置的优选结构框图二；
图9是根据本发明实施例的中央处理器CPU的结构框图；
图10是根据本发明实施例的描述链表示意图；
图11是根据本发明优选实施例的获取/释放buffer的方法的示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
在本实施例中提供了一种报文接收方法，图3是根据本发明实施例的报文接收方法的流程图，如图3所示，该流程包括如下步骤：
步骤S302，对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；
步骤S304，从统一分配的全局buffer指针中确定用于接收报文的buffer指针；
步骤S306，采用确定的buffer指针对应的buffer接收报文。
通过上述步骤，通过对各个芯片对应的buffer统一分配buffer指针，实现对各个芯片的buffer实现统一管理，解决了相关技术中存在buffer的利用率低，以及收包效率低的问题，进而达到了提高buffer利用率，为高优先等级的报文得到优先处理提供了基础的效果。
为保证buffer在相对较少时，高TC可以优先获取到buffer，从统一分配的全局buffer指针中确定用于接收报文的buffer指针时，可以采用以下方式来实现：先获取报文的流量等级TC；依据获取的TC从全局buffer指针中确定用于接收报文的buffer指针。其中，依据获取的TC从全局buffer指针中确定用于接收报文的buffer指针时，先确定全局buffer指针中剩余的可用指针的数量少于预定值(即在buffer不充足的时候)；判断获取的TC是否超过预定等级(即流量等级较高)；在判断结果为是的情况下，将全局buffer指针中剩余的可用指针分配给用于接收报文的buffer指针。通过采用上述处理，保证了在buffer相对较少时，优先为高TC的报文提供buffer，使得高TC的优先权得到体现。
为进一步提高buffer的利用率，在采用确定的buffer指针对应的buffer接收报文之后，还包括：释放buffer指针对应的buffer。即使得不工作的buffer尽量空闲下来，buffer得到高效利用。
优选地，在对一个或多个芯片中各个芯片对应的buffer统一分配全局buffer指针 之后，还包括：对统一分配的全局buffer指针采用全局数组的方式进行统一保存。采用全局数组存储buffer指针的方式，不仅读取快速，而且简单。
在本实施例中还提供了一种报文接收装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图4是根据本发明实施例的报文接收装置的结构框图，如图4所示，该装置包括：分配模块42、确定模块44和接收模块46，下面对该装置进行说明。
分配模块42，设置为对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；确定模块44，连接至上述分配模块42，设置为从统一分配的全局buffer指针中确定用于接收报文的buffer指针；接收模块46，连接至上述确定模块44，设置为采用确定的buffer指针对应的buffer接收报文。
图5是根据本发明实施例的报文接收装置中确定模块44的优选结构框图，如图5所示，该确定模块44包括：获取单元52和确定单元54，下面对该确定模块44进行说明。
获取单元52，设置为获取报文的流量等级TC；确定单元54，连接至上述获取单元52，设置为依据获取的TC从全局buffer指针中确定用于接收报文的buffer指针。
图6是根据本发明实施例的报文接收装置中确定模块44中确定单元54的优选结构框图，如图6所示，该确定单元54包括：确定子单元62、判断子单元64和分配子单元66，下面对该确定单元54进行说明。
确定子单元62，设置为确定全局buffer指针中剩余的可用指针的数量少于预定值；判断子单元64，连接至上述确定子单元62，设置为判断获取的TC是否超过预定等级；分配子单元66，连接至上述判断子单元64，设置为在判断子单元的判断结果为是的情况下，将全局buffer指针中剩余的可用指针分配给用于接收报文的buffer指针。
图7是根据本发明实施例的报文接收装置的优选结构框图一，如图7所示，该装置除包括图4所示的所有模块外，还包括：释放模块72，下面对该释放模块72进行说明。
释放模块72，连接到上述接收模块46，设置为释放buffer指针对应的buffer。
图8是根据本发明实施例的报文接收装置的优选结构框图二，如图8所示，该装置除包括图4所示的所有模块外，还包括：保存模块82，下面对该保存模块82进行说明。
保存模块82，连接至上述分配模块42和确定模块44，设置为对统一分配的全局buffer指针采用全局数组的方式进行统一保存。
图9是根据本发明实施例的中央处理器CPU的结构框图，如图9所示，该CPU 90，包括上述任一项的报文接收装置92。
根据本发明实施例，提供了一种报文接收设备，包括上述任一项实施例所述的装置。
根据本发明又一实施例，提供了一种计算机存储介质，所述计算机存储介质存储有执行指令，所述执行指令用于执行上述实施例中任一项所述的方法。
针对相关技术中的上述问题，在本实施例中，提供了一种提高DMA Buffer利用率及CPU收包效率的方法。该方法主要包括如下处理：
步骤A.系统初始化，初始化的时候堆叠系。使用全局数组统一保存各芯片分配的buffer指针，并定义一个全局下标变量标记当前可用的buffer在全局数组中的下标，并使用该数组初始化每个环形描述符链，例如，每个芯片分配200个buffer，对于双芯片级联的系统，定义大小为200*2的全局数组保存每个buffer的首地址。
步骤B.获取buffer，根据通道号(即TC队列)从全局数组中返回当前可用的buffer指针，并将下标变量后移。这里制定规则根据TC值来判断是否能获取到buffer，以保证在buffer相对较少时只给高TC的通道用；初始化描述符链表时通过该接口获取buffer指针；CPU每从描述符链next2Receive指向的buffer读取报文交由应用程序处理后，也通过该接口获取buffer指针，分配给该描述链中next2Return指向的描述符，并置该描述符DMA可用。图10是根据本发明实施例的描述链表示意图，例如，可以参见图10所示的描述符链表。
步骤C.释放buffer，全局数组的可用buffer下标前移，将该buffer首地址存储在该下标位置的全局数组中。当协议模块(应用程序)处理完报文后，调用该接口进行buffer的释放，可用buffer数加一。
通过统一管理DMA buffer的方法，从而有效地提高了buffer利用率并使得高队列报文的高优先级得到体现。
图11是根据本发明优选实施例的获取/释放buffer的方法的示意图，如图11所示，该方法包括如下处理：
步骤A.系统初始化，使用全局数组g_rx_buf_pool[]统一保存各芯片分配buffer的指针，并定义一个全局下标变量标记当前可用的buffer在全局数组中的下标g_rx_buf_pos，每个描述符链的初始化都从该全局数组中获取buffer地址，例如，每个 芯片分配200个buffer，对于双芯片级联的系统，定义g_rx_buf_pool[400]保存每个buffer的首地址。
步骤B.获取buffer，根据通道号(即TC队列)从全局数组中返回当前可用的buffer指针，并将下标变量g_rx_buf_pos++。这里制定规则根据TC值来判断是否能获取到buffer，以保证在buffer相对较少时只给高TC的通道用；初始化描述符链表时通过该接口获取buffer指针；CPU每从描述符链next2Receive指向的buffer读取报文交由应用程序处理后，也通过该接口获取buffer指针，分配给该描述链中next2Return指向的描述符，并置该描述符DMA可用。例如，可以参见图10所示的描述符链表。
步骤C.释放buffer，全局数组的可用buffer下标g_rx_pool_pos--；，将该buffer首地址存储在该下标位置的全局数组中g_rx_buff_pool[g_rx_pool_pos]＝buffer。当协议模块(应用程序)处理完报文后，调用该接口进行buffer的释放，可用buffer数加一。
显然，本领域的技术人员应该明白，上述的本发明实施例的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，通过上述实施例及优选实施方式，解决了相关技术中存在buffer的利用率低，以及收包效率低的问题，进而达到了提高buffer利用率，为高优先等级的报文得到优先处理提供了基础的效果。

Claims (13)

  1. 一种报文接收方法，包括：
    对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；
    从统一分配的全局buffer指针中确定用于接收报文的buffer指针；
    采用确定的所述buffer指针对应的buffer接收所述报文。
  2. 根据权利要求1所述的方法，其中，从统一分配的所述全局buffer指针中确定用于接收所述报文的所述buffer指针包括：
    获取所述报文的流量等级TC；
    依据获取的所述TC从所述全局buffer指针中确定用于接收所述报文的所述buffer指针。
  3. 根据权利要求2所述的方法，其中，依据获取的所述TC从所述全局buffer指针中确定用于接收所述报文的所述buffer指针包括：
    确定所述全局buffer指针中剩余的可用指针的数量少于预定值；
    判断获取的所述TC是否超过预定等级；
    在判断结果为是的情况下，将所述全局buffer指针中剩余的可用指针分配给用于接收所述报文的所述buffer指针。
  4. 根据权利要求1所述的方法，其中，在采用确定的所述buffer指针对应的所述buffer接收所述报文之后，还包括：
    释放所述buffer指针对应的所述buffer。
  5. 根据权利要求1至4中任一项所述的方法，其中，在对所述一个或多个芯片中各个芯片对应的buffer统一分配所述全局buffer指针之后，还包括：
    对统一分配的全局buffer指针采用全局数组的方式进行统一保存。
  6. 一种报文接收装置，包括：
    分配模块，设置为对一个或多个芯片中各个芯片对应的缓冲区buffer统一分配全局buffer指针；
    确定模块，设置为从统一分配的全局buffer指针中确定用于接收报文的buffer指针；
    接收模块，设置为采用确定的所述buffer指针对应的buffer接收所述报文。
  7. 根据权利要求6所述的装置，其中，所述确定模块包括：
    获取单元，设置为获取所述报文的流量等级TC；
    确定单元，设置为依据获取的所述TC从所述全局buffer指针中确定用于接收所述报文的所述buffer指针。
  8. 根据权利要求7所述的装置，其中，所述确定单元包括：
    确定子单元，设置为确定所述全局buffer指针中剩余的可用指针的数量少于预定值；
    判断子单元，设置为判断获取的所述TC是否超过预定等级；
    分配子单元，设置为在所述判断子单元的判断结果为是的情况下，将所述全局buffer指针中剩余的可用指针分配给用于接收所述报文的所述buffer指针。
  9. 根据权利要求6所述的装置，其中，还包括：
    释放模块，设置为释放所述buffer指针对应的所述buffer。
  10. 根据权利要求6至9中任一项所述的装置，其中，还包括：
    保存模块，设置为对统一分配的全局buffer指针采用全局数组的方式进行统一保存。
  11. 一种中央处理器CPU，包括权利要求6至9中任一项所述的装置。
  12. 一种报文接收设备，包括权利要求6至10中任一项所述的装置。
  13. 一种计算机存储介质，所述计算机存储介质存储有执行指令，所述执行指令用于执行权利要求1至5中任一项所述的方法。
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