WO2016131719A1

WO2016131719A1 - Level control circuit and method

Info

Publication number: WO2016131719A1
Application number: PCT/EP2016/053015
Authority: WO
Inventors: Junhu LIU; Johannes Hubertus Gerardus Op Het Veld; Binghong WANG; Christian Hattrup
Original assignee: Philips Lighting Holding B.V.
Priority date: 2015-02-17
Filing date: 2016-02-12
Publication date: 2016-08-25

Abstract

A level control circuit uses a reference voltage generated from a mains voltage signal by a reference circuit to provide a feedforward control signal. This control signal is used to generate a control signal for controlling a switched mode power converter. The reference circuit comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains the level information. In an embodiment, the reference circuit comprises a voltage divider comprising a resistor circuit and the combining circuit comprises an adjustment module to which a pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control. The level control further comprises a buffering capacitor or a buffered low pass filter coupled to the output (SET) of the voltage divider. This provides a power factor correction approach for active level control, and which can be implemented very simply and with low cost. It can be used for controlling lighting dimming.

Description

Level control circuit and method

FIELD OF THE INVENTION

This invention relates to controlling the signal level applied to a load, such as the current level, and in particular to lighting dimming circuits and methods. BACKGROUND OF THE INVENTION

The use of LED lighting has been growing rapidly. The cost of the lighting system is becoming more and more important as a result of the fierce competition which exists in LED lighting. Being one of the key components for LED lighting, the electronics driver is continuously being developed to achieve high performance and low cost solutions. The driver cost, component count, and size have been reduced significantly.

LEDs are current-driven DC devices. To drive LED devices using a mains AC supply, a switched mode power supply is typically used to convert the mains input supply to a power supply suitable for application to the LED load.

A first approach for implementing a dimming function is to provide analogue dimming for example by peak current control of the switched mode power supply. Typically, the instantaneous current through the SMPS is measured by using a sense resistor (called a shunt resistor). The voltage on the sense resistor is compared to a threshold value. When the actual current exceeds the threshold value, the main power switch (which may be a bipolar transistor or a MOS transistor) is switched off. This means that the peak current of the converter is controlled by the threshold value.

As the current profile (and the peak current) determines the power of the converter, the threshold value also determines the output power.

By injecting an analogue control signal it is possible to influence or determine the threshold value. Dimming is then realized by injecting an appropriate analogue control signal to reduce the output power of the converter to generate the desired power level. For lighting applications, this results in setting the desired light level of a lamp.

An example of this technique is shown in simplified form in Figure 1. The circuit comprises a switch mode power supply 10 in the form of a fly-back converter having an inductor 12, diode 14 and main control switch 16. The main control switch controls the flow of current through the primary winding of a transformer, to ground through a shunt resistor 17. The secondary winding of the transformer functions as the inductor 12 of the switched mode power supply 10. The output load comprises a string of LEDs 18. A sense resistor 20 (Rled) is used to sense the output current, and the corresponding voltage is compared with a reference Vref by opamp 22. The resulting error signal Verr is provided to a comparator 24 which also receives as input the voltage across the shunt resistor. This shunt resistor voltage is indicative of the current flowing through the main switch 16 of the switched mode power converter. The comparator output is provided to a latch circuit 25 which in turn controls the gate of the main transistor 16. In this way, there cyclic control of the switching of the switched mode power converter based on the current through the shunt resistor 17.

The latch 25 functions to initiate and keep the main switching transistor 16 off just after it is triggered off by the comparator 24. As soon as transistor 16 switches off, the fly-back diode 14 starts conducting. When the current through fly-back diode 14 becomes zero the transistor is switched 16 automatically on by the latch circuit 25 which has an input dependent on the current through the coil 12.

Modulating the signal Vref allows the output current to be controlled. This example has a DC input 26, and does not implement any power factor compensation.

The circuit of Figure 1 applies analogue dimming using a peak current control circuit. The peak current for one dimming level will be a constant.

In many applications, and especially in applications above a certain power level (e.g. 25W), some requirements on the input current shape of the converter have to be fulfilled. For example, the input current provided by the mains to the switched mode power converter has to have a more or less sinusoidal shape without any phase shift.

Ideally the converter behaves like a resistor. The shape and the phase angle of the converter input current is described by the so called power factor and by its harmonics. Circuits providing a high power factor are called power factor correction (PFC) circuits.

There are circuits available on the market which provide both a high power factor and dimming capability but these are typically based on a two-stage concept. The first stage takes care of the PFC function and second stage takes care of the output control such as voltage or current.

It is possible to combine both functions in a single stage. For example, to generate the desired current shape at the output, typically a feed forward control is applied. This control simply uses a voltage divider from the rectified mains voltage to determine a sinusoidal sense signal. This signal is used to set the threshold voltage that is compared to the voltage at the current sense resistor. In this way, the peak current through the coil of the converter will also have a sinusoidal shape. As a consequence the input current also has a nearly sinusoidal wave shape improving power factor and harmonics.

However, such a converter requires expensive control means such as operational amplifiers and multipliers. Especially the multiplier function is very expensive. By way of example, Figure 2 shows an implementation of power factor correction using a multiplier, as a modification to the circuit of Figure 1, and for a circuit having a mains input.

The comparator 24 receives a control input Vi provided by a multiplier 30. This multiplies a voltage divided version Vsin of the rectified mains input Vin with the error signal Verr As in the circuit of Figure 1, the error signal is generated by the error amplifier 22 which has compared the output current through the LED string (received as a voltage across the current sense resistor 20) with the reference Vref The output of this error amplifier 22 is then multiplied by the signal Vsin. In this way, the mains input signal is used to shape the control signal provided to the switched mode power converter 10.

There is a need for a circuit which enables a dimming (or other level control) function to be implemented and also gives low harmonic distortion and which is able to operate at high power. There is furthermore a need for such a circuit which avoids the need for multiple stages or expensive and complicated control circuitry.

US20130076246A1 discloses a solution in which a power source voltage Vcc and a PWM modulation signal are combined to provide a reference signal for load current.

SUMMARY OF THE INVENTION

In the prior art US20130076246A1, the generated reference signal P7 is modulated in high frequency to a high level or to a low level, causing the input current following this reference signal also varying in high frequency to either a high level or a low level. This burst current needs to be smoothed by a large mains filter, in order to get a high PFC. Thus this mains filter is bulky low frequency low pass filter and needs large capacitor and inductor.

The invention is defined by the claims.

According to examples in accordance with an aspect of the invention, there is provided a level control circuit for controlling level, comprising:

a reference circuit for generating a reference voltage from a mains voltage signal; a switched mode power converter comprising a main switching transistor for controlling the cycles of the switched mode power converter, to generate a level control circuit output for application to a load; and

a control circuit for generating a control signal for application to the main switching transistor based on the reference voltage,

wherein the reference circuit comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains the level information.

More specifically, the reference circuit comprises a voltage divider including an adjustment module to which a pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control. This embodiment provides a more detailed way of providing the reference voltage and combining the pulse width modulation control signal. It should be noted other kind of way for providing the reference voltage as well as embedding the level information in the reference voltage are also applicable.

The output of the voltage divider may be provided to a buffering capacitor or to a low pass filter. For example, a capacitor and one or more of the resistors of the voltage divider circuit may form a low pass filter for filtering the high frequency components of the pulse width modulation signal. Alternatively a buffered low pass filter can be used. In this embodiment, the reference signal is more stable and so is the input current, thus the circuit does not need a large input filter /mains filter to smooth the input current.

This circuit makes use of a feedforward level control. This enables the shape of the rectified mains input to be used as the control signal for the switched mode power converter. In this way, the peak current output from the switched mode power converter is not capped but the peak is instead made to follow the rectified mains signal. This provides a power factor correction approach but which enables active level control. The circuit can be implemented very simply and with low cost to allow level control and power factor correction at the same time.

One preferred application of the level control circuit is to control a lighting load, wherein the level control circuit comprises a dimming circuit.

The voltage divider comprises a resistor circuit and the combining circuit may comprise a resistor-transistor circuit including an adjustment transistor to which the pulse width modulation control signal is applied, thereby to change the effective voltage divider ratio.

The transistor is used to enable or disable the operation of one or more resistors in the voltage divider circuit, so that the voltage divider ratio is controlled at high frequency. At lower frequencies (i.e. at the mains frequency), this corresponds to a general overall change in voltage divider ratio and therefore reference signal.

The resistor circuit may comprise a first resistor between the rectified mains voltage signal and the voltage divider output, a further resistor (R_DIV) between the voltage divider output and ground, and the resistor-transistor circuit comprises a second resistor and the adjustment transistor in series between the voltage divider output and ground, wherein the pulse width modulation control signal is applied to a control terminal of the adjustment transistor.

This provides a resistive divider, with one of the resistors, which connects to ground, implemented as a variable resistor by means of a PWM switch.

In an embodiment, the level control circuit provides the level control circuit output to a lighting load, wherein the level control circuit comprises a dimming circuit, said pulse width modulation control signal is indicative of a dimming level, and said level control circuit further comprises: a rectifier for providing a rectified mains voltage signal for the voltage divider. This embodiment provides the application of the invention in lighting.

Note that the resistor which connects to the rectified mains may instead be implemented as the variable resistor by means of the PWM switch.

The pulse width modulation control signal preferably has a frequency at least

20K Hz.

This ensures that the voltage divider ratio is seen as a constant value at the mains frequency.

In an embodiment, the control circuit comprises a comparator circuit for comparing a voltage indicative of active power stored in the switched mode power converter with the output from the voltage divider, and a latch circuit for controlling the main switching transistor of the switched mode power converter according to an output of the comparator circuit. This embodiment provides an implementation of the control circuit.

In another embodiment, the level control circuit further comprises a unit for generating said pulse width modulation control signal, wherein said unit is adapted to:

comparing a voltage indicative of power delivered out by the switch mode power converter with a further reference voltage, and outputting said pulse width modulation control signal according to a result of the comparing. This embodiment provides an implementation of how to generate the pulse width modulation control signal. It should be understood that this pulse width modulation control can also be input to the level control circuit from an external unit that configures the level control circuit, such as a dimmer operated by users.

The switched mode power converter may for example comprise a boost converter, a buck converter, a fly-back converter or a buck-boost converter.

In an alternative embodiment, the reference circuit comprises: a voltage divider adapted for providing a divided voltage from the mains voltage signal; a buffering unit; and a controllable coupling unit, adapted for selectively coupling said divided voltage to said buffer unit in response to said pulse width modulation control signal.

This embodiment provides an alternative implementation of the reference circuit.

The invention also provides a lighting circuit comprising a level control circuit as described above for implementing dimming control, and an LED lighting arrangement supplied with power by the level control arrangement.

According to examples in accordance with another aspect of the invention, there is provided a method of controlling a signal level applied to a load, comprising:

generating a reference voltage from a mains voltage signal;

generating a level control circuit output and applying it to a load using a switched mode power converter,

wherein the method comprises controlling the cycles of the switched mode power converter using the reference voltage, and wherein generating the reference voltage applying a pulse width modulation control signal indicative of said signal level such that the reference voltage contains information of said signal level.

In more detail, said generating the reference voltage comprises dividing the mains voltage signal based on a voltage dividing ratio, wherein said voltage dividing ratio is variable dependent on the pulse width modulation control signal. The output of the voltage divider may be low pass filtered, for filtering the high frequency components of the pulse width modulation signal.

This method provides a feedforward level control which enables the shape of the rectified mains input to be copied to the control signal for a switched mode power converter. This provides both power factor correction and level control. The reference voltage may be generated using a resistor-transistor circuit including an adjustment transistor, and the method comprises applying the pulse width modulation control signal to the adjustment transistor thereby to change the voltage divider ratio.

A pulse width modulation control signal may be used which has a frequency at least 20 times the mains frequency. The level control circuit output may be generated by controlling a boost converter, a buck converter, a fly-back converter or a buck-boost converter.

The method may be used to control dimming of a lighting load. It also can be used in power supplies with a DC output voltage. Instead of controlling the LED current one should control the DC output voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples of the invention will now be described in detail with reference to the accompanying drawings, in which:

Figure 1 shows an example of a known analogue dimming technique;

Figure 2 shows an example of a known implementation of power factor correction using a multiplier;

Figure 3 shows a first possible design for an adaptive voltage divider circuit; Figure 4 shows a second possible design for an adaptive voltage divider circuit;

Figure 5 shows level adjustment curves for the circuits of Figures 3 and 4;

Figure 6 shows a first example of dimming circuit at a block level;

Figure 7 shows a second example of dimming circuit at a block level;

Figure 8 shows a third example of dimming circuit at a block level;

Figure 9 shows a fourth example of dimming circuit at a block level;

Figure 10 shows a first example of dimming circuit at a component level;

Figure 11 shows a second example of dimming circuit at a component level;

Figure 12 shows a third example of dimming circuit at a component level; Figure 13 shows a fourth example of dimming circuit at a component level

Figure 14 shows another embodiment of the reference circuit; and

Figure 15 shows the curve for the input mains voltage and the reference voltage given different pulse width modulation signals. DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention provides a level control circuit in which a voltage is generated from a mains voltage signal by a reference circuit to provide a feedforward control signal. This control signal is used to generate a switch control signal for controlling a switched mode power converter. The reference circuit further comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains the level information. This provides a power factor correction approach for active level control, and which can be implemented very simply and with low cost. It can be used for controlling lighting dimming.

In a more detailed, embodiment, the reference circuit comprises a resistor circuit including an adjustment module to which a pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control. In this way, a dimming function is implemented using feed forward control of the peak current. This is achieved by replacing the known expensive analogue multiplier (for example as shown in Figure 2) with a low cost switched resistor voltage divider consisting of a switched resistor network (and preferably also a low pass filter (LPF)). By this method, the peak current will still follow the rectified mains voltage (with a sinusoidal shape) but the amplitude is adjustable for different dimming levels. Compared to known methods this is very simple and cheap and allows dimming and power factor correction (PFC) at the same time.

The approach can be used with any power converter topology. Examples of a Buck-Boost converter topology and a flyback topology are presented below, but the invention may be applied to any type of power converter. Furthermore, the approach is not limited to power factor correction circuits but can be used more generally to replace an analogue multiplier. If a unidirectional controlled switch is used, the multiplying functionality works for a positive input voltage only (single quadrant). If the modulator switch is replaced by a bidirectional controlled device, the device can be used for both negative and positive input voltages resulting into a two quadrant device.

Before describing examples of dimming circuit, the switched resistor voltage divider circuit concept will first be explained with reference to two examples shown in Figures 3 and 4.

Figure 3 shows the switched resistor circuit having separated stages of an adaptive voltage divider 40 and a buffered low pass filter 42. Figure 4 shows a second example of switched resistor circuit which provides a low pass filter function based on the un-buffered switched resistor node.

The adaptive resistor divider circuit comprises a resistor ¾_Ν between the output (which functions as a divided feedforward signal) and the bus Vbus, and a resistor R_DIV between the divided feedforward signal and ground. The resistor R_MOD is in series with a switch M_MOD and they together define a variable switchable resistor where the value of the variable resistor is determined by the duty cycle of the signal applied to the base of the switch M_MO_D and the resistance of resistor R_MO_D- The switched resistor R_MO_D is in parallel with a divider resistor R_DIV- The parallel resistance of these two resistors defines the lower resistor of the voltage divider.

The divided feedforward signal Vbus_sns will still have a sine wave voltage shape but with an adjustable voltage depending on the value of the variable resistor (i.e. RMOD and the duty cycle of M_MOD).

In the circuit of Figure 3, the filter circuit 42 makes use of a high input impedance low pass filter to reduce the high frequency distortion on the Vbus sns voltage that is generated by the switching action of transistor M_MOD-

The filter circuit as shown in Figure 4 for example has a capacitor Cs which together with Ri_N, R_MO_D, R_DIV and the duty cycle of the switch M_MO_D acts as a low pass filter to reduce the high frequency distortion on the Vbus sns voltage that is generated by the switching action of transistor M_MOD-

When the duty cycle of transistor M_MOD becomes 1 (constantly on), the signal Vbus sns will reach the lowest possible voltage and vice versa. The resistors R_IN, R_MOD, R_DIV and transistor M_MOD together from the adjustable voltage divider.

The time constant of the low pass filter function should be large enough to suppress the ripple caused by the PWM signal but small enough to be able to follow the rectified mains voltage at Vbus. This can be achieved by ensuring that the PWM frequency is much higher than the rectified mains frequency, for example a factor of 20 or more higher, or by using a higher order low pass filter.

Through control of the duty cycle δ of the transistor M_MOD, the signal

Vbus sns has a sinusoidal wave shape but with a controllable amplitude. As described above, the peak current is controlled by the injected signal and the input current follows the peak current amplitude leading to nearly sinusoidal input currents also at reduced (=dimmed) output power. In the design of the circuit components, the PWM signal used to switch the transistor M_MOD on and off should have a sufficiently high frequency in order to avoid significant disturbance at Vbus sns, which can also introduce harmonic components in the mains current.

The circuit of Figure 3, with a buffered low pass filter 42, enables the input impedance of the low pass filter to be much higher than the resistance RDIV- This can be achieved by either using an input unity gain op-amp at the input stage of the low pass filter or a high input resistance at the input stage of the low pass filter. As a consequence, the modulated voltage VMOD will alternate between two values depending on the PWM state. In this case, the circuit as shown in Figure 3 can be seen as a cascading of two circuits namely the modulating part and the filtering (averaging) part. The modulating part is formed by an inverter 44, the modulator switch M_MOD and the resistors RMOD, RDIV and RIN.

For the voltage on node V_MOD, two states can be distinguished, namely;

PWM = "1", which means M_MOD is off. ^{0≤T≤ 8}°^TP™ .

PWM = "0", which means M_MOD is on"⁵"⁷™/≤ t < T_PWM

For the voltage on node VMOD

In a practical design V_MOD « ¼_JUS which means that R_DIV « R_/W . This simplifies (1) to

The output voltage of the low pass filter Vb_us_sns will be the average of VMOD-

Substitution of both expressions from (2) in (3) gives

Rearranging (4) and substitution of

The first term R_DI_V/RIN gives the maximum value for K, denoted by K_NOM, and the second term between the brackets represents the dimming curve d. So (5) can be rewritten as:

This results in a linear level control curve for d between the values a and 1 for a duty cycle δ_α of 0 and 1 respectively.

The circuit of Figure 4 has an output capacitor Cs to form an unbuffered low pass filter.

The input impedance of the low pass filter thus cannot be neglected. As a consequence, Vbus sns cannot alternate between two values but remains stable during one PWM switching period. In this implementation, the modulating and filtering part are combined.

ates:

The overall contribution of both states to V_bus__sns during one PWM switching period is:

Substitution of both expressions from (7) in (8) gives the average state of

In a practical design V_{bus sns} « V_bus which means that R_DIV « R_/w. This simplifies (11) to:

The first term R_DIV/R_IN gives the maximum value for K, denoted by K_NOM, and the second term represents the dimming curve d. So (13) can be rewritten as:

This results in a non-linear level control curve for d between the values a and 1 for a duty cycle δ_α of 0 and 1 respectively.

Figure 5 shows the two level control curves of d versus δ_α - the linear curve 50 for the buffered implementation and the non-linear curve 52 for the un-buffered

implementation. These are for a=0.3.

The parallel resistor R_Div is optional. If R_DIV is not present this means R_DIV→ oo, and the expression for AT in (13) will become:

For a duty cycle δ_α approaching 1 , K tends to infinity. For this reason, the parallel resistor is preferred so that δ_α is limited to a well-defined level. Another way to limit K is by means of using a clamping circuit across R_DIV i.e. a Zener diode or comparable function.

Figures 3 and 4 have the modulated resistor between the output and ground, and a fixed resistor between the output and the voltage bus. The modulated resistor may instead be the resistor to the voltage bus, with a fixed resistor to ground.

When used in a dimming LED driver circuit, the voltage divider circuit described above provides a variable division factor K = Vbus_sns/Vbus to increase the power factor of the switched mode power converter and thereby to set the power level of the LED string.

The value K can be split into two factors K_NOM and d in order to distinguish between a nominal set value (K_NOM) and the influence of dimming (d), so K=dK_NOM, where d represents a dimming curve depending on a duty cycle (δ_α) of the PWM signal and K_NOM sets the nominal power level in the LED string corresponding to δ_α = 1 .

By definition, the resulting dimming curve always should have a maximal value of 1. The subscript a in δ_α is used to indicate that the purpose of the duty cycle is to dim in an analogue way such that it has no (negligible) interference with the switching frequency of the converter.

A number of possible drive circuits which make use of the switched resistor circuit will now be discussed.

Figures 6 to 9 shows examples which are modifications to the circuit design of Figure 2, shown at circuit block level. Figures 10 to 13 show some alternative designs using a buck-boost converter topology, and at a component level.

Figure 6 shows an example in which the multiplier 30 is replaced with a switched resistor circuit 55 of the unbuffered type shown in Figure 4. The error signal Verr from the opamp 22 controls a pulse width modulator 54 which provides the gate signal to the switch MMOD. This circuit has analogue control of the PWM signal.

Figure 7 shows an example in which the multiplier 30 is replaced with a switched resistor circuit 56 of the buffered type shown in Figure 3. The error signal Verr from the opamp 22 again controls a pulse width modulator 54 which provides the gate signal to the switch MMOD. This circuit has analogue control of the PWM signal.

Figure 8 shows an example in which there is digital control of the switched resistor circuit. The reference voltage across the sense resistor 20 is provided to a microcontroller 57 which generates the PWM signal for the switch MMOD of the switched resistor circuit. The microcontroller 57 receives a digital reference input Dref. This circuit uses the switched resistor circuit 55 of the unbuffered type shown in Figure 4.

Figure 9 shows an example in which there is again digital control of the switched resistor circuit. This circuit uses the switched resistor circuit 56 of the buffered type shown in Figure 3.

Figures 6 to 9 thus show different conceptual implementations.

Figure 10 shows a first more detailed component level example of dimming circuit. The circuit comprises the power converter 60 which in this example is a buck-boost converter. It has a mains input 62, a rectifier 64 and a switched mode power converter 66 including an inductor LI, fly-back diode Dl and main switching transistor Ql . The LED load will be connected between LED+ and LED-. The resistor 20 (Rled) is again used to measure the LED current and parallel capacitance Cled is used to reduce the rectified mains current ripple through the LED string.

The switching transistor control signal (i.e. the base signal for a bipolar transistor) is supplied by a PWM output of a control device which provides the signal "PWM" to the base of Q5. The switched resistor divider described above is shown as block 70 based on the unbuffered version of Figure 4.

The output "SET" of the block 70 is a function of the rectified mains Vin and the duty cycle according to equation (14) above. As in the examples above, the output is provided to a comparator 72 (implemented as a single transistor Q6 in this example) which in combination with the main converter switching transistor Ql implements a comparator and triggers a latch circuit/block 68.

The comparator 72 receives as input the output SET from the switched resistor divider circuit 70 and the base voltage of Ql, which itself is equal to the voltage across the shunt resistor 17 (Rshunt) plus the base-emitter voltage of transistor Ql .

The latch 68 functions to initiate and keep the main switching transistor Ql off just after it is triggered by the comparator 72. As soon as Ql switches off, the fly-back diode Dl starts conducting and a base drive circuit (not shown) will take over by applying a negative voltage across the base-emitter of transistor Ql . At this moment, the latch becomes automatically inactive but the base drive circuit keeps transistor Ql off.

At the moment that the current through fly-back diode Dl becomes zero, the converter coil LI starts ringing with the parasitic capacitance at the collector of transistor Ql and will switch Ql automatically on via the drive circuit (not shown).

Thus, the switched resistor modulator and low pass filter set the level (the voltage at the output SET, "Vset") of the peak current through the transistor Ql and as a consequence the peak inductor current through the converter coil LI . Because Vset is a function of Vin and the duty cycle, the peak inductor current will follow the rectified mains voltage but is adjustable by means of the duty cycle.

This version has some drawbacks.

(i) The PWM frequency should be very high due to the 1st order low pass filter in the switched resistor divider in order to reduce the PWM injected ripple. (ii) The comparator function is not very accurate because the base-emitter voltages of Ql and Q6 do not match which gives an offset of the peak current through current the sense resistor Rshunt. This means that the peak current trough the coil will deviate from the set value Vset.

(iii) The trigger action of the comparator will also not work at a low rectified mains voltage due to the minimum voltage needed to trigger the transistor Q3 of the latch.

Figure 11 shows a second implementation which improves on the disadvantages (ii) and (iii) explained above. The circuit is largely the same as Figure 10 and uses the same reference numbers. Only the comparator 72' and latch circuit/block 68' are modified.

The comparator 72' is more accurate because the switched mode power converter switch Ql is not involved in the comparison. The comparator function is implemented by two transistors Q6, Q8 which have as input the voltage across the current shunt resistor Rshunt (i.e. the voltage at the emitter of Ql) instead of the base voltage of Ql and the voltage at the output SET, "Vset". An output transistor Q13 triggers the latch circuit/block 68. The two transistors used in the comparison have similar base emitter voltages, i.e. Vbe(Q8) ~ Vbe(Q6).

The latch circuit/block 68' is modified but again functions to initiate and keep Ql off just after it has been triggered by the comparator. The latch functions in the same way as described above.

Figure 12 shows a third implementation which also improves on the disadvantages (ii) and (iii) in the same way as the circuit of Figure 11 and further improves significantly on disadvantage (i) by making use of a third order low pass filter in the switched resistor divider.

The circuit of Figure 12 uses the comparator 72' and latch circuit/block 68' of

Figure 11. However, a buffered switched resistor divider 70' is used, having a switched divider part 40 and a buffered third order low pass filter 42. Thus, the switched resistor divider 70' is based on the approach of Figure 3. The output Vset is a function of the rectified mains Vin and the duty cycle according to equation (6) above.

The other circuit blocks function in the same way as described above.

Figure 13 shows a fourth implementation which uses the same latch circuit/block 68 and comparator 72 as the example of Figure 10. A different design of switched resistor divider 70" is used. The input stage of the divider 70" is controlled by an open drain output of the PWM generator. This avoids the need for the transistor Q5 in the switched resistor divider circuit 70. This is a low cost implementation.

Of course, this change to the input stage can be applied to the implementations of Figures 10, 11 and 12 as well, when an open drain PWM signal is available.

In summary, Figure 10 uses an unbuffered filter stage and a low accuracy but simple latch and comparator design. Figure 11 also has an unbuffered filter stage but a more accurate latch and comparator design. Figure 12 has a buffered filter stage with the more accurate latch and comparator design of Figure 11. Figure 13 uses an open-drain switched resistor divider design and an un-buffered filter stage.

Note that the comparator function can be replaced by a real comparator component and the less accurate latch and comparator design of Figure 10.

Note that in all examples the latch function can be replaced by a real SR-latch and power switch.

In the above embodiments, the reference circuit is implemented by a voltage divider whose voltage dividing ratio is depending on the pulse width modulation control signal. Figure 14 provides another implementation in which the voltage divider has a constant dividing ratio but the divided input mains is phase cut in accordance with the pulse width modulation control signal, such that the reference voltage in phase with the input mains and also contains the level information contained by the pulse width modulation control signal.

More specifically, figure 14 is a part of a RCC (ring choke converter) circuit, wherein Q7 is the main power transistor, and the voltage on the capacitor C5 is the reference voltage. That reference voltage is applied on the base of the transistor Q10. The collector of the transistor Q10 is indicative of the converter power, thus when the reference voltage is high, the converter power needs to be high to make the transistor Q10 conductive so as to turn off the main transistor Q7.

As shown in figure 14, the voltage divider R12 and R12 provides a divided voltage in phase with the input mains on the Vbus. This voltage is coupled to the capacitor C5 via a switch Q5. The pulse width modulation control signal PWM DIM applies on the control terminal of the switch Q5. When the pulse width modulation control signal is high, the divided voltage applies on the capacitor C5, and when the pulse width modulation control signal is low, the capacitor C5 would discharge though the resistor R15. Thus the voltage on the capacitor C5 depends on the divided voltage and is also controlled by the duty cycle of the pulse width modulation control signal. Namely the reference voltage on the capacitor 15 contains the level information indicated by the pulse width modulation control signal. Figure 15 shows a I. _PEAK VS. V. _BU_S waveform on different T._ON duty. The upper trace is the V.BUS in a buck-boost mode, so it is a reversed sinusoids waveform, whereas the lower portion, the upper and lower traces are respective Ql I. _PEAK current reference for 100% and 40% T._ON duty respectively. It can be seen that the phase of the current reference follows the phase of the input mains voltage/Vbus thus high power factor can be obtained, meanwhile level control can also be achieved.

The invention can be applied in particular to low cost dimmable LED drivers or low cost lamps.

The invention can be used more generally in high power factor voltage/power supplies, where a multiplication function is needed. Thus, the invention is not limited to control of lighting circuits, but can be applied generally as a level control circuit.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A level control circuit for controlling level, comprising:

a reference circuit (70) for generating a reference voltage from a mains voltage signal (Vin);

a switched mode power converter (66) comprising a main switching transistor (Ql) for controlling the cycles of the switched mode power converter, to generate a level control circuit output for application to a load (18); and

a control circuit (68,72) for generating a control signal for application to the main switching transistor (Ql) based on the reference voltage,

wherein the reference circuit (70) comprises a combining circuit adapted to apply a pulse width modulation control signal indicative of said level such that said reference voltage contains information of said level;

wherein the reference circuit comprises:

- a voltage divider (¾_Ν, R_MO_D, R_DIV) including an adjustment module (Q5) to which the pulse width modulation control signal is applied thereby to change the effective voltage divider ratio to implement level control, and

- a buffering capacitor (Cs) or a buffered low pass filter (42) coupled to the output (SET) of the voltage divider.

2. A level control circuit as claimed in claim 1, wherein the voltage divider comprises a resistor circuit and the combining circuit comprises a resistor-transistor circuit, coupled to the resistor circuit, including an adjustment transistor (Q5) to which the pulse width modulation control signal is applied, thereby to change the effective voltage divider ratio.

3. A level control circuit as claimed in claim 2, wherein the resistor circuit comprises:

- a first resistor (R_IN) between the mains voltage signal and the voltage divider output (SET), and

a further resistor (R_DIV) between the voltage divider output and ground;

and the resistor-transistor circuit comprises: a second resistor (R_MOD) and the adjustment transistor (Q5) in series between the voltage divider output and ground, wherein the pulse width modulation control signal is applied to a control terminal of the adjustment transistor (Q5).

4. A level control circuit as claimed in claim 2, for providing the level control circuit output to a lighting load, wherein the level control circuit comprises a dimming circuit, said pulse width modulation control signal is indicative of a dimming level, and said level control circuit further comprises:

a rectifier (64) for providing a rectified mains voltage signal for the voltage divider (70).

5. A level control circuit as claimed in any preceding claim, wherein the pulse width modulation control signal has a frequency at least 20K Hz.

6. A level control circuit as claimed in any preceding claims 1 to 5, wherein the control circuit comprises a comparator circuit (24) for comparing a voltage indicative of active power stored in the switched mode power converter with the output (SET) from the voltage divider, and a latch circuit (25) for controlling the main switching transistor (Ql) of the switched mode power supply according to an output of the comparator circuit.

7. A level control circuit as claimed in claim 6, further comprises a unit (22, 54) for generating said pulse width modulation control signal, wherein said unit (22, 54) is adapted to:

- comparing a voltage indicative of power delivered out by the switch mode power converter with a further reference voltage, and

- outputting said pulse width modulation control signal according to a result of the comparing.

8. A level control circuit as claimed in any preceding claim, wherein the switched mode power converter comprises a boost converter a buck converter, a fly-back converter or a buck-boost converter.

9. A level control circuit as claimed in claim 1, wherein the reference circuit comprises: a voltage divider (Ri₂, R13) adapted for providing a divided voltage from the mains voltage signal (Vin);

a buffering unit (C5);

and the combining circuit comprises:

a controllable coupling unit (R15), adapted for selectively coupling said divided voltage to said buffer unit in response to said pulse width modulation control signal.

A lighting circuit comprising:

a level control circuit as claimed in any preceding claim; and

an LED lighting arrangement (18) supplied with power by the level control

11. A method of controlling a signal level applied to a load, comprising:

generating a reference voltage from a mains voltage signal;

wherein the method comprises controlling the cycles of the switched mode power converter using the reference voltage,

wherein generating the reference voltage comprises applying a pulse width modulation control signal indicative of said signal level such that the reference voltage contains information of said signal level,

wherein generating the reference voltage comprises dividing the mains voltage signal based on a voltage dividing ratio, wherein said voltage dividing ratio is variable dependent on the pulse width modulation control signal, and

the method further comprising low pass filtering the reference voltage which is the result of the dividing, before using the reference voltage to control the cycles of the switched mode power converter.

12. A method as claimed in claim 11, wherein the reference voltage is generated using a resistor-transistor circuit including an adjustment transistor (Q5), and the method comprises applying the pulse width modulation control signal to the adjustment transistor thereby to change the voltage divider ratio.