WO2016124128A1 - 一种应用于基带处理中的可重构调制解调方法 - Google Patents
一种应用于基带处理中的可重构调制解调方法 Download PDFInfo
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- WO2016124128A1 WO2016124128A1 PCT/CN2016/073139 CN2016073139W WO2016124128A1 WO 2016124128 A1 WO2016124128 A1 WO 2016124128A1 CN 2016073139 W CN2016073139 W CN 2016073139W WO 2016124128 A1 WO2016124128 A1 WO 2016124128A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/36—Modulator circuits; Transmitter circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
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- the invention belongs to the field of wireless communication technologies, and in particular relates to a reconfigurable modulation and demodulation method applied in baseband processing.
- the current short-range wireless communication technologies are basically targeted to specific application fields, including IEEE 802.15.1 (Bluetooth standard), IEEE 802.11b (Wi-Fi), IrDA (infrared data communication technology), UWB (Ultra Wide Band technology), and IEEE 802.15.4b (ZigBee standard) and the like.
- Short-range wireless communication technology has the status quo of multi-mode and multi-standard.
- new standards in terms of its development mode, under the existing various standards, there will be new standards to develop according to their respective technical routes.
- the emergence of new standards means that different metrics and performances may be required or different application areas require different design options. Therefore, for the new standard, it is necessary to redesign the entire wireless communication system.
- different systems have many difficulties in compatibility, upgrade, and adaptation.
- this method has a long development cycle and high development cost. Therefore, the concept of software radio emerges as the times require.
- the main idea is to connect some functional and modular hardware units into an open and generalized hardware platform by means of bus or exchange, and through upgradeable and reconfigurable
- the configured application software is loaded to implement various wireless communication functions, such as a working frequency band, a modem type, a data format, an encryption mode, and a communication protocol.
- the modulation mode can be converted by reconfiguration, but the separate modulation mapping scheme only solves the problem of transmitting signals, and still needs multiple demodulation systems for how to completely receive signals. It is not conducive to the realization of the communication system; in addition, some schemes hope to realize the algorithm of the basic module of the baseband processor by analyzing the processing algorithms needed in the real-time processing of the baseband processing, and using some basic granular units, although this scheme can be compared Flexible change of system parameters to achieve a configurable way of baseband processor, but the configuration content is complex and changeable. The more communication protocols are considered, the configuration content will be more complicated, and the interconnection will be greatly increased while improving resource utilization. The complexity of the line.
- the present invention provides a reconfigurable modulation and demodulation method for use in baseband processing by forming a reconfigurable modular unit in a baseband processor.
- the complete communication system is compatible with the modulation and demodulation modes commonly used in communication technology and conforms to the engineering implementation, which reduces the configuration content, and simplifies the complexity of the algorithm and the reconfigurable unit interconnections, making it easy to implement.
- a reconfigurable modulation and demodulation method applied in baseband processing includes the following steps:
- the transmitter decodes the instruction obtained by the processor, and determines a modulation mode and a corresponding modulation parameter according to a parameter preset in the processor, where the preset parameter includes a transmission code rate, a modulation and demodulation mode, Modulation frequency offset, parameter configuration of the filter;
- the receiver performs signal reception, and the analog data is subjected to analog-to-digital conversion to obtain I/Q two-channel signals with intermediate frequency, and the modulation mode of the received signal and the corresponding pre-stored correspondence in the machine are determined according to the result of decoding of the processor-side processor instruction.
- Demodulation method
- the method of the present invention is compatible with four modulation modes, namely: FSK, MSK, 2DPSK, QDPSK.
- the reconfigurable modulation module in the step (2) includes the following modular units:
- the reconfigurable storage operation unit is configured to obtain an output result by looking up the table according to the information and the input information stored in the RAM memory, or reconfiguring the information stored in the RAM memory according to the instruction of the processor to complete the corresponding computing function;
- the reconfigurable multiply-add operation unit is configured to implement the multiplication function of the complement code based on the Booth coding algorithm, and add the result of the basic unit of the Booth multiplier in the Wallace Tree mode to implement the multiplication and addition function;
- a reconfigurable accumulation operation unit for performing superposition calculation when modulating a signal by using phase information in a modulation process
- serial-to-parallel conversion unit for converting one-way serial bit data into two-way information
- a differential coding unit for differentially encoding data information.
- step (2) corresponds different data preprocessing modes, respectively: as follows: FSK modulation mode corresponding to The data preprocessing method is to oversample the serial bit data a k of the processor by a high frequency clock to obtain a data sequence b k-fsk ; the data preprocessing method corresponding to the 2DPSK modulation mode is to string the processor The row bit data a k is obtained by the differential encoding unit to obtain the data sequence b k-2dpsk ; the data preprocessing method corresponding to the MSK modulation mode is to first pass the serial bit data a k of the processor to the differential encoding unit, and then enter the string and The conversion unit obtains two data sequences q k-msk and p k-msk by oversampling; the data preprocessing method corresponding to the QDPSK modulation mode is to first obtain the serial bit data
- the different modulation modes in step (2) correspond to different waveform shaping modes, and each modulation mode generates I/Q two-way signals by waveform shaping, as follows:
- FSK modulation mode the sequence b k-fsk is reconfigurable multiply-added
- the arithmetic unit and the reconfigurable accumulating unit use the CORDIC algorithm to generate the I/Q two-way signal by using the phase angle information of the frequency change; for the MSK, 2DPSK, and QDPSK modulation methods, the half-wave shaping is implemented through the reconfigurable storage operation unit.
- the internal RAM of the reconfigurable memory operation unit stores the sine and cosine signals with a period twice the transmission rate period, and according to the data sequence obtained after the respective data is preprocessed, the I/ is obtained by the lookup table.
- Q two-way signal.
- the reconfigurable demodulation module in the step (5) includes the following modular units:
- the reconfigurable storage operation unit is configured to obtain an output result by looking up the table according to the information and the input information stored in the RAM memory, or reconfiguring the information stored in the RAM memory according to the instruction of the processor to complete the corresponding computing function;
- the reconfigurable multiply-add operation unit is configured to implement the multiplication function of the complement code based on the Booth coding algorithm, and add the result of the basic unit of the Booth multiplier in the Wallace Tree mode to implement the multiplication and addition function;
- the reconfigurable accumulation operation unit is configured to perform superposition calculation when demodulating the signal by using the phase information and the feedback information in the demodulation process.
- step (5) the original I/Q two fundamental frequency signals of the baseband processor are restored, including the following steps:
- the CORDIC algorithm circuit implemented by the same reconfigurable multiply-add operation unit and the reconfigurable accumulation operation unit on the transmitter side generates the intermediate frequency signals cos(w c t), sin(w c t), and then through the reconfigurable multiplication Adding an operation unit, realizing the calculation of the difference angle formula, filtering out the intermediate frequency component w c in the original I/Q two-way signal, and passing the obtained signal through a low-pass filter;
- the I/Q two-way signals originally transmitted by the transmitter are obtained through the above steps; for the 2DPSK and QDPSK modulation methods, the reconfigurable storage arithmetic unit and the difference formula are used to remove the fundamental frequency to obtain the transmitter. The original transmitted I/Q two-way signal.
- the thresholds of the modulation modes in step (6) are as follows: the thresholds of FSK and MSK are 0, the threshold of 2DPSK is ⁇ /2, and the threshold of QDPSK is ⁇ /4, 3 ⁇ /4, 5 ⁇ /4.
- the system is increased.
- Reconfigurable demodulation mode to enable communication systems
- the reconstruction mode is more complete and can be applied to engineering implementation.
- the reconfigurable mode can make the system improve resource utilization.
- FIG. 2 is a flowchart of a reconfigurable demodulation of the method of the present invention
- 3 is a comparison diagram of bit error performance of each modulation and demodulation method in a Gaussian channel and a theoretical value in the method of the present invention
- FIG. 4 is a comparison diagram of bit error performance of each modulation and demodulation method in the presence of a modulation frequency offset and no frequency offset processing in the method of the present invention.
- the reconfigurable storage arithmetic unit stores the required information through a random access memory (RAM), and the input information is obtained as a lookup table to obtain an output result and output.
- RAM random access memory
- the reconfigurable memory unit is required to perform other arithmetic functions, and the information stored in the RAM can be reconfigured to meet the requirements of the new function.
- the reconfigurable multiply-accumulate unit is based on the Booth encoding algorithm, and implements the basic unit of the multiplier of two 8-bit bandwidth data, and adds the results of the Booth multiplier basic unit in the Wallace Tree mode to achieve multiplication and addition. the result of.
- the most basic multiply-and-accumulate operation can be achieved through the Wallace Tree mode:
- the most multiplication and addition operations used in the baseband modulation and demodulation algorithm can be implemented by a reconfigurable multiply-add operation unit.
- the reconfigurable accumulation operation unit in the modulation and demodulation circuit, obtains different modulation signals by modulating the phase information, and generally adopts an iterative algorithm for obtaining the phase information, in addition to the above two operation units of the present invention, It is also necessary to use the superimposed feedback information, so the present invention employs a reconfigurable accumulation operation unit.
- the serial-to-parallel conversion unit converts one serial bit data into two pieces of information for the MSK and QDPSK modes, so a shared serial-to-parallel conversion unit is used.
- the processor is sent to the transmitter or the receiver by means of instructions.
- the SPI serial peripheral interface is used to send instructions to the processor for subsequent modulation
- the reconfigurable module unit is scheduled according to the data processing manner to implement the corresponding function.
- the instruction pool obtained by SPI represents the data processing mode indication of the transmitter processor in the modulation process.
- the transmitter first decodes the result by the processor instruction. Data preprocessing is performed on the serial bit data a k of the processor.
- the FSK modulation mode data is only oversampled by the high frequency clock to obtain a new sequence b k-fsk ;
- 2DPSK adopts single path difference
- the data sequence is obtained through the differential coding unit.
- ITU-T International Telecommunication Union Telecommunication Standardization Organization
- the MSK, 2DPSK, and QDPSK modulation methods implement half-wave shaping through a reconfigurable memory operation unit. By analyzing the number of over-sampling points, the internal RAM of the reconfigurable memory unit stores two times the sine and cosine signals of the transmission rate period.
- the data sequence after preprocessing by each modulation method is used, and the I/Q two-way signal is obtained by means of a look-up table, and the I-channel signal obtained by MSK is Q signal is
- the instruction pool issued by the SPI represents the data processing mode indication to the receiver processor during the demodulation process.
- the receiver performs signal reception, and the analog data passes through the modulus.
- the converted I/Q two-channel IF signals are with Firstly, the IF signal is filtered by the downmixing circuit and the difference angle formula, and the effect of filtering the image interference is also filtered out.
- the circuit first uses the same reconfigurable multiply-add operation unit as the transmitter and can be heavy.
- the I/Q two-way signals of FSK and MSK are zero intermediate frequency signals
- the I/Q two-way signals of 2DPSK and QDPSK are signals with a fundamental frequency and initial phase related to the code rate, and demodulation is performed by the initial phase difference.
- the I/Q two-way signal obtained in step (6) passes through the reconfigurable storage operation unit, and uses the phase angle information stored in the RAM to obtain the phase of the output sampling point according to the input value of the I/Q two-way signal in a lookup table.
- the angular information is filtered by the phase angle difference to remove a ⁇ generated by the intermediate frequency signal, and the difference between the phase angles of different modulation modes is realized by using different differential interval delay times.
- MSK and FSK have a positive frequency when the signal is transmitting "1", so the phase angle of the sampling point is increasing. When the signal is "0", the frequency is negative, the phase angle of the sampling point is decreasing, and the phase difference can be passed.
- the positive and negative values judge the transmission signal;
- 2DPSK uses the phase difference of the initial phase to realize the demodulation decision due to the differential encoding.
- the phase difference changes that the transmission signal is "1", and the transmission signal "0" is considered unchanged; similarly, QPDSK Due to the differential encoding rule, there are four possibilities for the absolute value of the phase angle difference result, and the two symbols transmitted can be judged by comparison with the threshold.
- the delay time of the phase difference, MSK and FSK are determined by the oversampling rate, 2DPSK is delayed by one signal period, QDPSK is delayed by two signal periods, and the threshold of the demodulation decision is determined according to the above analysis: FSK and MSK are judged by positive and negative values, so the threshold is "0"; 2DPSK phase difference absolute values are "0" and " ⁇ ", respectively, so the threshold is ⁇ /2; QDPSK has three thresholds, respectively ⁇ / 4, 3 ⁇ / 4, 5 ⁇ / 4.
- This embodiment simulates the reconfigurable modulation and demodulation method provided by the method of the present invention, and configures the serial peripheral interface SPI instruction to change the configuration content of the system and the relationship of the interconnection lines to realize different modulation modes and transmission codes. rate.
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Abstract
本发明公开了一种应用于基带处理中的可重构调制解调方法,通过在整个基带处理器中采用可重构调制、解调模块化单元形成完整的通信系统,并对解调方式进行调整来兼容FSK、MSK、2DPSK、QDPSK四种广泛应用的调制方式,解决了发送机端和接收机端的可重构模块匹配问题,在保证通信系统性能要求的前提下,兼容了通信技术中常用的调制解调模式且符合工程实现,降低了配置内容,精简了算法以及可重构单元互连线的复杂度,易于实现。
Description
本发明属于无线通信技术领域,尤其涉及一种应用于基带处理中的可重构调制解调方法。
在半导体和超大规模集成电路技术的高速发展以及低功耗、低成本等各类消费电子产品数据通信的强烈需求的推动下,人们不断的研究探索使得短距离无线通信技术得到了快速提高。目前的短距离无线通信技术基本都针对特定的应用领域,主要包括IEEE 802.15.1(Bluetooth标准)、IEEE 802.11b(Wi-Fi)、IrDA(红外线数据通信技术)、UWB(超宽带技术)和IEEE 802.15.4b(ZigBee标准)等。
短距离无线通信技术存在着多模多标准的现状。同时以其发展方式来看,在现有的多种标准下,还将会有新的标准按照各自的技术路线发展。而新的标准的出现意味着可能需要达到不同的指标和性能或者不同的应用领域需要不同的设计方案。因此,面对于新的标准就需要重新设计整个无线通信系统,同时不同的系统存在兼容、升级、自适应等各方面的诸多难点。而且这种方式的开发周期长,开发成本高。因此,软件无线电的概念应运而生,其主要思想是以总线或者交换的方式,将一些功能化、模块化的硬件单元连接成一个开放式的通用化硬件平台,并通过对可升级、可重新配置的应用软件的加载实现各种无线通信功能,如工作频段、调制解调类型、数据格式、加密模式和通信协议等。
软件无线电概念的提出,使得通过架构上的创新来提高系统性能与灵活性,己经成为了当今通信技术的发展趋势和研究热点。可重构处理架构由于其高效、灵活性的特点,正受到了学术界与工业界越来越多的重视。它的架构特点,使其可以从根本上解决通信系统多模多标准兼容的问题,满足灵活性与高性能并存的需求,是一个非常有前瞻性与挑战性的课题。
近十几年来,学术界已经对可重构基带处理器方面做了较为深入的研究,并提出了一系列解决多种标准协议兼容的调制映射方案,包括:新南威尔士大学(University of New South Wales)提出的MIMO系统中的可重构发射方案,该方案以流水线形式集成多个基带协议的处理单元,可动态选择各流水线处理单元执行特定的基带处理功能(Reconfigurable Pipelined Coprocessor for Multi-mode Communication Transmission,
Design Automation Conference(DAC),201350th ACM/EDAC/IEEE,2013);印度理工学院(IIT Kharagpur)提出的高速下高吞吐量的基于可重构调制映射方案的实现,包括的调制方式为GMSK和QPSK(Design and implementation of a generalized parametrizable modulator for a reconfigurable radio,TENCON 2009-2009IEEE Region 10Conference,2009)。这些方案中虽然兼容了不同的协议标准,可以通过重新配置的方式实现调制方式的转换,但是单独的调制映射方案只解决了发送信号的问题,对于如何完整接收信号仍然需要多个解调系统,不利于通信系统的实现;另外,一些方案希望通过分析基带处理现实中所需要实现的处理算法,利用一些基本的颗粒单元,可以实现基带处理器的基本模块的算法,虽然这种方案中可以比较灵活改变系统参数,实现基带处理器的可配置方式,但是配置内容复杂多变,考虑到的通信协议越多,配置内容将更加复杂,同时在提高资源利用率的同时将会极大地增加互连线的复杂度。
发明内容
发明目的:为了克服现有技术中存在的不足,本发明提供一种应用于基带处理中的可重构调制解调方法,通过在整个基带处理器中采用可重构调制解调模块化单元形成完整的通信系统,兼容了通信技术中常用的调制解调模式且符合工程实现,降低了配置内容,精简了算法以及可重构单元互连线的复杂度,使之易于实现。
技术方案:为实现上述目的,本发明提供的应用于基带处理中的可重构调制解调方法,包括以下步骤:
(1)发射机对处理器得到的指令进行指令译码,并根据处理器中预先设置的参数确定调制方式和对应的调制参数,所述预先设置的参数包括传输码率、调制解调方式、调制频偏、滤波器的参数配置;
(2)利用可重构调制模块根据所确定的调制方式对处理器的串行比特数据ak进行数据处理得到I/Q两路基频信号,所述数据处理包括数据预处理和波形整形;
(3)将所述I/Q两路信号传送至模数转化器进行电信号的加载得到调制信号并发射;
(4)接收机进行信号接收,模拟数据经过模数转换得到I/Q两路带中频的信号,根据接收机侧处理器指令译码的结果确定接收信号的调制方式和本机内预存的对应解调方式;
(5)利用可重构解调模块对所述带中频的信号滤除干扰信息还原出基带处理器原始的I/Q两路基频信号,利用相位差分的方式滤除I/Q两路基频信号中的相位误差;
(6)对不同调制方式采用预先设置的差分间隔和不同阈值来进行解调的判决,最终实现对整个数据流的解调。
其中,为了精简了算法以及可重构单元互连线的复杂度,本发明方法兼容四种调制方式,分别为:FSK、MSK、2DPSK、QDPSK。
其中,根据四种调制方式的数据处理方式,步骤(2)中的可重构调制模块包括以下模块化单元:
可重构存储运算单元,用于根据RAM存储器存储的信息和输入信息以查表的方式得到输出结果,或根据处理器的指令重新配置RAM存储器所存储的信息来完成相应的运算功能;
可重构乘加运算单元,用于以Booth编码算法为基础实现补码的乘法功能,并且以Wallace Tree模式将Booth乘法器基本单元的结果加起来实现乘加功能;
可重构累加运算单元,用于在调制过程中利用相位信息调制信号时进行叠加计算;
串并转换单元,用于将一路的串行比特数据转换为两路信息;
差分编码单元,用于对数据信息进行差分编码。
其中,为了实现电路最大可能的节省资源,对上述四种调制方式的实现算法进行了调整,步骤(2)中不同的调制方式对应不同的数据预处理方式,分别如下:FSK调制方式所对应的数据预处理方式为将所述处理器的串行比特数据ak经过高频时钟进行过采样得到数据序列bk-fsk;2DPSK调制方式所对应的数据预处理方式为将所述处理器的串行比特数据ak经过差分编码单元得到数据序列bk-2dpsk;MSK调制方式所对应的数据预处理方式为先将所述处理器的串行比特数据ak经差分编码单元,之后进入串并转换单元,过采样得到两路数据序列qk-msk和pk-msk;QDPSK调制方式所对应的数据预处理方式为先将所述处理器的串行比特数据ak经过串并转换单元得到两路数据序列ak-qdpsk和bk-qdpsk,再经过差分编码单元得到数据序列ck-qdpsk和dk-qdpsk。
步骤(2)中不同的调制方式对应不同的波形整形方式,各调制方式通过波形整形生成I/Q两路信号,分别如下:对于FSK调制方式,将序列bk-fsk通过可重构乘加运算单元以及可重构累加运算单元利用频率变化的相位角信息采用CORDIC算法,产生I/Q两路信号;对于MSK、2DPSK和QDPSK调制方式,经过可重构存储运算单元实现半波整形,
通过对过采样点数的分析,向可重构存储运算单元内部RAM存储周期为传输码率周期2倍的正弦和余弦信号,根据各自数据预处理之后得到的数据序列,通过查找表的方式得到I/Q两路信号。
其中,根据四种调制方式的数据处理方式,步骤(5)中的可重构解调模块包括以下模块化单元:
可重构存储运算单元,用于根据RAM存储器存储的信息和输入信息以查表的方式得到输出结果,或根据处理器的指令重新配置RAM存储器所存储的信息来完成相应的运算功能;
可重构乘加运算单元,用于以Booth编码算法为基础实现补码的乘法功能,并且以Wallace Tree模式将Booth乘法器基本单元的结果加起来实现乘加功能;
可重构累加运算单元,用于在解调过程中利用相位信息和反馈信息解调信号时进行叠加计算。
其中,步骤(5)中还原基带处理器原始的I/Q两路基频信号,包括以下步骤:
利用与发射机一侧相同的可重构乘加运算单元以及可重构累加运算单元实现的CORDIC算法电路产生中频信号cos(wct)、sin(wct),再通过可重构乘加运算单元,实现和差角公式的计算,滤除原始I/Q两路信号中的中频分量wc,并将所得信号经过低通滤波器;
对于FSK、MSK调制方式,经过上述步骤得到发射机原始发射的I/Q两路信号;对于2DPSK与QDPSK调制方式,还需要利用可重构存储运算单元以及和差公式去除基频才能得到发射机原始发射的I/Q两路信号。
其中,步骤(6)中各调制方式的阈值分别如下:FSK和MSK的阈值为0,2DPSK阈值为π/2,QDPSK有3个阈值,分别为π/4、3π/4、5π/4。
有益效果:利用可重构的调制解调模块,并设定不同调制方式在调制和解调过程中的数据处理,在保证通信系统性能要求的前提下,采用合理的实现算法,兼容了FSK、MSK、2DPSK与QDPSK多种模式的调制解调方案,适应当今通信系统协议标准多变的现状;由于采用了可重构调制解调模块,可以通过对指令的变换灵活来实现对系统参数的重新配置,从而实现无线通信调制解调中各个模块的功能。相对于各种单独的调制解调方式而言,算法分析与仿真均可发现系统性能与之相当,可以达到通信系统的要求;相较于当前提出的可重构调制映射方式,增加了系统的可重构解调模式,使通信系统的可
重构模式实现更为完整,可以应用于工程实现;相比于普通的多种可选择的调制解调方式,可重构模式可以使得系统提高资源利用率。
图1为本发明方法的可重构调制流程图;
图2为本发明方法的可重构解调流程图;
图3为本发明方法中各调制解调方式在高斯信道下与理论值的误比特性能比较图;
图4为本发明方法中各调制解调方式在调制频偏存在的情况下与不加频偏处理的误比特性能比较图。
下面结合实施例对本发明作更进一步的说明。
本实施例中的可重构调制解调模块采用以下基本颗粒的模块化单元:
可重构存储运算单元,通过随机存取存储器(RAM)存储需要的信息,输入信息以查找表的方式得到输出结果并且输出。当处理器的指令改变时,需要可重构存储运算单元完成其他的运算功能,可以重新配置RAM存储的信息以达到新功能的需求。
可重构乘加运算单元,以Booth编码算法为基础,实现两个8bit带宽的数据的乘法器的基本单元,并且以Wallace Tree模式的方式将Booth乘法器基本单元的结果加起来,实现乘加的结果。通过Wallace Tree模式可以实现最基本的乘加运算:
yout=a*b+c*d
基带调制解调算法中用的最多的乘法与加法运算均可以用可重构乘加运算单元实现。
可重构累加运算单元,调制解调电路中,通过调制相位信息得到不同的调制信号,对得到相位信息通常要采用到迭代算法,算法中除了要用到本发明上述的两种运算单元外,还需要用到叠加的反馈信息,因此本发明采用可重构累加运算单元。
串并转换单元,对于MSK和QDPSK两种模式,要将一路的串行比特数据转换为两路信息,故而采用共用的串并转换单元。
差分编码单元,MSK、QDPSK和BPSK三种模式,需要对数据信息进行差分编码,以便在解调算法统一的实现上较为容易,而选用差分编码单元,但需要实现两种差分编码模式,其中MSK与BPSK为单路差分,编码规则为bn=an⊕bn-1;QDPSK编码规则为对应两路码元akbk分别为“00”、“01”、“11”、“10”时,相位角变换Δθ分别为“3/4π”、“1/4π”、“-3/4π”、“-1/4π”。
调制解调实现的具体过程如下:
(1)确定可重构调制解调器可兼容的调制方法,包括最常用的FSK、MSK、2PSK和QPSK,预先设置处理器的一些参数,包括:传输码率、调制解调方式、调制频偏、滤波器的参数配置。
(2)确定上述基本颗粒的模块化单元,完成可重构电路实现的运算,预先设定四个调制方式在调制过程中的数据处理方式以及相应解调过程中的数据处理方式,数据处理方式通过指令形式送达发送机端或接收机端的处理器,如图1和图2所示,本实施例中用SPI串行外设接口将指令送达至处理器,用于在后续的调制、解调中根据数据处理方式调度可重构模块单元来实现相应功能。
(3)调整几种调制解调方法的实现算法,使实现电路最大可能的节省资源。其中FSK和MSK通过相位角差分实现解调。因此2PSK和QPSK采用2DPSK和QDPDK调制方式,在调制之前先通过对数据进行不同差分处理,在解调时通过相位角一个码元周期的差分来还原数据。
(4)如上所述,通过SPI得到的指令池代表调制过程中对发射机处理器的数据处理方式指示,按照图1的可重构调制流程,发射机端首先通过处理器指令译码的结果对处理器的串行比特数据ak进行数据预处理。
其中,FSK调制方式数据只经过高频时钟进行过采样得到新的序列bk-fsk;2DPSK采用单路差分,编码规则为bn=an⊕bn-1,经过差分编码单元得到数据序列bk-2dpsk;MSK采用单路差分,编码规则为bn=an⊕bn-1,先经差分编码单元,之后进入串并转换单元,过采样得到两路数据序列qk-msk和pk-msk;QDPSK先经过串并转换单元得到两路数据序列ak-qdpsk和bk-qdpsk,之后采用国际电信联盟远程通信标准化组织(ITU-T)建议的编码方式进行差分编码,其编码规则为对应两路输入信号码元akbk和输出信号前一周期码元ckdk分别为“00”、“01”、“11”、“10”时,对应相位角θ分别为“1/2π”、“0”、“3/2π”、“π”两个相位角之和为当前周期输出码元对应的相位角,从而得到当前周期输出码元ckdk,最后得到ck-qdpsk和dk-qdpsk,至此,数据处理通过译码指令对各个调制方式实现了数据预处理。
(5)分别对各种调制方式经过预处理的数据序列进行相位角运算实现波形整形,生
成最终输出的I/Q两路信号,将I/Q两路信号进行数模转换,最后进行调制信号发射。
其中,FSK信号通过可重构乘加运算单元以及可重构累加运算单元实现CORDIC算法,产生I路信号cos[2πfdt+θ(t)]和Q路信号sin[2πfdt+θ(t)],式中,fd为中频,此时为零中频信号fd=0,MSK、2DPSK和QDPSK调制方式经过可重构存储运算单元实现半波整形,通过对过采样点数的分析,将可重构存储运算单元内部RAM存储传输码率周期的2倍的正弦和余弦信号,利用各调制方式预处理之后的数据序列,并通过查找表的方式得到I/Q两路信号,MSK得到的I路信号为Q路信号为两路信号相减即可得到MSK信号;2DPSK得到的I路信号为cos(w0t+θk),Q路信号为sin(w0t+θk);QDPSK的I路信号为ck-qdpskcos(w0t),Q路信号为dk-qdpsksin(w0t),其中,θk=-π/4±π/2,Ts为传输数据周期。
(6)如上所述,SPI发出的指令池代表解调过程中对接收机处理器的数据处理方式指示,根据图2的可重构解调流程,接收机进行信号接收,模拟数据经过模数转换得到的I/Q两路带中频的信号分别为和先通过下混频电路利用和差角公式滤除中频信号,同时对系统起到滤除镜像干扰的效果,具体为:该电路首先利用与发射机相同的可重构乘加运算单元以及可重构累加运算单元实现的CORDIC算法电路,产生中频信号cos(wct)、sin(wct),再通过可重构乘加运算单元,实现和差角公式的计算,滤除原始I/Q两路信号中的中频分量wc,之后的信号经过低通滤波器滤除镜像干扰可能存在的高频信号,其中,低通滤波器采用有限冲击响应滤波器FIR,利用可重构存储运算单元存储滤波器系数,通过多个可重构乘加运算单元实现标准FIR滤波器的系数与信号的运算过程,最终得到的各调制方式发射机原始发射的I/Q两路信号,FSK调制方式的I/Q两路信号为cos[θ(t)]和sin[θ(t)];MSK调制方式的I/Q两路信号为和2DPSK的I/Q两路信号为
cos(w0t+θk)和sin(w0t+θk),其中θk=-π/4±π/2,Ts为传输数据周期;QDPSK的I路信号为ck-qdpskcos(w0t),Q路信号为dk-qdpsksin(w0t)。此时,FSK与MSK的I/Q两路信号为零中频信号,2DPSK与QDPSK的I/Q两路信号为带与码率相关的基频和初始相位的信号,通过初始相位差实现解调,2DPSK与QDPSK先要通过一个去基频的电路,得到一个仅与初始相位相关的I/Q两路信号,具体为通过利用可重构存储运算单元以LUT的方式产生此基频信号cos(w0t)和sin(w0t),再通过和差公式去除基频,得到初始相位角的正余弦的值cos(θk)和cos(θk),其中,对于2DPSK调制方式,θk=-π/4±π/2,对于QDPSK调制方式,θk=±π/4、±3π/4。
(7)由于初始相位的未同步将会产生一个Δθ的相位误差,所以之后还将通过求相位差的方式滤除这个误差。步骤(6)中得到的I/Q两路信号通过可重构存储运算单元,利用RAM存储的相位角信息,根据I/Q两路信号的输入值以查找表的方式得到输出采样点的相位角信息,再通过相位角求差的方式滤除去中频信号产生的一个Δθ,利用不同的差分间隔即时延时间实现对不同调制方式的相位角求差。
MSK与FSK由于信号在传输信号“1”时频率为正值,因此采样点相位角在不断增加,传输信号“0”时频率为负值,采样点相位角在不断减小,可以通过相位差的正负值判断传输信号;2DPSK由于差分编码的原因,利用初始相位的相位差实现解调判决,相位差变化这认为传输信号“1”,不变则认为传输信号“0”;同样,QPDSK由于差分编码规则,相位角差分结果的绝对值有四种可能,可以通过与阈值比较判断传输的两个码元。相位差的延迟时间,MSK和FSK由过采样率确定,2DPSK延迟一个信号周期,QDPSK延迟两个信号周期,根据上述分析确定解调判决的阈值:FSK和MSK由正负值判决,因此阈值为“0”;2DPSK相位差绝对值分别为“0”和“π”,因此阈值为π/2;QDPSK有3个阈值,分别为π/4、3π/4、5π/4。
本实施例对本发明方法提供的可重构调制解调方法进行了仿真实验,通过配置串行外设接口SPI指令来改变系统的配置内容和互连线的关系从而实现不同的调制方式和传输码率。
由于MSK的解调模式采用的是相干差分解调,与FSK解调的理论方案相同,仅仅是调制方式和调制频偏有差异,故而理论上的误比特率相同为:1/2exp(-r/4),其中r为
信噪比。同理,2DPSK与QDPSK回来理论误比特率为1/2exp(-r/2)。在传输速率为300kbps的情况下,通过仿真分析和比较可以发现:图3中,可重构调制解调系统的性能接近理论值,在短距离无线通信1%的误比特率的要求下,MSK与FSK分别在11.3dB与11.6dB与理论值大约有0.3dB和0.6dB的性能损失,2DPSK与QDPSK大致都在8.7dB左右,与理论值有大约0.9dB的性能损失。可见,误比特率的增加大致由系统的量化误差、以及算法运算处理过程的截短等原因促成,完全可以达到短距离无线通信系统的误码率需求。
在传输速率为300kbps,频率偏移为20kbps的情况下仿真得到图4,通过对比可以发现:20kbps的调制频偏下,系统性能大致损失0.5dB,可以达到12dB的信噪比下,最坏情况在1%的误码率以下。
Claims (8)
- 一种应用于基带处理中的可重构调制解调方法,其特征在于,该方法包括以下步骤:(1)发射机对处理器得到的指令进行指令译码,并根据处理器中预先设置的参数确定调制方式和对应的调制参数,所述预先设置的参数包括传输码率、调制解调方式、调制频偏、滤波器的参数配置;(2)利用可重构调制模块根据所确定的调制方式对处理器的串行比特数据ak进行数据处理得到I/Q两路基频信号,所述数据处理包括数据预处理和波形整形;(3)将所述I/Q两路信号传送至模数转化器进行电信号的加载得到调制信号并发射;(4)接收机进行信号接收,模拟数据经过模数转换得到I/Q两路带中频的信号,根据接收机侧处理器指令译码的结果确定接收信号的调制方式和本机内预存的对应解调方式;(5)利用可重构解调模块对所述带中频的信号滤除干扰信息还原出基带处理器原始的I/Q两路基频信号,利用相位差分的方式滤除I/Q两路基频信号中的相位误差;(6)对不同调制方式采用预先设置的差分间隔和不同阈值来进行解调的判决,最终实现对整个数据流的解调。
- 根据权利要求1所述的应用于基带处理中的可重构调制解调方法,其特征在于,该方法兼容四种调制方式,分别为FSK、MSK、2DPSK、QDPSK。
- 根据权利要求2所述的应用于基带处理中的可重构调制解调方法,其特征在于,所述步骤(2)中的可重构调制模块包括以下模块化单元:可重构存储运算单元,用于根据RAM存储器存储的信息和输入信息以查表的方式得到输出结果,或根据处理器的指令重新配置RAM存储器所存储的信息来完成相应的运算功能;可重构乘加运算单元,用于以Booth编码算法为基础实现补码的乘法功能,并且以Wallace Tree模式将Booth乘法器基本单元的结果加起来实现乘加功能;可重构累加运算单元,用于在调制过程中利用相位信息调制信号时进行叠加计算;串并转换单元,用于将一路的串行比特数据转换为两路信息;差分编码单元,用于对数据信息进行差分编码。
- 根据权利要求3所述的应用于基带处理中的可重构调制解调方法,其特征在于, 步骤(2)中不同的调制方式对应不同的数据预处理方式,分别如下:FSK调制方式所对应的数据预处理方式为将所述处理器的串行比特数据ak经过高频时钟进行过采样得到数据序列bk-fsk;2DPSK调制方式所对应的数据预处理方式为将所述处理器的串行比特数据ak经过差分编码单元得到数据序列bk-2dpsk;MSK调制方式所对应的数据预处理方式为先将所述处理器的串行比特数据ak经差分编码单元,之后进入串并转换单元,过采样得到两路数据序列qk-msk和pk-msk;QDPSK调制方式所对应的数据预处理方式为先将所述处理器的串行比特数据ak经过串并转换单元得到两路数据序列ak-qdpsk和bk-qdpsk,再经过差分编码单元得到数据序列ck-qdpsk和dk-qdpsk。
- 根据权利要求4所述的应用于基带处理中的可重构调制解调方法,其特征在于,步骤(2)中不同的调制方式对应不同的波形整形方式,各调制方式通过波形整形生成I/Q两路信号,分别如下:对于FSK调制方式,将序列bk-fsk通过可重构乘加运算单元以及可重构累加运算单元利用频率变化的相位角信息采用CORDIC算法,产生I/Q两路信号;对于MSK、2DPSK和QDPSK调制方式,经过可重构存储运算单元实现半波整形,通过对过采样点数的分析,向可重构存储运算单元内部RAM存储周期为传输码率周期2倍的正弦和余弦信号,根据各自数据预处理之后得到的数据序列,通过查找表的方式得到I/Q两路信号。
- 根据权利要求2所述的应用于基带处理中的可重构调制解调方法,其特征在于,所述步骤(5)中的可重构解调模块包括以下模块化单元:可重构存储运算单元,用于根据RAM存储器存储的信息和输入信息以查表的方式得到输出结果,或根据处理器的指令重新配置RAM存储器所存储的信息来完成相应的运算功能;可重构乘加运算单元,用于以Booth编码算法为基础实现补码的乘法功能,并且以Wallace Tree模式将Booth乘法器基本单元的结果加起来实现乘加功能;可重构累加运算单元,用于在解调过程中利用相位信息和反馈信息解调信号时进行叠加计算。
- 根据权利要求6所述的应用于基带处理中的可重构调制解调方法,其特征在于,步骤(5)中还原所述基带处理器原始的I/Q两路基频信号,包括以下步骤:利用与发射机一侧相同的可重构乘加运算单元以及可重构累加运算单元实现的CORDIC算法电路产生中频信号cos(wct)、sin(wct),再通过可重构乘加运算单元,实现和 差角公式的计算,滤除原始I/Q两路信号中的中频分量wc,并将所得信号经过低通滤波器;对于FSK、MSK调制方式,经过上述步骤得到发射机原始发射的I/Q两路信号;对于2DPSK与QDPSK调制方式,还需要利用可重构存储运算单元以及和差公式去除基频才能得到发射机原始发射的I/Q两路信号。
- 根据权利要求7所述的应用于基带处理中的可重构调制解调方法,其特征在于,步骤(6)中各调制方式的阈值分别如下:FSK和MSK的阈值为0,2DPSK阈值为π/2,QDPSK有3个阈值,分别为π/4、3π/4、5π/4。
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CN112702292A (zh) * | 2020-12-15 | 2021-04-23 | 中电科仪器仪表有限公司 | 一种基于查找表的基带码元映射方法 |
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CN115086126B (zh) * | 2021-03-12 | 2023-12-26 | 鹤壁天海电子信息系统有限公司 | 一种基于gmsk信号的同步方法、装置和计算机可读存储介质 |
CN113794562A (zh) * | 2021-09-27 | 2021-12-14 | 南京宁麒智能计算芯片研究院有限公司 | 一种双线性对计算加速系统及方法 |
CN118316769A (zh) * | 2024-06-06 | 2024-07-09 | 北京轩宇信息技术有限公司 | 一种多进制码移键控扩频加msk收发信机fpga的验证方法 |
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