WO2016115922A1 - 空口同步系统及其方法 - Google Patents

空口同步系统及其方法 Download PDF

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Publication number
WO2016115922A1
WO2016115922A1 PCT/CN2015/090734 CN2015090734W WO2016115922A1 WO 2016115922 A1 WO2016115922 A1 WO 2016115922A1 CN 2015090734 W CN2015090734 W CN 2015090734W WO 2016115922 A1 WO2016115922 A1 WO 2016115922A1
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Prior art keywords
synchronization
relay
air interface
base station
synchronization signal
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PCT/CN2015/090734
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English (en)
French (fr)
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田波亮
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中兴通讯股份有限公司
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Publication of WO2016115922A1 publication Critical patent/WO2016115922A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • Embodiments of the present invention relate to, but are not limited to, the field of communications technologies, and in particular, to an air interface synchronization system and method thereof.
  • Communication system synchronization is mainly to achieve synchronization between the core network, base station and communication terminal, especially for TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) and TD-LTE (Time Division).
  • TD-SCDMA Time Division-Synchronous Code Division Multiple Access
  • TD-LTE Time Division
  • Time slot alignment must be required. If the air interfaces between adjacent NodeBs (base stations) are not synchronized, inter-slot interference and uplink and downlink time slot interference may occur.
  • the main synchronization means for realizing synchronization of the communication system include IEEE 1588 (precision clock synchronization protocol standard of network measurement and control system) synchronization, GPS (Global Positioning System) synchronization, Beidou synchronization, air interface synchronization, and the like.
  • each clock state can be one or more of the following three states: slave clock (SLAVE), master clock (MASTER), and original master clock (PASSIVE). The state of each clock is based on the clock algorithm. decided.
  • the air interface synchronization refers to the communication terminal air interface or the relay (relay) base station backhaul link air interface to achieve frame synchronization to the base station air interface, the synchronization source is the base station, the synchronization intermediary is the antenna air interface, and the synchronous receiving device is the communication terminal or the relay base station. Therefore, air interface synchronization is currently commonly used as a synchronization mode for communication terminals or relay base stations.
  • GPS or Beidou as the base station synchronization source.
  • GPS or Beidou it is not only necessary to design a GPS receiver or a Beidou receiver in the base station, but also an external GPS.
  • Antenna or Beidou antenna and there are a lot of cables in the construction The cost of construction and construction.
  • Embodiments of the present invention provide an air interface synchronization system and method thereof.
  • a synchronization source base station configured to send a first synchronization signal to the relay based on an air synchronization technology
  • a relay configured to implement air interface synchronization with the synchronization source base station according to the first synchronization signal, and configured to convert the first synchronization signal into a second synchronization signal based on a preset air interface synchronization to 1588 master clock conversion algorithm And transmitting the second synchronization signal to the synchronous receiving base station;
  • the synchronization receiving base station is configured to perform synchronization with the synchronization source base station according to the second synchronization signal.
  • the relay comprises a relay base station, a communication terminal or a client terminal device CPE.
  • the policy that the trunk implements air interface synchronization with the synchronization source base station according to the first synchronization signal includes an initial synchronization policy and a periodic synchronization policy, where:
  • the initial synchronization strategy estimates a time offset using a time synchronization algorithm based on the first synchronization signal, and estimates a frequency offset based on a frequency synchronization algorithm of the first synchronization signal frequency domain correlation;
  • the periodic synchronization policy performs periodic air interface synchronization on the first MBSFN downlink subframe in the radio frame with the system frame number 0 after the relay enters the MBSFN subframe timing of the multicast single frequency network.
  • the relay converts the first synchronization signal into a second synchronization signal based on a preset air interface synchronization to 1588 primary clock conversion algorithm, including:
  • the relay After performing the air interface synchronization, the relay obtains the frame number, the time offset value, and the frequency offset value from the air interface; adjusts the local clock according to the frequency offset value, adjusts the 10 ms frame header according to the time offset value, and adjusts the initial frame number according to the frame number; Generating a local 1-pulse second PPS according to a 10ms frame header simulation, wherein the 1PPS is aligned with a 10ms frame header; the relay is based on the local 1PPS as a whole second, simulating TOD time information according to a local clock, and constraining the TOD Relationship between time information and corresponding frame number; The local 1PPS and TOD time information is obtained as a second synchronization signal that implements the 1588 master clock.
  • the method for implementing synchronization by using the air interface synchronization system as described above includes:
  • the synchronization source base station transmits the first synchronization signal to the relay based on the air synchronization technology
  • the relay implements air interface synchronization with the synchronization source base station according to the first synchronization signal, and converts the first synchronization signal into a second synchronization signal based on a preset air interface synchronization to 1588 master clock conversion algorithm, and is used for synchronization. Transmitting, by the base station, the second synchronization signal;
  • the synchronization receiving base station performs synchronization with the synchronization source base station according to the second synchronization signal.
  • the relay comprises a relay base station, a communication terminal or a CPE device.
  • the step of performing, by the relay, the air interface synchronization with the synchronization source base station according to the first synchronization signal comprises: an initial synchronization step and a period synchronization step, where:
  • the initial synchronization step includes estimating a time offset using a time synchronization algorithm based on the first synchronization signal, and estimating a frequency offset based on a frequency synchronization algorithm of the first synchronization signal frequency domain correlation;
  • the periodic synchronization step includes performing periodic air interface synchronization on the first MBSFN downlink subframe in the radio frame with the system frame number 0 after the relay enters the MBSFN subframe timing.
  • the step of the relay converting the first synchronization signal into the second synchronization signal based on a preset air interface synchronization to 1588 primary clock conversion algorithm includes:
  • the relay After performing air interface synchronization, the relay obtains a frame number, a time offset value, and a frequency offset value from the air interface;
  • the relay adjusts the local clock according to the frequency offset value, adjusts the 10 ms frame header according to the time offset value, and adjusts the initial frame number according to the frame number;
  • the relay generates a local 1PPS according to a 10ms frame header simulation, wherein the 1PPS is aligned with a 10ms frame header;
  • the relay is based on the local 1PPS as a whole second, simulating TOD time information according to the local clock, and constraining the relationship between the TOD time information and the corresponding frame number;
  • the relay obtains a second synchronization signal that implements the 1588 master clock according to the local 1PPS and TOD time information.
  • the embodiment of the invention further provides a computer readable storage medium storing program instructions, which can be implemented when the program instructions are executed.
  • the embodiment of the present invention provides a new synchronization source for the base station through the existing IEEE 1588 synchronization network port of the base station: air interface synchronization. It can achieve no GPS or Beidou receiver design, no need for external GPS or Beidou antenna, no need to set up GPS or Beidou cable, which can effectively reduce system cost.
  • FIG. 1 is a schematic structural diagram of an air interface synchronization system according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a process for converting from air interface synchronization to 1588 Master in the embodiment
  • FIG. 3 is a schematic diagram of a relay E02 generating a 1PPS and a local 80-bit counter in the embodiment
  • FIG. 4 is a schematic flowchart of an air interface synchronization method according to an embodiment of the present disclosure
  • FIG. 5 is a schematic flowchart of the relay E02 according to the embodiment, which converts the first synchronization signal into a second synchronization signal transmitted to the synchronization receiving base station E03 based on a preset air interface synchronization to 1588 master clock conversion algorithm.
  • an air interface synchronization system provided by this embodiment includes:
  • the synchronization source base station E01 is configured to send the first synchronization signal to the relay E02 based on the air synchronization technology
  • the relay E02 is configured to implement air interface synchronization with the synchronization source base station E01 according to the first synchronization signal, and set to convert the first synchronization signal to the second according to a preset air interface synchronization to 1588 master clock conversion algorithm. Synchronizing the signal and transmitting the second synchronization signal to the synchronization receiving base station;
  • the synchronization receiving base station E03 is arranged to perform synchronization with the synchronization source base station E01 in accordance with the second synchronization signal.
  • the relay E02 includes a relay base station, a communication terminal, or a CPE (Customer) Premise Equipment, customer terminal equipment, hereinafter referred to as CPE equipment).
  • CPE equipment Customer Premise Equipment, customer terminal equipment
  • the synchronous receiving base station E03 can be any type of base station, including 2G, 3G, 4G, and even future 5G standard base stations. From the perspective of base station functions, the synchronous receiving base station E03 It may be a macro base station, a micro base station, a Pico base station (pico base station) or the like.
  • the synchronization source base station E01 and the relay E02 are connected by the air interface L01, and the communication transmission mode is electromagnetic wave, and the relay E02 and the synchronous receiving base station E03 are connected by the Ethernet transmission interface L02, and the communication transmission mode is transmission.
  • the cable for example, the transmission cable can be a twisted pair cable or fiber.
  • the policy that the relay E02 implements air interface synchronization with the synchronization source base station E01 according to the first synchronization signal includes an initial synchronization policy and a periodic synchronization policy, where initial synchronization is usually performed only once, and periodic synchronization needs to continue. Intermittent, where:
  • the initial synchronization strategy estimating a time offset using a time synchronization algorithm based on the first synchronization signal, and estimating a frequency offset based on a frequency synchronization algorithm of the first synchronization signal frequency domain correlation.
  • the initial synchronization of the relay E02 air interface is completed by the relay E02 in the cell selection and Attach.
  • the relay E02 needs to transmit the frame number obtained from the synchronization source base station E01 to the BSP (Board Support Package), and subsequently the FPGA (Field Programmable Gate Array) according to the synchronization source base station E01.
  • the frame number maintenance scheme maintains the frame number.
  • the relay E02 transmits the parsed system, system frame number, time offset value, frequency offset value, and signal available in the PBCH (Physical Broadcast Channel) to the BSP during initial synchronization.
  • PBCH Physical Broadcast Channel
  • the BSP judges whether the received signal is available, and if the signal is available, it will adjust the time offset to keep the frame header synchronized; and use the time offset value to calculate the frequency offset value by writing a DAC (Digital to analog converter) To control the local clock.
  • DAC Digital to analog converter
  • a shared memory interface between the PHY and the BSP adds a flag indicating whether the PHY is performing cycle synchronization or initial synchronization, and the BSP determines according to this flag. Whether to use the system frame number passed by the PHY.
  • the period synchronization policy after the relay E02 enters the M subframe (ie, the MBSFN (Multicast Broadcast Single Frequency Network) subframe, referred to as the M subframe), the system frame number is 0.
  • the first MD (MBSFN Downlink, MBSFN downlink) subframe in the radio frame is used for periodic air interface synchronization.
  • the cycle synchronization does not require the control of the upper layer software, and the PHY of the relay E02 is completely derived from the main decision.
  • the period of the air interface synchronization is fixed in the code, for example, 1024 radio frame time; the period can also be shortened, for example, 100 radio frames to improve the synchronization precision. Since the system frame number is cyclically between 0 and 1023, in this embodiment, after the relay E02 enters the M subframe timing, the PHY performs a periodic air interface in the first MD subframe in the radio frame with the system frame number 0. Synchronize.
  • the cycle is synchronized, the frame header alignment is required to ensure the accuracy. However, the alignment cannot be adjusted only by time offset.
  • the frame header When the offset is greater than 1us, the frame header will be realigned. If the frame header is adjusted forward, the relay E02 will be disconnected from the network. In), the frequency offset is calculated according to the time offset and the adjusted time interval (high-precision frequency offset estimation, implemented in BSP), and the frame header is aligned by frequency offset adjustment. Finally, the PHY calculates the time offset, time interval, system, and signal available for transmission to the BSP during cycle synchronization.
  • the 1588Master must have a premise that is accurate time information (seconds and nanoseconds), but the air interface synchronization can only obtain an accurate 10ms, without accurate seconds and nanoseconds, so the related technology is not in the communication device.
  • This embodiment is based on the base station E03, which is a synchronous device.
  • the actual need is not accurate seconds and nanoseconds, but an accurate 10ms. Therefore, in the relay E02 device 1588Master, 10ms is used as the synchronization source, and the local seconds are simulated. Nanoseconds, then transmit clock synchronization information to E03 in standard IEEE1588Master mode.
  • the relay E02 After the air interface is synchronized, the relay E02 obtains the 10 ms frame header and the frame number, and extracts the latest frame number Fs after the 10 ms is valid (ie, effective), assuming that the local time corresponding to the Fs frame number is 0, and the estimated Fn (nth frame) corresponds to The local time is estimated by (Fn-Fs)/100. Fn corresponds to 1PPS (pulse per second) aligned with the 10ms frame header. At this time, the nanosecond bit of the 1588 80bit counter is cleared to 0, and the 10ms frame header is aligned with the entire second bit required by the local 1588. The implementation replaces the frame number with local time.
  • the step of generating the 1PPS and local 80bit counter time information by the relay E02 is as follows:
  • the flag Flag is set to be high
  • the 1PPS corresponding to the 10ms frame header obtained in the previous 4 steps is used as the basis of the whole second.
  • the local FPGA starts the counter timing and simulates the TOD (Time of Day) time information.
  • the relay E02 generates a 1PPS and a local 80-bit counter.
  • the improved calculation method is: after the air interface is synchronized, the relay E02 acquires the 10 ms frame header and the frame number, and extracts the nearest 100 integer multiple of the frame after 10 ms is valid. No. Fn, assuming that the local time corresponding to the 0 frame number is 0, the local time corresponding to Fn is estimated, and the estimation method is Fn/100. Fn corresponds to the 1PPS aligned with the 10ms frame header. At this time, the nanosecond bit of the 1588 80bit counter is cleared to 0, and the 10ms frame header is aligned with the entire second bit required by the local 1588. Therefore, the local time can be used instead of the frame number. .
  • the relay E02 generates 1PPS and the local 80bit counter time information improvement calculation method is shown in Figure 3, the steps are as follows:
  • the flag Flag is set to be high
  • the 1PPS corresponding to the 10ms frame header obtained in the previous 4 steps is used as the basis of the whole second, and the local FPGA starts the counter timing to simulate the TOD time information.
  • the policy flow of the relay E02 based on a preset air interface synchronous to 1588 primary clock conversion algorithm to convert the first synchronization signal into a second synchronization signal transmitted to the synchronous receiving base station E03 is :
  • the relay E02 After the air interface synchronization is performed by the relay E02, the relay E02 is from the synchronization source base station E01.
  • the air interface obtains the frame number, the time offset value, and the frequency offset value; adjusts the local clock according to the frequency offset value, adjusts the 10 ms frame header according to the time offset value, and adjusts the initial frame number according to the frame number; and generates a local 1PPS according to the 10 ms frame header simulation, wherein The 1PPS is aligned with a 10ms frame header; the relay E02 is based on the local 1PPS as a whole second, simulating TOD time information according to the local clock, and constraining the relationship between the TOD time information and the corresponding frame number; Following E02, a second synchronization signal implementing the 1588 master clock is obtained according to the local 1PPS and TOD time information.
  • the BSP adjusts the local clock and the FPGA timestamp reference by 1588 timestamp calculation, and then synchronizes 10ms;
  • the BSP acquires the TOD from the FPGA and maintains the frame number according to the constraint relationship
  • the synchronous receiving base station E03 takes 10ms and the frame number to adjust the local clock, and the synchronization is completed.
  • the embodiment further provides a method for implementing synchronization by using the air interface synchronization system as described above, which includes:
  • the synchronization source base station E01 sends a first synchronization signal to the relay E02 based on the air synchronization technology.
  • the relay E02 implements air interface synchronization with the synchronization source base station E01 according to the first synchronization signal, and converts the first synchronization signal into a second synchronization signal according to a preset air interface synchronization to 1588 master clock conversion algorithm. And transmitting the second synchronization signal to the synchronous receiving base station E03;
  • the synchronous receiving base station E03 performs synchronization with the synchronization source base station E01 according to the second synchronization signal.
  • the relay E02 includes a relay base station, a communication terminal, or a CPE device.
  • the synchronous base station E03 can be any type of base station, including 2G, 3G, 4G, and even future 5G base stations. From the perspective of base station functions, the synchronous base station E03 can It is a macro base station, a micro base station, a Pico base station, and the like.
  • the synchronization source base station E01 and the relay E02 are connected by the air interface L01, and the communication transmission mode is electromagnetic wave, and the relay E02 and the synchronous receiving base station E03 are connected through the Ethernet.
  • the port L02 is a communication connection, and the communication transmission mode is a transmission cable.
  • the transmission cable is a twisted pair network cable or an optical fiber.
  • the step of implementing air interface synchronization with the synchronization source base station E01 according to the first synchronization signal includes an initial synchronization step and a period synchronization step, where:
  • the initial synchronization step estimating a time offset using a time synchronization algorithm based on the first synchronization signal, and estimating a frequency offset based on a frequency synchronization algorithm of the first synchronization signal frequency domain correlation;
  • the relay E02 air interface initial synchronization is completed by the relay E02 at the time of cell selection and Attach.
  • the relay E02 needs to transmit the frame number acquired from the synchronization source base station E01 to the BSP, and then the FPGA maintains the frame number for maintenance.
  • the relay E02 transmits the parsed system, system frame number, time offset value, frequency offset value and signal available in the PBCH to the BSP during initial synchronization.
  • the BSP judges whether the received signal is available. If the signal is available, it will adjust the time offset to keep the frame header synchronized; and use the time offset value to calculate the frequency offset value to control the local clock by writing the DAC.
  • the shared memory interface between the PHY and the BSP adds a flag indicating whether the PHY is performing cycle synchronization or initial synchronization, and the BSP determines whether to use the system transmitted by the PHY according to this flag. Frame number.
  • the cycle synchronization step after the relay E02 enters the M subframe timing, performs periodic air interface synchronization in the first MD subframe in the radio frame with the system frame number 0.
  • the control of the upper layer software is not required, and the PHY of the relay E02 is completely derived from the main decision.
  • the period of the air interface synchronization is fixed in the code, for example, 1024 radio frame time; the period can also be shortened, for example, 100 radio frames to improve the synchronization precision. Since the system frame number is cyclically between 0 and 1023, in this embodiment, after the relay E02 enters the M subframe timing, the PHY performs a periodic air interface in the first MD subframe in the radio frame with the system frame number 0. Synchronize. When the cycle is synchronized, the frame header alignment is required to ensure the accuracy. However, the alignment cannot be adjusted only by time offset.
  • the frame header When the offset is greater than 1us, the frame header will be realigned. If the frame header is adjusted forward, the relay E02 will be disconnected from the network. In), the frequency offset is calculated according to the time offset and the adjusted time interval (high-precision frequency offset estimation, implemented in BSP), and the frame header is aligned by frequency offset adjustment. Finally, the PHY calculates the time offset, time interval, system, and signal available for transmission to the BSP during cycle synchronization.
  • This embodiment is based on the base station E03 as a synchronous device, and the actual need is not accurate seconds and nanoseconds, but accurate 10ms, so 10ms in the relay E02 device 1588Master Synchronize the source, virtualize the local seconds and nanoseconds, and then transmit the clock synchronization information to E03 in standard IEEE1588Master mode.
  • the relay E02 After the air interface is synchronized, the relay E02 obtains the 10 ms frame header and the frame number, and extracts the latest frame number Fs after 10 ms is valid. It is assumed that the local time corresponding to the Fs frame number is 0, and the local time corresponding to Fn is estimated. The calculation method is (Fn). -Fs)/100. Fn corresponds to the 1PPS aligned with the 10ms frame header. At this time, the nanosecond bit of the 1588 80bit counter is cleared to 0, and the 10ms frame header is aligned with the entire second bit required by the local 1588. Therefore, the local time can be used instead of the frame number. .
  • the step of generating the 1PPS and local 80bit counter time information by the relay E02 is as follows:
  • the flag Flag is set to be high
  • the 1PPS corresponding to the 10ms frame header obtained in the previous 4 steps is used as the basis of the whole second, and the local FPGA starts the counter timing to simulate the TOD time information.
  • the relay E02 generates a 1PPS and a local 80-bit counter.
  • the improved calculation method is: after the air interface is synchronized, the relay E02 acquires the 10 ms frame header and the frame number, and extracts the nearest 100 integer multiple of the frame after 10 ms is valid. No. Fn, assuming that the local time corresponding to the 0 frame number is 0, the local time corresponding to Fn is estimated, and the estimation method is Fn/100. Fn corresponds to the 1PPS aligned with the 10ms frame header. At this time, the nanosecond bit of the 1588 80bit counter is cleared to 0, and the 10ms frame header is aligned with the entire second bit required by the local 1588. Therefore, the local time can be used instead of the frame number. .
  • the relay E02 generates 1PPS and the local 80bit counter time information improvement calculation method is shown in Figure 3, the steps are as follows:
  • the flag Flag is set to be high
  • the 1PPS corresponding to the 10ms frame header obtained in the previous 4 steps is used as the basis of the whole second, and the local FPGA starts the counter timing to simulate the TOD time information.
  • the step of the relay E02 converting the first synchronization signal to the second synchronization signal transmitted to the synchronization receiving base station E03 based on the preset air interface synchronization to 1588 master clock conversion algorithm includes:
  • S201 After performing air interface synchronization, obtaining a frame number, a time offset value, and a frequency offset value from the air interface;
  • S203 Simulate TOD time information according to the local clock, and constrain the relationship between the TOD time information and the corresponding frame number, based on the local 1PPS as a whole second;
  • the BSP adjusts the local clock and the FPGA timestamp reference by 1588 timestamp calculation, and then synchronizes 10ms;
  • the BSP acquires the TOD from the FPGA and maintains the frame number according to the constraint relationship
  • the synchronous receiving base station E03 takes 10ms and the frame number to adjust the local clock, and the synchronization is completed.
  • the embodiment of the present invention provides a new synchronization source for the base station through the existing IEEE 1588 synchronization network port of the base station: air interface synchronization. It can achieve no GPS or Beidou receiver design, no need for external GPS or Beidou antenna, no need to set up GPS or Beidou cable, which can effectively reduce system cost.

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Abstract

本发明实施例公开了一种空口同步系统及其方法。所述系统包括：同步源基站，设置为基于空中同步技术向中继发送第一同步信号；中继，设置为依据所述第一同步信号与所述同步源基站实现空口同步，以及设置为基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；以及同步受用基站，设置为依据所述第二同步信号执行与所述同步源基站的同步。

Description

空口同步系统及其方法 技术领域
本发明实施例涉及但不限于通讯技术领域，尤其涉及一种空口同步系统及其方法。
背景技术
通信系统同步主要是要实现核心网、基站、通信终端三者之间的同步，特别对于TD-SCDMA(Time Division-Synchronous Code Division Multiple Access，时分同步码分多址)和TD-LTE(Time Division Long Term Evolution，分时长期演进)而言，要支持同频组网必须要求时隙对齐，如果相邻NodeB(基站)之间空口不同步，会产生时隙间干扰和上下行时隙干扰。
相关技术中，实现通讯系统同步的主要同步手段包括IEEE 1588(网络测量和控制系统的精密时钟同步协议标准)同步、GPS(Global Positioning System，全球定位系统)同步、北斗同步、空口同步等。
其中，IEEE 1588标准是关于联网度量和控制系统的精确时钟同步协议，用于精确地同步网络和系统的时钟。一个1588精密时钟系统包括多个节点，每一个节点都代表一个时钟，时钟之间经由网络连接。在网络中，每一个时钟状态可以是下面3种状态的一种或多种：从属时钟(SLAVE)、主时钟(MASTER)和原主时钟(PASSIVE)，每个时钟所处的状态是根据时钟算法决定的。
空口同步是指通信终端空口或Relay(中继)基站回传链路空口向基站空口实现帧同步，其同步源头是基站，同步中介是天线空口，同步受用设备是通信终端或Relay基站。因此，空口同步目前通常作为通信终端或Relay基站的同步方式。
相关技术中，大多数将GPS或北斗作为基站同步源，在实际应用当中，在将GPS或北斗作为基站同步源时，不仅仅需要在基站内设计GPS接收机或北斗接收机，还需要外接GPS天线或北斗天线，且在施工时有不菲的线缆成 本和施工成本。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本发明实施例提供一种空口同步系统及其方法。
其中，本发明实施例提供的一种空口同步系统，包括：
同步源基站，设置为基于空中同步技术向中继发送第一同步信号；
中继，设置为依据所述第一同步信号与所述同步源基站实现空口同步，以及设置为基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；以及
同步受用基站，设置为依据所述第二同步信号执行与所述同步源基站的同步。
可选地，其中，所述中继包括中继基站、通信终端或客户终端设备CPE。
可选地，其中，所述中继依据所述第一同步信号与所述同步源基站实现空口同步的策略包括初始同步策略和周期同步策略，其中：
所述初始同步策略，采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏；
所述周期同步策略，在所述中继进入多播单频网络MBSFN子帧时序后，在系统帧号为0的无线帧中的第一个MBSFN下行子帧做周期空口同步。
可选地，其中，所述中继基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，包括：
在执行空口同步后，所述中继从空口获取帧号、时偏值、频偏值；根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；根据10ms帧头模拟产生本地1脉冲秒PPS，其中，所述1PPS与10ms帧头对齐；所述中继以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；所述中继依据所述 本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
其中，本发明实施例提供的一种应用如上所述的空口同步系统实现同步的方法，其包括：
同步源基站基于空中同步技术向中继发送第一同步信号；
中继依据所述第一同步信号与所述同步源基站实现空口同步，以及基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；
同步受用基站依据所述第二同步信号执行与所述同步源基站的同步。
可选地，其中，所述中继包括中继基站、通信终端或CPE设备。
可选地，其中，所述中继依据所述第一同步信号与所述同步源基站实现空口同步的步骤包括：初始同步步骤和周期同步步骤，其中：
所述初始同步步骤包括，采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏；
所述周期同步步骤包括，在所述中继进入MBSFN子帧时序后，在系统帧号为0的无线帧中的第一个MBSFN下行子帧做周期空口同步。
可选地，其中，所述中继基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号的步骤包括：
在执行空口同步后，所述中继从空口获取帧号、时偏值、频偏值；
所述中继根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；
所述中继根据10ms帧头模拟产生本地1PPS，其中，所述1PPS与10ms帧头对齐；
所述中继以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；
所述中继依据所述本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
本发明实施例还提供一种计算机可读存储介质，存储有程序指令，当该程序指令被执行时可实现上述方法。
本发明实施例通过基站已有的IEEE 1588同步网口，为基站提供一种新的同步源：空口同步。可达到不需GPS或北斗接收机设计、不需外接GPS或北斗天线、不需架设GPS或北斗线缆，可有效降低系统成本。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
图1为本实施例提供的一种空口同步系统架构示意图；
图2为本实施例中实现从空口同步向1588Master的转换流程示意图；
图3为本实施例中中继E02产生1PPS和本地80bit计数器的示意图；
图4为本实施例提供的一种空口同步方法流程示意图；
图5为本实施例提供的中继E02基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为向同步受用基站E03传输的第二同步信号的流程示意图。
本发明的实施方式
下面结合附图对本发明实施例作详细描述。
参考图1所示，本实施例提供的一种空口同步系统，包括：
同步源基站E01，设置为基于空中同步技术向中继E02发送第一同步信号；
中继E02，设置为依据所述第一同步信号与所述同步源基站E01实现空口同步，以及设置为基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；
同步受用基站E03，设置为依据所述第二同步信号执行与所述同步源基站E01的同步。
本实施例中，所述中继E02包括中继基站、通信终端或CPE(Customer  Premise Equipment，客户终端设备，以下称为CPE设备)。从基站的制式角度而言，所述同步受用基站E03可以为任何一种制式的基站，包括2G、3G、4G，甚至未来的5G制式基站，从基站功能角度而言，所述同步受用基站E03可以为宏基站、微基站、Pico基站(微微基站)等。
参考图1，所述同步源基站E01与中继E02通过空口L01通讯连接，通讯传输方式为电磁波，所述中继E02与同步受用基站E03通过以太网传输接口L02通讯连接，通讯传输方式为传输线缆，例如所述传输线缆可以为双绞网线或光纤。
可选地，所述中继E02依据所述第一同步信号与所述同步源基站E01实现空口同步的策略包括初始同步策略和周期同步策略，初始同步通常只进行1次，周期同步需要持续不间断进行，其中：
所述初始同步策略：采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏。
中继E02空口初始同步由中继E02在小区选择与Attach(附着)时完成。中继E02需要将从同步源基站E01获取到的帧号传给BSP(Board Support Package，板级支持包)，后续由FPGA(Field Programmable Gate Array，现场可编程门阵列)按照同步源基站E01的帧号维护方案来维护帧号。中继E02在初始同步时将PBCH(Physical Broadcast Channel，物理广播信道)中解析的制式、系统帧号、时偏值、频偏值和信号是否可用传输给BSP。BSP根据收到的信号是否可用进行判断，如果信号可用则将进行时偏的调整，保持帧头的同步；并利用时偏值计算出频偏值通过写DAC(Digital to analog converter，数字模拟转换器)来控制本地时钟。为了区分中继E02的PHY(Physical Layer，物理层)是否向BSP传递帧号，PHY和BSP之间的共享内存接口增加一个标志位，指示PHY正在执行周期同步还是初始同步，BSP根据这个标志决定是否使用PHY传过来的系统帧号。
所述周期同步策略：在所述中继E02进入M子帧(即MBSFN(Multicast Broadcast Single Frequency Network，多播单频网络)子帧，简称M子帧)时序后，在系统帧号为0的无线帧中的第一个MD(MBSFN Downlink，MBSFN下行)子帧做周期空口同步。
周期同步不需要上层软件的控制，完全由中继E02的PHY来自主决策。空口同步的周期在代码中固定，比如，1024个无线帧时间；也可以将周期缩短，比如，100个无线帧，以提高同步的精度。由于系统帧号在0～1023之间循环，在本实施例中：在中继E02进入M子帧时序后，PHY在系统帧号为0的无线帧中的第一个MD子帧做周期空口同步。周期同步的时候，需要帧头对齐才能保证精度，但是不能只靠时偏调整对齐(时偏大于1us就会重新对齐帧头，如果是向前调整帧头，中继E02就会脱网重新接入)，要按照时偏和调整的时间间隔算出频偏(高精度频偏估计，在BSP实现)，通过频偏调整来对齐帧头。最终，PHY在周期同步时将计算得到的时偏值、时间间隔、制式和信号是否可用传输给BSP。
根据IEEE1588规范，1588Master必须具备一个前提即精确的时间信息(秒和纳秒)，但是空口同步只能获取到准确的10ms，不具备准确的秒和纳秒，所以相关技术在通信设备中没有将空口同步转1588Master的先例。
本实施例立足于作为同步受用设备的基站E03，实际需要的不是准确的秒和纳秒，而是准确的10ms，因此在中继E02设备1588Master中以10ms为同步源头，模拟了本地的秒和纳秒，然后以标准IEEE1588Master方式向E03传输时钟同步信息。
空口同步后，中继E02获取到10ms帧头和帧号，提取10ms有效(即生效)后的最近的帧号Fs，假设Fs帧号对应的本地时间为0，推算Fn(第n帧)对应的本地时间，推算方法为(Fn-Fs)/100。Fn对应着与10ms帧头对齐的1PPS(pulse per second，脉冲秒)，此时将1588的80bit计数器的纳秒位清0，达到了10ms帧头与本地1588需要的整秒位对齐，因此可以实现用本地时间替代帧号传递。
其中，中继E02产生1PPS和本地80bit计数器时间信息步骤如下：
(1)10ms帧头和帧号有效时，置标志Flag为高；
(2)Flag为高后用10ms锁存起始帧号Fs，下一帧头处从1开始计时；
(3)帧号Fn＝Fs+100整数倍时，产生1PPS，此时读取锁存的帧号，计算相对于起始帧号Fs的整秒数，整秒数＝(Fn-Fs)/100；
(4)计算整数秒与本地实时的80bit计数器秒位的偏差，将偏差值补偿到1588的本地实时80bit计数器，并将ns(纳秒)位清零，补偿完成后置Flag为0；
(5)以前面4步获取到的与10ms帧头对应1PPS作为整秒基础，本地FPGA开始进行计数器计时，模拟TOD(Time of Day，一天的时间)时间信息。
特别地，为了更容易实现，中继E02产生1PPS和本地80bit计数器改进计算方法为：空口同步后，中继E02获取到10ms帧头和帧号，提取10ms有效后的最近的100整数倍的帧号Fn，假设0帧号对应的本地时间为0，推算Fn对应的本地时间，推算方法为Fn/100。Fn对应着与10ms帧头对齐的1PPS，此时将1588的80bit计数器的纳秒位清0，达到了10ms帧头与本地1588需要的整秒位对齐，因此可以实现用本地时间替代帧号传递。
其中，中继E02产生1PPS和本地80bit计数器时间信息改进计算方法见附图3所示，步骤如下：
(1)10ms帧头和帧号有效时，置标志Flag为高；
(2)Flag为高后用10ms锁存帧号，判断锁存的帧号的下一帧是否为100的整数倍，如果是，下一帧头处从0开始计时；
(3)Fn为100的整数倍时，产生1PPS，此时读取锁存的帧号，计算相对于帧号为0时的整秒数，整秒数＝Fn/100(Fn是100的整数倍)；
(4)计算整数秒与本地实时的80bit计数器秒位的偏差，将偏差值补偿到1588的本地实时80bit计数器,并将ns位清零，补偿完成后置Flag为0；
(5)以前面4步获取到的与10ms帧头对应1PPS作为整秒基础，本地FPGA开始进行计数器计时，模拟TOD时间信息。
参考图2，本实施例中，所述中继E02基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为向同步受用基站E03传输的第二同步信号的策略流程为：
在所述中继E02执行空口同步后，所述中继E02从所述同步源基站E01 的空口获取帧号、时偏值、频偏值；根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；根据10ms帧头模拟产生本地1PPS，其中，所述1PPS与10ms帧头对齐；所述中继E02以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；所述中继E02依据所述本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
同步受用基站E03作为1588Slave，算法恢复了10ms(此10ms与中继E02的10ms同步)，并调整本地时钟与10ms同步，过程为：
(1)同步受用基站E03作为1588Slave，与中继E02完成1588时钟同步；
(2)BSP通过1588时间戳计算调整本地时钟和FPGA时间戳基准，进而同步10ms；
(3)BSP从FPGA获取TOD并根据约束关系维护帧号；
(4)同步受用基站E03拿到10ms和帧号调整本地时钟，同步完成。
相应地，参考图4所示，本实施例还提供了一种应用如上所述的空口同步系统实现同步的方法，其包括：
S10、同步源基站E01基于空中同步技术向中继E02发送第一同步信号；
S20、中继E02依据所述第一同步信号与所述同步源基站E01实现空口同步，以及基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站E03传输所述第二同步信号；
S30、同步受用基站E03依据所述第二同步信号执行与所述同步源基站E01的同步。
本实施例中，所述中继E02包括中继基站、通信终端或CPE设备。
从基站的制式角度而言，所述同步受用基站E03可以为任何一种制式基站，包括2G、3G、4G，甚至未来的5G制式基站，从基站功能角度而言，所述同步受用基站E03可以为宏基站、微基站、Pico基站等。
参考图1，所述同步源基站E01与中继E02通过空口L01通讯连接，通讯传输方式为电磁波，所述中继E02与同步受用基站E03通过以太网传输接 口L02通讯连接，通讯传输方式为传输线缆，例如所述传输线缆为双绞网线或光纤。
可选地，依据所述第一同步信号与所述同步源基站E01实现空口同步的步骤包括初始同步步骤和周期同步步骤，其中：
所述初始同步步骤：采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏；
在该初始同步步骤中，中继E02空口初始同步由中继E02在小区选择与Attach时完成。中继E02需要将从同步源基站E01获取到的帧号传给BSP，后续由FPGA按来进行维护帧号。中继E02在初始同步时将PBCH中解析的制式、系统帧号、时偏值、频偏值和信号是否可用传输给BSP。BSP根据收到的信号是否可用进行判断，如果信号可用则将进行时偏的调整，保持帧头的同步；并利用时偏值计算出频偏值通过写DAC来控制本地时钟。为了区分中继E02的PHY是否向BSP传递帧号，PHY和BSP之间的共享内存接口增加一个标志位，指示PHY正在执行周期同步还是初始同步，BSP根据这个标志决定是否使用PHY传过来的系统帧号。
所述周期同步步骤：在所述中继E02进入M子帧时序后，在系统帧号为0的无线帧中的第一个MD子帧做周期空口同步。
在该周期同步步骤中，不需要上层软件的控制，完全由中继E02的PHY来自主决策。空口同步的周期在代码中固定，比如，1024个无线帧时间；也可以将周期缩短，比如，100个无线帧，以提高同步的精度。由于系统帧号在0～1023之间循环，在本实施例中：在中继E02进入M子帧时序后，PHY在系统帧号为0的无线帧中的第一个MD子帧做周期空口同步。周期同步的时候，需要帧头对齐才能保证精度，但是不能只靠时偏调整对齐(时偏大于1us就会重新对齐帧头，如果是向前调整帧头，中继E02就会脱网重新接入)，要按照时偏和调整的时间间隔算出频偏(高精度频偏估计，在BSP实现)，通过频偏调整来对齐帧头。最终，PHY在周期同步时将计算得到的时偏值、时间间隔、制式和信号是否可用传输给BSP。
本实施例立足于作为同步受用设备的基站E03，实际需要的不是准确的秒和纳秒，而是准确的10ms，因此在中继E02设备1588Master中以10ms为 同步源头，虚拟了本地的秒和纳秒，然后以标准IEEE1588Master方式向E03传输时钟同步信息。
空口同步后，中继E02获取到10ms帧头和帧号，提取10ms有效后的最近的帧号Fs，假设Fs帧号对应的本地时间为0，推算Fn对应的本地时间，推算方法为(Fn-Fs)/100。Fn对应着与10ms帧头对齐的1PPS，此时将1588的80bit计数器的纳秒位清0，达到了10ms帧头与本地1588需要的整秒位对齐，因此可以实现用本地时间替代帧号传递。
其中，中继E02产生1PPS和本地80bit计数器时间信息步骤如下：
(1)10ms帧头和帧号有效时，置标志Flag为高；
(2)Flag为高后用10ms锁存起始帧号Fs，下一帧头处从1开始计时；
(3)帧号Fn＝Fs+100整数倍时，产生1PPS，此时读取锁存的帧号，计算相对于起始帧号Fs的整秒数，整秒数＝(Fn-Fs)/100；
(4)计算整数秒与本地实时的80bit计数器秒位的偏差，将偏差值补偿到1588的本地实时80bit计数器，并将ns位清零，补偿完成后置Flag为0；
(5)以前面4步获取到的与10ms帧头对应1PPS作为整秒基础，本地FPGA开始进行计数器计时，模拟TOD时间信息。
特别地，为了更容易实现，中继E02产生1PPS和本地80bit计数器改进计算方法为：空口同步后，中继E02获取到10ms帧头和帧号，提取10ms有效后的最近的100整数倍的帧号Fn，假设0帧号对应的本地时间为0，推算Fn对应的本地时间，推算方法为Fn/100。Fn对应着与10ms帧头对齐的1PPS，此时将1588的80bit计数器的纳秒位清0，达到了10ms帧头与本地1588需要的整秒位对齐，因此可以实现用本地时间替代帧号传递。
其中，中继E02产生1PPS和本地80bit计数器时间信息改进计算方法见附图3所示，步骤如下：
(1)10ms帧头和帧号有效时，置标志Flag为高；
(2)Flag为高后用10ms锁存帧号，判断锁存的帧号的下一帧是否为100的整数倍，如果是，下一帧头处从0开始计时；
(3)Fn为100的整数倍时，产生1PPS，此时读取锁存的帧号，计算相 对于帧号为0时的整秒数，整秒数＝Fn/100(Fn是100的整数倍)；
(4)计算整数秒与本地实时的80bit计数器秒位的偏差，将偏差值补偿到1588的本地实时80bit计数器，并将ns位清零，补偿完成后置Flag为0；
(5)以前面4步获取到的与10ms帧头对应1PPS作为整秒基础，本地FPGA开始进行计数器计时，模拟TOD时间信息。
参考图5所示，所述中继E02基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为向同步受用基站E03传输的第二同步信号的步骤包括：
S201、在执行空口同步后，从空口获取帧号、时偏值、频偏值；
根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；
S202、根据10ms帧头模拟产生本地1PPS，其中，所述1PPS与10ms帧头对齐；
S203、以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；
S204、依据所述本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
同步受用基站E03作为1588Slave，算法恢复了10ms(此10ms与E02的10ms同步)，并调整本地时钟与10ms同步，过程为：
(1)同步受用基站E03作为1588Slave，与中继E02完成1588时钟同步；
(2)BSP通过1588时间戳计算调整本地时钟和FPGA时间戳基准，进而同步10ms；
(3)BSP从FPGA获取TOD并根据约束关系维护帧号；
(4)同步受用基站E03拿到10ms和帧号调整本地时钟，同步完成。
本领域普通技术人员可以理解上述方法中的全部或部分步骤可通过程序来指令相关硬件完成，上述程序可以存储于计算机可读存储介质中，如只读 存储器、磁盘或光盘等。可选地，上述实施例的全部或部分步骤也可以使用一个或多个集成电路来实现。相应地，上述实施例中的各模块/单元可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。本发明实施例不限制于任何特定形式的硬件和软件的结合。
工业实用性
本发明实施例通过基站已有的IEEE 1588同步网口，为基站提供一种新的同步源：空口同步。可达到不需GPS或北斗接收机设计、不需外接GPS或北斗天线、不需架设GPS或北斗线缆，可有效降低系统成本。

Claims (9)

  1. 一种空口同步系统，包括：
    同步源基站，设置为基于空中同步技术向中继发送第一同步信号；
    中继，设置为依据所述第一同步信号与所述同步源基站实现空口同步，以及设置为基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；以及
    同步受用基站，设置为依据所述第二同步信号执行与所述同步源基站的同步。
  2. 如权利要求1所述的空口同步系统，其中，所述中继包括中继基站、通信终端或客户终端设备CPE。
  3. 如权利要求1所述的空口同步系统，其中，所述中继依据所述第一同步信号与所述同步源基站实现空口同步的策略包括初始同步策略和周期同步策略，其中：
    所述初始同步策略，采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏；
    所述周期同步策略，在所述中继进入多播单频网络MBSFN子帧时序后，在系统帧号为0的无线帧中的第一个MBSFN下行子帧做周期空口同步。
  4. 如权利要求3所述的空口同步系统，其中，所述中继基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，包括：
    在执行空口同步后，所述中继从空口获取帧号、时偏值、频偏值；根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；根据10ms帧头模拟产生本地1脉冲秒PPS，其中，所述1PPS与10ms帧头对齐；所述中继以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；所述中继依据所述本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
  5. 一种应用如权利要求1所述的空口同步系统实现同步的方法，包括：
    同步源基站基于空中同步技术向中继发送第一同步信号；
    中继依据所述第一同步信号与所述同步源基站实现空口同步，以及基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号，并向同步受用基站传输所述第二同步信号；
    同步受用基站依据所述第二同步信号执行与所述同步源基站的同步。
  6. 如权利要求5所述的方法，其中，所述中继包括中继基站、通信终端或客户终端设备CPE。
  7. 如权利要求5所述的方法，其中，所述中继依据所述第一同步信号与所述同步源基站实现空口同步的步骤包括：初始同步步骤和周期同步步骤，其中：
    所述初始同步步骤包括，采用基于第一同步信号的时间同步算法来估算时偏，以及基于第一同步信号频域相关的频率同步算法来估算频偏；
    所述周期同步步骤包括，在所述中继进入MBSFN子帧时序后，在系统帧号为0的无线帧中的第一个MBSFN下行子帧做周期空口同步。
  8. 如权利要求7所述的方法，其中，所述中继基于预设的空口同步转1588主时钟转换算法将所述第一同步信号转换为第二同步信号的步骤包括：
    在执行空口同步后，所述中继从空口获取帧号、时偏值、频偏值；
    所述中继根据频偏值调整本地时钟，根据时偏值调整10ms帧头，以及根据帧号调整初始帧号；
    所述中继根据10ms帧头模拟产生本地1PPS，其中，所述1PPS与10ms帧头对齐；
    所述中继以所述本地1PPS为整秒基础，根据本地时钟模拟TOD时间信息，并约束所述TOD时间信息和对应帧号的关系；
    所述中继依据所述本地1PPS和TOD时间信息得到实现1588主时钟的第二同步信号。
  9. 一种计算机可读存储介质，存储有程序指令，当该程序指令被执行时可实现权利要求5-8任一项所述的方法。
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