WO2016110031A1

WO2016110031A1 - Data flow decoding method and device

Info

Publication number: WO2016110031A1
Application number: PCT/CN2015/078498
Authority: WO
Inventors: 陈峻峰
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-01-06
Filing date: 2015-05-07
Publication date: 2016-07-14
Also published as: CN105828083A

Abstract

Disclosed are a data flow decoding method and device. The method comprises: receiving multiple compressed data flows, the compressed data flows being data flows using a first coding mode, and the first coding mode needing a serial decoding mode for decoding; performing parallel decoding on the multiple compressed data flows by using multiple decoders, so as to obtain multiple decoded data flows; caching the multiple decoded data flows; and performing subsequent decoding processing on the multiple cached and decoded data flows by means of polling. The problem of low decoding speed because serial decoding must be performed one by one in the JPEG decoding process in the related art is solved, thereby achieving the effects of simplifying the circuit structure, saving FPGA resources and increasing the decoding speed.

Description

Data stream decoding method and device

Technical field

The present invention relates to the field of communications, and in particular to a method and apparatus for decoding a data stream.

Background technique

The invention relates to a high-speed JPEG image decoding device based on Field Programable Gate Array (FPGA), in particular to a codec technology in the field of image digital processing.

With the rapid development of computers and communication and multimedia technologies, people are increasingly demanding the storage and transmission of image data. This requires that the image be stored in a smaller space and the image transmitted at a lower bit rate while maintaining image quality, which is achieved by image compression encoding and decoding techniques. The Joint Photographic Experts Group (JPEG) standard is widely used because of its good image quality, high coding efficiency, and moderate computational complexity.

FPGA is a large-scale programmable logic device. Digital signal and image processing with FPGA can solve the problem of parallelism and speed. Its flexible configurability makes the system composed of FPGA easy to modify, test and upgrade. It is widely used in real-time image processing, radio communication and satellite navigation.

The decoding of JPEG is the inverse process of encoding. The flow of JPEG decoding process is shown in Figure 1. The Huffman decoding process determines that the decoding process can only be decoded one by one, because of the characteristics of huffman coding. A code can't solve a code before, so this link becomes the key link that affects the speed of the whole algorithm. If it is not solved, the parallel processing capability of the FPGA cannot be fully utilized for algorithm acceleration.

For the related art, only one serial decoding in the JPEG decoding process leads to a problem of low decoding speed, and an effective solution has not been proposed.

Summary of the invention

The embodiments of the present invention provide a method and an apparatus for decoding a data stream, so as to at least solve the problem that the decoding speed can be reduced only by one serial decoding in the JPEG decoding process in the related art.

According to an embodiment of the present invention, a method for decoding a data stream is provided, including: receiving a multi-channel compressed data stream, where the compressed data stream is a data stream adopting a first coding mode, and the first coding mode needs to be adopted. Serial decoding mode for decoding; using multiple decoders to perform parallel decoding on the multiple compressed data streams, Obtaining a multi-channel decoded data stream; buffering the multi-channel decoded data stream; and performing subsequent decoding processing on the buffered multi-channel decoded data stream by using a polling manner.

Cacheing the multiplexed data stream includes: buffering the multiplexed data stream into a plurality of first input first output (FIFO) memories.

The method further includes: when the buffered data stream is buffered, performing a subsequent decoding process, where the method further includes: when the multiple compressed data stream is further encoded by using the second encoding mode, The multi-channel decoded data is inverse-coded by using an inverse coding method corresponding to the second coding mode to obtain an inverse coding result, and the inverse coding result is buffered into a FIFO memory.

After being buffered to the FIFO memory, the method further includes: performing inverse quantization processing, inverse discrete cosine transform DCT processing, and color space conversion processing on the inverse encoding result.

The first coding mode is a Huffman huffman coding mode, and the second coding mode is a Z-word coding and a run-length coding.

The compressed data stream is a compressed data stream of a JPEG file.

According to another embodiment of the present invention, there is further provided a decoding apparatus for a data stream, comprising: a receiving module, configured to receive a compressed data stream, wherein the compressed data stream is a data stream adopting a first encoding mode, The first coding mode needs to be decoded by using a serial decoding mode; the first decoding module is configured to perform parallel decoding on the multiple compressed data streams by using multiple decoders to obtain a multi-channel decoded data stream; The second decoding module is configured to perform subsequent decoding processing on the buffered data stream after the buffering by using the polled data stream.

The cache module is further configured to buffer the multiplexed decoded data streams into a plurality of first-in first-out FIFO memories.

The second decoding module is further configured to perform, when the multiplexed compressed data stream is further encoded by using a second encoding manner, using the inverse encoding method corresponding to the second encoding mode to perform the multiplexed decoded data. Inverse encoding, the inverse encoding result is obtained, and the inverse encoding result is buffered into the FIFO memory.

The embodiment of the present invention adopts a receiving multiple compressed data stream, wherein the compressed data stream is a data stream adopting a first encoding mode, and the first encoding mode needs to be decoded by using a serial decoding manner; and multiple decoders are used. Parallel decoding of the multi-channel compressed data stream to obtain a multi-channel decoded data stream; buffering the multi-channel decoded data stream; and performing subsequent decoding on the buffered multi-channel decoded data stream by polling deal with. The invention solves the problem that the decoding speed can be reduced by only one serial decoding in the JPEG decoding process in the related art, thereby achieving the effect of simplifying the circuit structure, saving FPGA resources and improving the decoding speed.

DRAWINGS

The drawings described herein are intended to provide a further understanding of the invention, and are intended to be a part of the invention. In the drawing:

1 is a flowchart of JPEG image decoding in the related art;

2 is a flow chart of a method of decoding a data stream according to an embodiment of the present invention;

FIG. 3 is a structural block diagram of a decoding apparatus for a data stream according to an embodiment of the present invention; FIG.

4 is a block diagram of a multi-channel compressed data stream processing structure in the related art;

FIG. 5 is a block diagram showing a structure of a multiplexed compressed data stream according to an embodiment of the present invention.

detailed description

The invention will be described in detail below with reference to the drawings in conjunction with the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

In this embodiment, a method for decoding a data stream is provided. FIG. 2 is a flowchart of a method for decoding a data stream according to an embodiment of the present invention. As shown in FIG. 2, the process includes the following steps:

Step S102, receiving a multiplexed compressed data stream, where the compressed data stream is a data stream adopting a first coding mode, and the first coding mode needs to be decoded by using a serial decoding manner;

Step S104, using multiple decoders to perform parallel decoding on the multiple compressed data streams to obtain a multi-channel decoded data stream;

Step S106, buffering the multiplexed data stream;

Step S108, performing subsequent decoding processing on the buffered multi-channel decoded data stream by using polling.

Through the above steps, multiple decoders perform parallel decoding on the multi-channel compressed data stream, and perform subsequent decoding processing on the multi-channel decoded data stream by polling. Compared with the related art, the decoding process can only be one string. Row decoding, unable to solve a code before the previous code is solved, the above steps solve the problem that the decoding speed can be reduced by only one serial decoding in the JPEG decoding process in the related art, thereby achieving a simplified circuit structure. Save FPGA resources and improve decoding speed.

The above step S106 involves buffering the multiplexed data stream. In an optional embodiment, the multiplexed data stream is buffered into a plurality of first-in first-out FIFO memories, thereby completing multi-channel decoding. After the cache processing of the data stream.

The process of encoding a multiplexed compressed data stream may involve encoding the multiplexed compressed data stream in a plurality of manners. In an alternative embodiment, after the first encoding of the multiplexed compressed data stream, When the second encoding method performs encoding, the multiplexed decoded data is inverse-coded using an inverse encoding method corresponding to the second encoding method to obtain an inverse encoding result, and the inverse encoding result is buffered into the FIFO memory.

After performing inverse encoding on the multiplexed compressed data stream, in an optional embodiment, the inverse encoding result is sequentially subjected to inverse quantization processing, inverse discrete cosine transform DCT processing, and color space conversion processing, thereby completing the multiplexed compressed data stream. The final decoding.

In an optional embodiment, the first coding mode is a Huffman huffman coding mode, and the second coding mode is a Z-word coding and a run-length coding.

In an alternative embodiment, the compressed data stream is a compressed data stream of a JPEG file.

In the embodiment, a decoding device for the data stream is also provided. The device is configured to implement the foregoing embodiments and preferred embodiments, and details are not described herein. As used below, the term "module" may implement a combination of software and/or hardware of a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.

FIG. 3 is a structural block diagram of a decoding apparatus for a data stream according to an embodiment of the present invention. As shown in FIG. 3, the apparatus includes: a receiving module 32 configured to receive a compressed data stream, wherein the compressed data stream is used In the data stream of the first coding mode, the first coding mode needs to be decoded by using a serial decoding mode; the first decoding module 34 is configured to perform parallel decoding on the multiple compressed data streams by using multiple decoders to obtain multi-channel decoding. After the data stream, the cache module 36 is configured to cache the multiplexed data stream; the second decoding module 38 is configured to perform subsequent decoding processing on the buffered multiplexed data stream by using a polling manner. .

The cache module 36 is further configured to buffer the multiplexed data streams into a plurality of first-in first-out FIFO memories.

The second decoding module 38 is further configured to perform inverse encoding on the multiplexed decoded data by using an inverse encoding method corresponding to the second encoding mode when the multiplexed compressed data stream is further encoded by using the second encoding method. The result is encoded and the inverse encoded result is buffered into the FIFO memory.

It should be noted that each of the above modules may be implemented by software or hardware. For the latter, the foregoing may be implemented by, but not limited to, the foregoing modules are all located in the same processor; or, the above modules are respectively located. In the first processor, the second processor, and the third processor.

For the above-mentioned problems existing in the related art, the following description will be made in conjunction with an alternative embodiment in which the above-described optional embodiments and alternative embodiments thereof are combined.

The optional embodiment provides a device for batch processing JPEG decoding by using FPGA. Compared with the conventional JPEG decoding device, the decoding speed is doubled under the premise of a slight increase in device complexity.

The FPGA parallel batch processing JPEG picture decoding device of the alternative embodiment is composed of the following parts: multiple parallel huffman decoders, several first input first output (FIFO) buffers, and one inverse Z-coded and inverse-stroke encoder, 1 inverse quantizer, 1 inverse (Discrete Cosine Transform, DCC for short) converter and 1 color space converter.

The implementation of this alternative embodiment includes the following steps:

The first step: multiple huffman decoders (6 to 8) respectively receive compressed data streams of multiple JPEG files independently, and independently perform huffman decoding. The decoding result is placed in the corresponding FIFO of each channel.

Step 2: The inverse z-word encoding and the anti-stroke encoder poll the multi-channel FIFO from top to bottom, read out the first non-empty FIFO data polled for anti-z-word and anti-stroke decoding and put the result into The next level of FIFO.

The third step: the inverse quantizer reads the data of the upper FIFO and searches for the corresponding quantization table according to the channel number in the data for inverse quantization.

The fourth step: the inverse quantization result of the inverse quantization.

Step 5: Send the result of the inverse DCT transform to the color converter for color space conversion, and finally split the red and green (Red Green Blue) RGB data of each channel.

The focus of this alternative embodiment is on the multiplexing structure of the multiple parallel huffman decoders designed in the present apparatus.

Interpretation of terms for selected undergraduate embodiments:

FPGA: It is a field programmable gate array. It has the characteristics of flexible architecture, logic unit, high integration and wide application range. It can be used to realize large-scale circuits and flexible programming. At present, the main manufacturers have xilinx, altera, lattice and so on. The FPGA is internally organized by logic function blocks and connected by programmable interconnect resources.

Huffman Decoder: Huffman Coding is an encoding method that compresses data efficiently and without loss. Widely used in file, image and video compression, huffman decoding is the inverse of encoding.

Anti-Z-word and anti-stroke encoder: Z-word encoding and run-length encoding are also encoding methods, which is very helpful for the compression of image data. Anti-Z-word encoding and anti-stroke encoding are their inverse processes, which are used in decoding.

Inverse Quantizer: Inverse quantization is the inverse of quantization. Images need to be quantized during compression coding to ignore details that are insensitive to human eyes and reduce the amount of data.

Inverse DCT converter: the inverse process of DCT transform, DCT transform is cosine transform, the image transforms the time domain signal into frequency domain signal by cosine transform in the process of compression, because the physiological characteristics of the human eye are insensitive to high frequency signals, so High frequency signals in the frequency domain can be ignored to achieve the purpose of compressing the amount of data.

Color space converter: The general picture is RGB (ie red, green, blue) format, this format is not suitable for compression, you need to convert to YUV (ie TV video or computer monitor video) format is suitable for compression.

4 is a block diagram of a multi-channel compressed data stream processing structure in the related art. As shown in FIG. 4, the multiplexed JPEG picture code streams respectively pass through respective huffman decoders, inverse z-word inverse-stroke encoders, inverse quantizers, and inverse DCTs. The converter and color space converter complete the decoded output. This design structure does not fully utilize the processing speed asymmetry between the huffman decoder module and other modules. The inverse z-word inverse-stroke encoder, inverse quantizer, inverse DCT converter and color space conversion are designed separately for each channel. The resulting circuit is extremely complex, occupies a lot of resources, directly affects the circuit layout and working frequency, and is limited by FPGA resources, and the number of parallel paths is impossible.

This alternative embodiment makes full use of the fact that the huffman decoding speed is slow and the other modules are fast. This asymmetry designates the parts other than the huffman decoding module into a multiplexing structure. Multiple huffman decoders in the device perform huffman decoding independently, and the decoding results are placed in each respective FIFO. Anti-Z character of the latter stage The encoder and the anti-stroke encoder poll each FIFO and process the data in each FIFO using a "first come, first served" strategy. Then, after the FIFO buffer, inverse quantizer inverse quantization, inverse DCT transform and color space converter conversion, the RGB data decoded by each picture is finally output. Compared to the circuit structure of Figure 4, it is greatly simplified.

5 is a block diagram of a multi-channel compressed data stream processing structure according to an embodiment of the present invention. As shown in FIG. 5, multiple huffman encoders, FIFO buffers, inverse Z-word encoders, and inverse-stroke encoders are described in the present design. The connection relationship between the inverse quantizer, the inverse DCT converter, and the color space converter. Eight JPEG pictures are input simultaneously, and eight huffman decoders in the device independently perform huffman decoding. The speed of 8-channel decoding is unequal and unpredictable, and the huffman decoding result is placed in each FIFO. The anti-Z-encoder and the anti-stroke encoder of the latter stage poll each FIFO, and use the "first come, first served" strategy to process the data in each FIFO. Then, after the FIFO buffer, inverse quantizer inverse quantization, inverse DCT transform and color space converter conversion, the RGB data decoded by each picture is finally output.

In summary, the present invention eliminates the speed bottleneck by adopting a multiplexed parallel processing method for the serial link in the JPEG decoding process, improves the overall decoding speed, and greatly speeds up the decoding speed of the batch JPEG picture. Compared with the conventional multi-processing structure, the design of the present invention greatly simplifies the circuit structure by fully multiplexing certain unit modules, saves FPGA resources, and can achieve the effect of improving the working frequency.

In another embodiment, a software is provided that is configured to perform the technical solutions described in the above embodiments and preferred embodiments.

In another embodiment, a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.

It will be apparent to those skilled in the art that the various modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Industrial applicability

As described above, a method and an apparatus for decoding a data stream provided by an embodiment of the present invention have the following beneficial effects: solving the problem that the decoding speed can be reduced only by one serial decoding in the JPEG decoding process in the related art. In turn, the circuit structure is simplified, the FPGA resources are saved, and the decoding speed is improved.

Claims

A method for decoding a data stream, comprising:

Receiving a multi-channel compressed data stream, wherein the compressed data stream is a data stream adopting a first coding mode, and the first coding mode needs to be decoded by using a serial decoding manner;

Parallel decoding the multiple compressed data streams by using multiple decoders to obtain a multi-channel decoded data stream;

Cache the multi-channel decoded data stream;

The buffered multiplexed data stream is subjected to subsequent decoding processing by means of polling.
The method of claim 1, wherein the buffering the multi-channel decoded data stream comprises:

The multiplexed decoded data streams are respectively buffered into a plurality of first-in first-out FIFO memories.
The method according to claim 1, wherein the buffering of the multiplexed data stream is performed in a subsequent manner in a polling manner, the method further comprising:

When the multiplexed compressed data stream is further encoded by using the second coding mode, the multiplexed decoded data is inverse-coded by using an inverse coding method corresponding to the second coding mode to obtain an inverse coding result, and The inverse encoding result is buffered into the FIFO memory.
The method of claim 3, wherein the buffering to the FIFO memory further comprises:

The inverse coding result is sequentially subjected to inverse quantization processing, inverse discrete cosine transform DCT processing, and color space conversion processing.
The method according to claim 3, wherein said first encoding mode is a Huffman huffman encoding mode, and said second encoding mode is Z-word encoding and run length encoding.
The method of any of claims 1 to 5, wherein the compressed data stream is a compressed data stream of a JPEG file.
A decoding device for a data stream, comprising:

The receiving module is configured to receive the multiplexed compressed data stream, where the compressed data stream is a data stream that adopts the first encoding mode, and the first encoding mode needs to be decoded by using a serial decoding manner;

The first decoding module is configured to perform parallel decoding on the multiple compressed data streams by using multiple decoders to obtain a multi-channel decoded data stream;

a cache module, configured to cache the multi-channel decoded data stream;

The second decoding module is configured to perform subsequent decoding processing on the buffered data stream after the multi-channel decoding.
The apparatus of claim 7, wherein the cache module is further configured to buffer the multiplexed decoded data streams into a plurality of first-in first-out FIFO memories, respectively.
The apparatus according to claim 7, wherein said second decoding module is further configured to use an inverse encoding corresponding to said second encoding mode when said multiplexed compressed data stream is further encoded by said second encoding mode The method performs inverse encoding on the multiplexed decoded data to obtain an inverse encoding result, and buffers the inverse encoding result into a FIFO memory.
The apparatus according to claim 9, wherein said first encoding mode is a Huffman huffman encoding mode, and said second encoding mode is Z-word encoding and run length encoding.