WO2016107299A1 - 一种状态机的合并方法和装置 - Google Patents

一种状态机的合并方法和装置 Download PDF

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WO2016107299A1
WO2016107299A1 PCT/CN2015/094444 CN2015094444W WO2016107299A1 WO 2016107299 A1 WO2016107299 A1 WO 2016107299A1 CN 2015094444 W CN2015094444 W CN 2015094444W WO 2016107299 A1 WO2016107299 A1 WO 2016107299A1
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block
state
sub
input
state machine
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PCT/CN2015/094444
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English (en)
French (fr)
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王磊
杨磊
谢少林
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中国科学院自动化研究所
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Definitions

  • the present invention relates to the field of digital integrated circuits, and more particularly to a method and apparatus for merging state machines to reduce the circuit complexity of the dynamically configurable pipeline and the difficulty of developing the configuration program.
  • the pipeline and the connection between the various pipeline stages and the pipeline stages on the state machine control pipeline are a common form of digital integrated circuits, such as the pipeline of instructions, the pipeline for processing packets in the network processor, and the processing of baseband signals.
  • Instruction pipeline technology refers to a processing technique in which multiple instructions overlap when a program is executed. It breaks down instructions into different stages, allowing the circuit to more fully utilize hardware resources according to specified operations.
  • Dynamic reconfigurable pipelines are a technique for the development of such circuit structures in a more flexible and programmable direction.
  • the essence of its reconfigurability is to describe the behavior of each state machine on the pipeline in a program, so that the function of the circuit pipeline can be changed at any time after the chip is streamed.
  • a debugging pipeline was set up outside the execution environment, and the pipeline was built in a reconfigurable manner for hardware and software debugging.
  • the "Processor with Multi-State Instruction Set Architecture” patent proposed by the Institute of Automation of the Chinese Academy of Sciences in 2013 uses the dynamic reconfigurable pipeline method for processor design, so that the functions of the processor can be redefined and modified according to requirements. This increases and expands the flexibility and application areas of the processor.
  • the present invention proposes a method and apparatus for merging state machines, combining the state machines of each functional component into a composite state machine, and only need to use one configuration file. Controls this state machine, which greatly reduces the workload of writing state machine and algorithm application, greatly simplifies the microcode programming of state machine control hardware, and the reusability and debugability of the program are greatly improved. Improvement.
  • the present invention proposes a method of merging state machines, comprising the following steps:
  • Step 1 analyzing the states of all the input sub-state machines, and converting the state transition diagrams of all the sub-state machines into one or more status blocks connected in sequence;
  • Step 2 taking out the first status block of all the input sub-state machines, judging the splicability of the status blocks and the splicing type of the output sub-state machine;
  • step determines that the splicability is a splicing rule, and the splicing type is one of a full-order block type, a full-cycle block type, or a full-nested cyclic block type it is determined whether the number of loops is the same, and if they are the same, all input sub-states are The machine is placed in the input of step 5, until the sub-state machine does not have a sub-state machine in this input, and jumps to step 5, if the number of cycles is not the same, the equivalent conversion rule is used to determine, and the process proceeds to step 3 to perform sub-state machine extraction rule determination;
  • the step determines that the splicability is an equivalent conversion rule, and the splicing type is a full-circular block type with a nested cyclic block, the sub-state machine whose current state block is a cyclic block is placed in the input of the next step 2 , the current state block is a sub-state machine of the nested loop block into the input of step 3, until there is no sub-state machine in this input, skip to step 3;
  • the step determines that the splicability is an equivalent conversion rule, and the splicing type is a non-full-order block type, the sub-state machine whose current state block is the sequential block is placed in the input of the next step 2, and the current status block is The sub-state machine of the non-sequential block is placed in the input of step 3, and skips to step 3 until there is no sub-state machine in this input;
  • step determines that the splicability and the output splicing type do not meet the above conditions, the method output sub-state machine cannot be spliced, and the method ends;
  • Step 3 receiving a status block that meets the equivalent conversion rule, determining the number of states to be extracted according to the state block combination and outputting to step 4;
  • Step 4 The input sub-state machine is equivalently transformed according to the splicing type, and the equivalent sub-state machine and the input sub-state machine function are completely identical, but the state block structure is different, and the sub-state machine state after the equivalent transformation
  • the block indicates that the state block representation of the replacement atomic state machine is output to the input of step 2, and the splicability determination is performed again; if the input splicing type is a non-full-order block type, Then all the input sub-state machines are equivalently transformed by the extraction order block. If the input splicing type is a full-circular block type with nested cyclic blocks, all the input sub-state machines are equivalently transformed by the decimating cyclic block. If there is no sub-state machine in the input that requires equivalent conversion, skip to step 2;
  • step 5 all the input sub-state machine status blocks are spliced, and the merge state machine is output; if there is a status block that cannot be spliced, the process jumps to step 2.
  • step 1 includes:
  • Sub-step 1.0 reading the current state of an input sub-state machine, determining which state block is the starting state of the state block, and jumping to the sub-step of the corresponding state block analysis;
  • Sub-step 1.1 collecting the states conforming to the characteristics of the sequential blocks, and outputting them to a sequential block;
  • Sub-step 1.2 collecting the state that conforms to the characteristics of the loop block, and outputting it to a loop block, and recording the loop condition of the loop block;
  • Sub-step 1.3 identifying and outputting a loop state block having only one state, and recording a loop condition of the loop block;
  • Sub-step 1.4 deleting the state transition of the nested loop in the input sub-state machine state transition diagram, and outputting the state transition information to sub-step 1.5;
  • Sub-step 1.5 according to the state of the input, the nested information of the nested cyclic block outputs the status block representation of the sub-state machine to the input of step 2.
  • sub-step 1.5 includes the following steps:
  • the input status block is placed in the current nested loop block
  • the input status block is a nested loop block
  • the current nested loop block is switched to the input status block
  • the current nested loop block is exited, and the current nested loop block is switched to the previous nested loop block, if the previous one does not exist Layer nesting a loop block, and outputting the nested loop block to a state block representation of the substate machine;
  • the input status block is output to the status block representation of the sub-state machine
  • the splicing type of the output sub-state machine described in step 2 includes: a full-circular block type, a non-full-order block type, a full-order block type, a full-circular block type, and a full-nested cyclic block type including nested cyclic blocks. .
  • step 3 The step of determining the number of states to be extracted according to the state block combination described in step 3 and outputting to step 4 for sub-state machine equivalent transformation includes:
  • the number of outputs to be extracted is 1, and jump to step 4;
  • the current state block is a full-circular block type with a nested loop block
  • the number of extractions is the product of the difference between the number of cycles and the number of internal states of the loop body, and the number to be extracted is output, and the process proceeds to step 4.
  • step 5 is as follows:
  • Sub-step 5.0 according to the splicing type outputted in step 2, all sub-state machine state block representations in the input are put into corresponding sub-step inputs;
  • Sub-step 5.1 extracting the current state block of the input sub-state machine (definitely a sequential block) into a state, and merging them into a composite state, placing the composite state into the input of sub-step 5.5, and jumping Go to sub-step 5.4;
  • Sub-step 5.2 changing the current state block (definitely a cyclic block) type of the input sub-state machine to a sequential block, and placing the loop condition and the loop end state position of the current loop state block into the input of step 5.4, and jumping Go to sub-step 5.4;
  • Sub-step 5.3 replacing the current state block of the input sub-state machine with the state block set inside the nested loop block, and setting the loop condition and the loop end status bit of the current nested loop state block Putting it into the input of step 5.4 and jumping to sub-step 5.4; and substituting the sub-state machine state block representation after replacing the nested loop block into the input of step 2 to replace the atomic state machine state block representation;
  • Sub-step 5.4 for recording and checking whether the current splicing state is at the end position of a composite cyclic block, and notifying sub-step 5.5 of outputting the state of the cyclic state transition and the cyclic state transition; and sub-step 5.5 for outputting the composite in the input State transitions and state transitions for the composite state.
  • the present invention also provides a state machine merging apparatus, comprising: a module for storing a sub-state machine input, a state block structure analysis module 2, a module for saving a logic state block, and an equivalent conversion module. 4.
  • the splicability and splicing rule determination module 5 the splicing state block registration module 6, the flow control module 7, and the state block splicing module 8;
  • the structure analysis module 2 receives the set of sub-state machines input by the module 1 input by the storage sub-state machine, outputs a status block of the tag type, and stores it in the module 3 of the save logic status block;
  • the module 3 holding the logic status block is used to store the memory of the logic status block queue
  • the splicability and splicing rule determining module 5 reads the logic state block stored in the module 3 of the saved logic state block, and outputs different state blocks to be spliced after being compared and determined, and registers the state block to be spliced.
  • the block registration module 6 wherein the directly spliced state block is output to the state block splicing module 8 for splicing, and the equivalent conversion output is required to the equivalent conversion module 4;
  • the equivalence transform module 4 converts the case that needs to be transformed, and outputs it to the logic state block queue stored in the module 3 of the save logic state block or directly outputs the state block splicing module 8 to the state block splicing;
  • the state block splicing module 8 implements a splicing module process of all state blocks and outputs a merge result, and terminates the splicing process and outputs error information for a state block that cannot be spliced;
  • the flow control module 7 controls the progress of the splicing process, and controls the continuous backward and end of the entire splicing process according to whether the queue of the state machine to be spliced is empty and the state block splicing process.
  • the present invention also provides a merging apparatus for a state machine, comprising:
  • a device that takes out the first state block of all sub-state machines in the input, determines the splicability of the state blocks, and outputs the splicing type of the sub-state machine;
  • the input sub-state machine is equivalently transformed according to the splicing type.
  • the equivalent sub-state machine has the same function as the input sub-state machine, but the state block structure is different, and the equivalent sub-state machine status block represents the output. Substituting the state block representation of the atomic state machine into the input of the device for determining the splicing type, and re-doing the splicability determination device;
  • the means for placing all of the sub-state machine status block inputs in the input into the input of the corresponding device is based on the splicing type of the device output of the splicing type.
  • the splicing type of the sub-state machine includes: a full-circular block type, a non-full-order block type, a full-order block type, a full-circular block type, and a full-nested cyclic block type including nested cyclic blocks.
  • the method and apparatus for the merge state machine of the present invention can control the entire state machine using only one configuration file, thereby greatly reducing the workload of writing the state machine and the algorithm application, so that the state machine manipulates the hardware microcode program.
  • the design work is greatly simplified, and the reusability and debugability of the program are greatly improved.
  • step 1 is a flow chart of step 1 in the method of the merge state machine of the present invention.
  • step 4 is a flow chart of step 4 of the method of the merge state machine of the present invention.
  • Figure 3 is a schematic structural view of the apparatus of the combined state machine of the present invention.
  • FIG. 4 is a schematic structural view of a state machine to be spliced in a specific embodiment of the present invention.
  • Figure 5 is a schematic diagram of a first step output status block of an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a third step output status block according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a fifth step output status block according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a seventh step output status block according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a ninth sub-step 4.4 output state machine according to an embodiment of the present invention.
  • Figure 10 is a schematic illustration of a final generated composite state machine in accordance with an embodiment of the present invention.
  • Figure 11 is a schematic flow diagram of the entire inventive method of one embodiment of the present invention.
  • the present invention proposes a method of merging state machines and a state machine merging apparatus based on the method.
  • the method of the merge state machine of the present invention is to combine a plurality of independent state machines (referred to as sub-state machines) into a complex state machine (referred to as a composite state machine) according to a given step, and the method ensures the composite state machine. It is exactly the same as the function of several original sub-state machines.
  • Several sub-state machines are usually represented by a state machine for controlling each flow level on a pipeline. The independence is manifested as the state transition time of the sub-state machine and the transition-to-target state without a constraint relationship between the sub-state machines.
  • a composite state machine typically behaves as a state machine that controls each flow level on a pipeline, each state of the state machine containing the current state of all of the original substates.
  • the steps specified in the method of the present invention include a sub-state machine structure analysis step, a sub-state machine equivalence determination step, a sub-state machine extraction rule decision step, a sub-state machine equivalent conversion step, and a sub-state machine splicing step.
  • the state machine merging device based on the method of the present invention refers to a device capable of accepting one or more sub-state machine inputs, performing all the steps in the state machine merging method, and outputting the composite state machine. The device can assist the programmer to still write the configuration program of the state machine according to the sub-state machine, and get the configuration program of the merged state machine.
  • the present invention provides a method for merging state machines, comprising the steps of: sub-state machine structure analysis step, sub-state machine equivalence judgment step, sub-state machine extraction rule decision step, sub-state machine equivalent conversion step, and sub-state machine Stitching step.
  • the purpose of this step is to transform the state transition diagram of the input substate machine into one or more state blocks that are sequentially connected.
  • the state transition diagram of a substate machine contains one or several states, each state containing a functional description containing a connection line between one and more states, each connection line containing a condition of state transition.
  • a predecessor state of the current state refers to a direct connection with the current state through a connection line, the start end of the connection line becomes a precursor state, and the termination end of the connection line is the current state.
  • a successor state of the current state means that the current state is directly connected through the connection line, the start end of the connection line is the current state, and the terminating end of the connection line is referred to as the successor state of the current state.
  • State A block is a collection of one or several state or state blocks, where the properties of the collection include order, loop, and nested loops.
  • the step includes a sub-state machine current state identification sub-step, a sequence state block analysis sub-step, a loop state block analysis sub-step, a nested loop block analysis sub-step, and a status block output sub-step. As shown in Figure 1.
  • This sub-step reads the current state of an input sub-state machine, determines which state block is the starting state of the state block, and jumps to the sub-step of the corresponding state block analysis.
  • This substep collects the states that match the characteristics of the sequential blocks and outputs them to a sequential block.
  • the sequence block contains one or several states, with the exception of the first and last states, each state having one and only one precursor state and one successor state.
  • the sub-step is characterized by receiving the current state of the input. If the subsequent state of the current state has one and only one precursor state and one successor state, the current state is switched to the subsequent state, and the process is repeated if the subsequent state of the current state is not If there is a condition with one and only one precursor state and one successor state, the end of the sequence block is marked, the status block is placed in the input of sub-step 1.5, the jump to sub-step 1.5, and the current state is switched to the successor state.
  • This substep collects the states that match the characteristics of the loop block and outputs them to a loop block, and records the loop conditions of the loop block.
  • the loop state block is characterized in that except for the first and last states, all states have one and only one precursor state and one successor state; the first state has two precursor states and one successor state; the last state has one precursor.
  • the state and the two subsequent states, and one of the precursor states of the first state of the state block is the last state of the state block, and a subsequent state of the last state of the same state block is the first state of the state block.
  • the sub-step is characterized by receiving the current state of the input, if the successor state of the current state has one and only one precursor The state and a successor state, the current state is switched to the subsequent state, and the process is repeated; if the subsequent state of the current state has one and only one precursor state and two subsequent state conditions, and one of the successor states is the state block a state, receiving a successor state of the current state, marking the end of the loop block, and marking the state transition condition of the current state to the first state of the state block as a loop condition, placing the state block into sub-step 1.5 In the input, jump to sub-step 1.5 and switch the current state to one of the successor states of the loop block end state, which is not the first state of the loop block; if the successor state of the current state has two or more The precursor state marks the currently received status block as a sequential block, places the sequence block into the input of sub-step 1.4, and jumps to step 1.4 and switches the current state to the first state of the sequence block.
  • This substep identifies and outputs a loop status block with only one state and records the loop condition of the loop block.
  • the sub-step is characterized by outputting the current state into the loop block, and marking the state transition condition that jumps to itself as a loop condition, placing the state block into the input of sub-step 1.5, and jumping to sub-step 1.5, And switch the current state to a successor state.
  • This sub-step deletes the state transition of the nested loop in the input sub-state machine state transition diagram and outputs the state transition information to sub-step 1.5.
  • a nested loop block does not contain a state and contains one or several sub-state blocks containing at least one loop status block or a nested loop status block.
  • Nested loop blocks may contain combinations of loop state blocks and sequential state blocks, combinations of loop state blocks and loop state blocks, and multiple nested combinations.
  • the sub-step is characterized in that the state transition from the precursor state to the current state is deleted from the state farthest from the precursor state of the current state, and the deleted sub-state machine state transition map is placed in the input of the sub-step 1.0.
  • This sub-step outputs the state block representation of the sub-state machine to the input of step 2 based on the state of the input, nested information of the nested loop block.
  • the sub-step is characterized by: determining whether there is any The loop condition of the nested loop, if any, creates a new nested loop block, records the end state of the nested loop block, and places the state block in the input into the nested loop block, and the new Nesting a loop block as an input status block; if the currently nested loop block is not finished, put the input status block into the current nested loop block; if the input status block is a nested loop block, the current nested loop The block switches to the input status block; if the last state of the currently input status block is the end state of the current nested loop block mark, the current nested loop block is exited, and the current nested loop block is switched to the previous level of nesting a loop block, if there is no previous nested loop
  • This step takes the first status block of all the sub-state machines in the input, and determines the splicability of these status blocks and the splicing type of the output sub-state machine.
  • the splicability of the status block refers to whether there is a rule that can concatenate the first status block of all input sub-state machines into one status block.
  • the rules include splicing rules and equivalent transformation rules.
  • the splicing type of the output sub-state machine includes a full-circular block type, a non-full-order block type, a full-order block type, a full-circular block type, and a fully-nested cyclic block type with nested loop blocks.
  • the step determines that the splicability is a splicing rule, and the splicing type is a full-order block type, a full-circular block type or a fully-nested cyclic block type, it is determined whether the number of loops is the same, and the same is true for all input sub-state machines.
  • step 5 Put it into the input of step 5, until the sub-state machine has no sub-state machine in this input, skip to step 5, if the number of cycles is not the same, use the equivalent conversion rule to determine, jump to step 3 to determine the sub-state machine splicing rule;
  • the splicability is an equivalent conversion rule
  • the splicing type is a full-circular block type with a nested cyclic block
  • the sub-state machine whose current state block is a cyclic block is placed in the input of the next step 2
  • step 3 determines that the splicability is an equivalent conversion rule, and the splicing type is a non-full-order block type, the sub-state machine whose current state block is the sequential block is placed in the input of the next step 2, Put the current state block into a non-sequential block sub-state machine into the input of step 3, until the sub-state machine does not have a sub-state machine in this input, skip to step 3;
  • the step determines that the splicability and the splicing type of the output do not meet the above conditions, the method output sub-state machine cannot be spliced, and the method ends.
  • the feature of this step is that a status block conforming to the equivalent conversion rule is received, and the number of states to be extracted (the number to be extracted) is determined according to the state block combination and output to step 4 for sub-state machine equivalent conversion.
  • This step determines the combination of the current state block, which may be one of several cases, such as a non-full-order block type, a full-circular block type with a nested loop block, and a full-loop block.
  • the extracted rules are:
  • the number of outputs to be extracted is 1, and jump to step 4;
  • the current state block is a full-circular block type with a nested loop block
  • the number of extractions is the product of the difference between the number of cycles and the number of internal states of the loop body, and the number to be extracted is output, and the process proceeds to step 4.
  • the input sub-state machine is equivalently transformed according to the splicing type, and the equivalent sub-state machine and the input sub-state machine function are completely identical, but the state block structure is different, and the sub-state machine status block is equivalently transformed.
  • the input splicing type is a non-full-order block type, all the input sub-state machines are equivalently transformed by the decimating order block.
  • the input splicing type is a full-circular block type with nested cyclic blocks, all the children to be input will be input.
  • the state machine performs the equivalent transformation of the decimation loop block. When there is no substate machine in the input that requires equivalent transformation, it jumps to step 2.
  • This step splicing the status block output in step 2 according to the type output in step 2.
  • the step includes a splicing type determining sub-step, a sequential block splicing sub-step, a cyclic block splicing sub-step, a cyclic block tail checking sub-step, and a splicing result output sub-step. as shown in picture 2.
  • This sub-step puts all sub-state machine status block representations in the input into the corresponding sub-step inputs according to the splicing type output in step 2.
  • the sub-step extracts a state of the current state block of the input sub-state machine (definitely a sequential block), and merges them into a composite state, puts the composite state into the input of sub-step 5.5, and jumps Go to substep 5.4.
  • the sub-step deletes the first state in the current state block of each sub-state machine. If there is no state in the first state block after the deletion, the state block is deleted, and the changed sub-state machine state block representation is placed.
  • the replacement atomic state machine status block in the input of step 2 indicates that if there is no remaining status block in the sub state machine status block representation after the status block is deleted, the sub state machine is deleted from the input of step 2.
  • the sub-step changes the current state block (definitely a cyclic block) type of the input sub-state machine to a sequential block, and places the loop condition and the loop end state position of the current loop state block into the input of step 5.4, and jumps Go to substep 5.4.
  • this sub-step will place the sub-state machine status block representation after changing the status block type into the input of step 2 to replace the atomic state machine status block representation.
  • This substep replaces the current state block of the input substate machine (definitely a nested loop block) with the set of state blocks inside the nested loop block, and sets the loop condition and loop end state position of the current nested loop state block. Place in the input of step 5.4 and jump to sub-step 5.4.
  • this sub-step replaces the atomic state machine state block representation in the input of step 2 by replacing the sub-state machine state block representation after the nested loop block.
  • This sub-step is used to record and check whether the current splice state is at the end of a composite loop block, and informs sub-step 5.5 of the conditions for outputting the loop state transition and the loop state transition.
  • the feature of this step is: if the loop condition and loop end state position in the input are not empty, then The input is saved in the current loop queue, and the current stitching state position is saved as the loop start position in the current loop queue, and jumps to step 2; when the loop condition and the loop end state position in the input are empty, the current stitching is checked. Whether the status position is the same as the end position status saved in the current loop queue.
  • the corresponding loop condition and loop start address are placed in the input of sub-step 5.5, and the information of the loop is from the current Delete in the loop queue, repeat this process until there is no matching item in the current loop queue, jump to sub-step 5.5.
  • This sub-step is used to output the composite state in the input and the state transition and state transition condition of the composite state.
  • the sub-step is characterized in that the composite state in the input is output to the composite state machine, and an input state transition of the state is added, the precursor is the last state of the composite state machine; if there is a loop condition and a loop start in the input The state position adds an output state transition for that state, followed by a composite state at the loop start state position, the transition condition being a loop condition, and the process is repeated until there is no loop condition and loop start state position in the input. If there is no status block representation of the sub-state machine in step 2, the method ends successfully, otherwise it jumps to step 2.
  • the state machine merge device is shown in Figure 3. It includes several functional modules, such as a state block structure analysis module 2, a splicability and splicing rule determination module 5, an equivalent transformation module 4, and a state block splicing module 8.
  • the auxiliary module includes a module for storing the sub-state machine input, a module for saving the logic status block, a block registration module 6 to be spliced, a flow control module 7, and an output error message 9 and an output composite state machine 10.
  • the device inputs the set of sub-state machines 1, outputs the combined state machine 10 after processing by the merging device, or prompts the corresponding error information 9 for the state machine that cannot be spliced.
  • the structure analysis module 2 implements the sub-state machine structure analysis step 1 in the method, which receives the input sub-state machine set 1 of the device, and outputs the status block (logical state of the tag type (sequence block, cyclic block, nested loop block) Block 3).
  • Module 3 is a memory for storing logical state block queues.
  • the equivalence judging module 5 is designed according to the splicability and splicing rule decision step 2.
  • the module reads the logic state block stored by the module 3, and outputs different types to be spliced after comparison and determination.
  • the status block is registered in the module 6, wherein the directly spliced status block is output to the status block splicing module 8 for splicing, and the equivalent transformation is required to be output to the equivalent conversion module 4 according to the splicing requirement.
  • the equivalent transformation module 4 implements an equivalent transformation step of the method.
  • the module transforms the situation that needs to be transformed and outputs it to the logic state block 3 queue or directly to the state block splicing module 8 for state block splicing.
  • Module 8 is designed in accordance with the step 5 substate machine splicing step. This module implements the splicing module process for all state blocks and outputs the composite state machine. The status block (not equivalent) that cannot be spliced terminates the splicing process and outputs an error message.
  • the flow control unit 7 controls the progress of the splicing process, and controls the continuous backward and end of the entire splicing process according to whether the queue of the state machine to be spliced is empty and the state block splicing process.
  • the sub-state machine 1 includes a state A1 that is cycled three times, and the sub-state machine 2 includes a single state B1 and a state B2 that is cycled three times.
  • Step 1 Step 1 substate machine analysis step
  • Sub-step 1.0 Analysis of sub-state machine 1, state A1 is the current state, the state has 2 precursors and 2 successors, and one of the precursors and one of the successors is the current state, jumping to sub-step 1.3.
  • Sub-step 1.3 The current state A1 conforms to the cyclic state block condition, put A1 into sub-step 1.5, and jump to sub-step 1.5.
  • Sub-step 1.5 Output loop block A1, the number of loops is 3, and sub-state machine 1 is deleted from step 1.0 input. The substate machine 1 state block analysis ends.
  • Sub-state machine 2 is input to sub-step 1.0.
  • Sub-step 1.0 Analysis of sub-state machine 2, state B1 is the current state, the state has 1 precursor and 1 successor, jumping to sub-step 1.1.
  • Sub-step 1.1 There is only one state B1 composite sequential block feature, the marking sequence block ends, and jumps to sub-step 1.5.
  • Sub-step 1.5 Output sequence block B1, jump to sub-step 1.0, and modify the current state to B2.
  • Sub-step 1.0 The current state B2 has 2 precursors and 2 successors, and one of the precursors and one of the successors is the current state, jumping to sub-step 1.3.
  • Sub-step 1.3 The current state B2 conforms to the cyclic state block condition, put B2 into sub-step 1.5, and jump to sub-step 1.5.
  • Sub-step 1.5 Output loop block B2, the number of loops is 3, and sub-state machine 2 is deleted from step 1.0 input. The substate machine 2 state block analysis ends. Step 1 ends and skips to step 2.
  • the status block that ends the output of step 1 is: loop block A1, the number of loops is 3; the order block B1; the loop block B2, and the number of loops is 3.
  • Output to the logic status block register (see module 3 in Figure 3), as shown in Figure 5.
  • Step 2 Sub-state machine splicability and splicing rule determination steps
  • the first state block of sub-state machine 1 and sub-state machine 2 is removed.
  • the splicability can be determined.
  • the two status blocks are the cyclic block and the sequential block, respectively, and cannot be directly spliced.
  • the loop block A1 is output to step 4, and the sequence block B1 is output to the next step 2, and jumps to step 4.
  • Step 3 Step 4 Substate Machine Equivalent Transformation Step
  • the loop block A1 that is looped 3 times is split into a sequence block A1 and a loop block A1 that is looped twice, and the first sequence block A1 is in the front, and its successor state is the loop block A1 of the 2 loops, skipping to Step 2. See Figure 6.
  • step 2 sub-state machine splicability and splicing rule determination steps
  • the first state block 1 is the sequence block A1
  • the first state block of the child state machine 2 is the sequence block B1, which conforms to the splicing rule, and can be spliced by the state block. Skip to step 5.
  • Step 5 Step 5 sub-state machine splicing steps
  • Sub-step 5.0 The current two blocks to be spliced are sequential status blocks, skipping to sub-step 5.1.
  • Sub-step 5.1 Combine A1 and B1 as a new composite status block A1B1 and jump to sub-step 5.4.
  • Sub-step 5.4 Output the stitching result sequence block A1B1.
  • the A1 sequential block and the B1 sequential block in the queue are deleted, the sub-state machine 1 reads backward the cyclic block A1 of the next status block 2 times, and the sub-state machine 2 reads the cyclic block of the next status block 3 times backward.
  • B2 the queue to be spliced is not empty, and returns to sub-step 5.0.
  • Sub-step 5.0 The current two status blocks cannot be spliced, and return to step 2.
  • the status block at this time is shown in Figure 7.
  • Step 6 Step 2 Sub-state machine splicability and splicing rule determination steps
  • the 2 cyclic blocks of A1 and the 3 cyclic blocks of B2 are not splicable, and an equivalent transformation is required.
  • the A1 cyclic block and the B2 cyclic block are output to step 3, and the process proceeds to step 4.
  • Step 7 Step 4 Substate Machine Equivalent Transformation Step
  • the three-cycle loop block B2 is split into a two-cycle loop block B2 and one sequence block B2, and one subsequent state of the second-cycle block B2 is the sequence block B2. Skip to step 2.
  • the status block at this time is shown in Figure 8.
  • Step 8 Step 2 Sub-state machine splicability and splicing rule determination steps
  • the substate machine 1 at this time is the first state block of the second cycle block A1, and the first state block of the substate machine 2 is the second cycle block B2, which conforms to the splicing rule, and can be spliced by the state block. Skip to step 5.
  • Step 9 Step 5 sub-state machine splicing steps
  • Sub-step 5.0 The current two blocks to be spliced are all cyclic blocks and the number of cycles is the same, skipping to sub-step 5.2.
  • Sub-step 5.2 Combine the cyclic blocks A1 and B2 as the new 2nd composite cyclic block status block A1B2, jumping to sub-step 5.4.
  • Sub-step 5.4 Output stitching result 2 loop blocks A1B2. Delete the A1 loop block and the B2 loop block in the queue. Sub-state machine 1 reads the next status block backwards. Sub-state machine 2 reads the next status block backwards into the sequence block B2. The queue to be stitched is not empty. , return to substep 5.0. The status block at this time is shown in Figure 9.
  • Sub-step 5.0 The queue to be spliced of the sub-state machine 1 is empty, and the remaining sub-state machine 2 status block B2 is outputted with the current composite state tail, the sub-state machine 2 status block queue is cleared, and the sub-step 5.4 is skipped.
  • Sub-step 5.4 The two sub-state machine queues are all empty, and the splicing ends, and the current composite state machine is output: the sequential block A1B1, the second-order cyclic block A1B2, and the sequential block B2.

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Abstract

本发明公开了一种状态机的合并方法，包括子状态机结构分析步骤、子状态机等价性判定步骤、子状态机提取规则判定步骤、子状态机等价变换步骤和子状态机拼接步骤。以及一种采用该方法的状态机合并装置。本发明的方法和装置能够在实现动态可配置流水线时，将用于描述流水线各个流水级上状态机的配置程序由若干个减少为一个，降低控制电路和配置电路的复杂度，能够辅助程序员仍然按照子状态机编写状态机的配置程序，并且得到合并后一个状态机的配置程序。

Description

一种状态机的合并方法和装置 技术领域
本发明涉及数字集成电路领域，更具体地涉及一种状态机的合并方法和装置，以降低动态可配置流水线的电路复杂度和配置程序的开发难度。
背景技术
流水线以及用状态机控制流水线上的各个流水级和流水级之间的连接关系是一种普遍应用的数字集成电路形式，例如指令的流水线、网络处理器里处理数据包的流水线、基带信号处理的流水线等。指令流水线技术是指在程序执行时多条指令重叠进行操作的一种处理技术，它将指令分解成不同的阶段，让电路能够按照指定的操作更加充分的利用硬件资源。
动态可重配流水线是这种电路结构向更灵活的可编程方向发展的一种技术。其可重配置的本质是用程序描述流水线上各个状态机的行为，从而在芯片流片后可以随时更改电路流水线的功能。例如，微软公司2011年的专利《调试流水线》中，在执行环境之外建立调试流水线，用可以重配的方式建立流水线进行软硬件的调试。中科院自动化所于2013年提出的《具有多态指令集体系结构的处理器》专利正是使用了动态可重配流水线方法进行处理器的设计，使得处理器的功能可以根据需求重新定义和修改，从而提高和扩展了处理器的灵活性和应用领域。
然而，动态可重配流水线在电路上实现却很困难。其中一个重要的原因是随着电路复杂度的增加和状态机的增多，为每个功能部件的状态机编写应用程序和配置文件变得非常复杂。传统的做法中每个状态机都需要一个配置，也可以很多个状态机用一个配置程序控制但是编程很复杂。
发明内容
针对上述技术问题，本发明提出了一种状态机的合并方法和装置，将每个功能部件的状态机合并为一个复合状态机，并只需要使用一个配置文 件控制这个状态机，从而大大减少编写状态机和算法应用程序的工作量，使得状态机操控硬件的微码程序设计工作大大简化，并且程序的可复用性和可调试性都得到了很大的提高。
为了实现上述目的，作为本发明的一个方面，本发明提出了一种状态机的合并方法，包括以下步骤：
步骤1，对输入的所有子状态机的状态进行分析，并将所述所有子状态机的状态转换图转变为顺序连接的一个或多个状态块；
步骤2，将输入的所有子状态机的首个状态块取出，判断这些状态块的可拼接性和输出子状态机的拼接类型；
若该步骤判定可拼接性是采用拼接规则，且拼接类型是全顺序块类型、全循环块类型或全嵌套循环块类型之一，则判断循环次数是否相同，若相同则将所有输入子状态机放入步骤5的输入中，直到本次输入中没有子状态机时跳到步骤5，若循环次数不相同则采用等价变换规则判定，跳转至步骤3进行子状态机提取规则判定；
若该步骤判定可拼接性是采用等价变换规则，且拼接类型是有嵌套循环块的全循环块类型，则将当前状态块为循环块的子状态机放入下一次步骤2的输入中，将当前状态块为嵌套循环块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
若该步骤判定可拼接性是采用等价变换规则，且拼接类型是非全顺序块类型，则将当前状态块为顺序块的子状态机放入下一次步骤2的输入中，将当前状态块为非顺序块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
若该步骤判定可拼接性和输出的拼接类型不符合上述情况时，该方法输出子状态机不可拼接，该方法结束；
步骤3，接收符合等价变换规则的状态块，根据状态块组合的情况判定需要提取的状态数量并输出给步骤4；
步骤4，将输入的子状态机按照拼接类型进行等价变换，等价变换后的子状态机与输入子状态机功能完全一致，但状态块结构不同，并且等价变换后的子状态机状态块表示输出到步骤2的输入中替换原子状态机的状态块表示，重新做可拼接性判定；若输入的拼接类型是非全顺序块类型， 则将输入的所有子状态机做抽取顺序块等价变换，若输入的拼接类型是有嵌套循环块的全循环块类型，则将输入的所有子状态机做抽取循环块等价变换，当输入中没有需要等价变换的子状态机时，跳转到步骤2；
步骤5，对输入的所有子状态机状态块进行拼接，输出合并状态机；若存在不能拼接的状态块，则跳转到步骤2。
其中，所述步骤1包括：
子步骤1.0，读取一个输入子状态机的当前状态，判断该状态是哪种状态块的起始状态，并跳转到相应状态块分析的子步骤；
子步骤1.1，收集符合顺序块特征的状态，并输出到一个顺序块中；
子步骤1.2，收集符合循环块特征的状态，并输出到一个循环块中，并记录循环块的循环条件；
子步骤1.3，识别并输出只有一个状态的循环状态块，并记录循环块的循环条件；
子步骤1.4，删除输入子状态机状态转换图中该嵌套循环的状态转换，并将该状态转换信息输出到子步骤1.5；以及
子步骤1.5，根据输入的状态，嵌套循环块的嵌套信息将子状态机的状态块表示输出到步骤2的输入中。
其中，所述的子步骤1.5包括以下步骤：
判断输入中是否有嵌套循环的循环条件，若有，则创建一个新的嵌套循环块，记录该嵌套循环块的结束状态，并将输入中的状态块放入该嵌套循环块中，并将该新嵌套循环块作为输入的状态块；
若当前有嵌套循环块未结束，则将输入的状态块放入当前嵌套循环块；
若输入的状态块是嵌套循环块则将当前嵌套循环块切换到输入的状态块；
若当前输入的状态块的最后一个状态是当前嵌套循环块标记的结束状态，则退出当前嵌套循环块，将当前嵌套循环块切换为上一层嵌套循环块，若不存在上一层嵌套循环块，则将该嵌套循环块输出到该子状态机的状态块表示中；
若当前没有嵌套循环块且输入不是嵌套循环块，则将输入的状态块输出到该子状态机的状态块表示中；
判断若当前状态是状态机的结束状态，则将该子状态机从子步骤1.0的输入中删除，若子步骤1.0的输入中没有子状态机则跳转到步骤2。
其中，步骤2中所述的输出子状态机的拼接类型包括：含有嵌套循环块的全循环块类型、非全顺序块类型、全顺序块类型、全循环块类型和全嵌套循环块类型。
其中，步骤3中所述的根据状态块组合的情况判定需要提取的状态数量并输出给步骤4进行子状态机等价变换的步骤包括：
判定当前状态块的组合情况，若为非全顺序块类型、含有嵌套循环块的全循环块类型或全循环块，则提取的规则是：
若当前状态块为非全顺序块类型，输出待提取数量为1，跳至步骤4；
若当前状态块为含有嵌套循环块的全循环块类型，则进入循环体并将循环块内部状态视为顺序块处理，递归调用该步骤并输出提取数量，跳至步骤4；以及
若当前状态块为全循环块，而各个循环块的已循环次数不同，此时提取数量为已循环数量之差与循环体内部状态数量的乘积，输出该待提取数量，跳至步骤4。
其中，所述的步骤5包括：
子步骤5.0，根据步骤2输出的拼接类型将输入中所有子状态机状态块表示放入到对应的子步骤输入中；
子步骤5.1，将输入的子状态机的当前状态块(肯定是顺序块)分别提取出一个状态，并将其合并成一个复合状态，将该复合状态放入子步骤5.5的输入中，并跳转到子步骤5.4；
子步骤5.2，将输入的子状态机的当前状态块(肯定是循环块)类型改变成顺序块，并将当前循环状态块的循环条件和循环结束状态位置放入步骤5.4的输入中，并跳转到子步骤5.4；
子步骤5.3，将输入的子状态机的当前状态块替换为该嵌套循环块内部的状态块集合，并将当前嵌套循环状态块的循环条件和循环结束状态位 置放入步骤5.4的输入中，并跳转到子步骤5.4；并将替换嵌套循环块后的子状态机状态块表示放入步骤2的输入中替换原子状态机状态块表示；
子步骤5.4，用于记录和检查当前拼接状态是否在一个复合循环块的结束位置，并通知子步骤5.5输出循环状态转换以及循环状态转换的条件；以及子步骤5.5，用于输出输入中的复合状态和该复合状态的状态转换以及状态转换条件。
作为本发明的另一个方面，本发明还提出了一种状态机合并装置，包括：存储子状态机输入的模块1、状态块结构分析模块2、保存逻辑状态块的模块3、等价变换模块4、可拼接性和拼接规则判定模块5、待拼接状态块寄存模块6、流程控制模块7和状态块拼接模块8；其中
所述结构分析模块2接收所述存储子状态机输入的模块1输入的子状态机集合，输出标记类型的状态块，并存储在所述保存逻辑状态块的模块3中；
所述保存逻辑状态块的模块3用于存储逻辑状态块队列的存储器；
所述可拼接性和拼接规则判定模块5读取所述保存逻辑状态块的模块3中存储的逻辑状态块，经过比较和判定后输出不同类型待拼接的状态块并寄存在所述待拼接状态块寄存模块6中，其中可直接拼接的状态块输出给所述状态块拼接模块8进行拼接，需要进行等价变换的输出给所述等价变换模块4；
所述等价变换模块4将需要变换的情况进行变换后输出到所述保存逻辑状态块的模块3中存储的逻辑状态块队列中或者直接输出给所述状态块拼接模块8进行状态块拼接；
所述状态块拼接模块8实现所有状态块的拼接模块过程并输出合并结果，对于不能进行拼接的状态块终止拼接进程并输出错误信息；
所述流程控制模块7控制拼接流程的进行，根据待拼接状态机队列是否为空以及状态块拼接的过程控制整个拼接流程的持续向后推进和结束。
作为本发明的再一个方面，本发明还提出了一种状态机的合并装置，包括：
将输入子状态机的状态转换图转变为顺序连接的一个或若干个状态块的装置；
将输入中的所有子状态机的首个状态块取出，判断这些状态块的可拼接性和输出子状态机的拼接类型的装置；
接收符合等价变换规则的状态块，根据状态块组合的情况判定需要提取的状态数量并输出给下述等价变换装置进行子状态机等价变换的装置；
将输入的子状态机按照拼接类型进行等价变换，等价变换后的子状态机与输入子状态机功能完全一致，但状态块结构不同，并等价变换后的子状态机状态块表示输出到上述判断拼接类型的装置的输入中替换原子状态机的状态块表示，重新做可拼接性判定的装置；以及
根据上述判断拼接类型的装置输出的拼接类型将输入中所有子状态机状态块表示放入到对应的装置的输入中的装置。
其中，所述子状态机的拼接类型包括：含有嵌套循环块的全循环块类型、非全顺序块类型、全顺序块类型、全循环块类型和全嵌套循环块类型。
通过上述技术方案可知，本发明的合并状态机的方法和装置能够只使用一个配置文件控制整个状态机，从而大大减少编写状态机和算法应用程序的工作量，使得状态机操控硬件的微码程序设计工作大大简化，并且程序的可复用性和可调试性都得到了很大的提高。
附图说明
图1是本发明的合并状态机的方法中步骤1的流程图；
图2是本发明的合并状态机的方法中步骤4的流程图；
图3是本发明的合并状态机的装置的结构示意图；
图4是本发明一个具体实施例的待拼接子状态机的结构示意图；
图5是本发明一个具体实施例的第一步输出状态块的示意图；
图6是本发明一个具体实施例的第三步输出状态块的示意图；
图7是本发明一个具体实施例的第五步输出状态块的示意图；
图8是本发明一个具体实施例的第七步输出状态块的示意图；
图9是本发明一个具体实施例的第九步子步骤4.4输出状态机的示意图；
图10是本发明一个具体实施例的最终生成的复合状态机的示意图；
图11是本发明一个具体实施例的整个发明方法的流程示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
本发明提出一种合并状态机的方法以及一个基于该方法的状态机合并装置。本发明的合并状态机的方法是通过将若干个独立状态机(简称子状态机)，按照给定的步骤，组合为一个复杂的状态机(简称复合状态机)，并且该方法保证复合状态机与原若干个子状态机的功能完全一致。若干个子状态机通常表现为一条流水线上用于控制各个流水级的状态机，其独立性表现为子状态机的状态转换时间和转换到的目标状态在各子状态机之间没有约束关系。复合状态机通常表现为一条流水线上用于控制各个流水级的一个状态机，该状态机的每个状态完成包含原所有子状态机在当前的状态。本发明的方法中所述给定的步骤包括：子状态机结构分析步骤、子状态机等价性判定步骤、子状态机提取规则判定步骤、子状态机等价变换步骤和子状态机拼接步骤。本发明的基于该方法的状态机合并装置是指能够接受一个或多个子状态机输入，执行该状态机合并方法中的所有步骤，输出复合状态机的装置。该装置可以辅助程序员仍然按照子状态机编写状态机的配置程序，并且得到合并后一个状态机的配置程序。下面对本发明的状态机合并方法和装置进行详细地阐述。
本发明提供了一种合并状态机的方法，包括以下步骤：子状态机结构分析步骤、子状态机等价性判断步骤、子状态机提取规则判定步骤、子状态机等价变换步骤和子状态机拼接步骤。
1.子状态机分析步骤
该步骤的作用是将输入子状态机的状态转换图转变为顺序连接的一个或多个状态块。子状态机的状态转换图包含一个或若干个状态，每个状态包含一个功能描述，包含一个和多个状态之间的连接线，每个连接线包含一个状态转换的条件。一个当前状态的前驱状态是指与当前状态通过连接线直接连接，连接线的起始端成为前驱状态，连接线的终止端为当前状态。一个当前状态的后继状态是指与当前状态通过连接线直接连接，连接线的起始端为当前状态，连接线的终止端称为当前状态的后继状态。状态 块是包含一个或若干个状态或状态块的集合，其中集合的属性包括顺序、循环和嵌套循环。该步骤包含子状态机当前状态识别子步骤、顺序状态块分析子步骤、循环状态块分析子步骤、嵌套循环块分析子步骤、状态块输出子步骤。如图1所示。
1.0子状态机当前状态识别子步骤
该子步骤读取一个输入子状态机的当前状态，判断该状态是哪种状态块的起始状态，并跳转到相应状态块分析的子步骤。
若当前状态有且只有一个前驱状态和一个后继状态，则跳转到子步骤1.1；
若当前状态有且只有两个前驱状态和一个后继状态，跳到子步骤1.2；
若当前状态有且只有两个前驱状态和两个后继状态，且其中的一个前驱和一个后继是当前状态，则跳到子步骤1.3；
若当前状态为其他情况，则跳到子步骤1.4。
1.1顺序状态块分析子步骤
该子步骤收集符合顺序块特征的状态，并输出到一个顺序块中。其中顺序块包含一个或若干个状态，除第一个和最后一个状态外，每个状态有且只有一个前驱状态和一个后继状态。该子步骤的特征在于接收输入的当前状态，若当前状态的后继状态有且只有一个前驱状态和一个后继状态，则将当前状态切换为这个后继状态，重复此过程，若当前状态的后继状态不符合有且只有一个前驱状态和一个后继状态的条件，则标记该顺序块结束，将该状态块放入子步骤1.5的输入中，跳转到子步骤1.5，并将当前状态切换为后继状态。
1.2循环状态块分析子步骤
该子步骤收集符合循环块特征的状态，并输出到一个循环块中，并记录循环块的循环条件。其中循环状态块的特征是除了首尾两个状态外，其它状态都有且只有一个前驱状态和一个后继状态；第一个状态有2个前驱状态和1个后继状态；最后一个状态有1个前驱状态和2个后继状态，且状态块的第一个状态的一个前驱状态是状态块的最后一个状态，同理状态块的最后一个状态的一个后继状态是状态块的第一个状态。该子步骤的特征在于：接收输入的当前状态，若当前状态的后继状态有且只有一个前驱 状态和一个后继状态，则将当前状态切换为这个后继状态，重复此过程；若当前状态的后继状态有且只有一个前驱状态和两个后继状态的条件，且其中一个后继状态是状态块的第一个状态，则接收当前状态的后继状态，标记该循环块结束，并将当前状态跳转到状态块的第一个状态的状态转换条件标记为循环条件，将状态块放入子步骤1.5的输入中，跳转到子步骤1.5，并将当前状态切换为循环块结束状态的其中一个后继状态，该后继状态不是循环块第一个状态；若当前状态的后继状态有两个或两个以上前驱状态，则标记当前接收的状态块为顺序块，将该顺序块放入子步骤1.4的输入，并跳转到步骤1.4，并将当前状态切换到顺序块的第一个状态。
1.3单状态循环块分析子步骤
该子步骤识别并输出只有一个状态的循环状态块，并记录循环块的循环条件。该子步骤的特征在于将当前状态输出到循环块中，并且将跳转到自身的状态转换条件标记为循环条件，将该状态块放入子步骤1.5的输入中，跳转到子步骤1.5，并将当前状态切换为后继状态。
1.4嵌套循环块分析子步骤
该子步骤删除输入子状态机状态转换图中该嵌套循环的状态转换，并将该状态转换信息输出到子步骤1.5。嵌套循环块不包含状态，包含一个或若干个子状态块，其中至少包含1个循环状态块或嵌套循环状态块。嵌套循环块可能包含循环状态块和顺序状态块的组合、循环状态块和循环状态块的组合以及多重嵌套组合等。该子步骤的特征在于，从当前状态的前驱状态中距离最远的状态，删除这个前驱状态到当前状态的状态转换，并将删除后的子状态机状态转换图放入子步骤1.0的输入中替换原子状态机的状态转换图，将删除的状态转换上状态转换条件标记为该嵌套循环块的循环条件，输出给子步骤1.5，若当前状态只有一个或没有前驱状态则跳转到分析错误，该拼接方法结束，若该步骤输入中有顺序块，则将顺序块放入子步骤1.5的输入中，并将当前状态切换为该顺序块最后一个状态的后继状态，否则将当前状态保持不变。
1.5状态块输出子步骤：
该子步骤根据输入的状态，嵌套循环块的嵌套信息将子状态机的状态块表示输出到步骤2的输入中。该子步骤的特征在于：判断输入中是否有 嵌套循环的循环条件，若有，则创建一个新的嵌套循环块，记录该嵌套循环块的结束状态，并将输入中的状态块放入该嵌套循环块中，并将该新嵌套循环块作为输入的状态块；若当前有嵌套循环块未结束，则将输入的状态块放入当前嵌套循环块；若输入的状态块是嵌套循环块则将当前嵌套循环块切换到输入的状态块；若当前输入的状态块的最后一个状态是当前嵌套循环块标记的结束状态，则退出当前嵌套循环块，将当前嵌套循环块切换为上一层嵌套循环块，若不存在上一层嵌套循环块，则将该嵌套循环块输出到该子状态机的状态块表示中；若当前没有嵌套循环块且输入不是嵌套循环块，则将输入的状态块输出到该子状态机的状态块表示中。判断若当前状态是状态机的结束状态，则将该子状态机从子步骤1.0的输入中删除，若子步骤1.0的输入中没有子状态机则跳转到步骤2。
2.子状态机可拼接性和拼接规则判定步骤
该步骤将输入中的所有子状态机的首个状态块取出，判断这些状态块的可拼接性和输出子状态机的拼接类型。其中状态块的可拼接性是指是否存在一种规则能将所有输入子状态机的首个状态块拼接成一个状态块。其中规则包括拼接规则和等价变换规则。其中输出子状态机的拼接类型包括含有嵌套循环块的全循环块类型、非全顺序块类型、全顺序块类型、全循环块类型和全嵌套循环块类型。
若该步骤判定可拼接性是采用拼接规则，且拼接类型是全顺序块类型，全循环块类型或全嵌套循环块类型之一，则判断循环次数是否相同，相同则将所有输入子状态机放入步骤5的输入中，直到本次输入中没有子状态机时跳到步骤5，若循环次数不相同则采用等价变换规则判定，跳转至步骤3进行子状态机拼接规则判定；若该步骤判定可拼接性是采用等价变换规则，且拼接类型是有嵌套循环块的全循环块类型，则将当前状态块为循环块的子状态机放入下一次步骤2的输入中，将当前状态块为嵌套循环块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
若该步骤判定可拼接性是采用等价变换规则，且拼接类型是非全顺序块类型，则将当前状态块为顺序块的子状态机放入下一次步骤2的输入中， 将当前状态块为非顺序块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
若该步骤判定可拼接性和输出的拼接类型不符合上述情况时，该方法输出子状态机不可拼接，该方法结束。
3.子状态机提取规则判定步骤
该步骤的特征是接收符合等价变换规则的状态块，根据状态块组合的情况判定需要提取的状态数量(待提取数量)并输出给步骤4进行子状态机等价变换。该步骤判定当前状态块的组合情况，可能为非全顺序块类型、含有嵌套循环块的全循环块类型、全循环块等几种情况之一，提取的规则是：
若当前状态块为非全顺序块类型，输出待提取数量为1，跳至步骤4；
若当前状态块为含有嵌套循环块的全循环块类型，则进入循环体并将循环块内部状态视为顺序块处理，递归调用该步骤并输出提取数量，跳至步骤4；
若当前状态块为全循环块，而各个循环块的已循环次数不同，此时提取数量为已循环数量之差与循环体内部状态数量的乘积，输出该待提取数量，跳至步骤4。
4.子状态机等价变换步骤
该步骤将输入的子状态机按照拼接类型进行等价变换，等价变换后的子状态机与输入子状态机功能完全一致，但状态块结构不同，并等价变换后的子状态机状态块表示输出到步骤2的输入中替换原子状态机的状态块表示，重新做可拼接性判定。若输入的拼接类型是非全顺序块类型，则将输入的所有子状态机做抽取顺序块等价变换，若输入的拼接类型是有嵌套循环块的全循环块类型，则将输入的所有子状态机做抽取循环块等价变换，当输入中没有需要等价变换的子状态机时，跳转到步骤2。
5.子状态机拼接步骤
该步骤将步骤2输出的状态块按照步骤2输出的类型进行拼接。该步骤包括拼接类型判断子步骤、顺序块拼接子步骤、循环块拼接子步骤、循环块尾部检查子步骤、拼接结果输出子步骤。如图2所示。
5.0拼接类型判断子步骤
该子步骤根据步骤2输出的拼接类型将输入中所有子状态机状态块表示放入到对应的子步骤输入中。
若2个当前拼接类型都是全顺序块类型，则跳转到子步骤5.1。
若2个当前拼接类型都是全循环块类型，则跳转到子步骤5.2。
若2个当前拼接类型中是全嵌套循环块类型，则跳转到子步骤5.3。
若当前状态块不能进行拼接，则返回步骤2。
5.1顺序块拼接子步骤
该子步骤将输入的子状态机的当前状态块(肯定是顺序块)分别提取出一个状态，并将其合并成一个复合状态，将该复合状态放入子步骤5.5的输入中，并跳转到子步骤5.4。此外，该子步骤将每个子状态机的当前状态块中的第一个状态删除，若删除后首个状态块中没有状态，则删除该状态块，将改变后的子状态机状态块表示放入步骤2的输入中替换原子状态机状态块表示，若删除状态块后子状态机状态块表示中没有剩余状态块，则将该子状态机从步骤2的输入中删除。
5.2循环块拼接子步骤
该子步骤将输入的子状态机的当前状态块(肯定是循环块)类型改变成顺序块，并将当前循环状态块的循环条件和循环结束状态位置放入步骤5.4的输入中，并跳转到子步骤5.4。此外，该子步骤将改变状态块类型后的子状态机状态块表示放入步骤2的输入中替换原子状态机状态块表示。
5.3嵌套循环块拼接子步骤
该子步骤将输入的子状态机的当前状态块(肯定是嵌套循环块)替换为该嵌套循环块内部的状态块集合，并将当前嵌套循环状态块的循环条件和循环结束状态位置放入步骤5.4的输入中，并跳转到子步骤5.4。此外，该子步骤将替换嵌套循环块后的子状态机状态块表示放入步骤2的输入中替换原子状态机状态块表示。
5.4循环块尾部检查子步骤
该子步骤用于记录和检查当前拼接状态是否在一个复合循环块的结束位置，并通知子步骤5.5输出循环状态转换以及循环状态转换的条件。该步骤的特征是：若输入中的循环条件和循环结束状态位置不为空，则将 该输入保存在当前循环队列中，并且将当前拼接状态位置作为循环起始位置保存在当前循环队列中，跳转至步骤2；输入中的循环条件和循环结束状态位置为空，则检查当前拼接的状态位置是否与当前循环队列中保存的循环结束状态位置，若有匹配的项，则将对应的循环条件和循环起始地址放入子步骤5.5的输入中，并将该循环的信息从当前循环队列中删除，重复此过程，直到当前循环队列中没有匹配的项为止，跳转到子步骤5.5。
5.5拼接结果输出子步骤
该子步骤用于输出输入中的复合状态和该复合状态的状态转换以及状态转换条件。该子步骤的特征是，将输入中的复合状态输出到复合状态机中，并添加一个该状态的输入状态转换，前驱是复合状态机的最后一个状态；若输入中存在循环条件和循环起始状态位置，则添加一个该状态的输出状态转换，其后继是循环起始状态位置上的复合状态，其转换条件是循环条件，重复此过程直到输入中没有循环条件和循环起始状态位置为止。若此时步骤2中没有子状态机的状态块表示则该方法成功结束，否则跳转到步骤2。
合并状态机的装置：
状态机合并装置如图3所示。包括状态块结构分析模块2、可拼接性和拼接规则判定模块5、等价变换模块4、状态块拼接模块8等几个功能性模块。辅助性模块包括存储子状态机输入的模块1、保存逻辑状态块的模块3、待拼接状态块寄存模块6、流程控制模块7，以及输出的错误信息9和输出的复合状态机10。
该装置输入子状态机集合1，经过合并装置的处理后输出组合状态机10，或者对于不能拼接的状态机提示相应的错误信息9。
结构分析模块2实现了该方法中的子状态机结构分析步骤1，它接收装置的输入子状态机集合1，输出标记类型(顺序块、循环块、嵌套循环块)的状态块(逻辑状态块3)。
模块3是用于存储逻辑状态块队列的存储器。
等价判断模块5按照可拼接性和拼接规则判定步骤2进行设计。该模块读取模块3存储的逻辑状态块，经过比较和判定后输出不同类型待拼接 的状态块并寄存在模块6中，其中可直接拼接的的状态块输出给状态块拼接模块8进行拼接，需要进行等价变换的根据拼接需要输出给等价变换模块4。
等价变换模块4实现了该方法的等价变换步骤。该模块将需要变换的情况进行变换后输出到逻辑状态块3队列中或者直接输出给状态块拼接模块8进行进行状态块拼接。
模块8按照步骤5子状态机拼接步骤进行设计。该模块实现所有状态块的拼接模块过程并输出复合状态机。对于不能进行拼接的状态块(非等价情况)终止拼接进程并输出错误信息。
流程控制单元7控制拼接流程的进行，根据待拼接状态机队列是否为空以及状态块拼接的过程控制整个拼接流程的持续向后推进和结束。
为使能清楚地理解本发明方法的流程，下面结合附图和具体实施例对本发明做进一步阐述。以一个简单的流水线为示例，说明指令状态机拼接的过程。
如图4所示的两个待拼接子状态机。子状态机1包括一个循环3次的状态A1，子状态机2包括一个单独的状态B1和一个循环3次的状态B2。
第一步：步骤1子状态机分析步骤
将接收子状态机1作为输入，进入子步骤1.0：
子步骤1.0：分析子状态机1，状态A1为当前状态，该状态有2个前驱和2个后继，且其中的一个前驱和一个后继是当前状态，跳至子步骤1.3。
子步骤1.3：当前状态A1符合循环状态块条件，将A1放入子步骤1.5中，跳至子步骤1.5。
子步骤1.5：输出循环块A1，循环次数为3，将子状态机1从步骤1.0输入中删除。子状态机1状态块分析结束。
将子状态机2输入至子步骤1.0。
子步骤1.0：分析子状态机2，状态B1为当前状态，该状态有1个前驱和1个后继，跳至子步骤1.1。
子步骤1.1：只有一个状态B1复合顺序块特征，标记顺序块结束，跳至子步骤1.5。
子步骤1.5：输出顺序块B1，跳至子步骤1.0，将当前状态修改为B2。
子步骤1.0：当前状态B2存在2个前驱和2个后继，且其中的一个前驱和一个后继是当前状态，跳至子步骤1.3。
子步骤1.3：当前状态B2符合循环状态块条件，将B2放入子步骤1.5中，跳至子步骤1.5。
子步骤1.5：输出循环块B2，循环次数为3，将子状态机2从步骤1.0输入中删除。子状态机2状态块分析结束。步骤1结束，跳至步骤2。
此时步骤1结束输出的状态块为：循环块A1，循环次数为3；顺序块B1；循环块B2，循环次数为3。输出至逻辑状态块寄存器(参见图3中的模块3)中，如图5所示。
第二步：步骤2子状态机可拼接性和拼接规则判定步骤
取出子状态机1和子状态机2的第一个状态块。首先判定可拼接性，两个状态块分别是循环块和顺序块，不可直接拼接。将循环块A1输出到步骤4中，顺序块B1输出到下一次步骤2中，跳至步骤4。
第三步：步骤4子状态机等价变换步骤
将循环3次的循环块A1拆分为一个顺序块A1和一个循环2次的循环块A1，且第一个顺序块A1在前，他的后继状态是2次循环的循环块A1，跳至步骤2。见图6所示。
第四步：步骤2子状态机可拼接性和拼接规则判定步骤
子状态机1此时首个状态块为顺序块A1，子状态机2首个状态块为顺序块B1，符合拼接规则，可以进行状态块拼接。跳至步骤5。
第五步：步骤5子状态机拼接步骤
子步骤5.0：当前两个待拼接状态块都是顺序状态块，跳至子步骤5.1。
子步骤5.1：合并A1和B1作为新的复合状态块A1B1，跳至子步骤5.4。
子步骤5.4：输出拼接结果顺序块A1B1。删除队列中的A1顺序块和B1顺序块，子状态机1向后读取下一个状态块为2次的循环块A1，子状态机2向后读取下一个状态块为3次的循环块B2，待拼接队列不为空，返回子步骤5.0。
子步骤5.0：当前两个状态块不能拼接，返回步骤2。此时状态块如图7所示。
第六步：步骤2子状态机可拼接性和拼接规则判定步骤
判定拼接规则，A1的2次循环块和B2的3次循环块不可拼接，需要进行等价变换，将A1循环块和B2循环块输出至步骤3，跳至步骤4。
第七步：步骤4子状态机等价变换步骤
对应2次循环的循环块A1，将3次循环的循环块B2拆分为一个2次循环的循环块B2和1个顺序块B2，且2次循环块B2的一个后继状态为顺序块B2。跳至步骤2。此时状态块如图8所示。
第八步：步骤2子状态机可拼接性和拼接规则判定步骤
子状态机1此时首个状态块为2次循环块A1，子状态机2首个状态块为2次循环块B2，符合拼接规则，可以进行状态块拼接。跳至步骤5。
第九步：步骤5子状态机拼接步骤
子步骤5.0：当前两个待拼接状态块都是循环块且循环次数相同，跳至子步骤5.2。
子步骤5.2：合并循环块A1和B2作为新的2次复合循环块状态块A1B2，跳至子步骤5.4。
子步骤5.4：输出拼接结果2次循环块A1B2。删除队列中的A1循环块和B2循环块，子状态机1向后读取下一个状态块为空，子状态机2向后读取下一个状态块为顺序块B2，待拼接队列不为空，返回子步骤5.0。此时状态块如图9所示。
子步骤5.0：子状态机1的待拼接队列为空，输出剩余的子状态机2状态块B2加之当前复合状态机尾，清空子状态机2状态块队列，跳至子步骤5.4。
子步骤5.4：两个子状态机队列均为空，拼接结束，输出当前复合状态机：顺序块A1B1、2次循环块A1B2、顺序块B2。
最终拼接得到的复合状态机如图10所示。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

  1. 一种状态机的合并方法，包括以下步骤：
    步骤1，对输入的所有子状态机的状态进行分析，并将所述所有子状态机的状态转换图转变为顺序连接的一个或多个状态块；
    步骤2，将输入的所有子状态机的首个状态块取出，判断这些状态块的可拼接性和输出子状态机的拼接类型；
    若该步骤判定可拼接性是采用拼接规则，且拼接类型是全顺序块类型、全循环块类型或全嵌套循环块类型之一，则判断循环次数是否相同，若相同则将所有输入子状态机放入步骤5的输入中，直到本次输入中没有子状态机时跳到步骤5，若循环次数不相同则采用等价变换规则判定，跳转至步骤3进行子状态机提取规则判定；
    若该步骤判定可拼接性是采用等价变换规则，且拼接类型是有嵌套循环块的全循环块类型，则将当前状态块为循环块的子状态机放入下一次步骤2的输入中，将当前状态块为嵌套循环块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
    若该步骤判定可拼接性是采用等价变换规则，且拼接类型是非全顺序块类型，则将当前状态块为顺序块的子状态机放入下一次步骤2的输入中，将当前状态块为非顺序块的子状态机放入步骤3的输入中，直到本次输入中没有子状态机时跳到步骤3；
    若该步骤判定可拼接性和输出的拼接类型不符合上述情况时，该方法输出子状态机不可拼接，该方法结束；
    步骤3，接收符合等价变换规则的状态块，根据状态块组合的情况判定需要提取的状态数量并输出给步骤4；
    步骤4，将输入的子状态机按照拼接类型进行等价变换，等价变换后的子状态机与输入子状态机功能完全一致，但状态块结构不同，并且等价变换后的子状态机状态块表示输出到步骤2的输入中替换原子状态机的状态块表示，重新做可拼接性判定；若输入的拼接类型是非全顺序块类型，则将输入的所有子状态机做抽取顺序块等价变换，若输入的拼接类型是有 嵌套循环块的全循环块类型，则将输入的所有子状态机做抽取循环块等价变换，当输入中没有需要等价变换的子状态机时，跳转到步骤2；
    步骤5，对输入的所有子状态机状态块进行拼接，输出合并状态机；若存在不能拼接的状态块，则跳转到步骤2。
  2. 根据权利要求1所述的状态机的合并方法，其中所述步骤1包括：
    子步骤1.0，读取一个输入子状态机的当前状态，判断该状态是哪种状态块的起始状态，并跳转到相应状态块分析的子步骤；
    子步骤1.1，收集符合顺序块特征的状态，并输出到一个顺序块中；
    子步骤1.2，收集符合循环块特征的状态，并输出到一个循环块中，并记录循环块的循环条件；
    子步骤1.3，识别并输出只有一个状态的循环状态块，并记录循环块的循环条件；
    子步骤1.4，删除输入子状态机状态转换图中该嵌套循环的状态转换，并将该状态转换信息输出到子步骤1.5；以及
    子步骤1.5，根据输入的状态，嵌套循环块的嵌套信息将子状态机的状态块表示输出到步骤2的输入中。
  3. 根据权利要求2所述的状态机的合并方法，其中所述的子步骤1.5包括以下步骤：
    判断输入中是否有嵌套循环的循环条件，若有，则创建一个新的嵌套循环块，记录该嵌套循环块的结束状态，并将输入中的状态块放入该嵌套循环块中，并将该新嵌套循环块作为输入的状态块；
    若当前有嵌套循环块未结束，则将输入的状态块放入当前嵌套循环块；
    若输入的状态块是嵌套循环块则将当前嵌套循环块切换到输入的状态块；
    若当前输入的状态块的最后一个状态是当前嵌套循环块标记的结束状态，则退出当前嵌套循环块，将当前嵌套循环块切换为上一层嵌套循环块，若不存在上一层嵌套循环块，则将该嵌套循环块输出到该子状态机的状态块表示中；
    若当前没有嵌套循环块且输入不是嵌套循环块，则将输入的状态块输出到该子状态机的状态块表示中；
    判断若当前状态是状态机的结束状态，则将该子状态机从子步骤1.0的输入中删除，若子步骤1.0的输入中没有子状态机则跳转到步骤2。
  4. 根据权利要求1所述的状态机的合并方法，其中步骤2中所述的输出子状态机的拼接类型包括：含有嵌套循环块的全循环块类型、非全顺序块类型、全顺序块类型、全循环块类型和全嵌套循环块类型。
  5. 根据权利要求1所述的状态机的合并方法，其中步骤3中所述的根据状态块组合的情况判定需要提取的状态数量并输出给步骤4进行子状态机等价变换的步骤包括：
    判定当前状态块的组合情况，若为非全顺序块类型、含有嵌套循环块的全循环块类型或全循环块，则提取的规则是：
    若当前状态块为非全顺序块类型，输出待提取数量为1，跳至步骤4；
    若当前状态块为含有嵌套循环块的全循环块类型，则进入循环体并将循环块内部状态视为顺序块处理，递归调用该步骤并输出提取数量，跳至步骤4；以及
    若当前状态块为全循环块，而各个循环块的已循环次数不同，此时提取数量为已循环数量之差与循环体内部状态数量的乘积，输出该待提取数量，跳至步骤4。
  6. 根据权利要求1所述的状态机的合并方法，其中所述的步骤5包括：
    子步骤5.0，根据步骤2输出的拼接类型将输入中所有子状态机状态块表示放入到对应的子步骤输入中；
    子步骤5.1，将输入的子状态机的当前状态块(肯定是顺序块)分别提取出一个状态，并将其合并成一个复合状态，将该复合状态放入子步骤5.5的输入中，并跳转到子步骤5.4；
    子步骤5.2，将输入的子状态机的当前状态块(肯定是循环块)类型改变成顺序块，并将当前循环状态块的循环条件和循环结束状态位置放入步骤5.4的输入中，并跳转到子步骤5.4；
    子步骤5.3，将输入的子状态机的当前状态块替换为该嵌套循环块内部的状态块集合，并将当前嵌套循环状态块的循环条件和循环结束状态位置放入步骤5.4的输入中，并跳转到子步骤5.4；并将替换嵌套循环块后的子状态机状态块表示放入步骤2的输入中替换原子状态机状态块表示；
    子步骤5.4，用于记录和检查当前拼接状态是否在一个复合循环块的结束位置，并通知子步骤5.5输出循环状态转换以及循环状态转换的条件；以及子步骤5.5，用于输出输入中的复合状态和该复合状态的状态转换以及状态转换条件。
  7. 一种状态机合并装置，包括：存储子状态机输入的模块(1)、状态块结构分析模块(2)、保存逻辑状态块的模块(3)、等价变换模块(4)、可拼接性和拼接规则判定模块(5)、待拼接状态块寄存模块(6)、流程控制模块(7)和状态块拼接模块(8)；其中
    所述结构分析模块(2)接收所述存储子状态机输入的模块(1)输入的子状态机集合，输出标记类型的状态块，并存储在所述保存逻辑状态块的模块(3)中；
    所述保存逻辑状态块的模块(3)用于存储逻辑状态块队列的存储器；
    所述可拼接性和拼接规则判定模块(5)读取所述保存逻辑状态块的模块(3)中存储的逻辑状态块，经过比较和判定后输出不同类型待拼接的状态块并寄存在所述待拼接状态块寄存模块(6)中，其中可直接拼接的状态块输出给所述状态块拼接模块(8)进行拼接，需要进行等价变换的输出给所述等价变换模块(4)；
    所述等价变换模块(4)将需要变换的情况进行变换后输出到所述保存逻辑状态块的模块(3)中存储的逻辑状态块队列中或者直接输出给所述状态块拼接模块(8)进行状态块拼接；
    所述状态块拼接模块(8)实现所有状态块的拼接模块过程并输出合并结果，对于不能进行拼接的状态块终止拼接进程并输出错误信息；
    所述流程控制模块(7)控制拼接流程的进行，根据待拼接状态机队列是否为空以及状态块拼接的过程控制整个拼接流程的持续向后推进和结束。
  8. 一种状态机的合并装置，包括：
    将输入子状态机的状态转换图转变为顺序连接的一个或若干个状态块的装置；
    将输入中的所有子状态机的首个状态块取出，判断这些状态块的可拼接性和输出子状态机的拼接类型的装置；
    接收符合等价变换规则的状态块，根据状态块组合的情况判定需要提取的状态数量并输出给下述等价变换装置进行子状态机等价变换的装置；
    将输入的子状态机按照拼接类型进行等价变换，等价变换后的子状态机与输入子状态机功能完全一致，但状态块结构不同，并等价变换后的子状态机状态块表示输出到上述判断拼接类型的装置的输入中替换原子状态机的状态块表示，重新做可拼接性判定的装置；以及
    根据上述判断拼接类型的装置输出的拼接类型将输入中所有子状态机状态块表示放入到对应的装置的输入中的装置。
  9. 根据权利要求1所述的状态机的合并装置，其中所述子状态机的拼接类型包括：含有嵌套循环块的全循环块类型、非全顺序块类型、全顺序块类型、全循环块类型和全嵌套循环块类型。
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