WO2016106413A1 - Poursuite de bruit de phase des oscillateurs locaux pour transmission à porteuse unique - Google Patents

Poursuite de bruit de phase des oscillateurs locaux pour transmission à porteuse unique Download PDF

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Publication number
WO2016106413A1
WO2016106413A1 PCT/US2015/067646 US2015067646W WO2016106413A1 WO 2016106413 A1 WO2016106413 A1 WO 2016106413A1 US 2015067646 W US2015067646 W US 2015067646W WO 2016106413 A1 WO2016106413 A1 WO 2016106413A1
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WO
WIPO (PCT)
Prior art keywords
phase
symbols
noise
symbol
block
Prior art date
Application number
PCT/US2015/067646
Other languages
English (en)
Inventor
Nirmal C. Warke
Lars Morten Jorgensen
Srinath Hosur
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2017534323A priority Critical patent/JP6622810B2/ja
Priority to CN201580070168.2A priority patent/CN107113262B/zh
Priority to EP15874370.8A priority patent/EP3259890B1/fr
Publication of WO2016106413A1 publication Critical patent/WO2016106413A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0044—Control loops for carrier regulation
    • H04L2027/0053—Closed loops
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0083—Signalling arrangements
    • H04L2027/0089—In-band signals
    • H04L2027/0093—Intermittant signals

Definitions

  • phase noise from the transmit and receive radio frequency (RF) carrier local oscillators (LO) significantly corrupts transmission.
  • Phase noise on the carrier is a significant impairment to supporting higher order modulations.
  • Digital baseband data is modulated, such as using 256-QAM (Quadrature Amplitude Modulation), onto a carrier and up-converted to an RF carrier frequency using an LO signal.
  • Phase noise is introduced in the up-converted signal by the LO signal. This causes the QAM constellation to rotate as the LO phase changes over time.
  • a forward/backward Decision-Directed Phase Tracking Loop removes phase noise from received single-carrier signals.
  • One embodiment of a system for correcting phase error in a received signal includes a first buffer that is configured to store a block of input symbols.
  • the block of input symbols starts with a first pilot symbol and ends with a last pilot symbol.
  • the block of input symbols includes unknown data symbols between the first pilot symbol and the last pilot symbol and may include additional pilot symbols between the first last pilot symbols.
  • a phase rotator is configured to apply phase-noise compensation to the block of input symbols on a symbol-by-symbol basis.
  • a feedback loop is coupled to the phase rotator and provides a phase-noise compensation signal to the phase rotator.
  • the phase compensation signal provided may be generated based upon phase-noise-error detection for each pilot symbol, phase-noise- error detection over an entire block of input symbols, phase-noise-error detection using every h pilot symbol in the block of input symbols, or any other appropriate process.
  • a first output buffer is configured to store a first block of phase-noise-compensated symbols output from the phase-rotator. The symbols in the first block of phase-noise- compensated symbols are sequentially received from the phase rotator starting with the first pilot symbol.
  • a second output buffer is configured to store a second block of phase-noise- compensated symbols output from the phase-rotator. The symbols in the second block of phase- noise-compensated symbols are sequentially received from the phase rotator starting with the last pilot symbol.
  • a combiner is configured to combine associated symbols from the first and second blocks of phase-noise-compensated symbols to create output symbols.
  • the feedback loop includes a hard decision module that receives the output from the phase rotator and determines a closest point in a modulation constellation for each received symbol.
  • a phase estimator in the feedback loop receives a first input from the phase rotator and a second input from the hard decision module.
  • a loop filter is coupled to the output of the phase estimator.
  • a numerically controlled oscillator is coupled to the output of the loop filter. The numerically controlled oscillator provides the phase-noise compensation signal to the phase rotator.
  • the associated symbols from the first and second blocks of phase-noise-compensated symbols may be combined using a process selected from the group consisting of: symbol-by- symbol averaging; weighted symbol-by-symbol combining; and weighted symbol-by-symbol combining using an error metric, a Log-Likelihood Ratio (LLR) metric, a Minimum-Mean- Square Error (MMSE) error metric, and the like.
  • LLR Log-Likelihood Ratio
  • MMSE Minimum-Mean- Square Error
  • the initial phase-noise-error compensation that is applied to the first-received pilot symbol for a block of input symbols may be based upon, for example, a phase-noise-error compensation applied to a prior block of input symbols or to a last symbol in a prior block of input symbols.
  • a Forward Error Correction (FEC) decoder may be coupled to an output of the combiner and configured to decode the output symbols.
  • the output of the FEC decoder may be coupled to the phase estimator.
  • the phase estimator may use decoded output symbols in place of the input from the hard decision module.
  • One or more additional iterations of tracking phase-noise error may be applied using the decoded symbols from the FEC decoder.
  • FIG. 1 is a block diagram of a receiver according to one embodiment.
  • FIG. 2 illustrates a continuous stream of single carrier modulated data that may be processed using disclosed embodiments.
  • FIG. 3 is a block diagram of one embodiment of a forward/backward DDPLL.
  • FIG. 4 is a block diagram of a DDPLL phase estimator according to one embodiment.
  • FIG. 5 is a block diagram of a second-order loop filter according to one embodiment of the DDPLL.
  • FIG. 6 illustrates another embodiment in which the DDPLL method described above is iterated with the FEC decoder.
  • FIG. 7 is a flowchart illustrating a method for correcting phase error in a received signal according to one embodiment.
  • FIG. 1 is a block diagram of a receiver 101 according to one embodiment.
  • Data 102 is down converted and input to receiver 101.
  • Received data is processed in digital front end 103 and equalizer 104.
  • Forward ackward DDPLL 105 removes phase noise in the equalized symbols and provides an input to FEC decoder 106.
  • FIG. 2 illustrates a continuous stream of single carrier modulated data 200 that may be received at the input to DDPLL 105 of receiver 101.
  • Periodic known pilot symbols 201 are inserted into the data stream by the transmitter. Between each known pilot symbol 201 are unknown data symbols 202.
  • the symbols in the single carrier modulated data 200 are grouped into DDPLL blocks 203.
  • Each DDPLL block begins with a pilot symbol 201a and ends with another pilot symbol 201n. Any number of additional pilot symbols and unknown data symbols may be between the beginning and ending pilot symbols 201a, 201n for each DDPLL block.
  • FIG. 3 is a block diagram of one embodiment of a forward ackward DDPLL 300.
  • Phase-noise-corrupted symbols are received at the input to forward/backward DDPLL 300.
  • the phase-noise-corrupted symbols may include single carrier modulated data as illustrated in FIG. 2.
  • the phase-noise-corrupted symbols may be passed to the forward/backward DDPLL from a digital front end and equalizer as illustrated in receiver 101 of FIG. 1.
  • the phase-noise- corrupted symbols are stored to input buffer 301 as groups of symbols in a DDPLL block.
  • Input buffer 301 provides the input to phase rotator 302, which provides a phase rotation based on the latest phase estimate in the DDPLL.
  • the symbols in the phase-noise- corrupted block that is stored in input buffer 301 may be played into phase rotator 302 in both the forward and backward directions.
  • a DDPLL block 203 having beginning and ending pilot symbols 201a, 201n may be alternately provided from input buffer to phase rotator 302 starting with known pilot symbol 201a (i.e., forward playback) or starting with known pilot symbol 201n (i.e., backward playback).
  • Phase rotator 302 applies phase-noise compensation to the received symbols to counteract the phase rotation in the received signal.
  • the phase-noise compensation is generated by a second order loop that tracks phase and frequency.
  • Feedback loop 303 including hard decision block 304, phase estimator 305, loop filter 306, and numerically controlled oscillator (NCO) 307.
  • Phase estimator 305 receives two inputs. One input is the unmodified output of phase rotator 302. The other input comes from hard decision 304, which estimates the demodulated symbol.
  • Hard decision 304 compares the symbols in the output of phase rotator 302 to the relevant modulation constellation. The output of hard decision block 304 corresponds to the actual point constellation point that is closest to each symbol in the output of phase rotator 302.
  • Phase estimator 305 generates a phase-error estimate based upon the input and output of hard decision 304. Phase estimator 305 compares the two inputs and estimates the phase difference between the symbols that have been corrected by phase rotator 302 and the intended phase for each symbol.
  • phase estimator 305 is filtered in loop filter 306 to remove noise outside the signal bandwidth.
  • NCO 307 accumulates filtered error estimates and provides the latest phase estimate as an a phase-noise compensation signal to phase rotator 302.
  • phase rotator 302 When phase rotator 302 receives a forward playback of phase-noise-corrupted symbols from input buffer 301, the phase-noise-compensated symbols output from phase rotator 302 are stored to forward output buffer 308. When phase rotator 302 receives a backward playback of phase-noise-corrupted symbols from input buffer 301, the phase-noise-compensated symbols output from phase rotator 302 are stored to backward output buffer 309. Output buffers 308 and 309 are generally the same size as input buffer 301 as they store the same number of symbols. Averaging block 310 then averages or combines the forward and backward phase-noise- compensated symbols to generate input data for the FEC decoder.
  • DDPLL 300 operates over blocks of data that can span several pilot symbols as illustrated in FIG. 2.
  • the DDPLL phase is reset at the start of processing each block of phase- noise-corrupted symbols and tracks over that block.
  • the start phase for the block may be initialized with the phase estimate based on the known pilot symbols on the ends of the block - e.g., known pilot symbols 201a or 201n.
  • the start phase for the DDPLL may be initialized based on an error metric, such as a Minimum-Mean-Square Error (MMSE) phase estimate over a window of data symbols on either side of the pilot assuming the phase to be constant over the window.
  • MMSE Minimum-Mean-Square Error
  • the DDPLL may apply a different weight to the unknown data symbols compared to the known pilot symbols since the phase error detection in the known pilots will have greater reliability.
  • Each block has a forward and backward run through DDPLL 300.
  • the forward DDPLL run starts with the pilot symbol that occurs first in time (e.g., pilot 201a), and the backward DDPLL starts with the pilot that occurs later in time at the end of the phase-noise-corrupted block (e.g., pilot 201n).
  • the phase-noise- compensated symbols from the forward and backward DDPLL runs are combined to generate effective phase-noise-compensated samples over the block.
  • the phase- noise estimates from the forward and backward DDPLL runs are combined over the block.
  • the phase-noise-compensated symbols may be combined using any appropriate method, such as a simple symbol-by-symbol average, a weighted symbol-by-symbol combining using the Log- Likelihood Ratio (LLR) metric, or a weighted combining of the forward and backward DDPLL runs based on an error metric such as the MMSE over the block.
  • the error metric may determine which run - the forward or backward run - generates the more accurate phase compensation. The (forward or backward) run with the most accurate phase compensation may then be used as the input to the FEC decoder without combining the two runs.
  • FIG. 4 is a block diagram of a DDPLL phase estimator 400 according to one embodiment.
  • DDPLL phase estimator has two inputs.
  • Input 401 (y) is the phase noise compensated sample from the phase rotator, which also serves as the input to the hard decision block.
  • Input 402 (x) is the hard decision value output by the hard decision block.
  • the function lm(x ⁇ y * ) provides an estimate of the phase error.
  • An optional weighting function w( ⁇ x ⁇ ) may be applied to the phase error estimate.
  • the weighting function is based upon the magnitude of the hard decision input (x). For example, in a system using QAM modulation, smaller amplitudes may be more affected by thermal noise and hence the phase-noise estimate from them may be less reliable.
  • FIG. 5 is a block diagram of a second-order loop filter 500 according to one embodiment of the DDPLL.
  • the input to loop filter 500 is the output of the phase estimator.
  • Higher order filtering 501 eliminates noise outside the bandwidth of the DDPLL and provides a phase correction to combiner 502.
  • the output of filter 501 also passes through amplifier 503 and integrator/accumulator 504 to provide a frequency correction.
  • the phase correction and frequency correction are combined in 502 to generate an input to the NCO.
  • user bits may be loaded on to the pilot symbols with sufficient margin for reliable decoding of the pilot relative to the data symbols. For example, in a system that uses 256 QAM modulation for data symbols, data may be modulated on to the pilots symbols using 32 or 64 QAM.
  • FIG. 6 illustrates another embodiment in which the DDPLL method described above is iterated with the FEC decoder.
  • Phase-noise-corrupted symbols are cleaned up in a first DDPLL run 601.
  • the phase-noise-compensated samples from the first DDPLL run are provided to the FEC decoder for a first decoding 602.
  • the decoded symbols output from FEC decoder run 602 have a much lower error rate compared to the hard decision symbols used in the first run of DDPLL 601 by virtue of the coding gain provided by the FEC.
  • the DDPLL can be run for a second time 603 (i.e., first iteration) using the decoded symbols from FEC decoding 602 rather than making hard decisions.
  • the DDPLL hard decisions are not completely reliable and may make errors in the phase estimate, which would inadvertently add error in tracking the phase in the symbols.
  • Using the decoded symbols substantially increases the performance of the DDPLL.
  • the DDPLL cleaned up samples from the second run 603 are then sent for a second FEC decoding 604. If the FEC decoding improves quality, then the process may be repeated for subsequent DDPLL 605 and FEC decoding 606 iterations.
  • the hard decision is used to estimate and track phase for the first DDPLL run.
  • the FEC decoder is used in place of the hard decision in the second and subsequent runs. As a result, more reliable phase-noise-compensated symbols are provided to the subsequent FEC decoder runs.
  • embodiments may be used with any digital modulation scheme, such as QAM, Quadrature Phase Shift Keying (QPSK), etc.
  • QAM Quadrature Phase Shift Keying
  • QPSK Quadrature Phase Shift Keying
  • the DDPLL may process the symbol blocks in different ways for various embodiments.
  • the DDPLL may make symbol-by-symbol corrections to the phase error correction in one embodiment and provide an symbol-by-symbol output to the FEC decoder.
  • the DDPLL may store an entire block and track the phase across the entire block, such as estimating one phase error correction to be applied to the entire block. This embodiment may provide a block-by-block output to the FEC decoder.
  • the DPPLL may assume that the phase error is constant across multiple symbols and may use every N 111 symbol to determine the phase-error correction to be applied by the phase rotator.
  • FIG. 7 is a flowchart illustrating a method for correcting phase error in a received signal according to one embodiment.
  • a block of input symbols is received.
  • the block of input symbols starts with a first pilot symbol and ending with a last pilot symbol.
  • the block of input symbols may be stored to an input buffer.
  • the block of input symbols includes unknown data symbols between the first pilot symbol and the last pilot symbol and may also include additional pilot symbols between the first and last pilot symbols.
  • step 702 phase-noise compensation is applied to the block of input symbols in a forward direction starting with the first pilot symbol.
  • a first block of phase-noise- compensated symbols are stored to a first output buffer. The first block of phase-noise- compensated symbols corresponding to the forward-direction block of input symbols.
  • step 704 phase-noise compensation is applied to the block of input symbols in a backward direction starting with the last pilot symbol.
  • step 705 a second block of phase- noise-compensated symbols is stored to a second output buffer. The second block of phase- noise-compensated symbols corresponding to the backward-direction block of input symbols.
  • step 706 associated symbols from the first and second blocks of phase-noise- compensated symbols are combined to create output symbols.
  • the associated symbols from the first and second blocks of phase-noise-compensated symbols may be combined to create output symbols using a process such as symbol-by-symbol averaging, weighted symbol-by-symbol combining, weighted symbol-by-symbol combining using an error metric, weighted symbol-by- symbol combining using a LLR metric, weighted symbol-by-symbol combining using a MMSE error metric.
  • the output symbols may be created by selecting which phase- compensated symbol is more reliable between associated symbols within the first and second blocks of phase-compensated symbols.
  • a phase-noise compensation signal may be generated in a feedback loop including a hard decision module receiving phase-noise-compensated symbols and determining a closest point in a modulation constellation for each received symbol, a phase estimator phase estimator receiving phase-noise-compensated symbols at a first input and receiving an output from the hard decision module at a second input, a loop filter coupled to an output of the phase estimator, and a numerically controlled oscillator coupled to an output of the loop filter, the numerically controlled oscillator providing the phase-noise compensation signal to a phase rotator.
  • the phase-noise compensation signal may be generated using one or more of phase- noise-error detection for each pilot symbol, phase-noise-error detection over an entire block of input symbols, or phase-noise-error detection using every h pilot symbol in the block of input symbols.
  • the initial phase-noise-error compensation applied to the first-received pilot symbol from the block of input symbols may be based upon a phase-noise-error compensation applied to a prior block of input symbols or to a last symbol in a prior block of input symbols.
  • the output symbols may be provided to a FEC decoder.
  • Decoded symbols from the FEC decoder may be used to apply phase-noise compensation to the block of input symbols in a forward direction and backward direction during one or more additional iterations.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

Dans des exemples décrits, un système et un procédé permettant la poursuite du bruit dans un signal reçu utilisent une boucle de poursuite de phase dirigée par décisions (303) pour générer un signal de compensation de bruit de phase qui élimine un bruit de phase de signaux à porteuse unique reçus.
PCT/US2015/067646 2014-12-23 2015-12-28 Poursuite de bruit de phase des oscillateurs locaux pour transmission à porteuse unique WO2016106413A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017534323A JP6622810B2 (ja) 2014-12-23 2015-12-28 単一キャリア伝送のための局部発振器位相ノイズ追跡
CN201580070168.2A CN107113262B (zh) 2014-12-23 2015-12-28 用于单载波传输的本地振荡器相位噪声跟踪
EP15874370.8A EP3259890B1 (fr) 2014-12-23 2015-12-28 Poursuite de bruit de phase des oscillateurs locaux pour transmission à porteuse unique

Applications Claiming Priority (2)

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US14/580,595 US9258107B1 (en) 2014-12-23 2014-12-23 Local oscillator phase noise tracking for single carrier transmission
US14/580,595 2014-12-23

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JP (1) JP6622810B2 (fr)
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US10367484B2 (en) * 2016-07-28 2019-07-30 Texas Instruments Incorporated Ramp based clock synchronization for stackable circuits
RU2626246C1 (ru) * 2016-08-10 2017-07-25 Общество с ограниченной ответственностью "Радио Гигабит" Способ компенсации влияния фазового шума на передачу данных в радиоканале
US10708107B1 (en) * 2019-09-10 2020-07-07 Huawei Technologies Co., Ltd. Method and decoder for suppressing phase noise in an orthogonal frequency division multiplexing signal

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Publication number Publication date
EP3259890B1 (fr) 2019-07-31
JP2018502507A (ja) 2018-01-25
EP3259890A4 (fr) 2018-04-18
US9258107B1 (en) 2016-02-09
CN107113262A (zh) 2017-08-29
CN107113262B (zh) 2020-05-08
JP6622810B2 (ja) 2019-12-18
EP3259890A1 (fr) 2017-12-27

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