WO2016103878A1

WO2016103878A1 - Endoscope

Info

Publication number: WO2016103878A1
Application number: PCT/JP2015/079608
Authority: WO
Inventors: 秀範橋本; 文行大河; 泰憲松井
Original assignee: オリンパス株式会社
Priority date: 2014-12-26
Filing date: 2015-10-20
Publication date: 2016-06-30
Also published as: CN207785129U

Abstract

The endoscope (1) comprises a CMOS image sensor (11) which has a Bayer pattern primary color filter, progressively scans an imaging signal, and outputs the signal as a video signal. The endoscope (1) is provided with a signal processing unit (24) for an interlaced format, capable of converting a progressive signal from the CMOS image sensor (11) to an interlaced signal compatible with an interlaced image processing circuit (33) of a video processor (3) compatible with an interlaced format, and outputting the interlaced signal.

Description

Endoscope

The present invention relates to an endoscope that can output an imaging signal from an imaging unit as a progressive video signal.

Conventionally, endoscopes equipped with an image sensor have been widely used in the medical field and the industrial field. There is also a known technique for constituting an endoscope system, which is detachably connected to an endoscope and performs various signal processing related to the endoscope by a signal processing device called a video processor.

An endoscope in this type of endoscope system includes an endoscope that scans and outputs an imaging signal from an imaging unit by an interlace method, and an endoscope that scans and outputs the imaging signal by a progressive method. A mirror is known, and a video processor that can handle any of these systems is conventionally known in Japanese Patent Application Laid-Open No. 2002-209836.

As described above, the endoscope system described in Japanese Patent Application Laid-Open No. 2002-209836 includes an interlace video signal processing unit and a progressive signal in a video processor (camera control unit) to which the endoscope is connected. Both processing units are provided, and a processing system is selected in accordance with the identification result of the type of endoscope (interlace method or progressive method) to be connected.

That is, in the endoscope system described in Japanese Patent Laid-Open No. 2002-209836 described above, the image processing signal is changed by switching the signal processing system provided in the video processor according to the type of endoscope to be connected. It corresponds to an endoscope that scans and outputs an image using an interlace method, and an endoscope that scans and outputs an image signal using a progressive method.

However, for example, when a video processor that supports only one of the interlace method and the progressive method is assumed as the video processor, there arises a problem that the video processor cannot support an endoscope having the other output method. It will be.

In particular, even if an endoscope that scans an image signal from an image capturing unit by a progressive method is connected to a video processor that includes only an interlace signal processing circuit, it is difficult to connect due to the difference in the signal processing unit.

The present invention has been made in view of the above points, and even an endoscope that scans an image pickup signal from an image pickup unit by a progressive method can be adapted to a video processor equipped only with an interlace signal processing circuit. An object of the present invention is to provide an endoscope.

The endoscope according to one aspect of the present invention includes a pixel portion configured by a plurality of pixels that photoelectrically convert light to generate a pixel signal, and a Bayer array primary color filter provided on the pixels, In the imaging unit that generates an imaging signal composed of pixel signals generated by the plurality of pixels, a reading unit that reads out the imaging signal from the imaging unit and outputs it as a progressive video signal, and the reading unit A conversion unit that converts the processing format of the read video signal into a processing format that can be processed by a separate signal processing device connected to a subsequent stage, and the video signal whose processing format has been converted by the conversion unit And an output unit that outputs the signal to the signal processing device.

FIG. 1 is a diagram showing a configuration of an endoscope and an interlace-compatible video processor according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of an interlace signal processing unit in the endoscope according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a pixel arrangement in the CMOS image sensor of the endoscope according to the first embodiment of the present invention. FIG. 4 is a diagram showing an example of a pixel array of a CCD in a conventional endoscope connectable to an interlace-compatible video processor connected to the endoscope according to the first embodiment of the present invention. FIG. 5 is a diagram showing another example of a CCD pixel array in a conventional endoscope connectable to an interlace-compatible video processor connected to the endoscope of the first embodiment of the present invention. FIG. 6 is a diagram showing a connection relationship between the endoscope according to the first embodiment of the present invention, a conventional endoscope, and an interlace-compatible video processor. FIG. 7 illustrates the effects of intermittent pixel correction and P / I conversion when converting from a Bayer pixel array to a three-plate CCD pixel array in the interlace signal processing unit of the endoscope according to the first embodiment of the present invention. To do. FIG. 8 illustrates the effects of intermittent pixel correction and P / I conversion when converting from a Bayer pixel array to a three-plate CCD pixel array in the interlace signal processing unit of the endoscope according to the first embodiment of the present invention. To do. FIG. 9 illustrates the effects of intermittent pixel correction and P / I conversion when converting from a Bayer pixel array to a three-plate CCD pixel array in the interlace signal processing unit of the endoscope according to the first embodiment of the present invention. To do. FIG. 10 illustrates the operation of intermittent pixel correction and P / I conversion when the interlace signal processing unit in the endoscope according to the first embodiment of the present invention converts from a Bayer pixel array to a two-plate CCD pixel array. Figure. FIG. 11 is a diagram illustrating a connection relationship between the endoscope, the interlace-compatible video processor, and the progressive-compatible video processor according to the first embodiment of the present invention. FIG. 12 is a diagram showing a configuration when the endoscope according to the first embodiment of the present invention is connected to an interlace-compatible video processor. FIG. 13 is a diagram showing a configuration when the endoscope according to the first embodiment of the present invention is connected to a progressive video processor. FIG. 14 is a flowchart showing an operation of signal processing selection processing in the endoscope according to the first embodiment of the present invention. FIG. 15 is a diagram showing a configuration when an endoscope according to a second embodiment of the present invention is connected to an interlace-compatible video processor. FIG. 16 is a diagram showing a configuration when an endoscope according to a second embodiment of the present invention is connected to a progressive video processor. FIG. 17 is a flowchart showing an operation of signal processing selection processing in the endoscope according to the second embodiment of the present invention. FIG. 18 is a diagram showing a configuration when an endoscope according to a third embodiment of the present invention is connected to an interlace-compatible video processor. FIG. 19 is a diagram showing a configuration when an endoscope according to a third embodiment of the present invention is connected to a progressive video processor. FIG. 20 is a diagram showing a configuration when an endoscope according to a fourth embodiment of the present invention is connected to an interlace-compatible video processor. FIG. 21 is a diagram showing a configuration when an endoscope according to a fourth embodiment of the present invention is connected to a progressive video processor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
As shown in FIG. 1, an endoscope 1 according to a first embodiment of the present invention is provided at the distal end of an insertion portion to be inserted into a subject, picks up an optical image of the subject, and performs a predetermined digital imaging signal To the CMOS image sensor 11 (hereinafter referred to as the CMOS sensor 11), the cable 40 connected to the CMOS sensor 11 for transmitting the digital imaging signal, and the video processor 3 as a signal processing device for performing predetermined video signal processing. And a connector unit 20 to be connected.

The CMOS sensor 11 receives a clock and synchronization signals HD and VD generated by a video processor 3 to be described later, and generates a pulse for processing various signals, and an optical image of the subject. A predetermined analog imaging signal is generated and the imaging unit 12 (PD 12) having a primary color filter in a Bayer array, and a predetermined signal processing is performed on the imaging unit 12 and the digital imaging signal is converted and output A And an AFE circuit 13 including a / D conversion unit, and a P / S circuit 14 that performs parallel / serial conversion on the digital imaging signal from the AFE circuit 13 and outputs the converted signal to the subsequent stage.

In the present embodiment, the CMOS sensor 11 is an image sensor having R (red), G (green), and B (blue) Bayer filters, and scans and outputs an image pickup signal by a progressive method. It has become.

The imaging unit 12 is provided on the plurality of pixels, a pixel unit including a plurality of pixels that captures an optical image of a subject based on a predetermined pulse from the timing generator 15 and generates a predetermined analog imaging signal. A primary color filter (hereinafter referred to as a Bayer filter) having a Bayer arrangement.

The AFE circuit 13 performs A / D conversion on the CDS circuit that performs a predetermined correlated double sampling process on the analog imaging signal from the imaging unit 12 and the analog imaging signal that has been subjected to the correlated double sampling process. And an output A / D conversion circuit.

The cable 40 transmits a predetermined clock and the synchronization signals HD and VD from the video processor 3 to the CMOS sensor 11, and the digital image signal of the serial signal converted in parallel / serial in the P / S circuit 14 in the subsequent stage. To transmit.

In the present embodiment, a circuit for performing predetermined signal processing on the digital imaging signal is configured in the connector unit 20 by an FPGA (hereinafter referred to as FPGA 21).

The FPGA 21 receives the clock and the synchronization signals HD and VD generated in the video processor 3 and outputs them to the timing generator 15 in the CMOS sensor 11 and generates predetermined processing pulses in each circuit in the FPGA 21. A timing generator 22, an S / P conversion circuit 23 for serial / parallel conversion of the digital imaging signal of the serial signal output from the CMOS sensor 11, and an interlace signal processing unit 24 connected to the S / P conversion circuit 23; The progressive signal processing unit 25 is also connected to the S / P conversion circuit 23.

Returning to FIG. 1, the FPGA 21 further includes a signal path switching unit 26 that switches output signal paths between the interlace signal processing unit 24 and the progressive signal processing unit 25, and an output signal from the signal path switching unit 26. P / S circuit 27 that performs parallel / serial conversion and outputs the signal to the processor, and a processor that switches the signal path in the signal path switching unit 26 according to the type (ID) of the processor connected to the endoscope 1 And a detection circuit 28.

Here, a video processor to which the endoscope 1 of the present embodiment is connected will be described.

As a video processor to which the endoscope 1 of the present embodiment is connected, a processor (interlace compatible video) corresponding to an endoscope (interlace scanning type endoscope) that scans and outputs an image pickup signal from a CCD sensor by an interlace method. Processor).

Here, the interlace scanning endoscope described above adopts a so-called three-plate type or two-plate type CCD sensor as an image sensor. As an endoscope that employs this interlaced three-plate type or two-plate type CCD sensor, for example, a three-plate type sensor having R, G, and B filters in each sensor as shown in FIG. An endoscope having a two-plate sensor provided with R / B and G filters in each sensor as shown in FIG. 5 is known.

In other words, the video processor assumed to be connected to the endoscope 1 (progressive scanning type endoscope having the CMOS sensor 11) of the present embodiment employs the above-described CCD 111 as shown in FIG. This is an interlace-compatible video processor 3 corresponding to an endoscope (interlace scanning type endoscope) 101.

FIG. 1 shows a state in which the video processor 3 (interlace-compatible video processor) is connected to the endoscope 1 of the present embodiment.

As shown in FIG. 1, the video processor 3 receives a clock synchronization signal generation circuit 31 that generates a predetermined clock and synchronization signals HD and VD, and a serial signal from the P / S circuit 27 in the connected endoscope 1. An S / P conversion circuit 32 that performs serial / parallel conversion and a parallel signal (the signal is an interlace signal) from the S / P conversion circuit 32 are input, and predetermined image processing is performed. An interlaced image processing circuit 33 that outputs to an external monitor and a processor ID information unit 34 for transmitting the ID information of the video processor 3 to the processor detection circuit 28 in the endoscope 1 are provided.

The processor ID information unit 34 may transmit predetermined ID information to the processor detection circuit 28 under the control of a CPU (not shown) included in the video processor 3, or the endoscope 1 may be a video. A known means for informing the endoscope 1 of the type (corresponding to ID) of the video processor 3 by means of an electrical or mechanical determination means when connected to the processor 3 may be adopted.

Here, as described above, since the video processor 3 performs image processing on an endoscope employing an interlaced three-plate or two-plate CCD sensor, the interlaced image processing circuit in the video processor 3 is used. Reference numeral 33 denotes a known function for processing interlaced video signals from these three-plate or two-plate CCD sensors.

On the other hand, as described above, the endoscope 1 according to the present embodiment employs an image sensor including an RGB Bayer color filter as the CMOS sensor 11 and scans an imaging signal by a progressive method. It is designed to output.

Here, a Bayer pixel array of the CMOS sensor 11 in the endoscope 1 of the present embodiment is shown in FIG.

As described above, the endoscope according to the present invention (progressive scanning type endoscope) includes a Bayer array filter and employs an image sensor that reads out and outputs an image signal by progressive scanning. Even if an image signal as it is, that is, an image signal based on a progressive signal is transmitted to the above-described interlace-compatible video processor without using the configuration, appropriate image processing cannot be performed in the interlace-compatible video processor.

In view of such circumstances, the present invention is a progressive scanning type endoscope, and even when connected to an interlace-compatible video processor, specially devised interlace signal processing so that proper image signal processing can be performed in the processor. A portion 24 is provided.

Next, the interlace signal processing unit 24 and the progressive signal processing unit 25 will be described.

FIG. 2 is a diagram illustrating a configuration of an interlace signal processing unit in the endoscope according to the first embodiment of the present invention.

As shown in FIG. 2, the interlace signal processing unit 24 is a video signal of the S / P conversion circuit 23 obtained by serial / parallel conversion of the serial signal from the P / S circuit 14 in the CMOS sensor 11 (in this state, a progressive signal). ) To perform predetermined pixel correction, a progressive / interlace conversion unit 52 that converts the progressive signal corrected by the intermittent pixel correction unit 51 into an interlace signal, and processing in the video processor 3 And a format conversion unit 53 that performs format conversion of a predetermined video signal in accordance with the form.

The conversion processing in the format conversion unit 53 is, for example, processing such as output rate, synchronization signal superposition, and the like. For interlace output that is output through the control unit 51, progressive / interlace conversion unit 52, and format conversion unit 53. The video signal is in a state suitable for image processing in the interlaced image processing circuit 33 in the video processor 3.

Next, pixel correction in the intermittent pixel correction unit 51 and progressive / interlace conversion (P / I conversion) in the progressive / interlace conversion unit 52 will be described.

<Conversion from Bayer pixel array to 3-plate CCD pixel array>
First, an example in which the interlaced image processing circuit 33 in the video processor 3 performs image processing corresponding to a three-plate CCD will be described with reference to FIGS.

7 to 9 show the effects of intermittent pixel correction and P / I conversion in the case of converting from a Bayer pixel array to a three-plate CCD pixel array in the interlace signal processing unit in the endoscope of the first embodiment. It is a figure explaining.

Further, the left side view of FIG. 7 shows a state of intermittent pixel correction relating to G (green) pixels in the Bayer pixel array, and the right side view of FIG. 7 shows progressive correction of the G (green) pixel group after pixel correction. A state in which interlace conversion (P / I conversion) is performed is shown.

Similarly, the left side view of FIG. 8 shows a state of intermittent pixel correction related to the B (blue) pixel in the Bayer pixel array, and the right side view of FIG. 8 shows the pixel corrected B (blue) pixel group. Is shown as progressive interlace conversion (P / I conversion).

Similarly, the left diagram of FIG. 9 shows the state of intermittent pixel correction related to the R (red) pixel in the Bayer pixel array, and the right diagram of FIG. 9 shows the pixel corrected R (red) pixel. A state in which a group is subjected to progressive interlace conversion (P / I conversion) is shown.

As shown in FIG. 7, FIG. 8, and FIG. 9, the intermittent pixel correction unit 51 corrects the intermittent pixels with the surrounding pixel information for each R, G, B in the Bayer pixel array.

Here, when the pixel is G (green), as shown in FIG. 7, it is always corrected by the addition average value of the four adjacent pixels. On the other hand, when the pixel is B (blue) or R (red), two-stage correction is performed as shown in FIGS.

That is, first, intermittent pixels whose adjacent four pixels are sensor reading data are corrected by the addition average value of the four pixels (see FIGS. 8 and 9), and then the intermittent pixels whose adjacent two pixels are sensor reading data are corrected. Then, the correction is performed with the average value of these two pixels and two adjacent intermittent pixels corrected in advance (see FIGS. 8 and 9). Thus, B (blue) and R (red) can be corrected with higher accuracy than correction from two adjacent upper and lower pixels.

Next, the progressive / interlace conversion unit 52 performs, for each color in which the intermittent pixel is corrected by the intermittent pixel correction unit 51, the left side view of FIG. 7 → the right side view of FIG. 7, and the left side view of FIG. As shown in the left side diagram of FIG. 9 and the right side of FIG. 9, the progressive signal is converted to the interlaced signal by line addition.

Specifically, among the odd frame signals of the progressive signal, the “2 × n−1” line (n is an integer of 1 or more, the same applies hereinafter) and the “2 × n” line are added to the interlace 1st field. “2 × n−1” line signal is used, and “2 × n” line and “2 × (n + 1) -1” line are added to the signal of even frame, and “2 × n” of 2nd field of interlace is added. Line signal. Note that such line addition contributes to improvement in sensitivity.

<Conversion from Bayer pixel array to 2-plate CCD pixel array>
Next, an example in which the interlaced image processing circuit 33 in the video processor 3 performs image processing corresponding to a two-plate CCD will be described with reference to FIG.

FIG. 10 is a diagram for explaining the operation of intermittent pixel correction and P / I conversion when converting from a Bayer pixel array to a two-plate CCD pixel array in the interlace signal processing unit in the endoscope of the first embodiment. The left side view of FIG. 10 shows the state of intermittent pixel correction related to the B (blue) and R (red) pixels in the Bayer pixel array, and the right side view of FIG. A state in which progressive interlace conversion (P / I conversion) is performed on a pixel group of blue and red (red) is shown.

When converting from this Bayer pixel array to a two-plate CCD pixel array, if the pixel is G (green), as shown in FIG. Correction is performed using an average value of four adjacent pixels.

On the other hand, when the pixels are B (blue) and R (red), correction is performed with two upper and lower pixels as shown in FIG.

Next, for the G (green) pixel, the progressive interlace conversion unit 52 replaces the G (green) pixel whose intermittent pixel has been corrected by the intermittent pixel correction unit 51 with the left side diagram of FIG. 7, the progressive signal is converted into the interlace signal by line addition.

On the other hand, B (blue) and R (red) are also converted from a progressive signal to an interlace signal by line addition, as shown in the left diagram of FIG. 10 → the right diagram of FIG.

As described above, according to the endoscope 1 of the present embodiment, when the interlace signal processing unit 24 having the above-described configuration is provided, the progressive scan type endoscope is connected to the interlace-compatible video processor. However, appropriate image signal processing can be performed in the processor.

Returning to FIG. 1, in this embodiment, the progressive signal processing unit 25 passes through the imaging signal (progressive signal) scanned by the progressive method as it is and sends it to the subsequent signal path switching unit 26. ing.

Incidentally, the endoscope 1 of the present embodiment can be connected to a progressive video processor capable of processing an original progressive signal in addition to the video processor 3 which is an interlace compatible video processor.

FIG. 11 is a diagram showing a connection relationship between the endoscope, the interlace-compatible video processor, and the progressive-compatible video processor of the present embodiment.

As shown in FIG. 11, the video processor 3A includes a CMOS sensor 11 and includes a signal processing circuit (not shown) corresponding to the endoscope 1 that scans and outputs an imaging signal by a progressive method.

Next, the operation when the endoscope 1 of the present embodiment is connected to the interlace-compatible video processor 3 or the progressive-compatible video processor 3A will be described.

FIG. 12 is a diagram showing a configuration when the endoscope according to the first embodiment of the present invention is connected to an interlace-compatible video processor, and FIG. 13 is an endoscope according to the first embodiment of the present invention. It is a figure which shows the structure at the time of being connected to the progressive corresponding | compatible video processor. Furthermore, FIG. 14 is a flowchart showing the operation of the signal processing selection process in the endoscope according to the first embodiment of the present invention.

As shown in FIG. 14, when the endoscope 1 is first connected to a predetermined video processor, the processor detection circuit 28 obtains predetermined ID information from the processor ID information section 34 in the connected video processor (step S1). .

Thereafter, the processor detection circuit 28 determines whether the connected processor is the interlace-compatible video processor 3 or the progressive-compatible video processor 3A based on the obtained ID information (step S2).

If the connected processor is the interlace compatible video processor 3, the processor detection circuit 28 performs interlace signal processing (step S3).

That is, in step S3, the processor detection circuit 28 controls the signal path switching unit 26 so that the imaging signal output from the P / S circuit 27 passes through the interlace signal processing unit 24. Switching (see FIG. 12).

Here, as described above, when the imaging signal output from the P / S circuit 27 is selected so as to pass through the interlace signal processing unit 24, the P / S circuit 27 receives the signal from the video processor 3. An interlace video signal suitable for the interlace image processing circuit 33 is transmitted.

Thus, in the interlace image processing circuit 33 to which the interlace video signal is input (even if the progressive scan system endoscope 1 is connected), the video processor 3 performs normal interlace image processing. Can do.

On the other hand, when the connected processor is the progressive compatible video processor 3A, the processor detection circuit 28 performs progressive signal processing (step S4).

That is, in step S 4, the processor detection circuit 28 controls the signal path switching unit 26 to change the signal path so that the imaging signal output from the P / S circuit 27 passes through the progressive signal processing unit 25. Switching (see FIG. 13).

Here, as described above, in the present embodiment, the progressive signal processing unit 25 passes through the imaging signal as it is and sends it to the subsequent signal path switching unit 26. Therefore, the progressive video processor Even in 3A, appropriate signal processing can be performed.

As described above, according to the first embodiment, even an endoscope that scans an imaging signal from an imaging unit by a progressive method can be adapted to a video processor equipped only with an interlace signal processing circuit. It is possible to provide an endoscope.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

FIG. 15 is a diagram showing a configuration when an endoscope according to the second embodiment of the present invention is connected to an interlace-compatible video processor, and FIG. 16 is an endoscope according to the second embodiment of the present invention. It is a figure which shows the structure at the time of being connected to the progressive corresponding | compatible video processor. Further, FIG. 17 is a flowchart showing the operation of the signal processing selection process in the endoscope according to the second embodiment of the present invention.

The basic configuration of the endoscope of the second embodiment is the same as that of the first embodiment, and only a part of the configuration within the FPGA 21 in the connector unit 20 is different. Accordingly, only the differences from the first embodiment will be described here, and descriptions of common parts will be omitted.

In the first embodiment described above, the FPGA 21 includes the processor detection circuit 28 that switches the signal path in the signal path switching unit 26 according to the type of the processor connected to the endoscope 1 (see FIG. 1). In the second embodiment, as shown in FIGS. 15 and 16, a switching instruction unit 28 a that sends a switching instruction signal for switching the signal path in the signal path switching unit 26 is provided instead of the processor detection circuit 28. It is characterized by that.

The switching instruction unit 28a sends the switching instruction signal to the signal path switching unit 26 by an operation (not shown) or the like (for example, setting by a user). This switching instruction signal is an instruction signal for switching between a first signal path through which the digital imaging signal passes through the interlace signal processing section 24 and a second signal path through which the progressive signal processing section 25 passes. It is.

In the second embodiment, the signal path switching unit 26 switches between the first signal path and the second signal path in response to a switching instruction signal from the switching instruction unit 28a. .

As described above, in the second embodiment, the type of processor connected to the endoscope 1 (interlace-compatible video processor 3B; see FIG. 15) or progressive-compatible video processor 3C; see FIG. In 1, the above-described signal path switching can be performed without detection.

Next, the operation when the endoscope 1 of the present embodiment is connected to the interlace compatible video processor 3B or the progressive compatible video processor 3C will be described with reference to FIG.

As shown in FIG. 17, when the switching instruction signal is sent from the switching instruction unit 28a in the endoscope 1 (step S11), the switching instruction in the switching instruction unit 28a is the interlace-compatible video processor 3B, or Based on whether the video processor is a progressive video processor 3C (step S12), the signal path switching unit 26 switches between the first signal path and the second signal path.

That is, when the switching instruction indicates the interlace compatible video processor 3B in step S12, the first signal path through the interlace signal processing unit 24 is selected (step S13).

On the other hand, when the switching instruction indicates the progressive-compatible video processor 3C, the second signal path through the progressive signal processing unit 25 is selected (step S14).

As described above, according to the second embodiment, even in an endoscope that scans an image pickup signal from an image pickup unit by a progressive method, an interlace signal processing circuit is detected without detecting the type of a connected processor. It is possible to provide an endoscope that can be adapted to a video processor equipped only with a video processor.

In the above-described embodiment, the FPGA 21 is disposed in the connector unit 20. However, the present invention is not limited thereto, and may be disposed in an operation unit or the like in the endoscope 1.

In the present embodiment, a CMOS image sensor is assumed as the imaging element of the endoscope 1, but is not limited to a CMOS image sensor, and a solid-state imaging element capable of outputting an imaging signal from an imaging unit as a progressive video signal. The present invention can also be applied to an endoscope that employs.

(Third embodiment)
Next, a third embodiment of the present invention will be described.

FIG. 18 is a diagram showing a configuration when an endoscope according to the third embodiment of the present invention is connected to an interlace-compatible video processor, and FIG. 19 is an endoscope according to the third embodiment of the present invention. It is a figure which shows the structure at the time of being connected to the progressive corresponding | compatible video processor.

The basic configuration of the endoscope of the third embodiment is the same as that of the first and second embodiments, and only a part of the configuration within the FPGA 21 in the connector unit 20 is different. is there. Accordingly, only the differences from the first and second embodiments will be described here, and descriptions of common parts will be omitted.

In the second embodiment described above, the FPGA 21 includes a switching instruction unit 28a that transmits a switching instruction signal for switching a signal path in the signal path switching unit 26.

As shown in FIGS. 18 and 19, also in the endoscope of the third embodiment, the FPGA 21 includes the switching instruction unit 28a.

In the third embodiment, the interlace-compatible video processor 3B and the progressive-compatible video processor 3C identify the type of endoscope to be connected, and communicate the identification information to the endoscope. Have

On the other hand, when the endoscope according to the third embodiment is connected to the FPGA 21 with the interlace-compatible video processor 3B or the progressive-compatible video processor 3C, the endoscope is connected to the endoscope from the control communication unit 35 described above. A control communication unit 29 for receiving identification information related to the mirror is formed.

The control communication unit 29 is connected to the switching instruction unit 28a, and transmits the received identification information to the switching instruction unit 28a.

In the third embodiment, the switching instruction unit 28 a sends a switching instruction signal to the signal path switching unit 26 according to the identification information transmitted from the control communication unit 29.

Also in the third embodiment, the switching instruction signal sent from the switching instruction unit 28a includes the first signal path through which the digital imaging signal passes through the interlace signal processing unit 24 and the progressive signal processing unit 25. This is an instruction signal for switching the second signal path passing through.

The signal path switching unit 26 switches between the first signal path and the second signal path in response to a switching instruction signal from the switching instruction unit 28a.

Next, the operation when the endoscope of the third embodiment is connected to the interlace compatible video processor 3B or the progressive compatible video processor 3C will be described.

When the endoscope 1 is connected to the interlace-compatible video processor 3B or the progressive-compatible video processor 3C shown in FIGS. 18 and 19, the video processor 3B or the video processor 3C includes the control communication unit 35, the control communication unit 29, The type of the connected endoscope 1 is detected and identified by the above communication or by a predetermined detection method.

Thereafter, the video processor 3B or the video processor 3C transmits identification information based on the above-described identification result from the control communication unit 35 on the video processor side to the control communication unit 29 on the endoscope side.

The control communication unit 29 transmits the received identification information to the switching instruction unit 28a, and a predetermined switching instruction signal is sent to the signal path switching unit 26 from the switching instruction unit 28a that has received the identification information.

Thereafter, the signal path switching unit 26 switches between the first signal path and the second signal path in accordance with a switching instruction signal from the switching instruction unit 28a.

That is, when the switching instruction indicates the interlace-compatible video processor 3B, the first signal path via the interlace signal processor 24 is selected (see FIG. 18), while the switching instruction indicates the progressive-compatible video processor 3C. Is selected, the second signal path through the progressive signal processing unit 25 is selected (see FIG. 19).

As described above, according to the third embodiment, even an endoscope that scans an imaging signal from an imaging unit by a progressive method can be adapted to a video processor equipped only with an interlace signal processing circuit. It is possible to provide an endoscope.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.

FIG. 20 is a diagram showing a configuration when an endoscope according to the fourth embodiment of the present invention is connected to an interlace-compatible video processor, and FIG. 21 shows an endoscope according to the 34th embodiment of the present invention. It is a figure which shows the structure at the time of being connected to the progressive corresponding | compatible video processor.

The basic configuration of the endoscope of the fourth embodiment is the same as that of the first and second embodiments, and only a part of the configuration within the FPGA 21 in the connector unit 20 is different. is there. Accordingly, only the differences from the first and second embodiments will be described here, and descriptions of common parts will be omitted.

20 and 21, also in the endoscope of the fourth embodiment, the FPGA 21 includes the switching instruction unit 28a.

In the fourth embodiment, the interlace-compatible video processor 3B and the progressive-compatible video processor 3C include a scope detection unit 71 that receives the scope ID information from the connected endoscope and detects the type of the scope.

On the other hand, in the endoscope 1 according to the fourth embodiment, a scope ID information unit 61 for storing ID information unique to the endoscope is formed in the FPGA 21, and a signal for detecting the type of the connected video processor is detected. A specification detector 62 is formed.

When the interlace-compatible video processor 3B or the progressive-compatible video processor 3C is connected to the endoscope 1, the signal specification detection unit 62 outputs an image pickup element (output from the clock synchronization signal generation unit 31 in these video processors ( In this embodiment, a clock signal for driving the CMOS sensor 11) and a synchronization signal (HD, VD) are received, and the type of the video processor is detected from the specification of the signal.

The signal specification detection unit 62 is connected to the switching instruction unit 28a, and transmits the detected video processor type information (identification information) to the switching instruction unit 28a.

In the fourth embodiment, the switching instruction unit 28a sends a switching instruction signal to the signal path switching unit 26 in accordance with the identification information transmitted from the signal specification detection unit 62.

Also in the fourth embodiment, similarly to the above, the switching instruction signal transmitted from the switching instruction unit 28a includes the first signal path through which the digital imaging signal passes through the interlace signal processing unit 24, and An instruction signal for switching between the second signal path passing through the progressive signal processing unit 25, and the signal path switching unit 26 is configured to change the first signal path according to the switching instruction signal from the switching instruction unit 28a. A signal path and the second signal path are switched.

Next, the operation when the endoscope of the fourth embodiment is connected to the interlace compatible video processor 3B or the progressive compatible video processor 3C will be described.

When the endoscope 1 is connected to the interlace-compatible video processor 3B or the progressive-compatible video processor 3C shown in FIGS. 20 and 21, the video processor 3B or the video processor 3C is first connected in the scope detection unit 71. The type of the endoscope 1 is detected based on the ID information stored in the scope ID information unit 61 in the endoscope 1.

Thereafter, the video processor 3B or the video processor 3C determines the imaging element in the endoscope 1 (the CMOS sensor 11 in the endoscope 1 of the present embodiment) according to the ID information of the endoscope 1 detected by the scope detection unit 71. ) Is output from the clock synchronization signal generation unit 31 (clock signal, synchronization signal HD, VD).

On the other hand, the endoscope 1 receives the signal (clock signal, synchronization signal HD, VD) output from the clock synchronization signal generation unit 31 in the signal specification detection unit 62 formed in the FPGA 21, and The type of video processor is detected from the specification.

Thereafter, the signal specification detection unit 62 transmits the detected video processor type information (identification information) to the switching instruction unit 28 a, and the switching instruction unit 28 a responds to the identification information transmitted from the signal specification detection unit 62. A switching instruction signal is sent to the signal path switching unit 26.

Also in the fourth embodiment, similarly to the above, the signal path switching unit 26 switches between the first signal path and the second signal path in response to the switching instruction signal from the switching instruction unit 28a. Switch.

That is, when the switching instruction indicates the interlace-compatible video processor 3B, the first signal path via the interlace signal processing unit 24 is selected (see FIG. 20), while the switching instruction indicates the progressive-compatible video processor 3C. Is selected, the second signal path through the progressive signal processor 25 is selected (see FIG. 21).

As described above, according to the fourth embodiment, even an endoscope that scans an imaging signal from an imaging unit by a progressive method can be adapted to a video processor equipped only with an interlace signal processing circuit. It is possible to provide an endoscope.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various aspects of the invention can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

This application is filed on the basis of the priority claim of Japanese Patent Application No. 2014-265540 filed in Japan on December 26, 2014, and the above disclosure is disclosed in the present specification, claims, It shall be cited in the drawing.

Claims

A pixel signal generated by a plurality of pixels having a pixel portion composed of a plurality of pixels that photoelectrically convert light to generate a pixel signal and a Bayer array primary color filter provided on the pixels. An imaging unit for generating a configured imaging signal;
A readout unit that reads out the imaging signal from the imaging unit and outputs it as a progressive video signal;
A conversion unit that converts the processing format of the video signal read by the reading unit into a processing format that can be processed by a separate signal processing device connected to a subsequent stage;
An output unit that outputs the video signal whose processing format has been converted by the conversion unit to the signal processing device;
An endoscope comprising:
The conversion unit converts the progressive video signal read by the reading unit into an interlaced processing format that can be processed by a separate signal processing device connected to a subsequent stage. The endoscope according to Item 1.
The endoscope according to claim 2, wherein the conversion unit includes an intermittent pixel correction unit that performs predetermined pixel correction on the progressive video signal read by the reading unit.
The conversion unit includes a progressive interlace conversion unit that converts the progressive video signal into an interlace video signal by line addition for each color in which the intermittent pixel is corrected by the intermittent pixel correction unit, and outputs the interlace video signal. The endoscope according to claim 3.
The conversion unit, for the interlaced video signal output from the progressive interlace conversion unit, a predetermined video in accordance with a processing form in a separate signal processing device connected to a subsequent stage of the conversion unit The endoscope according to claim 4, further comprising a format conversion unit that performs signal format conversion.
The endoscope according to claim 3, wherein the intermittent pixel correction unit corrects intermittent pixels with peripheral pixel information for each of RGB filters in the primary color filter of the Bayer array in the imaging unit.
As a separate signal processing apparatus connected to the subsequent stage, a first video processor including an interlaced image processing unit capable of processing only an interlaced video signal and a second video capable of processing a progressive video signal A video signal output unit capable of connecting a processor;
A first signal path for converting the progressive video signal read by the reading unit into an interlace video signal via the conversion unit, and the progressive video signal via the conversion unit. A signal path switching unit that switches between the second signal path that is output in the state of the progressive video signal without the
The endoscope according to claim 2, further comprising:
The image processing apparatus further includes an identification unit capable of identifying whether the separate signal processing device connected to the video signal output unit is the first video processor or the second video processor. ,
The endoscope according to claim 7, wherein the signal path switching unit switches between the first signal path and the second signal path according to an identification result of the identification unit.
A switching instruction unit that outputs a switching instruction signal for switching between the first signal path and the second signal path;
The signal path switching unit switches between the first signal path and the second signal path in accordance with the switching instruction signal output from the switching instruction unit. Endoscope.