WO2016101485A1

WO2016101485A1 - Method and device for writing tcam entries

Info

Publication number: WO2016101485A1
Application number: PCT/CN2015/078209
Authority: WO
Inventors: 姜海明; 朱延灵
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-12-26
Filing date: 2015-05-04
Publication date: 2016-06-30
Also published as: CN105786733A; CN105786733B

Abstract

A method and device for writing TCAM entries. The method comprises: writing a predetermined data block into a first in first out (FIFO) buffer of a TCAM interface by means of direct memory access (DMA), the predetermined data block comprising multiple TCAM entries; and writing the TCAM entries in the FIFO buffer into a TCAM.

Description

Method and device for writing TCAM entries

Technical field

This paper relates to the field of communications, and in particular to a method and apparatus for writing TCAM entries.

Background technique

Today's network development is amazing, network traffic growth and the emergence of new services require network equipment to have wire-speed and flexible processing capabilities. Currently, the network chip includes two types: Application Specific Integrated Circuit (ASIC) and Network Processor (NP). With its high-speed processing and flexible programmability, network processors have become an effective solution for data processing in today's networks. There are many different memories in the network processor, such as Static Random Access Memory (SRAM), Ternary Content Addressable Memory (TCAM), Synchronous Dynamic Random Memory (Synchronous Dynamic). Random Access Memory (SDRAM), etc., these memories store various business items, such as port tables, MAC tables, routing tables, and so on.

In the related art, the TCAM update method is a single update, and the rate is very slow. For example, an access control list (ACL) is used to configure an ACL to contain 2K entries. 2K TCAM entries are sent one by one, and each is sent to the TCAM. The disadvantage of this method is that each TCAM entry is written to the TCAM hardware and requires full CPU intervention. The hardware is written byte by byte under the control of the CPU, and the completion of the write hardware requires the CPU to know that the update is completed by hardware interrupt or CPU polling, so that one can start writing one. If the user configures the ACL to include 30K entries, it takes a long time to write all the TCAMs, which may reach ten or even tens of seconds.

Summary of the invention

The present invention provides a method and apparatus for writing a TCAM entry to solve the problem that the TCAM entry is written to the TCAM one by one in the related art, and the write rate is low.

A method of writing a TCAM entry, comprising: writing a predetermined data block to a first in first out FIFO buffer of a TCAM interface by direct memory access DMA, wherein the predetermined data block includes a plurality of TCAM entries; The plurality of TCAM entries are written to the TCAM.

Optionally, before writing the predetermined data block to the FIFO buffer of the TCAM interface by direct memory access DMA, the method further comprises: acquiring the predetermined data block.

Optionally, acquiring the predetermined data block comprises: converting, by the central processing unit, the TCAM data into a TCAM entry; writing the converted TCAM entry into the buffer space to obtain the predetermined data block.

Optionally, writing the converted TCAM entry into the buffer space to obtain the predetermined data block comprises: determining whether the written TCAM entry is the last TCAM entry converted according to the TCAM data; If not, the next TCAM entry obtained by the conversion is continuously written into the buffer space; if the determination result is yes, the formed by the plurality of TCAM entries written is obtained from the cache space. The predetermined data block is described.

Optionally, writing the predetermined data block to the FIFO buffer of the TCAM interface by using the direct memory access DMA includes: determining the predetermined data block according to the physical address of the predetermined data block, the FIFO cache address, and the data block size. Write to the FIFO buffer.

An apparatus for writing a TCAM entry, comprising: a first write module configured to: write a predetermined data block into a first in first out FIFO buffer of a TCAM interface by direct memory access DMA, wherein the predetermined data block includes a TCAM entry; a second write module configured to: write the plurality of TCAM entries in the FIFO buffer to the TCAM.

Optionally, the device further includes: an obtaining module, configured to: acquire the predetermined data block.

Optionally, the obtaining module includes: a converting unit, configured to: the central processing unit CPU converts the TCAM data into a TCAM entry; and the writing unit is configured to: write the converted TCAM entry into the buffer space, to obtain the Predetermine the data block.

Optionally, the writing unit includes: determining a secondary unit, configured to: determine whether the written TCAM entry is the last TCAM entry converted according to the TCAM data; and the first write secondary unit is set to: If the result of the determination is no, the next TCAM entry obtained by the conversion is continuously written into the buffer space; the second write secondary unit is set as: In the case of the cache space, the predetermined data block formed by the plurality of TCAM entries written is acquired.

Optionally, the first writing module is configured to: write the predetermined data block into the FIFO buffer according to a physical address, a FIFO buffer address, and a data block size of the predetermined data block.

A FIFO buffer for writing a predetermined block of data to a TCAM interface by direct memory access DMA, wherein the predetermined block of data includes a plurality of TCAM entries; writing the plurality of TCAM entries in the FIFO buffer The TCAM solves the problem in the related art that when the TCAM entries are written one by one, the CPU needs to be fully intervened, the write rate is low, and the CPU resource overhead is large, and the TCAM entries are written in batches, and the TCAM entries are written. effectiveness.

BRIEF abstract

1 is a flow chart of a method of writing a TCAM entry in accordance with an embodiment of the present invention;

2 is a flow chart of another method of writing a TCAM entry in accordance with an embodiment of the present invention;

3 is a block diagram showing the structure of a device for writing a TCAM entry according to an embodiment of the present invention;

4 is a block diagram showing another structure of a device for writing a TCAM entry according to an embodiment of the present invention;

FIG. 5 is a structural block diagram of an acquisition module 40 for writing a TCAM entry device according to an embodiment of the present invention;

6 is a block diagram showing the structure of a write unit 402 for writing a TCAM entry device according to an embodiment of the present invention;

7 is a schematic diagram of a connection relationship of a CPU, an NP, a TCAM, and a DMA for writing a TCAM entry according to an embodiment of the present invention;

8 is a flow chart of a method of writing a TCAM entry in accordance with a preferred embodiment of the present invention.

Embodiments of the invention

Embodiments of the present invention will be described hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the embodiments and the features in the embodiments may be combined with each other.

In the embodiment of the present invention, a method for writing a TCAM entry is provided. FIG. 1 is a flowchart according to an embodiment of the present invention. As shown in FIG. 1, the process may include the following steps:

Step S100, writing a predetermined data block to the FIFO buffer of the TCAM interface by direct memory access DMA, wherein the predetermined data block includes a plurality of TCAM entries;

Step S102, writing the plurality of TCAM entries in the FIFO buffer to the TCAM. The network chip TCAM interface usually has a FIFO buffer inside, and writes TCAM entries in the FIFO buffer to the TCAM through the physical bus between the network chip and the external TCAM.

In this embodiment, a plurality of TCAM entries cached by the DMA are used to write the TCAM adaptation module FIFO buffer of the network chip at one time, and the DMA controller can quickly access the internal module of the network chip and the characteristics of less CPU resource overhead, and the related technology is solved. In the case of writing TCAM entries one by one, the CPU needs full intervention, the write rate is low, and the CPU resource overhead is large, and the TCAM entries are written in batches, and the efficiency of writing TCAM entries is improved.

A method for writing a TCAM entry is also provided in the embodiment of the present invention. FIG. 2 is a flowchart according to an embodiment of the present invention. As shown in FIG. 2, the process may include the following steps:

Step S200, acquiring a predetermined data block;

Step S202, writing a predetermined data block to the FIFO buffer of the TCAM interface by direct memory access DMA, wherein the predetermined data block includes a plurality of TCAM entries;

Step S204, writing the plurality of TCAM entries in the FIFO buffer to the TCAM.

Optionally, obtaining the predetermined data block may include: converting, by the central processing unit, the TCAM data into a TCAM entry; writing the converted TCAM entry into a buffer space (ie, a memory) to obtain the predetermined data block.

The CPU control layer converts the service data related to the upper layer service (for example, ACL, flow mirroring, and the like) into a TCAM entry according to the TCAM storage format, where the TCAM entry is used for the packet lookup table of the upper layer service traffic forwarding. The converted TCAM entry is written to the cache space. The size of the cache space can be adjusted according to the number of TCAM entries.

Optionally, writing the converted TCAM entry into the buffer space to obtain the predetermined data block may include: determining whether the written TCAM entry is the last TCAM entry converted according to the TCAM data; If the result is no, continue to convert the resulting The next TCAM entry is written to the cache space; if the result of the determination is YES, the predetermined data block formed by the written plurality of TCAM entries is acquired from the cache space.

Currently, the relevant data of each upper layer service message is converted into multiple TCAM entries. The CPU control plane writes multiple TCAM entries one by one to the DMA. In order to save time and improve efficiency, it is necessary to write all the TCAM entries into the memory, and then start the TCAM interface that writes the TCAM entries from the memory to the network chip. FIFO buffer. If the multiple TCAM entries are not all written to the DMA, the CPU control plane will continue to write the remaining TCAM entries to memory until all are written to the memory. The ACL (Access Control List) is used as an example. The user configures an ACL to contain 2000 entries. Up to 2000 TCAM entries are written to the memory. The cache space of the memory stops acquiring multiple TCAM entries of the ACL. 2000 entries have all been written to the DMA cache space.

In the above embodiment or the optional implementation, the writing of the predetermined data block to the FIFO buffer of the TCAM interface by direct memory access DMA may further include: determining, according to the physical address of the predetermined data block, the FIFO cache address, and the data. A block size that writes the predetermined block of data to the FIFO buffer.

After the upper application TCAM entry is written to the memory, the network chip configures the DMA controller to write the TCAM entry from the memory into the FIFO buffer of the TCAM interface of the network chip through the CPU interface of the network chip. The network chip turns on the DMA transfer to write the TCMA entry into the FIFO buffer, needs to specify the physical address of the predetermined data block, the FIFO cache address, and the data block size, writes the predetermined data block to the FIFO buffer, and then writes the data to the TCAM through the physical bus. hardware. In the embodiment, the DMA controller of the network chip is used to write a plurality of TCAM entries in the DMA buffer to the FIFO buffer of the TCAM interface of the network chip in batches, and the DMA controller can quickly access the characteristics of the internal modules of the network chip. TCAM entries can be quickly written to the hardware, increasing the efficiency of writing TCAM entries and reducing CPU usage.

FIG. 3 is a structural block diagram of an apparatus for writing a TCAM entry according to an embodiment of the present invention. As shown in FIG. 3, the apparatus may include:

The first write module 30 is configured to: write a predetermined data block into the FIFO FIFO buffer of the TCAM interface by direct memory access DMA, wherein the predetermined data block includes a plurality of TCAM entries; and the second write module 32 Connected to the first write module 30, set to: FIFO in the buffer The plurality of TCAM entries are written to the TCAM.

FIG. 4 is a structural block diagram of another apparatus for writing a TCAM entry according to an embodiment of the present invention. As shown in FIG. 4, the apparatus may include:

The obtaining module 40 is configured to: acquire the predetermined data block; the first writing module 42 is connected to the obtaining module 40, and is configured to: write the predetermined data block into the first-in first-out FIFO buffer of the TCAM interface by direct memory access DMA The predetermined data block includes a plurality of TCAM entries; the second write module 44 is coupled to the first write module 42 and configured to write the plurality of TCAM entries in the FIFO buffer to the TCAM.

Optionally, as shown in FIG. 5, the obtaining module 40 may further include: a converting unit 401 configured to: convert the TCAM data into a TCAM entry; and the writing unit 402 is connected to the converting unit 401, and is configured to: convert the obtained A TCAM entry is written to the cache space to obtain the predetermined data block.

Optionally, as shown in FIG. 6, the writing unit 402 may further include: a determining sub-unit 4021, configured to: determine whether the written TCAM entry is the last TCAM entry converted according to the TCAM data; the first write The sub-unit 4022 is connected to the judging sub-unit 4021, and is configured to: continue to write the converted next TCAM entry into the buffer space if the determination result is no; the second write sub-unit 4023 is connected to The first write subunit 4022 is configured to: when the determination result is YES, acquire the predetermined data block formed by the written plurality of TCAM entries from the cache space.

In the above embodiment or implementation, the first write module 30 and the first write module 42 may be further configured to: according to the physical address of the predetermined data block, the FIFO cache address, and the data block size. A predetermined data block is written to the FIFO buffer.

Through the device provided by the embodiment of the present invention, a plurality of TCAM entries are written into the buffer space by the CPU, and the network chip writes a plurality of TCAM entries in the memory into the FIFO buffer in the network chip in batches through the DMA controller, and then passes through the physical bus. Writing TCAM entries to the external TCAM solves the problem that the TCAM entries are written to the TCAM one by one, and the write rate is low, which enables batch writing of TCAM entries, improves the efficiency of writing TCAM entries, and reduces CPU consumption.

It should be noted that the first write module 30, the second write module 32, and the first mentioned above The writing module 42 and the second writing module 44, or the functions and functions of the first writing sub-unit 4022 and the second writing sub-unit 4023 are the same or similar, they may be the same module, or may be different. Module.

FIG. 7 is a schematic diagram of a connection relationship of a CPU, an NP, and a TCAM for writing a TCAM entry according to an embodiment of the present invention, and FIG. 7 is as follows:

The central processing unit CPU 70 is connected to the network processor NP through the data bus PCI-E, and is configured to convert the related data of the upper layer service message into a TCAM entry according to the TCAM storage format, and in the DDR3 SDRAM (Double Data Rate 3 Synchronous Dynamic) Random Access Memory (eight times data rate synchronous dynamic random access memory) applies for cache space.

DDR3 SDRAM 72, connected to CPU 70, is set to: cache multiple TCAM entries.

An NP (Network Processer) 74 is connected to the TCAM 76. The NP 74 internally includes a CPU interface 741 and a TCAM interface 742. Among them, the TCAM interface 742 has a first in first out FIFO buffer. The CPU interface 741 has a DMA controller inside, and the NP can access the DDR3 SDRAM 72 through the DMA controller to enable DMA transfer, and the entire block of data can be transmitted without intervention by the CPU. The DMA can support fast access to NP internal modules. The data stored in the DDR3 SDRAM 72 is written to the FIFO buffer. Each transfer requires specifying the physical address of the data source, the address of the destination NP internal block, and the block size, and then turning on DMA transfer, which allows quick access to the NP internal block.

TCAM 76, interconnected with NP 74 via the Interlaken bus.

In the embodiment of the present invention, a method for writing a TCAM entry is provided. FIG. 8 is a flowchart according to an embodiment of the present invention. As shown in FIG. 8, the process includes the following steps:

Step S800, the CPU control plane applies for a cache space;

The CPU control requests a contiguous physical memory for the DDR3 SDRAM to be used as the buffer space. The cache space is used to cache the TCAM entries assembled by the CPU control plane, and can accept the network chip DMA controller or the DMA memory. The size of the cache space is related to the upper layer service. For example, the fourth generation Internet Protocol Version 4 (IPV4) IPV4 ACL, the user configures an ACL instance, up to 32K TCAM entries, and each TCAM entry is wide. The degree is 20 bytes, and the size of the cache space can be defined as 32K*20 bytes.

Step S802, the CPU control plane assembles the TCAM entry;

The CPU control plane converts the service-related data sent by the upper-layer application into the data format of the TCAM write table, that is, the TCAM entry, including the TCAM entry physical address and the write table data, according to the TCAM data format.

Step S804, writing a TCAM entry into the buffer space;

The TCAM entries assembled in step S802 are written one by one into the DMA buffer, that is, the DDR3 SDRAM buffer space requested by the CPU in step S800.

Step S806, determining whether the TCAM entry is the last one;

The CPU thread maintains a global variable N and records the current cache space address. N starts at 0 and corresponds to the Nth entry in the cache. Each time a TCAM entry is written in the cache space, the global variable N=N+1. With the ACL example mentioned above, the 32K entry is the last TCAM entry. In the case where the TCAM entry in the write buffer space is not the last TCAM entry, the process jumps to step S802 to continue assembling the next TCAM entry and buffering it into the N+1th cache address in the cache space.

Step S808, writing a TCAM entry in the cache space to the FIFO buffer;

In the case where the TCAM entry in the write buffer space is the last TCAM entry, it is considered that the TCAM entry in the CPU control plane write cache space has all been written. The network chip turns on DMA transfer, and by configuring the DMA controller, the data is written into the FIFO buffer in the TCAM interface of the NP through the CPU interface of the NP. The CPU interface of the NP usually has a DMA controller, which can perform the whole block data transmission without the intervention of the CPU. The DMA can support fast access to NP internal modules. Each transfer requires specifying the physical address of the data source, the address of the destination NP internal module, and the data block size. The DMA transfer is enabled, which allows quick access to the NP internal modules, including the TCAM interface in the NP and the FIFO buffer in the TCAM interface.

Step S810, writing a TCAM entry in the FIFO buffer to the TCAM.

The NP writes the TCAM entry in the FIFO buffer to the TCAM hardware via the Interlaken bus between the NP and the external TCAM.

Related art TCAM entries are written one by one in an update manner, each time a TCAM entry is transmitted At the same time, it is necessary to participate in controlling the data movement, the CPU resource overhead is large, and the TCAM entry is updated slowly. The method provided by the embodiment of the invention can quickly access the internal module of the network chip and the characteristic of low CPU resource consumption by using the DMA controller, and write the cached plurality of TCAM entries into the TCAM of the NP in batches through the NP controller of the NP. The adapter module FIFO buffer enables fast writing of TCAM entries to the TCAM, reducing CPU usage.

In summary, the embodiment of the present invention provides a novel TCAM batch write table fast update method, which applies a cache space to the memory by the CPU, and caches multiple TCAM entries sent by the upper layer service until the last TCAM entry. After the completion of the delivery, the write operation is triggered; in the case of a small amount of CPU intervention, the network chip can use the DMA controller to write TCAM entries in batches, enabling fast writing of TCAM entries and reducing CPU usage. The method and device for writing TCAM entries provided in this paper have fast TCAM entries and low CPU usage, and have great promotion and application value.

One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.

Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.

The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.

When the device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Industrial applicability

This document uses a FIFO buffer for writing a predetermined data block to a TCAM interface by DMA, wherein the predetermined data block includes a plurality of TCAM entries; writing the plurality of TCAM entries in the FIFO buffer to the TCAM to solve In the related art, when the TCAM entry is written one by one, the CPU needs to intervene in a whole process, the write rate is low, and the CPU resource overhead is large, and the TCAM entry is written in batches, and the efficiency of writing the TCAM entry is improved.

Claims

A method of writing a tri-state content addressed memory TCAM entry, comprising:

Writing a predetermined data block to the first in first out FIFO buffer of the TCAM interface by direct memory access DMA, wherein the predetermined data block includes a plurality of TCAM entries;

The plurality of TCAM entries in the FIFO buffer are written to the TCAM.
The method of claim 1, before the predetermined data block is written to the FIFO buffer of the TCAM interface by direct memory access DMA, the method further comprising:

Obtaining the predetermined data block.
The method of claim 2 wherein obtaining the predetermined block of data comprises:

The central processing unit CPU converts the TCAM data into a TCAM entry;

The converted TCAM entry is written to the cache space to obtain the predetermined data block.
The method of claim 3, wherein writing the converted TCAM entry to the cache space to obtain the predetermined data block comprises:

Determining whether the written TCAM entry is the last TCAM entry converted according to the TCAM data;

If the judgment result is no, the next TCAM entry obtained by the conversion is continuously written into the buffer space;

In the case where the determination result is YES, the predetermined data block formed by the written plurality of TCAM entries is acquired from the buffer space.
The method according to any one of claims 1 to 4, wherein the writing of the predetermined data block to the FIFO interface of the TCAM interface by direct memory access DMA comprises:

The predetermined data block is written to the FIFO buffer according to a physical address of the predetermined data block, a FIFO cache address, and a data block size.
A device for writing TCAM entries, including:

The first write module is configured to: write a predetermined data block by direct memory access DMA a first in first out FIFO buffer of the TCAM interface, wherein the predetermined data block includes a plurality of TCAM entries;

The second write module is configured to: write the plurality of TCAM entries in the FIFO buffer to the TCAM.
The apparatus of claim 6 further comprising:

The obtaining module is configured to: acquire the predetermined data block.
The apparatus of claim 7, wherein the obtaining module comprises:

a conversion unit, configured to: convert TCAM data into a TCAM entry;

The writing unit is configured to: write the converted TCAM entry into the buffer space to obtain the predetermined data block.
The apparatus of claim 8 wherein said writing unit comprises:

Determining the secondary unit, configured to: determine whether the written TCAM entry is the last TCAM entry converted according to the TCAM data;

The first write secondary unit is configured to: continue to convert the converted next TCAM entry into the buffer space if the determination result is negative;

The second write secondary unit is configured to: obtain, when the determination result is YES, the predetermined data block formed by the written plurality of TCAM entries from the cache space.
The apparatus according to any one of claims 6 to 9, wherein the first writing module is configured to:

The predetermined data block is written to the FIFO buffer according to a physical address of the predetermined data block, a FIFO cache address, and a data block size.
A computer readable storage medium storing computer executable instructions for performing the method of any of claims 1-5.