WO2016095340A1 - 数据发送成功的确认方法及装置 - Google Patents

数据发送成功的确认方法及装置 Download PDF

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WO2016095340A1
WO2016095340A1 PCT/CN2015/073249 CN2015073249W WO2016095340A1 WO 2016095340 A1 WO2016095340 A1 WO 2016095340A1 CN 2015073249 W CN2015073249 W CN 2015073249W WO 2016095340 A1 WO2016095340 A1 WO 2016095340A1
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host
test data
data
mapping
window
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French (fr)
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于在宇
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

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  • the present invention relates to the field of storage based on non-transparent bridges, and in particular to a method and apparatus for confirming successful data transmission.
  • NTB Non- Transparent Bridge
  • the dual-point Back-Back tunnel mode that is, two NTB chips are used in the two control rooms, and one topology is connected to the subordinate side.
  • the multi-point Primary side is connected to the same transparent bridge Switch, that is, one controller is used as the master (or called the switch controller), and the switch controller chip that integrates multiple transparent bridges is used on the main controller.
  • Multiple slave controllers are connected in star form to each transparent bridge of the primary controller.
  • the master controller looks at the slave controller as the End Point node of the new generation peripheral peripheral bus standard (PCI-E) bus of the main controller, and the communication between the multiple controllers can be realized.
  • PCI-E peripheral peripheral peripheral bus standard
  • each slave controller uses an NTB chip (also known as an NT chip), and an NTB connects the Subordinate side to the transparent bridge of the main controller.
  • the manage host can be understood as an abbreviation of the control host;
  • the Back-Back topology is used as an example to describe the address mapping method and software design method commonly used in the prior art, as shown in Figure 4.
  • the Mem in Figure 4 is the abbreviation of the memory memory, which is the Back-Back extension.
  • the dual-machine NT interconnection working mode In the mapping mode, the host 1 (Host1) sends data to the host 2 (Host 2) as an example, and the configuration method of the base address register (BAR) address and the address translation register is explained.
  • BAR base address register
  • the mapping relationship is described by taking a specific address as an example.
  • P indicates the register on the Primary side
  • S indicates the register on the Subordinate side.
  • the Primary Basic Address Register (PBAR) 4/5 Window Size and the dependent side base address are mentioned in the configuration method.
  • the Subordinate Basic Address Register (SBAR4)/5Window Size has different values for different applications.
  • 1G is taken as an example (simplification of the problem without loss of generality).
  • the data is written to the board between the Host domains as an example to illustrate the existing design method:
  • the mapping relationship of the packets in the configuration mode of Table 1 is as shown in Figure 5.
  • the dashed line is used to map the chip registers of the board, which can realize the "by doorbell"operation;
  • the dotted line is mapped to the board memory, and the message is sent from the CPU and falls in the BAR4/5 window on the Primary side.
  • the NTB address translation mechanism the message is forwarded to the position pointed to by the BAR4/5 address translation register (adding an offset) Then, the message will fall in the BAR4/5 window on the Subordinate side of the board, and is again forwarded to the address pointed to by the Subordinate side address translation register by the address translation mechanism, that is, in the memory of the board.
  • Out queue First Input First Output, FIFO for short
  • FIFO First Input First Output
  • the use case of data sent from Host1 to Host2 is implemented in the following way: the memory of Host2 is divided into data areas and The cursor area; Host1 sends data to the data area of Host2: using CPU or DMA for transport, the source address is the memory address of the local data, the destination address is the local BAR4/5 base address plus the appropriate offset; Host1 sends the cursor To the cursor area of Host2: the destination address is the base address of BAR4/5 plus the appropriate offset; optionally, Host1 accesses the doorbell register of Host2's NTB through BAR2/3 to send the doorbell; Host2 is triggered by the doorbell interrupt or uses the CPU wheel The query mode sense cursor is modified; Host2 sends the response back to Host1 in the same way; Host1 receives the response from Host2 and confirms that the data is sent successfully, so that the application process is registered backward.
  • Method 1 Wake up the CPU of Host2 to know the arrival of data by interrupt. This usage will cause the delay to increase due to interrupt->sensing->processing when the load is light, and may be temporarily disabled due to Host2. The interruption was further aggravated. From the measured data, the design causes hundreds of thousands of interrupts per second under the specific IO model, which increases the burden on the Host system.
  • Method 2 Using the Host2CPU infinite loop polling mode, a large amount of CPU resources are also consumed in the case of light load of the system, which increases the hardware performance requirements of the product and increases the product cost.
  • the embodiment of the invention provides a method and a device for confirming the success of data transmission, so as to at least solve the problem that the related technology is in the process of the interaction between the host 1 and the host 2, and the process of confirming whether the data is successfully sent depends on the host 2 CPU.
  • a method for confirming the success of data transmission is provided, which is applied to the interaction process between the first host and the second host, including: sending service data to the second host; Mapping data of the host is mapped to the second host, and mapping test data mapped to the second host to the first host; determining that the test data exists in the first host determines The service data is successfully transmitted.
  • the first host and the second host use a non-transparent bridge NTB for data interaction.
  • mapping test data written to the first host to the second host comprises: writing in a first window of a primary side base address register PBAR corresponding to an NTB of the first host Determining test data; mapping test data in the first window to a second window of the slave side SBAR corresponding to the NTB of the second host.
  • mapping the test data mapped to the second host to the first host comprises: mapping test data of the SBAR second window to an SBAR third window corresponding to the NTB of the first host Mapping the test data of the SBAR third window to the first host.
  • the test data is determined to be present in the first host by: monitoring data stored in a specified storage location in the first host; and monitoring when data stored in the specified storage location is the test data And determining that the test data exists in the first host.
  • the specified storage location is dedicated to storing the test data.
  • the specified storage location comprises at least one of: an interrupt register, a physical memory, a chip register, and an interrupt vector register.
  • a confirmation device for successfully transmitting data is provided, which is applied to a first host, comprising: a sending module, configured to send service data to a second host; and a mapping module configured to write to Mapping data of the first host is mapped to the second host, and test data mapped to the second host is mapped to the first host; and a determining module is configured to determine that the first host exists When the data is tested, it is determined that the service data is successfully transmitted.
  • the mapping module is configured to: when the first host and the second host use a non-transparent bridge NTB for data interaction, the method includes: a writing unit, configured to correspond to an NTB of the first host The test data is written in a first window of the primary side base address register PBAR; the first mapping unit is configured to map the test data in the first window to the slave side SBAR corresponding to the NTB of the second host The second window.
  • the mapping module includes: a second mapping unit, configured to map test data of the SBAR second window to an SBAR third window corresponding to the NTB of the first host; and the third mapping unit is configured to Mapping test data of the SBAR third window to the first host.
  • mapping test data written to the first host to the second host and mapping to the test in the second host Mapping the data to the first host, and determining the technical means for successfully transmitting the service data when determining the presence of the test data in the first host, and solving the related art in the host 1 and the host 2
  • the process of confirming whether the data is successfully sent depends on the increase of delay caused by the Host2CPU and wastes resources, greatly reducing the delay, and quickly knowing that the data has been successfully sent.
  • FIG. 1 is a schematic diagram of a topology of a dual-point Back-Back tunnel in the prior art
  • FIG. 2 is a schematic diagram of a multi-point NT-NT mode topology in the prior art
  • FIG. 3 is a schematic diagram of connecting to a Switch in a Back-Back manner in the prior art
  • FIG. 4 is a schematic diagram of a working mode of a dual-machine interconnection in a Back-Back topology in the prior art
  • FIG. 5 is a schematic diagram of packet mapping in a mapping mode in the prior art
  • FIG. 6 is a flowchart of a method for confirming successful data transmission according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of memory management division according to an embodiment of the present invention.
  • FIG. 8 is a structural block diagram of a device for confirming successful data transmission according to an embodiment of the present invention.
  • FIG. 9 is a block diagram showing still another structure of a device for successfully transmitting data according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of improved message mapping according to a preferred embodiment of the present invention.
  • Figure 11 is a flow chart of the behavior before improvement in accordance with a preferred embodiment of the present invention.
  • Figure 12 is a flow chart of the improved behavior in accordance with a preferred embodiment of the present invention.
  • FIG. 6 is a data transmission success according to an embodiment of the present invention.
  • the flow chart of the confirmation method is as shown in FIG. 6, and the process includes the following steps:
  • Step S602 sending service data to the second host
  • Step S604 mapping the test data written to the first host to the second host, and mapping the test data mapped to the second host to the first host;
  • Step S606 when it is determined that the test data exists in the first host, it is determined that the service data is successfully sent.
  • step 604 can be implemented by using a pre-configured address mapping mechanism, which is not limited by the embodiment of the present invention.
  • the first host and the second host use a non-transparent bridge NTB for data interaction.
  • the following optional embodiments are provided to implement the technical solution of the foregoing step S604: the primary side base address register corresponding to the NTB of the first host Writing the test data in the first window of the PBAR; mapping the test data in the first window to the second window of the slave side SBAR corresponding to the NTB of the second host; mapping the test data of the second window of the SBAR to The SBAR third window corresponding to the NTB of the first host; mapping test data of the SBAR third window to the first host.
  • the foregoing step S606 may be determined by determining, by using the following manner, that the foregoing test data exists in the first host; monitoring data stored in the specified storage location in the first host; and monitoring the storage of the specified storage location.
  • the data is the test data
  • the designated storage location is dedicated to storing the test data, that is, an area is separately opened in the first host for storing test data.
  • the above-defined areas that is, designated storage locations include, but are not limited to, interrupt registers, physical memory, chip registers, and interrupt vector registers.
  • the reason for the drawbacks of the prior art is that NTB can only write to the board memory and cannot read, so the Response can only be realized by relying on the board CPU to write back.
  • the address translation function of the NTB is used to implement a method similar to the hardware loopback.
  • Table 1 the technical solution provided by the embodiment of the present invention is used to form the following Table 2.
  • the schematic method shown (the horizontal line is the added content relative to Table 1):
  • the technical solution provided by the embodiment of the present invention is to provide a method for four-time address translation (local->board->local) and two-time tunnel mapping, and realizes recovery recovery without involving the CPU of the board. And dividing the shared memory in the first host into a primary mapping area (corresponding to other areas in the memory of the above embodiment except the specified storage location) and a secondary mapping area (corresponding to the above embodiment) Specifying the storage location)
  • the method of management (as shown in FIG. 7 , it should be noted that FIG. 7 is only described as a preferred example), escaping the dependence on the CPU of the board, and achieving very low latency Response recycling. Methods.
  • FIG. 8 is a structural block diagram of a device for confirming successful data transmission according to an embodiment of the present invention. As shown, the device includes:
  • the sending module 80 is configured to send service data to the second host.
  • the mapping module 82 is connected to the sending module 80, configured to map the test data written to the first host to the second host, and map the test data mapped to the second host to the first host;
  • the determining module 84 is connected to the mapping module 82, and is configured to determine that the service data is successfully sent when it is determined that the test data exists in the first host.
  • mapping test data written to the first host to the second host and mapping to the second host
  • mapping test data is mapped to the first host, and the technical means for successfully transmitting the service data is determined when determining the test data in the first host, and the related art is in the process of interaction between the host 1 and the host 2.
  • the process of confirming whether the data is successfully sent depends on the increase of delay caused by the Host2CPU and wastes resources, greatly reducing the delay, and quickly knowing that the data has been successfully sent.
  • the mapping module 82 is configured to: when the first host and the second host use the non-transparent bridge NTB for data interaction, the method includes: a writing unit 820, configured to be in the first host The test data is written in the first window of the primary side base address register PBAR corresponding to the NTB; the first mapping unit 822 is connected to the writing unit 820, and is configured to map the test data in the first window to the second The second window of the slave side SBAR corresponding to the NTB of the host; the mapping module 82 may further include the following unit: the second mapping unit 824 is connected to the first mapping unit 822, and is configured to map the test data of the SBAR second window to The SBAR third window corresponding to the NTB of the first host; the third mapping unit 826 is connected to the second mapping unit 824, and is configured to map the test data of the SBAR third window to the first host.
  • the method for confirming the success of sending data takes Host1's Response as an example for Host1, as long as a write operation is written to the 1M offset position of Primary BAR4/5 on Host1, such as writing 32.
  • An integer of -bit this pen write message will automatically loop back to Host1's memory physical address 0x200000000 through a series of hardware address translation mapping mechanism.
  • the software program above Host1 only needs to monitor 32 at address 0x200000000.
  • the write request reaches the PBAR4/5 window of Host1: the first mapping, Host1NTB translates the write request to the Host2SBAR2/3 window; the second mapping, Host2NTB translates the write request to Host2PBAR4/5 Window; for the third mapping, Host2NTB translates the write request to the Host1SBAR4/5 window; for the fourth mapping, Host1NTB translates the write request to Host1Mem.
  • NTB Due to the shared memory operation method implemented by NTB, applications generally use the producer/consumer model to perform concurrent process concurrent protection between boards. That is, at the same time, if a certain memory area is writable to the Remote Host, it is read-only for the Local Host; if it is readable and writable for the Local Host, then it is not available for the Remote Host. Operational. On the basis of the above improved methods, the concurrent protection of memory access becomes more complicated. The access method to the memory is performed by the previous two types: local read and write, writing to the board through the NTB mapping, and expanding to three types, and a kind of "local->board->local" loopback type writing.
  • the preferred embodiment of the present invention also proposes a Mem management area partitioning method to solve the concurrency protection problem at this time. That is, the memory is divided into a primary mapping area and a secondary mapping area, as shown in FIG. 7 as an example of a division method.
  • mapping area For the use of the mapping area, the usage restrictions are consistent with the usage of the improved method.
  • secondary mapping area For the secondary mapping area, the following usage is used:
  • the secondary mapping area is read-only if the Local CPU does not pass the NTB loopback mapping
  • the secondary mapping area can only be modified by using the local CPU using the "local->board->local" loopback type writing method
  • the local CPU modifies the information of the secondary mapping area by means of the second point, the information content can be read, and if the information is found to be the modified content, (in the case that there is no surprise down abnormal reporting)
  • the data sent to the board before the CPU loopback write operation is safely arrived at the board memory.
  • the dependency on the receiving board CPU in the data interaction process is simplified, and the performance and the system overhead are reduced.
  • the secondary mapping area is used as an example for memory. If the memory is replaced by another device having a physical address, it is within the protection scope of the present invention.
  • the secondary buffer can be the MSI interrupt vector register of the Local Host. Therefore, this loopback will automatically generate an interrupt on the Local Host.
  • the method for mapping the message is as shown in FIG. 10, wherein the message flows through the solid line.
  • the translation process is proposed in the embodiment of the present invention.
  • the message is sent from the CPU and falls to the rear 1M position of the Primary BAR2/3 window of the left controller, and is mapped by the address translation mechanism to the BAR2 of the Subordinate side of the right controller.
  • the address translation mechanism is mapped to the secondary mapping area in the BAR4/5 window on the Primary side of the right controller, and then mapped to the Subordinate side of the left controller via the address translation mechanism (PBAR4/5Trans on the right).
  • the BAR4/5 register is finally mapped to the secondary mapping memory of the left controller through the address translation mechanism to complete the entire loopback transmission process.
  • FIG. 11 is a flow chart of the pre-improvement behavior according to a preferred embodiment of the present invention. As shown in FIG. 11, the method includes the following steps:
  • Step S1102 the A control uses a tunnel to write data into the B control memory (1 ⁇ s);
  • Step S1104 the A control uses the primary tunnel mode to write the information area cursor into the B control memory (1 ⁇ s);
  • Step S1106 A control presses B to control "doorbell” (1 ⁇ s);
  • Step S1110 the B control interrupts the context wake-up processing thread (the general delay is above 40 ⁇ s);
  • Step S1112 the B control thread processes all the data sent by the A through the cursor, and returns an ACK after completion, and the process needs about 3 ⁇ s;
  • step S1114 the A control receives the ACK returned by the B control to notify the upper layer user that the data transmission is successful.
  • the entire transmission delay is equal to the transmission delay plus the delay of the comparison interrupt response, and the delay of the whole process is at least 40 ⁇ s, and the delay is longer if the B control is disabled.
  • Figure 12 is a flow chart of the improved behavior in accordance with a preferred embodiment of the present invention, as shown in Figure 12, including the following steps:
  • Step S1202 the A control uses a tunnel method to write data into the B control memory (1 ⁇ s);
  • Step S1204 the A control uses the primary tunnel mode to write the information area cursor to the B control memory (1us);
  • Step S1206 modifying the local secondary mapping area cursor (1 ⁇ s) by using the secondary tunnel loopback mode
  • Step S1208 polling the secondary mapping area cursor change can confirm that the first three steps are successfully completed, and returning data to the user is successfully sent;
  • step S1210 the B control asynchronously extracts data for processing.
  • the delay only needs to calculate the delay of the first three steps, and the actual measurement does not exceed 5 ⁇ s at about 3 ⁇ s. And all the time-consuming operations of the B control can be In order to complete the asynchronous completion after the A control returns to the user, in summary, compared with the improved delay before the improvement, there has been a substantial improvement.
  • the embodiment of the present invention achieves the following technical effects: in the related art, in the process of interaction between the host 1 and the host 2, the process of confirming whether the data is successfully transmitted depends too much on the increase delay caused by the Host2 CPU. The problem of wasting resources greatly reduces the delay and can quickly know that the data has been sent successfully.
  • a storage medium is further provided, wherein the software includes the above-mentioned software, including but not limited to: an optical disk, a floppy disk, a hard disk, an erasable memory, and the like.
  • modules or steps of the present invention described above can be implemented by a general-purpose computing device that can be centralized on a single computing device or distributed across a network of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein.
  • the steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof are fabricated as a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the method and apparatus for successfully confirming the data transmission provided by the embodiment of the present invention have the following beneficial effects: during the interaction between the host 1 and the host 2, the dependency of the process of confirming whether the data is successfully transmitted on the Host2 CPU is reduced. Reduce waste of resources, reduce latency, and quickly learn that data has been sent successfully.

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Abstract

本发明提供了一种数据发送成功的确认方法及装置，其中，所述方法包括：向第二主机发送业务数据；将写入到所述第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机；在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功。采用本发明提供的上述技术方案，解决了相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，大大减少了时延，并能够快速获知数据已发送成功。

Description

数据发送成功的确认方法及装置 技术领域
本发明涉及基于非透明桥的存储领域，具体而言，涉及一种数据发送成功的确认方法及装置。
背景技术
在存储设备中都有回写需求，为保证单点故障时数据不丢失，必须对业务数据做镜像处理，而双控间(或多控间)的传输通道普遍都选用非透明桥(Non-Transparent Bridge，简称为NTB)这种硬件，而现有技术常见利用NTB完成Host域隔离实现的方式主要包括：
1.如图1所示，双点Back-Back隧道方式，即两个控制间一共使用两颗NTB芯片，将从属Subordinate侧相连的一种拓扑方式；
2.如图2所示，多点Primary侧连接到同一透明桥Switch，即一个控制器作为主(或称为交换控制器)，主控制器上使用一颗集成了多透明桥的Switch芯片，多个从控制器以星形方式连接到主控制器的每一个透明桥下。这样在主控制器看从控制器就好比主控制器的新一代外围部分总线标准(Peripheral Component Interconnect-Express，简称为PCI-E)总线下的End Point节点，多控制器间就可以实现通信了。这里每个从控制器上使用一颗NTB芯片(又称NT芯片)，出一个NTB将Subordinate侧连接到主控制器的透明桥上，其中，manage host可以理解为是控制主机的简称；
3.如图3所示，多点分别以Back-Back方式连接到Switch，该方式与前一种(图2所示)类似，不同在于将主控制器上的透明桥调整为NTB，形成主控和每个从控制器之间都形成NTB-NTB这种拓扑方式。
这些拓扑形式广泛应用于存储产品的多头/双头间的大量数据和管理信息交互中，但在软件设计上和NTB映射关系配置上全都需要在远Remote端中央处理器(Central Processing Unit，简称为CPU)的参与下才能完成“ping”包或数据应答动作，在异常处理、响应速度、系统资源开销等方面尚有改进空间。
以Back-Back拓扑为例介绍现有技术中，应用普遍采用的地址映射方法和软件设计方法，如图4所示，其中，图4中的Mem为内存memory的简称，为Back-Back拓 扑下的双机NT互联工作方式。映射方式上，以主机1(Host1)向主机2(Host2)发送数据为例，阐述基地址寄存器(Basic Address Register，简称为BAR)地址和地址翻译寄存器的配置方法。为直观起见，以具体的地址为例对映射关系进行阐述。P表示Primary侧的寄存器，S表示Subordinate侧的寄存器，如下表一所示，配置方法中提到的主侧基地址寄存器(Primary Basic Address Register，简称为PBAR)4/5Window Size和从属侧基地址寄存器(Subordinate Basic Address Register，简称为SBAR4)/5Window Size的大小不同应用会有不同取值，此处以1G为例(不失一般性的情况下简化对问题的阐述)。在该配置下以Host域间向对板写入数据为例，说明现有的设计方法：
表一
Figure PCTCN2015073249-appb-000001
在上述表一的配置方式下报文的映射关系如图5所示，
Figure PCTCN2015073249-appb-000002
虚线用于映射对板的芯片寄存器，可以实现“按门铃”操作；
Figure PCTCN2015073249-appb-000003
虚线由于映射对板内存，报文从CPU发出后落在Primary侧的BAR4/5窗口中，根据NTB地址翻译机制，该报文会转发到BAR4/5地址翻译寄存器指向的位置(加偏移量)，那么该报文会落在对板Subordinate侧的BAR4/5窗口中，再次利用地址翻译机制被转发到Subordinate侧地址翻译寄存器所指向的地址，即对板的内存中。
在相关技术中，以存储产品为例，由于热拔插的场景存在，软件设计上几乎所有应用都不会设计出读对边共享内存的动作，因为一旦在读报文未返回的情况下拔出对板，本板CPU是可能发生挂死的，而且很多低价CPU是无法解决这个问题的，因此设计上绝不会采用读，并且，由于板间无法使用锁机制，所以只能用先入先出队列 (First Input First Output，简称为FIFO)这种免锁算法来进行设计，所以比如数据从Host1发送到Host2这个用例，现有技术中会以如下方式来实现：将Host2的内存分为数据区和游标区；Host1将数据发送Host2的数据区：使用CPU或DMA进行搬运，源地址是本地的数据所在内存地址，目标地址是本地的BAR4/5基地址加合适的偏移量；Host1将游标发送到Host2的游标区：目标地址是BAR4/5的基地址加合适的偏移量；可选地，Host1通过BAR2/3访问Host2的NTB的门铃寄存器发送门铃；Host2由门铃中断触发或使用CPU轮询方式感知游标被修改；Host2以同样方式将应答发送回Host1；Host1收到Host2的应答后确认数据发送成功，使应用流程寄存向后走。
但在上述流程中，存在的一个问题：由Host1向Host2发送数据的过程中必须由Host2的CPU参与才能完成整个发送、确认收到的流程，可以理解为以存储应用为例这里的确认收到信号是必要，应答响应过慢是会直接影响到对外呈现的输入输出(Input Output，简称为IO)时延的。
由于必须由Host2的CPU来发送Response响应，现有技术确实提供了以下两种处理方法：
方法一：通过中断的方式唤醒Host2的CPU感知到数据的到来，这种用法在负载较轻时会导致由于中断->感知->处理这几步使时延增加，而且可能由于Host2被暂时禁止中断而被进一步加剧。从实测数据看，该设计在特定IO模型下回导致每秒几十万次的中断，加重Host系统负担。
方法二：采用Host2CPU死循环轮询的方式，则在系统轻载情况下也会导致大量CPU资源被消耗，变相增加了产品对硬件性能的要求，提高了产品成本。
那么是否有办法使得整个发送流程不必依赖于Host2CPU的感知呢？本文第4部分会沿着该思路给出一种充分利用NTB映射能力而发明的改进方法，增加一次映射，使报文多一次映射，在不需要Host2CPU参与的情况下形成报文换回，可解决上述弊端。
针对相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种数据发送成功的确认方法及装置，以至少解决相关技术在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题。
根据本发明的一个方面，提供了一种数据发送成功的确认方法，应用于第一主机和第二主机的交互过程中，包括：向第二主机发送业务数据；将写入到所述第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机；在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功。
优选地，所述第一主机和所述第二主机采用非透明桥NTB进行数据交互。
优选地，将写入到所述第一主机的测试数据映射到所述第二主机中，包括：在所述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入所述测试数据；将所述第一窗口中的测试数据映射到所述第二主机的NTB对应的从属侧SBAR的第二窗口。
优选地，将映射到所述第二主机中的测试数据映射至所述第一主机，包括：将所述SBAR第二窗口的测试数据映射至所述第一主机的NTB对应的SBAR第三窗口；将所述SBAR第三窗口的测试数据映射到所述第一主机。
优选地，通过以下方式判定所述第一主机中存在所述测试数据；监测所述第一主机中指定存储位置存储的数据；在监测到所述指定存储位置存储的数据为所述测试数据时，判断所述第一主机中存在所述测试数据。
优选地，所述指定存储位置专用于存储所述测试数据。
优选地，所述指定存储位置包括以下至少之一：中断寄存器、物理内存、芯片寄存器、中断向量寄存器。
根据本发明的另一个方面，还提供了一种数据发送成功的确认装置，应用于第一主机，包括：发送模块，设置为向第二主机发送业务数据；映射模块，设置为将写入到第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机；确定模块，设置为在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功。
优选地，所述映射模块，设置为在所述第一主机和所述第二主机采用非透明桥NTB进行数据交互时，包括：写入单元，设置为在所述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入所述测试数据；第一映射单元，设置为将所述第一窗口中的测试数据映射到所述第二主机的NTB对应的从属侧SBAR的第二窗口。
优选地，所述映射模块，包括：第二映射单元，设置为将所述SBAR第二窗口的测试数据映射至所述第一主机的NTB对应的SBAR第三窗口；第三映射单元，设置为将所述SBAR第三窗口的测试数据映射到所述第一主机。
通过本发明，采用在数据发送完之后，采用一种轮回机制：将写入到所述第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机，进而在在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功的技术手段，解决了相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，大大减少了时延，并能够快速获知数据已发送成功。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1是现有技术中双点Back-Back隧道方式拓扑示意图；
图2是现有技术中多点NT-NT方式拓扑示意图；
图3是现有技术中以Back-Back方式连接到Switch示意图；
图4是现有技术中Back-Back拓扑下双机互联工作方式图；
图5是现有技术中映射方式下报文映射示意图；
图6是根据本发明实施例的一种数据发送成功的确认方法的流程图；
图7为根据本发明实施例内存管理划分示意图；
图8为根据本发明实施例的数据发送成功的确认装置的结构框图；
图9为根据本发明实施例的数据发送成功的确认装置的再一结构框图；
图10为根据本发明优选实施例的改进后报文映射示意图；
图11为根据本发明优选实施例的改进前行为流程图；
图12为根据本发明优选实施例的改进后行为流程图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本发明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
为了解决上述技术问题，在本实施例中提供了一种数据发送成功的确认方法，应用于第一主机和第二主机的交互过程中，图6是根据本发明实施例的一种数据发送成功的确认方法的流程图，如图6所示，该流程包括如下步骤：
步骤S602，向第二主机发送业务数据；
步骤S604，将写入到第一主机的测试数据映射到第二主机中，并将映射到第二主机中的测试数据映射至第一主机；
步骤S606，在判定第一主机中存在上述测试数据时，确定上述业务数据发送成功。
通过上述各个步骤，采用在数据发送完之后，采用一种轮回机制：将写入到上述第一主机的测试数据映射到上述第二主机中，并将映射到上述第二主机中的测试数据映射至上述第一主机，进而在在判定上述第一主机中存在上述测试数据时，确定上述业务数据发送成功的技术手段，解决了相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，大大减少了时延，并能够快速获知数据已发送成功，实际上，在具体实施过程 中，可以通过预先配置的一种地址映射机制来实现上述步骤604的过程，本发明实施例对此不作限定。
在本发明实施例中，上述第一主机和上述第二主机采用非透明桥NTB进行数据交互。
对于上述步骤S604的实现方式是有很多种的，在本发明实施例中，提供了以下可选实施例来实现上述步骤S604的技术方案：在上述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入上述测试数据；将上述第一窗口中的测试数据映射到上述第二主机的NTB对应的从属侧SBAR的第二窗口；将上述SBAR第二窗口的测试数据映射至上述第一主机的NTB对应的SBAR第三窗口；将上述SBAR第三窗口的测试数据映射到上述第一主机。
可选地，可以通过以下过程判断上述步骤S606，即通过以下方式判定上述第一主机中存在上述测试数据；监测上述第一主机中指定存储位置存储的数据；在监测到上述指定存储位置存储的数据为上述测试数据时，判断上述第一主机中存在上述测试数据，其中，指定存储位置专用于存储上述测试数据，即在第一主机中会单独开辟出一个区域用来存储测试数据。
上述开辟出的区域即指定存储位置包括但不限于：中断寄存器、物理内存、芯片寄存器、中断向量寄存器。
综上所述，考虑到现有技术弊端的原因是NTB只能写对板内存而不能读，所以Response只能依赖于对板CPU写回来才能实现。本发明实施例上述提出的利用NTB的地址翻译功能，实现一种类似硬件环回的方法：以表一所示的配置方式，采用本发明实施例上述提供的技术方案，最终形成如下表二所示的示意方法(横线部分为相对于表一增加的内容)：
表二
Figure PCTCN2015073249-appb-000004
Figure PCTCN2015073249-appb-000005
即本发明实施例提供的技术方案，旨在提供一种4次地址翻译(本地->对板->本地)、2次隧道映射的方法，在不需要对板CPU参与的前提下实现Response回收的的方法，并且将第一主机中的共享内存划分文一次映射区(相当于上述实施例内存中除所述指定存储位置之外的其他区域)和二次映射区(相当于上述实施例的指定存储位置)进行管理的方法(如图7所示，需要说明的是，图7仅作为一个优选示例进行说明)，摆脱对板CPU感知这一环节的依赖、实现极低时延的Response回收的方法。
在本实施例中还提供了一种数据发送成功的确认装置，应用于第一主机中，设置为实现上述实施例及优选实施方式，已经进行过说明的不再赘述，下面对该装置中涉及到的模块进行说明。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。图8为根据本发明实施例的数据发送成功的确认装置的结构框图。如图所示，该装置包括：
发送模块80，设置为向第二主机发送业务数据；
映射模块82，与发送模块80连接，设置为将写入到第一主机的测试数据映射到上述第二主机中，并将映射到上述第二主机中的测试数据映射至上述第一主机；
确定模块84，与映射模块82连接，设置为在判定上述第一主机中存在上述测试数据时，确定上述业务数据发送成功。
通过上述各个模块的综合作用，采用在数据发送完之后，采用一种轮回机制：将写入到上述第一主机的测试数据映射到上述第二主机中，并将映射到上述第二主机中的测试数据映射至上述第一主机，进而在在判定上述第一主机中存在上述测试数据时，确定上述业务数据发送成功的技术手段，解决了相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，大大减少了时延，并能够快速获知数据已发送成功。
可选地，如图9所示，映射模块82，设置为在上述第一主机和上述第二主机采用非透明桥NTB进行数据交互时，包括：写入单元820，设置为在上述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入上述测试数据；第一映射单元822，与写入单元820连接，设置为将上述第一窗口中的测试数据映射到上述第二主机的NTB对应的从属侧SBAR的第二窗口；映射模块82，还可以包括以下单元：第二映射单元824，与第一映射单元822连接，设置为将上述SBAR第二窗口的测试数据映射至上述第一主机的NTB对应的SBAR第三窗口；第三映射单元826，与第二映射单元824连接，设置为将上述SBAR第三窗口的测试数据映射到上述第一主机。
为了更好的理解上述发送数据成功的确认过程的具体流程，以下再结合以下优选实施例对上述技术方案进行详细说明，但不用于限定本发明实施例：
需要说明的是，本发明优选实施例以双点Back-Back方式应用为例，但其中的思路和原理完全可以通过简单类比应用于多点的两种典型拓扑中。
采用本发明实施例上述提供的发送数据成功的确认方法，以Host1需要Host2的Response为例，只要在Host1上向Primary BAR4/5的1M偏移量位置写入一笔写操作，比如写入32-bit的一个整型数，这个笔写报文会自动经过一系列硬件的地址翻译映射机制自动环回到Host1的内存的物理地址0x200000000位置，Host1上面的软件程序只需监视0x200000000地址处的32-bit整型数变化为这笔写所写内容，就可确认：“在这个时间点之前，所有向Host2发送的写报文都已经安全的送达了Host2的内存中”。此时Host1上的软件可直接根据具体应用的设计进行后续操作，不必等待Host2的CPU感知这一冗长的过程。
简而言之:写请求到达Host1的PBAR4/5窗口后：第1次映射，Host1NTB将写请求翻译后映射到Host2SBAR2/3窗口；第2次映射，Host2NTB将写请求翻译后映射到Host2PBAR4/5窗口；第3次映射，Host2NTB将写请求翻译后映射到Host1SBAR4/5窗口；第4次映射，Host1NTB将写请求翻译后映射到Host1Mem。
由于NTB实现的共享内存的操作方法，应用一般会使用生产者/消费者模型来做板间的异步流程并发保护。即，在同一时刻，某段内存区若对于Remote Host是可写入的，那么其对于Local Host则为只读的；若其对于Local Host是可读写的，那么其对于Remote Host则为不可操作的。而在我们提出了上述改进方法的基础上，对内存的访问的并发保护变得更加复杂了一些。对内存的访问方式由之前的两种：本地读写、对板通过NTB映射写入，扩展为3种，多了一种“本地->对板->本地”的环回型写入。因此，本发明优选实施例还提出了一种Mem管理区划分的方法来解决此时的并发保护问题。即，将内存划分为一次映射区和二次映射区，如图7是一种划分方法示例。
对于一次映射区使用限制与改进方法提出前的用法保持一致，对于二次映射区做如下使用方式的设计：
1.二次映射区对Local CPU若不经过NTB环回映射，是只读的；
2.二次映射区只能使用Local CPU利用“本地->对板->本地”的环回型写入法进行修改；
3.本地CPU在利用第2点的方式修改了二次映射区信息后，可读取该信息内容，若发现该信息确实变为所修改内容，(在无surprise down异常中断上报的情况下)在CPU环回写入操作之前所发送到对板的数据都已安全的到达对板内存。
采用本发明优选实施例上述提供的技术方案，将简化掉数据交互过程中对接收板CPU感知的依赖，提高性能、减少系统开销。
需要说明的是，本发明优选实施例仅作一示例进行解释说明，以二次映射区为内存做例进行阐述，若将内存换为其他具有物理地址的设备，均在本发明的保护范围内。例如：二次缓存区完全可以是Local Host的MSI中断向量寄存器，因此，这次环回将自动在Local Host产生一次中断。
基于现有技术中图5给出的技术方案，采用本发明实施例以及优选实施例上述提供的技术方案后，报文的映射方法如图10所示，其中，实线所流经的报文翻译过程是本发明实施例中提出的：首先报文从CPU发出，落在左侧控制器Primary BAR2/3窗口的后1M位置，会被地址翻译机制映射到右侧控制器的Subordinate侧的BAR2/3窗口中，再经过地址翻译机制映射到右侧控制器Primary侧的BAR4/5窗口中二次映射区中，再经过地址翻译机制(右侧PBAR4/5Trans)映射到左侧控制器Subordinate侧的BAR4/5寄存器，最终通过地址翻译机制映射到左侧控制器的二次映射内存中，完成整个环回发送流程。
为了更好的理解上述图5和图10之间的改进过程，以下结合附图11和如图12进行说明：
图11为根据本发明优选实施例的改进前行为流程图，如图11所示，包括以下步骤：
步骤S1102，A控利用一次隧道方式将数据写入B控内存(1μs)；
步骤S1104，A控利用一次隧道方式将信息区游标写入B控内存(1μs)；
步骤S1106，A控按B控“门铃”(1μs)；
步骤S1108，B控CPU收到中断(若有其他线程仅中断后带来不可预知的时延)；
步骤S1110，B控中断上下文唤醒处理线程(一般时延在40μs以上)；
步骤S1112，B控线程通过游标处理所有A控发来的数据，完成后返回ACK，这个过程需要3μs左右；
步骤S1114，A控收到B控返回的ACK通知上层用户数据传输成功。
从图11中可以看出整个发送时延等于发送时延加上对比中断响应的时延，整个过程的时延至少会大于40μs，而且如果B控被禁止中断这个时延还会更长。
图12为根据本发明优选实施例的改进后行为流程图，如图12所示，包括以下步骤：
步骤S1202，A控利用一次隧道方式将数据写入B控内存(1μs)；
步骤S1204，A控利用一次隧道方式将信息区游标写入B控内存(1us)；
步骤S1206，利用二次隧道环回方式修改本地二次映射区游标(1μs)；
步骤S1208，轮询二次映射区游标改变则可确认前3步均以成功完成，向用户返回数据发送成功；
步骤S1210，B控异步提取数据进行处理。
从图12中可以看出，采用本发明实施例提供的上述技术方案之后，时延只需要计算前3步的时延，在3μs左右，实测不会超过5μs。而B控的所有耗时操作都可 以在A控给用户返回成功后异步的完成，综上所述，对比改进前改进后的时延，有了大幅改善。
综上所述，本发明实施例达到了以下技术效果：解决了相关技术中，在主机1和主机2的交互过程中，确认数据是否发送成功的过程过多依赖Host2CPU而导致的增加时延进而浪费资源的问题，大大减少了时延，并能够快速获知数据已发送成功。
在另外一个实施例中，还提供了一种软件，该软件用于执行上述实施例及优选实施方式中描述的技术方案。
在另外一个实施例中，还提供了一种存储介质，该存储介质中存储有上述软件，该存储介质包括但不限于：光盘、软盘、硬盘、可擦写存储器等。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的对象在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
显然，本领域的技术人员应该明白，上述的本发明的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，可选地，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本发明不限制于任何特定的硬件和软件结合。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。
工业实用性
如上所述，本发明实施例提供的一种数据发送成功的确认方法及装置具有以下有益效果：在主机1和主机2的交互过程中，降低了确认数据是否发送成功的过程对Host2CPU的依赖性，降低浪费资源，减小时延，并能够快速获知数据已发送成功。

Claims (10)

  1. 一种数据发送成功的确认方法，应用于第一主机和第二主机的交互过程中，包括：
    向第二主机发送业务数据；
    将写入到所述第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机；
    在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功。
  2. 根据权利要求1所述的方法，其中，所述第一主机和所述第二主机采用非透明桥NTB进行数据交互。
  3. 根据权利要求2所述的方法，其中，将写入到所述第一主机的测试数据映射到所述第二主机中，包括：
    在所述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入所述测试数据；
    将所述第一窗口中的测试数据映射到所述第二主机的NTB对应的从属侧SBAR的第二窗口。
  4. 根据权利要求3所述的方法，其中，将映射到所述第二主机中的测试数据映射至所述第一主机，包括：
    将所述SBAR第二窗口的测试数据映射至所述第一主机的NTB对应的SBAR第三窗口；
    将所述SBAR第三窗口的测试数据映射到所述第一主机。
  5. 根据权利要求1所述的方法，其中，通过以下方式判定所述第一主机中存在所述测试数据；
    监测所述第一主机中指定存储位置存储的数据；
    在监测到所述指定存储位置存储的数据为所述测试数据时，判断所述第一主机中存在所述测试数据。
  6. 根据权利要求1至5任一项所述的方法，其中，所述指定存储位置专用于存储所述测试数据。
  7. 根据权利要求6所述的方法，其中，所述指定存储位置包括以下至少之一：中断寄存器、物理内存、芯片寄存器、中断向量寄存器。
  8. 一种数据发送成功的确认装置，应用于第一主机中，包括：
    发送模块，设置为向第二主机发送业务数据；
    映射模块，设置为将写入到第一主机的测试数据映射到所述第二主机中，并将映射到所述第二主机中的测试数据映射至所述第一主机；
    确定模块，设置为在判定所述第一主机中存在所述测试数据时，确定所述业务数据发送成功。
  9. 根据权利要求8所述的装置，其中，所述映射模块，设置为在所述第一主机和所述第二主机采用非透明桥NTB进行数据交互时，包括：
    写入单元，设置为在所述第一主机的NTB对应的主侧基地址寄存器PBAR的第一窗口中写入所述测试数据；
    第一映射单元，设置为将所述第一窗口中的测试数据映射到所述第二主机的NTB对应的从属侧SBAR的第二窗口。
  10. 根据权利要求9所述的装置，其中，所述映射模块，包括：
    第二映射单元，设置为将所述SBAR第二窗口的测试数据映射至所述第一主机的NTB对应的SBAR第三窗口；
    第三映射单元，设置为将所述SBAR第三窗口的测试数据映射到所述第一主机。
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