WO2016089831A1 - Interposeurs comprenant des modules de circuits encapsulés par un matériau moulable dans une cavité, et procédés de fabrication associés - Google Patents

Interposeurs comprenant des modules de circuits encapsulés par un matériau moulable dans une cavité, et procédés de fabrication associés Download PDF

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Publication number
WO2016089831A1
WO2016089831A1 PCT/US2015/063128 US2015063128W WO2016089831A1 WO 2016089831 A1 WO2016089831 A1 WO 2016089831A1 US 2015063128 W US2015063128 W US 2015063128W WO 2016089831 A1 WO2016089831 A1 WO 2016089831A1
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WIPO (PCT)
Prior art keywords
substrate
cavity
encapsulant layer
holes
encapsulant
Prior art date
Application number
PCT/US2015/063128
Other languages
English (en)
Inventor
Hong Shen
Liang Wang
Rajesh Katkar
Original Assignee
Invensas Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/558,462 external-priority patent/US9324626B2/en
Application filed by Invensas Corporation filed Critical Invensas Corporation
Publication of WO2016089831A1 publication Critical patent/WO2016089831A1/fr

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Definitions

  • the present invention relates to semiconductor technology, and more particularly to use of auxiliary substrates for interconnection of semiconductor integrated circuits and other components.
  • Fig. 2 illustrates a known ceramic or organic interposer 120 with a cover 210 over a die 110 (a die is an IC that was manufactured as part of a semiconductor wafer and then separated from the wafer; the wafer may contain multiple dies fabricated at the same time).
  • the interposer connects the die 110 to bottom contact pads 120C.B; lines 120L are not shown.
  • Cover 210 is attached to interposer 120 by epoxy 220. Cover 210 stiffens and flattens the interposer, and acts like a heat spreader: the heat generated by die 110 is conducted through thermal grease 230 to cover 210 and then to the ambient. See U.S. patent no.
  • the stiffener and the interposer can be made in a single substrate 120S as shown in Fig. 3 and described in the Eghan patent.
  • Substrate 120S has a cavity 304 containing the die 110; the die is surrounded by the substrate's "perimeter wall" 304P.
  • the assembly can be further strengthened by underfill 310 between the die and the interposer: the underfill is made of epoxy that glues the die to the interposer and thus relieves the stress on connections 140. Also, the underfill can be thermally conductive to spread the heat.
  • thermally conductive encapsulant 320 fills the spaces between the die and the walls 304P to protect the die and help in heat spreading.
  • the encapsulant may or may not cover the die, and an additional heat spreader (not shown) may be provided on top.
  • the dies 110 i.e. 110.1, 110.2, 110.3 of Fig. 4 can be underfilled and
  • FIGs. 1, 2, 3, 4 show vertical cross sections of structures with interposers according to prior art.
  • Figs. 5C, 5D, 5E, 5F, 5G, 5H, 51, 5J, 5K, 5L, 6, 7, 8A show vertical cross sections of interposers in the process of fabrication according to some embodiments of the present invention.
  • Fig. 8B is a top view of an interposer in the process of fabrication according to some embodiments of the present invention.
  • Wafer 510 is sufficiently thick to provide desired stiffness, heat dissipation, and/or other desired properties.
  • some embodiments use a monocrystalline silicon wafer of 200 or 300 mm diameter and at least 650 micron thickness.
  • the length of vertical wires to be made in the structure need not be taken into account in selecting the wafer thickness because the wire length is not defined by the wafer thickness.
  • Cavity 304 is formed in the top surface of wafer 510, by a masked etch for example. Multiple etches can be used, with different masks, to provide a stepped sidewall as in Fig. 4 if desired.
  • An exemplary cavity depth is 400 microns or less. The vertical wires will pass through the cavity's bottom wall 304B.
  • Holes 514.0 will contain conductive through-substrate vias (TSVs) for the vertical wires.
  • TSVs through-substrate vias
  • Conventional formation of high density TSVs is a challenging process because on the one hand, the TSVs should be narrow for high density, and on the other hand the substrate has to be thick to provide mechanical strength. Making narrow TSVs through a thick substrate is difficult.
  • the wafer of Figs. 5B.1, 5B.2 is strengthened by peripheral walls 304P, and the TSVs pass only through the bottom wall 304B. If the bottom wall 304B is thin, the TSVs can be narrow and therefore can be at higher density.
  • the bottom wall's thickness is 20 microns or less in some silicon embodiments.
  • circuitry (not shown) is formed in wafer 510, possibly including transistors, diodes, capacitors, and/or other circuit elements.
  • the circuitry can be formed in the walls 304P and/or 304B before formation of cavities 304 and/or at any other fabrication stages.
  • holes 514.0 As “level-zero holes” or “level L0 holes”. Other holes will be made at higher levels as described below. (We use the concept of levels for ease of description; the invention pertains to structures and methods and not to any description techniques.)
  • holes 514.0 are filled (or lined) with conductive material 520.0 to form TSVs that will serve as wire segments.
  • This can be done by sputtering or other techniques, e.g. electroplating (which is relatively inexpensive).
  • the electroplating uses a seed layer 520S formed to cover the anti-cavity side.
  • the seed layer may or may not enter the holes 514.0.
  • the seed layer is copper formed by sputtering.
  • the sputtering can be performed at an angle, i.e. the wafer can be inclined to prevent the copper molecules from reaching the cavity through the holes.
  • the seed layer can be foil (e.g. copper foil) laminated on the anti-cavity side. Other techniques can also be used.
  • Conductor 520.0 fills the holes 514.0, and thus provides contact pads at the cavity bottom, i.e. at the top surface of bottom wall 304B.
  • the contact pads may be wider than the holes 514.0.
  • Conductor 520.0, 520S may include multiple conductive layers.
  • the conductor top surfaces are usable as seed for electroplating of other wire segments as described below.
  • the dies are underfilled and encapsulated by a suitable dielectric encapsulant 524.1 (level-one or LI "encapsulant” below).
  • Underfilling can be done by capillary or no- flow techniques.
  • Encapsulation can be done by spin-on deposition and curing of moldable material or possibly by other techniques.
  • Suitable underfill and encapsulant materials can be conventional, including organic polymer resins—such as BCB (benzocyclobutene) or epoxy — with suitable fillers, or possibly other types.
  • BCB benzocyclobutene
  • encapsulant 524.1 reaches as high as the top surfaces of dies 510B and 5 IOC, thus encapsulating these dies laterally and below, but the encapsulant does not cover these dies.
  • the encapsulant covers the die 110A.
  • the encapsulant can reach any level, and in particular can cover more than one dies, and/or on the contrary can terminate below the top surfaces of one or more of the dies.
  • the top surface level can be adjusted by lowering the encapsulant level after deposition, e.g. using chemical etching or etching by abrasives (e.g. dry or wet blasting).
  • Holes 514.1 are formed in the encapsulant to expose contact pads 520.0 not covered by LI dies 110.
  • holes 514.1 are formed as level- 1 or LI holes.
  • a suitable process for making LI holes 514.1 depends on the encapsulant's material. For example, for resins, laser ablation can be used, which is a known technique in fabrication of through-mold vias (TMVs). If the encapsulant is photoimageable, then photolithographic techniques can be used, i.e. exposure to light through a glass-based mask followed by development in a developer solution. These examples are not limiting.
  • LI holes 514.1 expose contact pads 520.0.
  • the holes are filled or lined with conductor 520.1 (Fig. 5G) to form level-Ll wire segments. Segments 520.1 can be formed by electroplating: the plating current can be provided from the anti-cavity side through seed layer 520S and L0 wire segments 520.0, but connecting the seed layer to an electric power source's terminal 534.
  • Conductor 520.1 fills (or lines) LI holes 514.1, and thus provides contact pads ("LI contact pads") at the top surface of LI encapsulant 524.1.
  • the LI contact pads may be wider than the LI holes 514.1.
  • Figs. 5H-5L illustrate level L2 formation.
  • One or more dies 110 including the die HOD, are attached on top of level LI; the dies' contact pads are attached to LI contact pads 520.1.
  • die HOD has contact pads 112 both on top and bottom. The top contact pads 112 will be attached to overlying circuitry (not yet formed).
  • L2 encapsulant 524.2 is formed to underfill and encapsulate the L2 dies.
  • L2 holes 514.2 (Fig. 51) are formed in L2 encapsulant 524.2 to expose those LI contact pads 520.1 that are not covered by a die.
  • L2 holes 514.2 are filled or lined with conductor 520.2 (Fig. 5 J) which provides L2 wire segments.
  • Conductor 520.2 can be formed by electroplating; the plating current can be provided from the bottom side through seed layer 520S and lower- level wire segments 520.0, 520.1 by connecting the seed layer 520S to a terminal 534 of an electric power source.
  • the L2 wire segments 520.2 contact the underlying LI wire segments 520.1 and provide contact pads at the top of L2 encapsulant 524.2.
  • the contact pads can be wider than the L2 holes 514.2.
  • the L2 features can be formed using the same processes as described above for level LI .
  • Fig. 5K shows a final structure with four levels and a heat spreader 540 on top.
  • Level L3 includes a die 110E some of whose bottom contact pads are attached to the level L2 contact pads 520.2 (not marked in this figure). Other bottom contact pads of die 110E are attached to top contact pads 112 of L2 die 110D.
  • L3 die 110E is underfilled and laterally encapsulated by encapsulant 524.3 made of moldable material.
  • L3 wire segments 520.3 are vertical segments passing through encapsulant 524.3.
  • L4 die 110F has bottom contact pads attached to top contact pads of L3 die 110E and to the wire segments 520.3 (to the top contact pads provided by these segments).
  • L3 wire segments 520.3 can be formed by electroplating; the plating current can be provided from the bottom side through lower-level wire segments 520.0, 520.1, 520.2.
  • L4 die 11 OF is underfilled and laterally encapsulated by encapsulant 524.4 made of moldable material.
  • L4 wire segments 520.4 are vertical segments passing through encapsulant 524.4.
  • External circuits e.g. dies, MCMs, or discrete wires or other discrete components, can be attached to the top ends of segments 524.4. The top ends can be formed to facilitate such attachment; for example, if the attachment will be by solder, then a barrier layer such as nickel can be electroplated or electroless-plated to protect underlying portions of segments 524.4 from solder
  • the top level segments 520.4 can be formed by electroplating; the plating current can be provided from the bottom side through lower-level wire segments 520.0, 520.1, 520.2, 520.3. Any number of heat-removal wires can be provided; the heat-removal wires may or may not reach the heat spreader.
  • the top level L4 includes wire segments 520.4 that provide contact pads at the top of encapsulant 520.4 side-by-side with heat spreader 540. These contact pads can be connected to external circuits as mentioned above.
  • each encapsulant layer 524 is deposited and cured in a separate operation; the encapsulant layer does not have any separately-cured sub-layers. Therefore, the encapsulant layer does not have any internal surface boundaries that would be present between sub-layers.
  • An internal surface boundary is characterized by surface states. A surface state is a state with molecules having higher energies than below the surface;
  • surface states may be detectable visually (possibly using microscopy) or perhaps by ultrasound or other ways. The invention is not limited to such embodiments however.
  • the encapsulant layer may have a surface at the boundary between the underfill and laterally encapsulating portion of the encapsulant. Further, the laterally encapsulating portion can be made of a different material than the underfill.
  • the interposer's bottom can be processed to remove or pattern protective layer 532 and conductor 520S in any desired manner.
  • layer 532 is removed, and the conductor is thinned and patterned to provide contact pads 120C.B at the ends of wire segments 520.0.
  • These contact pads can be attached to other dies, MCMs, or packaging substrates such as PCBs or interposers.
  • Fig. 6 shows additional features that may be available in some embodiments.
  • level L3 includes a redistribution layer 610.3 which may have a number of conductive layers separated by dielectric layers.
  • the conductive layers provide interconnects 620.3 which extend both vertically and laterally (possibly horizontally). Interconnects 620.3 terminate in contact pads 630.3 at the top of the RDL. Interconnects 620.3 interconnect the underlying wire segments 520.2 and the overlying wire segments 520.3 as desired.
  • the dielectric layers of RDL 610.3 are formed of the same or similar materials as encapsulant layers 524 (e.g. moldable organic polymer deposited by a spin-on process, or from other materials described above), and are patterned by the same techniques (e.g.
  • the conductive layers can also be formed by other deposition and patterning techniques, e.g. using photolithography or by additive
  • RDL lines 620.3 connect L2 wire segments 520.2 to L3 wire segments 520.3.
  • a line 620.3 connects a top contact pad 112 of L2 die 110E to the top of an L2 wire segment 520.2.
  • Another line 620.3 connects an L2 wire segment 520.2 to a bottom contact pad of L3 die 110F.
  • Contact pads 630.3 at the ends of lines 620.3 can provide an area array pattern or other patterns as needed for connection to L3 dies and wire segments.
  • level L2 includes a die that has no bottom contact pads, but has only top contact pads connected to other circuitry by RDL 610.3. Any level may include a die having no bottom contact pads and having top contact pads attached to other circuits within or outside the cavity. Also a die may have no top contact pads. In the example of Fig. 7, die 110E has no top contact pads, and further L2 encapsulant 524.2 covers the die, and RDL 610.3 covers the encapsulant.
  • Level L3 wire segments 520.3 (Figs. 6, 7) can be formed at the top of RDL 610.3 by electroplating; the plating current is conducted from the bottom layer 520S to the top of RDL 610.3 through wire segments 620.3.
  • L4 wire segments 520.4 and their respective underlying L3 segments 520.3 are for heat removal.
  • RDL 610.3 is associated with level L3, but this is simply a matter of terminology: we could say that RDL 610.3 is part of level L2.
  • An RDL can be provided at any level. Also, multiple alternating RDLs and encapsulant layers can be provided in a single level, i.e. for a single set of dies 110 attached to the preceding level.
  • Substrate 510 can be assembled from different substrates, and an example is shown in Figs. 8A (vertical cross section) and 8B (top view on a smaller scale than Fig. 8A).
  • substrate 510 is includes a planar substrates 510.1 and a substrate 510.2 attached to planar substrate 510.1. The attachment is by adhesive 810, but direct bonding can also be used.
  • Fig. 8B multiple substrates 510.2 (called “frames" below) are attached to a single planar substrate 510.1, and multiple structures are formed of the type of Fig. 7 or other types discussed above on the same planar substrate 510.1.
  • the planar substrate 510.1 can be diced along lines (not shown) passing between the frames 510.2 at the end of fabrication or at any other fabrication stage.
  • Planar substrate 510.1 and frames 510.2 can be made of the same or different materials, including any materials mentioned above for wafer 510.
  • Adhesive 810 if present, can be any suitable adhesive, e.g. plastic deposited in a flowable form and then cured using heat, pressure, radiation, and/or other means. Non- flowable adhesives can also be used.
  • Substrate 510 may include a stack of more than two substrates, e.g. each frame 510.2 or planar substrate 510.1 may be a laminate of multiple substrates.
  • an interface region of the adjacent pieces is not uniform with respect to at least one of the properties mentioned above, i.e. chemical composition, density, elasticity modulus, conductivity, dielectric constant, ultrasound propagation speed for one or more wavelengths, light propagation speed for one or more wavelengths.
  • properties mentioned above i.e. chemical composition, density, elasticity modulus, conductivity, dielectric constant, ultrasound propagation speed for one or more wavelengths, light propagation speed for one or more wavelengths.
  • the interface region can be defined as including adhesive 810 and adjacent surfaces of substrates 510.1 and 510.2, and the interface is not uniform if the adhesive has a different chemical composition than the adjacent surfaces of substrate 510.1 or 510.2. If the attachment is by direct bonding of substrate 510.1 to 510.2 and the substrates are made of the same material (e.g. silicon), the interface can be uniform, and the substrate 510 can be indistinguishable from a substrate made initially from a single piece. However, the interface can also be non-uniform with respect to light or sound propagation speed, e.g. if the interface includes bubbles or other states detectable by US or spectral imaging.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Des puces empilées (110) sont encapsulées dans une cavité (304) d'un interposeur par de multiples couches d'encapsulation (524) formées d'un matériau moulable. Des chemins conducteurs (520, 620) connectent les puces à la paroi de fond (304B) de la cavité et, par des trous d'interconnexion traversant la paroi de fond, à un conducteur sous l'interposeur. Les chemins conducteurs peuvent être formés dans des segments qui sont chacun formés dans un trou débouchant (514) dans une couche d'encapsulation respective. Chaque segment peut être formé par électrodéposition sur un segment inférieur, le courant d'électrodéposition pouvant être fourni par en dessous de l'interposeur par le biais des trous d'interconnexion et de segments formés précédemment. La présente invention concerne également d'autres caractéristiques.
PCT/US2015/063128 2014-12-02 2015-12-01 Interposeurs comprenant des modules de circuits encapsulés par un matériau moulable dans une cavité, et procédés de fabrication associés WO2016089831A1 (fr)

Applications Claiming Priority (2)

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US14/558,462 US9324626B2 (en) 2014-03-12 2014-12-02 Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
US14/558,462 2014-12-02

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
EP1418617A2 (fr) * 2002-11-05 2004-05-12 Shinko Electric Co. Ltd. Composant semiconducteur et méthode de fabrication correspondante
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
EP1884994A2 (fr) * 2006-08-03 2008-02-06 Shinko Electric Industries Co., Ltd. Dispositif semi-conducteur et son procédé de fabrication
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
EP2555239A2 (fr) * 2011-08-04 2013-02-06 Sony Mobile Communications AB Emballage thermique avec gaine thermique pour empilements de puces
US20130099368A1 (en) * 2011-10-19 2013-04-25 SK Hynix Inc. Chip carriers, semiconductor devices including the same, semiconductor packages including the same, and methods of fabricating the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492726B1 (en) 2000-09-22 2002-12-10 Chartered Semiconductor Manufacturing Ltd. Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection
US7061102B2 (en) 2001-06-11 2006-06-13 Xilinx, Inc. High performance flipchip package that incorporates heat removal with minimal thermal mismatch
EP1418617A2 (fr) * 2002-11-05 2004-05-12 Shinko Electric Co. Ltd. Composant semiconducteur et méthode de fabrication correspondante
US7977579B2 (en) 2006-03-30 2011-07-12 Stats Chippac Ltd. Multiple flip-chip integrated circuit package system
EP1884994A2 (fr) * 2006-08-03 2008-02-06 Shinko Electric Industries Co., Ltd. Dispositif semi-conducteur et son procédé de fabrication
EP2555239A2 (fr) * 2011-08-04 2013-02-06 Sony Mobile Communications AB Emballage thermique avec gaine thermique pour empilements de puces
US20130099368A1 (en) * 2011-10-19 2013-04-25 SK Hynix Inc. Chip carriers, semiconductor devices including the same, semiconductor packages including the same, and methods of fabricating the same

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