WO2016084237A1 - 仮想計算機システムの制御方法及び仮想計算機システム - Google Patents
仮想計算機システムの制御方法及び仮想計算機システム Download PDFInfo
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- WO2016084237A1 WO2016084237A1 PCT/JP2014/081588 JP2014081588W WO2016084237A1 WO 2016084237 A1 WO2016084237 A1 WO 2016084237A1 JP 2014081588 W JP2014081588 W JP 2014081588W WO 2016084237 A1 WO2016084237 A1 WO 2016084237A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4825—Interrupt from clock, e.g. time of day
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
- G06F2009/45575—Starting, stopping, suspending or resuming virtual machine instances
Definitions
- the present invention relates to a virtual machine system that dynamically occupies and assigns an interrupt timer of a physical CPU to a virtual CPU.
- a virtual machine system is a platform that allows a virtual machine monitor (or hypervisor) to build a plurality of virtual machines using resources of a physical machine and run an operating system independently on each virtual machine. It is.
- the use of a virtual computer system has many advantages such as effective utilization of physical computer resources and easy management and maintenance of software, and is becoming popular.
- the program running on the virtual machine is particularly called a guest, and the virtual machine system (virtual machine monitor or the like) is particularly called a host.
- the virtual machine monitor has a CPU sharing mode and a CPU occupation mode as physical CPU scheduling modes.
- a CPU sharing mode in which physical CPUs are time-shared by more virtual CPUs than physical CPUs is often used.
- CPU occupation modes in which each virtual CPU occupies one specific physical CPU core has become widespread.
- CPU occupancy mode is beginning to be used in applications that are particularly demanding on latency (processing delay) such as in-memory databases and real-time control.
- the interrupt timer of the CPU is a timer included in an interrupt controller built in the CPU body.
- the timer consists of a remaining counter that subtracts at a fixed frequency. When a value is written to the remaining counter, the remaining counter starts subtraction, and when it reaches zero, it generates a timer interrupt to the CPU to which the interrupt controller belongs. It has an interval timer function that stops operation until a value is written to the remaining counter.
- Patent Document 1 describes a basic method for virtually realizing a virtual computer timer by sharing a physical computer timer in a virtual computer system.
- Patent Document 2 and Patent Document 3 describe a timer virtualization method for catching up with a virtual computer system when the timer of the virtual computer is delayed with respect to the actual time.
- Patent Document 4 describes a method for scheduling a context to a specific CPU in accordance with an access situation to a memory or a cache.
- Patent Document 5 describes a method of moving an I / O that is exclusively allocated to a virtual computer to be moved as the virtual computer moves between physical computers.
- the interrupt timer of the virtual CPU was emulated using the interrupt timer of the physical CPU.
- the overhead of this emulation is large, which may affect applications running on the virtual CPU.
- the interrupt timer of the physical CPU is also used for host processing activation, timeout detection, clock tick timer with a fixed period, etc., regardless of the operation of the application, not only spending CPU time but also TLB (Translation Lookaside Buffer) and In the above-mentioned application in which cache data is evicted and the TLB and the cache are severely demanded, performance may be degraded.
- TLB Translation Lookaside Buffer
- an object of the present invention is to control occupation of a physical CPU interrupt timer by a virtual CPU interrupt timer in conjunction with dynamic switching of a physical CPU scheduling mode in a virtual machine system.
- the present invention includes an interrupt controller including an interrupt timer, a physical processor including the interrupt controller, a physical computer including the physical processor and a physical memory, and a virtualization unit that allocates computer resources of the physical computer to a plurality of virtual computers.
- a virtual computer system control method in which the virtualization unit controls allocation of the physical processor, wherein the virtualization unit virtualizes the interrupt timer, and the interrupt A virtual processor to which a computer resource of the physical processor including a virtual interrupt controller that virtualizes a controller is generated, and a virtual memory to which a computer resource of the physical memory is allocated, are generated, and the plurality of virtual computers are generated.
- the virtualization unit includes the plurality A processor sharing mode in which one of the physical processors assigned to the virtual machine is shared by the plurality of virtual processors, and a processor that occupies one of the physical processors assigned to the plurality of virtual machines by the specific virtual processor
- a second step of setting one of the processor scheduling modes in the occupation mode and the virtualization unit sets an interrupt timer of the physical processor in which one of the processor sharing mode and the processor occupation mode is set,
- a timer scheduling mode that is set in conjunction with the processor scheduling mode is set in any one of a timer sharing mode shared by timer events of a plurality of virtual machines and a timer occupation mode occupied by a virtual timer of the specific virtual processor. Steps , Including the.
- the interrupt timer of the specific physical CPU is made to occupy the interrupt timer of the virtual CPU in conjunction with the occupation of the virtual CPU.
- the overhead of emulation of the interrupt timer of the virtual CPU can be minimized, and the physical timer can be controlled by preventing the TLB and cache data from being expelled by the host timer that occurred regardless of the operation of the program on the virtual CPU.
- CPU performance can be ensured.
- FIG. 5 is a graph illustrating a relationship between a timer event deadline and a remaining counter of an interrupt timer of a physical CPU in a timer sharing mode according to an embodiment of this invention.
- FIG. 6 is a graph illustrating a relationship between a timer event deadline and a remaining counter of an interrupt timer of a physical CPU in a timer sharing mode according to an embodiment of this invention.
- 7 is a flowchart illustrating an example of a process for updating a counter of a remaining interrupt timer of a virtual CPU in a physical CPU in the timer sharing mode according to an embodiment of this invention.
- FIG. 5 is a graph illustrating a relationship between a timer event deadline and a remaining counter of an interrupt timer of a physical CPU in a timer sharing mode according to an embodiment of this invention.
- FIG. 6 is a graph illustrating a relationship between a timer event deadline and a remaining counter of an interrupt timer of a physical CPU in a timer sharing mode according to an embodiment of this invention
- FIG. 9 is an example of the present invention, and is a first half of a flowchart illustrating an example of a timer interrupt transmission process of a virtual CPU in a physical CPU in a timer sharing mode.
- FIG. 6 is a second half of a flowchart illustrating an example of a timer interrupt transmission process of a virtual CPU in a physical CPU in the timer sharing mode according to an embodiment of this invention.
- FIG. 10 is a flowchart of a process for updating a counter of a remaining interrupt timer of a virtual CPU in a physical CPU in a timer occupation mode according to an embodiment of this invention.
- FIG. 7 is a flowchart of a timer interrupt transmission process of a virtual CPU interrupt timer in a physical CPU in a timer occupation mode according to the embodiment of this invention.
- FIG. 9 shows an embodiment of the present invention and is the first half of a flowchart of a dynamic change process of a timer scheduling mode of an interrupt timer of a physical CPU.
- FIG. 9 shows the embodiment of the present invention and is the latter half of the flowchart of the dynamic change processing of the timer scheduling mode of the interrupt timer of the physical CPU.
- 6 is a flowchart of a dynamic change process of a timer scheduling mode of an interrupt timer of a physical CPU according to an embodiment of this invention.
- FIG. 1 is a block diagram showing an example of a virtual machine system to which the present invention is applied.
- the virtual machine system includes a physical machine 1, a virtual machine monitor 100, and virtual machines 200a to 200c (1 to 3).
- the generic name of the virtual computer is indicated by reference numeral 200 without an alphabetic suffix, and each virtual computer is identified by reference symbols 200a to 200c with an alphabetic suffix.
- the type of the constituent element is specified by a code without an alphabetic subscript
- each constituent element is specified by a code with an alphabetic subscript.
- the physical computer 1 includes physical CPUs 10a to 10d (0 to 3), a memory 050, an I / O interrupt controller 060, one or more I / O devices 70, and a system time 80.
- the physical CPUs 10a to 10d (0 to 3) may be configured by a processor core of a multi-core processor.
- the physical CPUs 10a to 10d (0 to 3) include interrupt controllers 30a to 30d built in the CPU body.
- the interrupt controller 30a receives an external interrupt from an interrupt generation source, transmits an external interrupt to the physical CPU 0 (10a), and an inter-processor interrupt with another physical CPU 10 in a computer system including a plurality of physical CPUs 10. Provides the function to send and receive.
- the interrupt controller 30a further includes an interrupt timer 40a.
- the interrupt controller 30a is mounted on the physical CPU 10a as, for example, LOCAL APIC (Advanced Programmable Interrupt Controller).
- the interrupt timer 40a is mounted on the interrupt controller 30a as, for example, LOCAL APIC TIMER.
- the physical CPU 0 (10a) includes an external interrupt mask 20a.
- the external interrupt mask 20a provides a function that allows the external interrupt transmitted to the physical CPU 0 (10a) to be temporarily ignored while being suspended by closing the mask.
- a program such as an operating system uses an external interrupt mask between the start and end of a process in which normal operation cannot be guaranteed if an external interrupt occurs during execution.
- the other physical CPUs 1 to 3 (10b to 10d) are the same, and include an interrupt controller 30, an interrupt timer 40, and an external interrupt mask 20.
- the physical CPU includes a CPU virtualization assist function as a standard, but the present invention does not matter whether or not the physical CPU includes a CPU virtualization assist function. Therefore, in order to simplify the description, FIG. Then, the CPU virtualization assist function is omitted.
- the memory 50 is used as a volatile storage device for storing programs and data.
- the I / O interrupt controller 60 provides a function of transmitting a command completion notification from the I / O device 70 to the physical CPU 10 as an external interrupt to the interrupt controller 30 of the physical CPU 10.
- the I / O device 70 includes a disk controller that moves the disk drive and a network interface for communicating with an external computer system via a network.
- the system time 80 provides a common time among all physical CPUs 10 used by the virtual machine monitor 100 to acquire the current time and the elapsed time.
- the system time 80 may be RTC (Real Time Clock), HPET (High Precision Time Event), or the like.
- the virtual computer monitor 100 controls the computer resources of the physical computer 1 and generates one or more virtual computers 200 that are program execution environments recognized by a program represented by a general-purpose operating system as one computer.
- the virtual machine monitor 100 operates the program on the virtual machine 200, and provides a role of running the program in the same way as the physical machine 1 except for a slight performance degradation and timing difference compared to the physical machine 1. It is a program.
- the virtual machine monitor 100 includes a scheduler 110 and a timer management unit 120. Instead of the virtual machine monitor 100, a virtualization unit such as a hypervisor may be employed.
- the virtual machine monitor 100 controls the computer resources of the physical machine 1 to control the virtual CPU 0 (210a), the virtual CPU 1 (210b), the virtual memory 250, the virtual I / O device 260, and the virtual I / O interrupt controller.
- Virtual computers 200a to 200c (1 to 3) having 270 are constructed.
- the virtual CPU 0 (210a) includes an interrupt controller 220a that virtualizes the interrupt controller 30a.
- the interrupt controller (virtual interrupt controller) 220a includes an interrupt timer (virtual interrupt timer) 230a obtained by virtualizing the interrupt timer 40a.
- the virtual CPU 1 (210b) has the same configuration.
- the general-purpose operating system 201 operates on each of the virtual machines 200a to 200c.
- the general-purpose operating system 201 is particularly called a guest operating system 201.
- the virtual machine 2 (200b) and the virtual machine 3 (200c) are similarly configured.
- the virtual machine monitor 100 includes a dedicated process for performing processing for controlling the virtual machine system such as terminal control and virtual machine system management. These processes are particularly called host processes, and a dedicated process for providing host processes is called a host process. In the embodiment, the virtual machine monitor 100 operates a total of four host processes: a host process 1 (150a), a host process 2 (150b), a host process 3 (150c), and a host process 4 (150d).
- the scheduler 110 of the virtual machine monitor 100 and the functional units of the timer management unit 120 are loaded into the memory 50 as programs.
- the CPU 10 operates as a functional unit that provides a predetermined function by processing according to the program of each functional unit.
- the CPU 10 functions as the timer management unit 120 by performing processing according to the timer management program. The same applies to other programs.
- the CPU 10 also operates as a functional unit that provides each function of a plurality of processes executed by each program.
- a computer and a computer system are an apparatus and a system including these functional units.
- Information such as programs and tables for realizing each function of the virtual machine monitor 100 is a storage subsystem, nonvolatile semiconductor memory, hard disk drive, storage device such as SSD (Solid State Drive), or IC card, SD card, DVD Etc., and can be stored in a computer readable non-transitory data storage medium.
- FIG. 2 is a block diagram illustrating a detailed configuration related to the scheduler 110 and the timer management unit 120 in the embodiment.
- FIG. 2 only the physical CPU 0 (10a), the host process 1 (150a), the virtual CPU 0 (210a) of the virtual machine 1 (200), and the components directly related thereto are extracted. 2 applies to other physical CPUs 10, virtual CPUs 210, and host processes 150 in the same manner.
- the interrupt timer 40a of the physical CPU 0 (10a) includes a timer frequency 42a and a remaining counter 41a that subtracts a value set at a period corresponding to the frequency 42a.
- the interrupt controller 30a When a value is written in the remaining counter 41a, the remaining counter 41a starts subtraction, and when it becomes zero, the interrupt controller 30a generates a timer interrupt to the physical CPU 0 (10a). Then, after generating the timer interrupt, the interrupt controller 30a of the remaining counter 41a stops operating until a value is written to the remaining counter 41a next time. This function is called an interval timer function.
- the system time 80 includes a system time frequency 82 and a system time counter 81 that monotonously increases with the frequency 82 period.
- the reading value of the system time counter 81 may not be in the format of hour, minute and second.
- the scheduler 110 of the virtual machine monitor 100 assigns the virtual CPU 210 to one of the physical CPUs 10 so that the program on the virtual CPU 210 is executed. Further, the program on the host process 150 is executed by assigning the host process 150 to one of the physical CPUs 10.
- the scheduler 110 provides a CPU scheduling mode 111a for setting two values of the CPU occupation mode and the CPU sharing mode for the physical CPU 10a. Further, the scheduler 110 sets a run queue 112a and the like for executing the host process 150 and the like.
- the CPU scheduling mode 111a can be provided for each physical CPU 10a to 10d, and the CPU scheduling modes 111a to 111d are provided for each physical CPU 10a to 10d as shown in FIG. 3A described later.
- the run queue 112a can also be provided for each physical CPU 10a to 10d.
- the CPU occupation mode is a mode in which one virtual CPU 210 occupies one physical CPU
- the CPU sharing mode is a mode in which a plurality of virtual CPUs 210 share one physical CPU 10.
- the scheduler 110 has a timer queue 122a for storing timer events for the physical CPU 10a.
- a timer queue can be provided for each physical CPU 10a to 10d, and timer queues 122a to 122d are set for each physical CPU 10a to 10d as shown in FIG. 4A described later.
- the timer management unit 120 of the virtual machine monitor 100 virtually implements the interrupt timer 230a of the virtual CPU 210a using the interrupt timer 40a of the physical CPU 10a, starts up the host process 150 at a designated time, and operates. It provides roles for detecting program timeout, measuring CPU usage for each process, and updating statistical information.
- the timer management unit 120 provides each component with a data structure related to the timer in order to realize the above functions.
- the timer management unit 120 provides a timer scheduling mode 121a composed of two values of a timer occupation mode and a timer sharing mode in the interrupt timer 40a of the physical CPU 0 (10a).
- One timer scheduling mode 121a can be provided for each physical CPU 10a to 10d, and timer scheduling modes 121a to 121d are provided for each physical CPU 10a to 10d as shown in FIG. 4A described later.
- the timer occupation mode is a mode in which the interrupt timer 230 of one virtual CPU 210 occupies the interrupt timer 40 of one physical CPU
- the timer sharing mode is an interrupt timer of the physical CPU 10 in which a timer event of a plurality of virtual CPUs 210 is one. 40 is a sharing mode.
- the timer management unit 120 sets a timer event 130a of a clock tick timer that generates a timer interrupt at a constant period in order to share the physical CPU 0 (10a) among a plurality of virtual CPUs 210 in a time-sharing manner.
- the timer event 130a of the clock tick timer includes a start time 131a having a system time 80 as a time axis, a time limit 132a, a period 133a, and a valid / invalid status 134a.
- the clock tick timer may be a system timer.
- the timer event 130 of the clock tick timer is set for each physical CPU 10, and for example, timer events 130a to 130d of the clock tick timer can be provided as shown in FIG. 4A described later.
- the timer management unit 120 associates a timer event 160a with the host process 1 (150a) in order to start the host process 1 (150a) at a designated time or detect a timeout of the host process 1 (150a).
- the timer event 160a includes a time limit 161a with the system time 80 as a time axis, and a valid / invalid status 162a.
- the interrupt timer 230a of the virtual CPU 0 (210a) of the virtual machine 1 (200) is composed of a remaining counter 231a and a timer frequency 232a, like the interrupt timer 40a of the physical CPU 0 (10a).
- the timer management unit 120 associates the timer event 240a with the virtual CPU 0 (210a) in order to support emulation of the interrupt timer 230a.
- the timer event 240a includes a remaining counter update time 241a with the system time 80 as a time axis, a time limit 242a, and a valid / invalid status 243a.
- the frequency of the interrupt timer 40a of the physical CPU 10a and the frequency of the interrupt timer 230a of the virtual CPU 0 (210a) are equal, but may be different.
- the CPU scheduling mode 111 of the physical CPU 10 will be described in detail.
- the physical CPU 10 operates in the CPU occupancy mode, and the physical CPU 10 not occupied by one specific virtual CPU 210 operates in the CPU sharing mode.
- FIG. 3A shows a scheduling state when all physical CPUs operate in the CPU sharing mode.
- FIG. 3B is a diagram illustrating a scheduling state when the physical CPU 0 (10a) and the physical CPU 1 (10b) operate in the CPU occupation mode.
- an arbitrary virtual CPU 210 and host process 150 can operate on the physical CPU 10 in the CPU sharing mode.
- Scheduling of the physical CPU 10 in the CPU sharing mode basically includes scheduling performed independently for each physical CPU 10 and scheduling by load distribution according to the load status.
- Scheduling performed independently for each physical CPU 10 is enabled by associating the virtual CPU 210 and the host process 150 with the run queue 112 of one physical CPU 10 at a certain point in time.
- load distribution is performed by dynamically changing the correspondence between the run queue 112 for each physical CPU 10 and the virtual CPU 210 or the host process 150.
- the load distribution method a publicly known or well-known method may be adopted.
- the physical CPU 0 (10a) is time-shared between the host process 1 (150a), the virtual CPU 0 (210a) of the virtual machine 1 (200a), and the virtual CPU 0 (210a) of the virtual machine 2 (200b). Shared. The same applies to the physical CPU 1 (10b), the physical CPU 2 (10c), and the physical CPU 3 (10d).
- the physical CPU 0 (10a) is occupied by the virtual CPU 0 (210a) of the virtual machine 1 (200a).
- the virtual CPU 0 (210a) and the host process 1 (150a) of the virtual machine 2 (200b) operating on the physical CPU 0 (10a) are both moved to the physical CPU 2 (10c) in the CPU sharing mode. Is operating.
- the switching of the CPU scheduling mode 111a of the physical CPU 10 can be performed dynamically both from the CPU sharing mode to the CPU occupation mode or from the CPU occupation mode to the CPU sharing mode.
- the virtual machine monitor 100 includes the virtual CPU 0 (210a) of the virtual machine 2 (200b) and the host process 1 (150a) operating on the physical CPU 0 (10a). Both are moved to the physical CPU 2 (10c).
- the virtual machine monitor 100 changes the CPU scheduling mode 111a of the physical CPU 0 (10a) to the CPU occupation mode, and starts the occupation by the virtual CPU 0 (210a) of the virtual machine 1 (200). The same applies to the physical CPU 1 (10b).
- the virtual machine monitor 100 first switches the physical CPU 0 (10a) from the CPU occupation mode to the CPU sharing mode. Then, the virtual machine monitor 100 detects that the load on the physical CPU 0 (10a) is lower than the loads on the physical CPU 2 (10c) and the physical CPU 3 (010d).
- the virtual machine monitor 100 moves the virtual CPU 0 (210a) and the host process 1 (150a) of the virtual machine 2 (200b) from the physical CPU 2 (10c) to the physical CPU 0 (10a) by load balancing.
- the movement pattern of the virtual CPU 210 and the host process 150 accompanying the dynamic switching of the CPU scheduling mode 111a of the physical CPU 10a can change from time to time, and is not predetermined. The same applies to the physical CPU 1 (10b).
- the virtual machine monitor 100 links the timer scheduling mode 121a of the interrupt timer 40 of each physical CPU 10 with the CPU scheduling mode 111a of the corresponding physical CPU 10.
- the virtual machine monitor 100 links the timer scheduling mode 121a of the interrupt timer 230a of the physical CPU 0 (10a) with the CPU scheduling mode 111a of the physical CPU 0 (10a).
- the virtual machine monitor 100 sets the timer scheduling mode 121a of the interrupt timer 40a to the timer sharing mode when the physical CPU 0 (10a) is in the CPU sharing mode, and the interrupt timer 40a when the physical CPU 0 (10a) is in the CPU occupation mode.
- the timer scheduling mode 121a is set to the timer occupation mode.
- the timer scheduling mode 121a of the interrupt timer 40a can be dynamically switched. This switching is performed when the timer management unit 120 of the virtual machine monitor 100 receives a scheduling switching request.
- the virtual machine monitor 100 sets a scheduling mode switching request 123a for the physical CPU 0 (10a) in order to dynamically switch between the CPU scheduling mode 111 and the timer scheduling mode 121.
- the timer management unit 120 sets the received scheduling switching request as the scheduling mode switching request 123a.
- scheduling mode switching requests 123b to 123d are set, respectively.
- FIGS. 3A and 3B are conceptual diagrams of timer states when the scheduling state of the physical CPU 10 is FIGS. 3A and 3B, respectively.
- FIG. 4A is a diagram illustrating a state of the timer management unit 120 and each timer in the timer sharing mode.
- FIG. 4B is a diagram illustrating a state of the timer management unit 120 and each timer in the timer sharing mode and the timer occupation mode.
- FIG. 4A shows the case where the interrupt timers 40 of all the physical CPUs 10 are in the timer sharing mode
- FIG. 4B shows that the interrupt timer 40a of the physical CPU 0 (10a) and the interrupt timer 40b of the physical CPU 1 (10b) are in the timer occupation mode.
- the interrupt timer 40 of the physical CPU 10 includes the timer event 240 of the interrupt timer 230 of the virtual CPU 210 sharing the physical CPU 10, the timer event 160 of the host process 150, Shared among timer events 130 of the clock tick timer of the physical CPU 10.
- the timer event 240a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) and the timer event of the virtual CPU 0 (210a) of the virtual machine 2 (200b) The timer event 160a of the host process 1 (150a) is managed in the timer queue 122a.
- virtual machine 1 VM1
- virtual CPU0 VCPU0
- physical CPU0 PCPU0.
- the timer event 130a of the clock tick timer of the physical CPU 0 (10a) is managed without entering the timer queue 122a.
- the reason why the timer event 130a of the clock tick timer is not put into the timer queue 122a is that the timer event 130a of the clock tick timer does not move between the physical CPUs 10.
- the interrupt timer 40 of the physical CPU 10 is occupied by the interrupt timer 230 of the virtual CPU 210 that occupies the physical CPU 10.
- the timer event 240a of the interrupt timer 230a of the virtual CPU 210a is invalidated without being used, and the timer event 130a of the clock tick timer of the physical CPU 10a is also invalidated.
- the timer event that has entered the timer queue 122a of the physical CPU 10a has been moved to the timer queue of the physical CPU 10c in another timer sharing mode.
- the interrupt timer 40a of the physical CPU 0 (10a) in the timer occupation mode is occupied by the interrupt timer 230a of the virtual CPU 0 (210a) of the virtual machine 1 (200a).
- the timer event 240a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) is taken out from the timer queue 122a and invalidated, and the timer event 130a of the clock tick timer is invalidated.
- the timer event 160a of the host process 1 (150a) and the timer event 240c of the virtual CPU 0 (210a) of the virtual machine 2 (200b), both of which are in the timer queue 122a in FIG. 4A, are both the physical CPU 2 (10c). In the timer queue 122c.
- FIG. 5 is a diagram illustrating states of the scheduler 110 and the timer management unit 120 immediately before updating the remaining counter 231a of the interrupt timer 230a of the virtual CPU 0 (210a) of the virtual machine 1 (200a).
- FIG. 6 is a graph showing the relationship between the timer event deadline and the remaining counter 41a of the interrupt timer of the physical CPU 10 in the timer sharing mode.
- FIG. 6 is a graph showing the relationship between the timer event 160a of the host process 1 as a valid timer event and the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) in chronological order.
- the virtual CPU 0 (210a) of the virtual machine 1 (200a) is operating. Also, the interrupt counter 230a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) and the remaining counter 231a of the interrupt timer 230a of the virtual CPU 0 (210a) of the virtual machine 2 (200b) are both zero, and corresponding timer events. Both the statuses 243a and 243c of 240a and 240c are invalid.
- a value is set in the time limit 161a of the timer event 160a of the host process 1 (150a), and the status 162a is valid and is inserted in the timer queue 122a of the physical CPU 0 (10a). Also, the timer event 130a of the clock tick timer of the physical CPU 0 (10a) is set to a value for the time limit 132a and the status 134a is valid.
- the time limit 132a of the timer event 130a of the watch tick timer and the time limit 161a of the timer event 160a of the host process 1 (150a) come first in the time limit 132a of the timer event 130a of the watch tick timer. To do. Therefore, the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) is set with a time limit 132a of the timer event 130a of the clock tick timer.
- FIG. 7 is a graph showing the relationship between the timer event deadline and the remaining counter 41 of the interrupt timer 40 of the physical CPU 10 in the timer sharing mode.
- FIG. 8A is a flowchart illustrating an example of a process of updating the remaining counter of the interrupt timer 230a of the virtual CPU 210a in the physical CPU 10a in the timer sharing mode.
- the guest operating system 201 running on the virtual CPU 0 requests a value update from the remaining counter 231a of the interrupt timer 230a (step 601).
- the virtual machine monitor 100 traps an update request for the remaining counter 231a of the virtual CPU 210a and transfers control to the timer management unit 120 (step 602).
- the virtual machine monitor 100 may activate the timer management unit 120 at this point.
- the timer management unit 120 sets the value requested to be updated in the remaining counter 231a of the interrupt timer 230a of the virtual CPU 210a (step 603).
- the timer management unit 120 reads the value of the system time counter 81 at the system time 80 and acquires the current time. Then, the timer management unit 120 sets the acquired current time to the remaining counter update time 241a of the timer event 240a associated with the virtual CPU 0 (210a), and based on the following formula A, the time limit 242a of the timer event 240a Is updated (step 604).
- Time limit (242a) of timer event (240a) Current time + (remaining counter (231a) of interrupt timer (230a) ⁇ System time frequency (82)) / Interrupt timer frequency (232a) (Formula A)
- the virtual CPU 210 operates at the same frequency before and after the migration.
- the frequency of the physical CPU 10 depends on the physical computer 1, it may be different before and after the migration.
- the timer frequency 42 of the interrupt timer 40 of the physical CPU 10 and the timer frequency 232 of the interrupt timer 230 of the virtual CPU 210 often differ.
- the above equation A or the like allows the virtual CPU 210 to dynamically occupy the interrupt timer 40 of the physical CPU 10 in consideration of the above-described difference in timer frequency.
- the timer management unit 120 sets the status 243a of the timer event 240a to be valid and inserts it into the timer queue 122a (step 605).
- the timer management unit 120 compares the timer event deadlines in the timer queue 122a and rearranges them in ascending order (in the order of early deadlines) on the time axis of the system time 80.
- the timer management unit 120 compares the deadlines in the timer queue 122a as described above, and determines that the deadline 242a of the timer event 240a is closer to the deadline than the deadline 161a of the timer event 160a. 240a is moved to the head of the timer queue 122a.
- the timer management unit 120 When the timer management unit 120 finishes inserting the timer event 160a into the timer queue 122a, the timer management unit 120 compares the time limit 242a of the timer event 240a at the head of the timer queue 122a with the time limit 132a of the timer event 130a of the clock tick timer. The timer management unit 120 acquires the time limit of the timer event that is closest, as the latest time limit (step 606).
- the timer management unit 120 reads the system time counter 81 of the system time 80, acquires the current time, and calculates the remaining time by subtracting the current time from the latest time limit. Then, the timer management unit 120 converts the remaining time until the deadline to the count number (remaining count) of the interrupt timer 40a by the following equation B.
- the timer management unit 120 sets the value (remaining count) calculated by Expression B in the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) (step 607).
- Remaining count (remaining time x interrupt timer frequency 42a) / System time frequency 82a (Formula B)
- timer event 130a of the clock tick timer is always valid in the conventional virtual computer system except for a temporary case when the time limit 132a of the timer event 130a is updated. Therefore, even if the timer queue 122a is empty, the interrupt timer 40a of the physical CPU 0 (10a) does not stop, and the interrupt controller 30a continues to generate timer interrupts at least at a constant cycle.
- the guest OS 201 can determine that the update processing related to the remaining counter 231a of the interrupt timer 230a of the virtual CPU 210a has been completed.
- FIG. 8B is the first half of a flowchart showing an example of timer interrupt transmission processing of the virtual CPU 210 in the physical CPU 10 in the timer sharing mode.
- FIG. 8C is the second half of the flowchart showing an example of the transmission process.
- the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) is updated by the processing of FIG. 8A, the remaining counter 41a starts subtraction with a period of the frequency 42a.
- the interrupt controller 30a When the value of the remaining counter 41a becomes zero, the interrupt controller 30a generates a timer interrupt and notifies the physical CPU0 (10a) (step 620). The timer interrupt is transmitted to the virtual machine monitor 100, and the virtual machine monitor 100 activates the timer management unit 120 (step 621). If the timer management unit 120 has already been activated, the virtual machine monitor 100 starts control of the timer management unit 120.
- the timer management unit 120 reads the system time counter 81 of the system time 80 and acquires the current time (step 622). The timer management unit 120 determines whether or not the timer queue 122a of the physical CPU 0 (10a) is empty (step 623). If the timer queue 122a is not empty, the process proceeds to step 624, and if it is empty, the process proceeds to step 631 in FIG. 8C.
- the timer management unit 120 refers to the timer queue 122a and compares the time limit of the first timer event with the current time (step 624). Then, the timer management unit 120 determines whether or not the time limit of the top timer event in the timer queue 122a has passed the current time.
- step 625 If the time limit of the first timer event in the timer queue 122a has passed the current time, the process proceeds to step 625. If the time limit of the timer event has not passed the current time, the process proceeds to step 631 in FIG. 8C.
- step 625 since the time limit of the first timer event has passed the current time, the timer management unit 120 retrieves the timer event from the timer queue 122a and invalidates the status 243.
- step 626 the timer management unit 120 determines whether or not the timer event extracted in step 625 is the timer event 240a of the virtual CPU 210a. If it is the timer event 240a of the virtual CPU 210a, the process proceeds to step 626. Otherwise, the process proceeds to step 628.
- step 627 since it is the timer event 240a of the virtual CPU 0 (210a), the timer management unit 120 notifies the virtual CPU 0 (210a) of a timer interrupt.
- the virtual CPU 0 (210a) executes a predetermined process corresponding to the timer event 240a.
- step 628 the timer management unit 120 determines whether the timer event extracted in step 625 is the timer event 160a of the host process 1 and the time limit 161a has passed (execution start). If the time limit 161a has passed, the process proceeds to step 629; otherwise, the process proceeds to step 629; otherwise, the process proceeds to step 631 in FIG. 8C.
- step 629 processing of the host process 150a requested by the timer event 160a is executed.
- step 630 the timer management unit 120 determines whether the timer queue 122a is empty or whether the time limit of the first timer event in the timer queue 122a is later than the current time. If the timer queue 122a is not empty or the time limit of the first timer event is before the current time, the process returns to step 624 and the above processing is repeated. Otherwise, the process proceeds to step 631 in FIG. 8C.
- step 624 and subsequent steps the timer management unit 120 repeats the above processing until the timer queue 122a is empty or the time limit of the first timer event in the timer queue 122a is later than the current time.
- step 631 of FIG. 8C the timer management unit 120 compares the time limit 132a of the timer event 130a of the clock tick timer of the physical CPU 0 (10a) with the current time (step 631). The timer management unit 120 proceeds to step 632 if the time limit 132a of the timer event 130a has passed, and proceeds to step 634 otherwise.
- step 634 If the current time has passed the deadline 132a of the timer event 130a, the processing requested by the clock tick timer is executed (step 632).
- the timer management unit 120 updates the time limit 132a of the timer event 130a by the following formula C (step 633).
- Due date (132a) Start time 131a + ((Period 133a + current time-start time 131a) / Period 133a) x period 133a (formula C)
- the timer management unit 120 determines the time limit of the top timer event of the timer queue 122a of the physical CPU 0 (10a) and the time of the clock tick timer.
- the expiration date 132a of the timer event 130a is compared to obtain the closest expiration date (step 634).
- the timer management unit 120 converts the acquired unit of the deadline into a count number in the same manner as in the above formula B, and sets it to the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) (step 635).
- the timer management unit 120 notifies the computer resource corresponding to the timer event of the timer interrupt generated by the interrupt controller 30a, and executes the processing corresponding to the timer event. it can.
- the timer management unit 120 can notify the virtual CPU 210a of a timer interrupt and execute a predetermined process.
- the timer management unit 120 can set a new deadline in the remaining counter 41a of the interrupt timer 40a of the physical CPU 10 and prepare for the next timer interrupt.
- FIG. 9A is a flowchart showing an example of a process of updating the remaining counter of the interrupt timer of the virtual CPU 210a in the physical CPU 10a in the timer occupation mode.
- FIG. 9B is a flowchart illustrating an example of a timer interrupt transmission process of the interrupt timer 230a of the virtual CPU 210a in the physical CPU 10a in the timer occupation mode.
- the virtual machine monitor 100 sets the interrupt timer 40a to the state of the interrupt timer 230a of the virtual CPU 0 (210a) as it is.
- the guest operating system 201 operating above is recognized.
- the guest operating system 201 running on the virtual CPU 0 issues a request to write a value to the remaining counter 231a of the interrupt timer 230a (step 650).
- the timer management unit 120 of the virtual machine monitor 100 traps the write request of the guest operating system 201 and writes the value of the remaining counter 231a directly into the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) (step 651).
- the timer management unit 120 writes the value of the remaining counter 231a as it is in the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a).
- the interrupt controller 30a when the value is written, the remaining counter 41a starts subtraction with a period of the frequency 42a. Then, when the subtraction is repeated and the remaining counter 41a becomes zero, the interrupt controller 30a generates a timer interrupt and notifies the physical CPU0 (10a) (step 652). When receiving the timer interrupt, the virtual machine monitor 100 directly transmits the interrupt to the virtual CPU 0 (210a) (step 653).
- the timer management unit 120 can directly notify the virtual CPU 210a of the timer interrupt generated by the interrupt controller 30a and execute the process according to the timer event.
- FIGS. 10A and 10B an example in which the physical CPU 0 (10a) is switched from the CPU sharing mode (timer sharing mode) to the CPU occupying mode (timer occupying mode) by switching from FIG. 4A to FIG. 4B is shown in FIGS. 10A and 10B.
- FIG. 10A is the first half of a flowchart showing an example of dynamic change processing in the timer scheduling mode 121 of the interrupt timer of the physical CPU 10a.
- FIG. 10B is the latter half of the flowchart of the dynamic change process of the timer scheduling mode of the interrupt timer of the physical CPU.
- the virtual CPU 0 (210a) of the virtual machine 1 (200a), the virtual CPU 0 (210a) of the virtual machine 2 (200b), and the host process 1 (150a) is operating.
- FIG. 4B after switching to the CPU occupation mode, the virtual CPU 0 (210a) and the host process 1 (150a) of the virtual machine 2 (200b) are moved to the physical CPU 2 (10c).
- the virtual machine monitor 100 when the virtual machine monitor 100 switches the physical CPU 0 (10a) from the CPU sharing mode to the CPU occupation mode, it sets the scheduling mode switching request 123a of the interrupt timer 40a (step 660).
- the interrupt controller 30a of the physical CPU 0 (10a) generates a timer interrupt when the timer event currently being counted by the interrupt timer 40a reaches zero.
- the virtual machine monitor 100 receives a timer interrupt from counting up the interrupt timer 40a from the interrupt controller 30a (step 661).
- the interrupt timer 40a of the physical CPU 0 (10a) stops counting by the interval timer function because a new value is not set after the occurrence of the interrupt (step 662).
- the virtual machine monitor 100 activates the timer management unit 120.
- the timer management unit 120 executes the processing from step 622 to step 633 in FIGS. 8B and 8C described above. However, the timer management unit 120 does not execute the update process of the remaining counter 41a of the interrupt timer 40a of the physical CPU 10a (step 663). In the timer management unit 120, the interrupt timer 40a executes the above-described processing in the timer sharing mode.
- the timer management unit 120 determines whether or not the scheduling mode switching request 123a is set (step 664). When the scheduling mode switching request 123a is set, the process proceeds to step 665 in FIG. 10B, and when the scheduling mode switching request 123a is not set, the process proceeds to step 674.
- the timer management unit 120 first clears the scheduling mode switching request 123a (step 665). Next, the timer management unit 120 changes the timer scheduling mode 121a of the interrupt timer 40a to the timer occupation mode (step 666).
- the timer management unit 120 determines whether or not the timer event 240a of the virtual CPU 0 (210a) that occupies the physical CPU 0 (10a) is inserted in the timer queue 122a (step 667). If the timer event 240a is inserted in the timer queue 122a, the timer management unit 120 takes out the timer event 240a (step 668).
- the timer management unit 120 moves all timer events inserted in the timer queue 122a to the physical CPUs 10b to 10d in the CPU sharing mode (step 669).
- the timer event 240c of the virtual CPU 0 of the virtual machine 2 and the timer event 160a of the host process 1 in the timer queue 122a of the physical CPU 0 and the timer queue of the physical CPU 2 in the timer sharing mode as shown in FIG. Move to 122c.
- the timer management unit 120 invalidates the status 134a of the timer event 130a of the clock tick timer of the physical CPU 0 (10a) and stops the timer event 130a (step 670).
- the timer management unit 120 determines whether or not it is valid by referring to the status 243a of the timer event 240a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) taken out from the timer queue 122a in Step 668. (Step 671). If the status 243a is valid, the process proceeds to step 671. If the status 243a is invalid, the process is terminated.
- the timer management unit 120 invalidates the status 243a of the timer event 240a (step 672).
- the timer management unit 120 acquires the current time from the system time counter 81 at the system time 80, and converts the time limit 242a of the timer event 240a into the remaining count according to the following equation D.
- the timer management unit 120 sets the calculated remaining count in the remaining counter 41a of the interrupt timer 40a (step 673) and occupies the interrupt timer 40a of the physical CPU 0 (10a) by the interrupt timer 230a of the virtual CPU 0 (210a). To start.
- step 664 if it is determined in step 664 that the scheduling mode switching request 123a is not set, the timer management unit 120 executes the processing in steps 634 and 635 in FIGS. 674). Specifically, the timer management unit 120 updates the remaining counter 41a of the interrupt timer 40a of the physical CPU 10a and ends the process.
- the scheduling mode of the interrupt timer 40a can be dynamically switched from the timer sharing mode to the timer occupation mode as the physical CPU 0 (10a) in the CPU sharing mode is shifted to the CPU occupation mode.
- the interrupt timer 40a has an interval function to stop counting if a new value is not set after the timer counts up.
- the timer sharing mode is shifted to the timer occupation mode with the interrupt timer 40a stopped. This makes it possible to dynamically change the occupation mode of the interrupt timer 40a after reliably completing the timer event that has already started counting.
- the timer event 240a of the virtual CPU 0 (210a) set in the shared mode is invalidated in the above-described step 672, so that the interrupt timer 40a stops counting. Maintain state.
- FIG. 10C is a flowchart of the dynamic change process in the timer scheduling mode 121 of the interrupt timer 40 of the physical CPU 10.
- the above shows an example in which the virtual CPU 0 (210a) and the host process 1 (150a) of the virtual machine 2 (200b) return to the physical CPU 0 (10a) by load balancing thereafter.
- the virtual machine monitor 100 sets the scheduling mode switching request 123a of the interrupt timer 40a (step 680).
- the interrupt controller 30a of the physical CPU 0 (10a) generates a timer interrupt when the count of the timer event (remaining counter 41a) currently being counted by the interrupt timer 40a becomes zero.
- the virtual machine monitor 100 receives a timer interrupt from the interrupt controller 30a by counting up the interrupt timer 40a (step 681).
- the interrupt timer 40a of the physical CPU 0 (10a) stops counting by the above interval function (step 682) because a new value is not set after the interrupt occurs.
- the virtual machine monitor 100 transmits a timer interrupt directly to the virtual CPU 0 (210a), similarly to step 653 shown in FIG. 9B (step 683).
- the virtual machine monitor 100 determines whether or not the scheduling mode switching request 123a of the interrupt timer 40a of the physical CPU 0 (10a) is set (step 684). If the scheduling mode switching request 123a is set, the process proceeds to step 685, and if not set, the process is terminated.
- the virtual machine monitor 100 activates the timer management unit 120 (step 685).
- the timer management unit 120 clears the scheduling mode switching request 123a (step 686).
- the timer management unit 120 enables the status 134a of the timer event 130a of the clock tick timer of the physical CPU 0 (10a) and restarts the timer event 130a (step 687).
- the timer management unit 120 updates the time limit 132a of the timer event 130a according to the above (formula A) (step 688).
- the only timer event valid in the physical CPU 0 (10a) is the timer event 130a of the clock tick timer. Therefore, the remaining count is calculated by subtracting the current time acquired by reading the system time counter 81 of the system time 80 from the time limit 132a.
- the timer management unit 120 sets the value calculated by the above (formula B) from the remaining count in the remaining counter 41a of the interrupt timer 40a of the physical CPU 0 (10a) (step 689).
- timer event 240a of the virtual CPU 0 (210a) of the virtual machine 1 (200a) that previously occupied the physical CPU 0 (10a) has been invalidated in the above-described step 671.
- the timer management unit 120 changes the timer scheduling mode 121a of the interrupt timer 40a of the physical CPU 0 (10a) to the timer sharing mode, and the interrupt timer 230a of the virtual CPU 0 (210a) of the interrupt timer 40a of the physical CPU 0 (10a).
- the occupation by is terminated (step 689).
- the scheduling mode of the interrupt timer 40a can be dynamically switched from the timer occupation mode to the timer sharing mode.
- the timer occupation mode is dynamically switched from the timer occupation mode to the timer sharing mode by using the interval function of the interrupt timer 40a. This makes it possible to dynamically change the occupation mode of the interrupt timer 40a after reliably completing the timer event that has already started counting.
- the interrupt timer 40 of the physical CPU 10 can be occupied by the interrupt timer 230 of the virtual CPU 210 in conjunction with the occupation of the physical CPU 10 by the specific virtual CPU 210.
- the overhead of emulation of the interrupt timer of the virtual CPU can be minimized, and the physical timer can be controlled by preventing the TLB and cache data from being expelled by the host timer that occurred regardless of the operation of the program on the virtual CPU. CPU performance can be ensured.
- the interval function of the interrupt timer 40a is used to stop the operation after the interrupt controller 30a generates a timer interrupt and before a value is written to its remaining counter.
- the timer occupation mode and the timer sharing mode of the timer scheduling mode are dynamically switched.
- timer scheduling mode switching linked to the CPU scheduling mode sets the timer sharing mode linked to the CPU sharing mode, and sets the timer occupation mode linked to the CPU occupation mode.
- the clock tick timer that used the interrupt timer 40a is stopped, the timer event 160a of the host process 1 that used the interrupt timer of the physical CPU, a timer for timeout detection, etc.
- the timer event is moved to another physical CPU in the CPU sharing mode.
- the current value of the remaining counter 231a of the interrupt timer 230 of the virtual CPU 210 is written to the remaining counter 41a of the interrupt timer 40a of the physical CPU 10a, thereby starting the occupation of the interrupt timer 40a of the physical CPU 10a by the interrupt timer 230a of the virtual CPU 210.
- the program on the virtual CPU 210 writes a value to the remaining counter 231a of the interrupt timer 230a.
- the write request is trapped in the virtual machine monitor 100.
- the virtual machine monitor 100 writes the write value directly to the remaining counter 41a of the interrupt timer 40a of the physical CPU 10a.
- the interrupt timer 40a of the physical CPU 10a starts subtraction by writing to the remaining counter 41a, and when it reaches zero, the interrupt controller 30a generates a timer interrupt.
- the timer event 130 of the clock tick timer and the timer event 240a of the virtual CPU 210a are invalidated, so that the occurrence of a timer interrupt is suppressed and the performance of the physical CPU 10 is secured by preventing the TLB and cache from being evicted. can do.
- At least one physical CPU 10 is set to the timer sharing mode.
- the timer event 160 of the host process 150 and the timer event 130a of the clock tick timer can be reliably executed, and the timer for time-out detection and the clock tick timer can be continuously operated.
- the interrupt controller 30a when the physical CPU 10a is dynamically switched from the CPU exclusive mode to the CPU shared mode, the interrupt controller 30a generates a timer interrupt by counting up the interrupt timer 40a of the physical CPU 10a, and then stops counting by the interval function. Use.
- the virtual machine monitor 100 When receiving a timer interrupt from the interrupt controller 30a of the physical CPU 10a, the virtual machine monitor 100 directly transmits the timer interrupt to the virtual CPU 210.
- the virtual machine monitor 100 stops the interrupt timer 230a of the virtual CPU 210 by setting the remaining counter 231a to zero.
- the virtual machine monitor 100 restarts the timer event 130a of the clock tick timer that used the interrupt timer 40a of the physical CPU 10a, and the physical CPU 10a starts the host process 1 and detects a timeout, and interrupt timers of other virtual CPUs. 40 is permitted, and the occupation of the interrupt timer 40a of the physical CPU 10a by the interrupt timer 230 of the virtual CPU 210 is terminated.
- the interrupt timer 40 of at least one physical CPU 10 is not occupied by the interrupt timer 230 of a specific virtual CPU 210, so that the host process is started or a timeout is detected using the interrupt timer 40 of the physical CPU 10.
- the timer can be continuously operated.
- this invention is not limited to the above-mentioned Example, Various modifications are included.
- the above-described embodiments are described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described.
- a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
- any of the additions, deletions, or substitutions of other configurations can be applied to a part of the configuration of each embodiment, either alone or in combination.
- each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit.
- each of the above-described configurations, functions, and the like may be realized by software by the processor interpreting and executing a program that realizes each function.
- Information such as programs, tables, and files that realize each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.
- control lines and information lines indicate what is considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.
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Abstract
Description
= 現在時刻 +(割り込みタイマ(230a)の残りカウンタ(231a)
× システム時刻周波数(82))/ 割り込みタイマ周波数(232a) (式A)
/ システム時刻周波数82a (式B)
= 開始時刻131a
+((周期133a + 現在時刻 - 開始時刻131a)
/ 周期133a)× 周期133a (式C)
=(期限(242a) - 現在時刻)× タイマ周波数(42a)
/ システム時刻周波数(82)
(式D)
Claims (14)
- 割り込みタイマを含む割り込みコントローラと、前記割り込みコントローラを含む物理プロセッサと、前記物理プロセッサと物理メモリを含む物理計算機と、前記物理計算機の計算機資源を複数の仮想計算機に割り当てる仮想化部とを含む仮想計算機システムで、前記仮想化部が前記物理プロセッサの割り当てを制御する仮想計算機システムの制御方法であって、
前記仮想化部が、前記割り込みタイマを仮想化した仮想割り込みタイマと、前記割り込みコントローラを仮想化した仮想割り込みコントローラとを含む前記物理プロセッサの計算機資源を割り当てた仮想プロセッサと、前記物理メモリの計算機資源を割り当てた仮想メモリとを生成し、前記複数の仮想計算機を生成する第1のステップと、
前記仮想化部が、前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、複数の前記仮想プロセッサで共有するプロセッサ共有モードと、前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、特定の仮想プロセッサで占有するプロセッサ占有モードと、のいずれか一方のプロセッサスケジューリングモードを設定する第2のステップと、
前記仮想化部が、前記プロセッサ共有モードとプロセッサ占有モードの何れか一方を設定した前記物理プロセッサの割り込みタイマを、複数の仮想計算機のタイマイベントで共有するタイマ共有モードと、前記特定の仮想プロセッサの仮想タイマで占有するタイマ占有モードの何れか一方のタイマスケジューリングモードを前記プロセッサスケジューリングモードに連動して設定する第3のステップと、
を含むことを特徴とする仮想計算機システムの制御方法。 - 請求項1に記載の仮想計算機システムの制御方法であって、
前記仮想化部が、前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ共有モードとプロセッサ占有モードとの間で切り替える第4のステップと、
前記仮想化部が、前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを切り替える第5のステップと、
をさらに含むことを特徴とする仮想計算機システムの制御方法。 - 請求項2に記載の仮想計算機システムの制御方法であって、
前記第2のステップは、
前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、複数の前記仮想プロセッサで共有するプロセッサ共有モードに設定し、
前記第3のステップは、
前記プロセッサ共有モードの前記プロセッサスケジューリングモードに連動して、前記物理プロセッサの割り込みタイマを、複数の仮想計算機のタイマイベントで共有するタイマ共有モードに設定し、
前記第4のステップは、
前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ共有モードから前記プロセッサ占有モードに切り替えて、
前記第5のステップは、
前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを前記タイマ共有モードから前記タイマ占有モードへ切り替えることを特徴とする仮想計算機システムの制御方法。 - 請求項2に記載の仮想計算機システムの制御方法であって、
前記第2のステップは、
前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、特定の前記仮想プロセッサで占有するプロセッサ占有モードに設定し、
前記第3のステップは、
前記プロセッサ占有モードの前記プロセッサスケジューリングモードに連動して、前記物理プロセッサの割り込みタイマを、前記特定の仮想プロセッサの仮想タイマで占有するタイマ占有モードに設定し、
前記第4のステップは、
前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ占有モードから前記プロセッサ共有モードに切り替えて、
前記第5のステップは、
前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを前記タイマ占有モードから前記タイマ共有モードへ切り替えることを特徴とする仮想計算機システムの制御方法。 - 請求項3に記載の仮想計算機システムの制御方法であって、
前記第5のステップは、
前記タイマ共有モードで前記物理プロセッサの割り込みタイマに設定されていたタイマイベントを、前記タイマ共有モードに設定された他の物理プロセッサへ移動させてからタイマ占有モードへ切り替えることを特徴とする仮想計算機システムの制御方法。 - 請求項3に記載の仮想計算機システムの制御方法であって、
前記物理プロセッサの割り込みコントローラは、タイマ割り込みの発生後に前記割り込みタイマへ新たな値を書き込むまでカウントを停止し、
前記第5のステップは、
前記タイマ共有モードからタイマ占有モードへ切り替える前記物理プロセッサの割り込みコントローラがタイマ割り込みを発生した後に、前記タイマ共有モードからタイマ占有モードへの前記タイマスケジューリングモードの切り替えを実行することを特徴とする仮想計算機システムの制御方法。 - 請求項3に記載の仮想計算機システムの制御方法であって、
前記プロセッサ共有モードでは、前記複数の仮想プロセッサで物理プロセッサを時分割共有するために所定の周期でタイマ割り込みを発生する時計チックタイマを前記タイマイベントに含み、
前記第5のステップは、
前記タイマ共有モードからタイマ占有モードへ切り替える前記物理プロセッサの前記割り込みタイマの時計チックタイマのタイマイベントを無効にした後に、前記タイマ共有モードからタイマ占有モードへの前記タイマスケジューリングモードの切り替えを実行することを特徴とする仮想計算機システムの制御方法。 - 割り込みタイマを含む割り込みコントローラと、
前記割り込みコントローラを含む物理プロセッサと、
前記物理プロセッサと物理メモリを含む物理計算機と、
前記物理計算機の計算機資源を複数の仮想計算機に割り当てる仮想化部とを含む仮想計算機システムであって、
前記仮想化部は、
前記割り込みタイマを仮想化した仮想割り込みタイマと、前記割り込みコントローラを仮想化した仮想割り込みコントローラとを含む前記物理プロセッサの計算機資源を割り当てた仮想プロセッサと、前記物理メモリの計算機資源を割り当てた仮想メモリとを含む前記複数の仮想計算機を生成し、
前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、複数の前記仮想プロセッサで共有するプロセッサ共有モードと、前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、特定の仮想プロセッサで占有するプロセッサ占有モードと、のいずれか一方のプロセッサスケジューリングモードを設定し、
前記プロセッサ共有モードとプロセッサ占有モードの何れか一方を設定した前記物理プロセッサの割り込みタイマを、複数の仮想計算機のタイマイベントで共有するタイマ共有モードと、前記特定の仮想プロセッサの仮想タイマで占有するタイマ占有モードの何れか一方のタイマスケジューリングモードを前記プロセッサスケジューリングモードに連動して設定することを特徴とする仮想計算機システム。 - 請求項8に記載の仮想計算機システムであって、
前記仮想化部は、
前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ共有モードとプロセッサ占有モードとの間で切り替え、
前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを切り替えることを特徴とする仮想計算機システム。 - 請求項9に記載の仮想計算機システムであって、
前記仮想化部は、
前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、複数の前記仮想プロセッサで共有するプロセッサ共有モードに設定し、
前記プロセッサ共有モードの前記プロセッサスケジューリングモードに連動して、前記物理プロセッサの割り込みタイマを、複数の仮想計算機のタイマイベントで共有するタイマ共有モードに設定し、
前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ共有モードから前記プロセッサ占有モードに切り替えて、
前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを前記タイマ共有モードから前記タイマ占有モードへ切り替えることを特徴とする仮想計算機システム。 - 請求項9に記載の仮想計算機システムであって、
前記仮想化部は、
前記複数の仮想計算機に割り当てた物理プロセッサのうちのひとつを、特定の前記仮想プロセッサで占有するプロセッサ占有モードに設定し、
前記プロセッサ占有モードの前記プロセッサスケジューリングモードに連動して、前記物理プロセッサの割り込みタイマを、前記特定の仮想プロセッサの仮想タイマで占有するタイマ占有モードに設定し、
前記物理プロセッサの前記プロセッサスケジューリングモードをプロセッサ占有モードから前記プロセッサ共有モードに切り替えて、
前記プロセッサスケジューリングモードに連動して前記タイマスケジューリングモードを前記タイマ占有モードから前記タイマ共有モードへ切り替えることを特徴とする仮想計算機システム。 - 請求項10に記載の仮想計算機システムであって、
前記仮想化部は、
前記タイマ共有モードで前記物理プロセッサの割り込みタイマに設定されていたタイマイベントを、前記タイマ共有モードに設定された他の物理プロセッサへ移動させてからタイマ占有モードへ切り替えることを特徴とする仮想計算機システム。 - 請求項10に記載の仮想計算機システムであって、
前記物理プロセッサの割り込みコントローラは、タイマ割り込みの発生後に前記割り込みタイマへ新たな値を書き込むまでカウントを停止し、
前記タイマ共有モードからタイマ占有モードへ切り替える前記物理プロセッサの割り込みコントローラがタイマ割り込みを発生した後に、前記タイマ共有モードからタイマ占有モードへの前記タイマスケジューリングモードの切り替えを実行することを特徴とする仮想計算機システム。 - 請求項10に記載の仮想計算機システムであって、
前記プロセッサ共有モードでは、前記複数の仮想プロセッサで物理プロセッサを時分割共有するために所定の周期でタイマ割り込みを発生する時計チックタイマを前記タイマイベントに含み、
前記タイマ共有モードからタイマ占有モードへ切り替える前記物理プロセッサの前記割り込みタイマの時計チックタイマのタイマイベントを無効にした後に、前記タイマ共有モードからタイマ占有モードへの前記タイマスケジューリングモードの切り替えを実行することを特徴とする仮想計算機システム。
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