WO2016063501A1 - Dispositif semiconducteur et élément émetteur de lumière ultraviolette - Google Patents

Dispositif semiconducteur et élément émetteur de lumière ultraviolette Download PDF

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WO2016063501A1
WO2016063501A1 PCT/JP2015/005210 JP2015005210W WO2016063501A1 WO 2016063501 A1 WO2016063501 A1 WO 2016063501A1 JP 2015005210 W JP2015005210 W JP 2015005210W WO 2016063501 A1 WO2016063501 A1 WO 2016063501A1
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layer
electrode
semiconductor device
contact
nitride semiconductor
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English (en)
Japanese (ja)
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後藤　浩嗣
安田　正治
村井　章彦
卓哉 美濃
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パナソニックＩｐマネジメント株式会社
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Priority to JP2016555075A priority Critical patent/JP6331204B2/ja
Publication of WO2016063501A1 publication Critical patent/WO2016063501A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and an ultraviolet light emitting element, and more particularly to a semiconductor device and an ultraviolet light emitting element including an AlGaN layer and an electrode formed on the surface of the AlGaN layer.
  • a semiconductor device using a group III nitride semiconductor As a semiconductor device using a group III nitride semiconductor, a light emitting device typified by a light emitting diode, an electronic device typified by a high electron mobility transistor, and the like have been researched and developed in various places. Recently, high expectations have been placed on ultraviolet light emitting devices using group III nitride semiconductors in fields such as high-efficiency white illumination, sterilization, medical treatment, and applications for treating environmental pollutants at high speed.
  • a semiconductor device As a semiconductor device, a laminated film of an n-type layer, a light emitting layer, and a p-type layer has a mesa structure, an n-electrode provided on the exposed surface of the n-type layer, and a p-type layer
  • An ultraviolet semiconductor light emitting device including a p-electrode provided on the surface side is known (for example, Document 1 [Japanese Patent Application Publication No. 2014-96460]).
  • the n-type layer is composed of an n-type Al z Ga 1 -z N (0 ⁇ z ⁇ 1) layer.
  • An object of the present invention is to provide a semiconductor device and an ultraviolet light emitting element capable of improving moisture resistance.
  • the semiconductor device includes an AlGaN layer, an electrode, an insulating film, and a passivation film.
  • the electrode includes a contact electrode formed on the surface of the AlGaN layer and a pad electrode formed on the surface side of the contact electrode.
  • the insulating film is formed on the surface of the AlGaN layer so as to surround a contact region of the contact electrode with the AlGaN layer.
  • the passivation film is formed on at least the pad electrode, and an opening that exposes the central portion of the pad electrode is formed.
  • the pad electrode is formed across the contact electrode and the insulating film in a plan view.
  • the electrode includes an Al layer that includes the opening in a plan view below the pad electrode.
  • An ultraviolet light-emitting device includes a substrate, and a nitride semiconductor layer formed on one surface side of the substrate and having an n-type nitride semiconductor layer, a light-emitting layer, and a p-type nitride semiconductor layer in that order from the one surface side.
  • a positive electrode formed on the surface of the p-type nitride semiconductor layer, a negative electrode formed on an exposed surface of the n-type nitride semiconductor layer, an insulating film, and a passivation film.
  • the light emitting layer is configured to emit light having a light emission wavelength in the ultraviolet wavelength range.
  • the positive electrode includes a first contact electrode formed on the surface of the p-type nitride semiconductor layer and a first pad electrode formed on the surface side of the first contact electrode.
  • the negative electrode includes a second contact electrode formed on the surface of the AlGaN layer in the n-type nitride semiconductor layer, and a second pad electrode formed on the surface side of the second contact electrode.
  • the insulating film is formed on a surface of the p-type nitride semiconductor layer and a surface of the AlGaN layer, and a second contact hole exposing the first contact electrode and a second contact electrode is exposed. Contact holes are formed.
  • the passivation film is formed on at least the second pad electrode, and an opening for exposing a central portion of the second pad electrode is formed.
  • the second pad electrode is formed across the second contact electrode and the insulating film in plan view.
  • the negative electrode includes an Al layer including the opening in a plan view below the second pad electrode.
  • FIG. 1 is a schematic cross-sectional view of the semiconductor device of the embodiment.
  • FIG. 2 is a schematic plan view of the semiconductor device of the embodiment.
  • FIG. 3 is a schematic cross-sectional view of a main part of the semiconductor device of the embodiment.
  • FIG. 4 is a schematic diagram of a solidified structure in the semiconductor device of the embodiment.
  • FIG. 5 is an optical micrograph obtained by observing the electrode of the semiconductor device of the embodiment from the second surface side of the substrate.
  • FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a first modification of the embodiment.
  • FIG. 7 is a schematic cross-sectional view of a semiconductor device according to a second modification of the embodiment.
  • FIGS. 1 is a schematic cross-sectional view taken along the line XX in FIG.
  • the semiconductor device 100 includes an AlGaN layer 31, an electrode 90, an insulating film 10, and a passivation film 11.
  • the electrode 90 includes a contact electrode 91 formed on the surface 31 a of the AlGaN layer 31 and a pad electrode 92 formed on the surface side of the contact electrode 91.
  • the insulating film 10 is formed on the surface 31 a of the AlGaN layer 31 so as to surround the contact region of the contact electrode 91 with the AlGaN layer 31.
  • the passivation film 11 is formed so as to cover the insulating film 10 and the end portion of the pad electrode 92, and an opening 13 exposing the central portion of the pad electrode 92 is formed.
  • the pad electrode 92 is formed across the contact electrode 91 and the insulating film 10 in plan view.
  • the electrode 90 includes an Al layer 93 including the opening 13 in a plan view below the pad electrode 92.
  • the semiconductor device 100 can improve moisture resistance.
  • “Below the pad electrode 92” means that the AlGaN layer 31 is positioned closer to the AlGaN layer 31 than the pad electrode 92 in the direction along the thickness direction of the AlGaN layer 31.
  • an Al layer 93 having a larger planar size than the opening size of the opening 13 is provided between the pad electrode 92 and the AlGaN layer 31.
  • Al layer 93 including opening 13 in plan view means a vertical projection region of Al layer 93 whose projection direction is along the thickness direction of AlGaN layer 31 (that is, perpendicular to the thickness direction of AlGaN layer 31). This means that the opening 13 is included in the vertical projection area onto the surface to be projected.
  • the semiconductor device 100 of this embodiment is an ultraviolet light emitting element. More specifically, the semiconductor device 100 has an n-type nitride semiconductor layer 3 having at least an AlGaN layer 31 and an emission wavelength in the ultraviolet wavelength region (ultraviolet wavelength region) formed on the n-type nitride semiconductor layer 3. A light emitting layer 4 that emits light and a p-type nitride semiconductor layer 5 formed on the light emitting layer 4 are provided. Thereby, the semiconductor device 100 can constitute an ultraviolet light emitting element. Therefore, the ultraviolet light emitting element which is the semiconductor device 100 of the present embodiment can improve moisture resistance.
  • the semiconductor device 100 is formed on the substrate 1 and one surface (hereinafter also referred to as “first surface”) 1a side of the substrate 1, and the n-type nitride semiconductor layer 3, the light emitting layer 4 and p are sequentially formed from the first surface 1a side.
  • Nitride semiconductor layer 20 having type nitride semiconductor layer 5.
  • the semiconductor device 100 includes a positive electrode 8 formed on the surface 5a of the p-type nitride semiconductor layer 5 and a negative electrode 9 formed on the exposed surface 3a of the n-type nitride semiconductor layer 3.
  • the exposed surface 3 a of the n-type nitride semiconductor layer 3 is a part of the nitride semiconductor layer 20 in the depth direction of the n-type nitride semiconductor layer 3 from the surface 5 a side of the p-type nitride semiconductor layer 5. It means the surface exposed by removing up to.
  • the exposed surface 3 a of the n-type nitride semiconductor layer 3 is configured by the surface 31 a of the AlGaN layer 31, and the negative electrode 9 is configured by the electrode 90.
  • the nitride semiconductor layer 20 is formed on the first surface 1 a side of the substrate 1 as described above.
  • the second surface 1b opposite to the first surface 1a of the substrate 1 preferably constitutes a light extraction surface.
  • the chip size of the semiconductor device 100 is set to 400 ⁇ m ⁇ (400 ⁇ m ⁇ 400 ⁇ m), but is not limited thereto.
  • the chip size can be appropriately set within a range of, for example, about 200 ⁇ m ⁇ (200 ⁇ m ⁇ 200 ⁇ m) to 1 mm ⁇ (1 mm ⁇ 1 mm).
  • the planar shape of the semiconductor device 100 is not limited to a square shape, and may be, for example, a rectangular shape. When the planar shape of the semiconductor device 100 is rectangular, the chip size of the semiconductor device 100 can be set to, for example, 500 ⁇ m ⁇ 240 ⁇ m.
  • the semiconductor device 100 can be, for example, an ultraviolet light emitting diode having an emission wavelength (emission peak wavelength) in the ultraviolet wavelength region of 210 nm to 280 nm.
  • the semiconductor device 100 can be used in fields such as high-efficiency white illumination, sterilization, medical treatment, and uses for treating environmental pollutants at high speed.
  • an ultraviolet light emitting element such as an ultraviolet light emitting diode
  • the semiconductor device 100 preferably has an emission wavelength in the UV-C wavelength region.
  • the wavelength range of UV-C is, for example, 100 nm to 280 nm according to the classification by the wavelength of ultraviolet rays in the International Commission on Illumination (CIE).
  • the “emission peak wavelength” is a main emission peak wavelength at room temperature (27 ° C.).
  • the substrate 1 can be constituted by, for example, a sapphire substrate whose first surface 1a is a (0001) surface. That is, the substrate 1 can be constituted by a c-plane sapphire substrate ( ⁇ -Al 2 O 3 substrate).
  • the sapphire substrate preferably has an off angle from the (0001) plane of 0 to 0.4 °.
  • the semiconductor device 100 preferably includes a buffer layer 2 between the substrate 1 and the n-type nitride semiconductor layer 3.
  • the buffer layer 2 is preferably formed on the first surface 1a of the substrate 1, and the n-type nitride semiconductor layer 3 is preferably formed on the buffer layer 2.
  • the buffer layer 2 is configured by an Al y Ga 1-y N (0 ⁇ y ⁇ 1) layer.
  • the buffer layer 2 is preferably composed of an AlN layer.
  • the buffer layer 2 is a layer provided for the purpose of reducing threading dislocations. If the buffer layer 2 is too thin, the reduction of threading dislocations tends to be insufficient, and if the thickness is too thick, cracks due to lattice mismatch may occur, or a wafer forming a plurality of semiconductor devices 100 may be formed. There is a possibility that warping becomes too large. Therefore, the thickness of the buffer layer 2 is preferably set in the range of, for example, about 500 nm to 10 ⁇ m, and more preferably set in the range of 1 ⁇ m to 5 ⁇ m. As an example, the thickness of the buffer layer 2 is set to 4 ⁇ m.
  • the n-type nitride semiconductor layer 3 is a layer for transporting electrons to the light emitting layer 4.
  • the n-type nitride semiconductor layer 3 can be composed of, for example, an n-type AlGaN layer 31.
  • the composition ratio of the n-type AlGaN layer 31 constituting the n-type nitride semiconductor layer 3 is preferably set so that ultraviolet rays emitted from the light-emitting layer 4 can be efficiently emitted.
  • the Al composition ratio of the well layer is 0.5
  • the Al composition ratio of the barrier layer is 0.7.
  • the Al composition ratio of the AlGaN layer 31 of the mold can be set to 0.7, which is the same as the Al composition ratio of the barrier layer. That is, when the well layer of the light emitting layer 4 is composed of an Al 0.5 Ga 0.5 N layer and the barrier layer is composed of an Al 0.7 Ga 0.3 N layer, the n-type nitride semiconductor layer 3 is, for example, an n-type Al 0.7 Ga It can be composed of a 0.3 N layer.
  • the Al composition ratio of the n-type nitride semiconductor layer 3 is not limited to being the same as the Al composition ratio of the barrier layer, and may be different.
  • the n-type nitride semiconductor layer 3 is not limited to a single layer film, and may be formed of, for example, a multilayer film in which a plurality of n-type AlGaN layers having different Al composition ratios are stacked.
  • the thickness of the n-type nitride semiconductor layer 3 is set to 2 ⁇ m.
  • the donor impurity of the n-type nitride semiconductor layer 3 for example, Si is preferable.
  • the electron concentration of the n-type nitride semiconductor layer 3 may be set, for example, in the range of about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 .
  • the light emitting layer 4 is a layer for converting injected carriers (here, electrons and holes) into light.
  • the light emitting layer 4 is a layer that emits ultraviolet rays by recombination of two types of injected carriers (electrons and holes).
  • the light emitting layer 4 preferably has a quantum well structure.
  • the well layer of the quantum well structure is composed of Al a Ga 1-a N (0 ⁇ a ⁇ 1) layer, and the barrier layer of the quantum well structure is Al b Ga 1-b N (0 ⁇ It is preferable that b ⁇ 1 and b> a) layers.
  • the light emitting layer 4 having a well layer made of Al a Ga 1-a N (0 ⁇ a ⁇ 1) layer has an emission wavelength in the range of 210 nm to 360 nm by changing the Al composition ratio a of the well layer. It is possible to set an arbitrary emission wavelength. For example, when the desired emission wavelength is around 265 nm, the Al composition ratio a may be set to 0.50.
  • the well layer of the quantum well structure may be composed of an InAlGaN layer.
  • the quantum well structure may be a multiple quantum well structure or a single quantum well structure. If the thickness of the well layer is too large, the light-emitting layer 4 has a spatial characteristic in which electrons and holes injected into the well layer are caused by a piezoelectric field due to lattice mismatch in the quantum well structure. It is assumed that the light emission efficiency is lowered. Further, in the light emitting layer 4, when the thickness of the well layer is too thin, it is presumed that the carrier confinement effect is lowered and the light emission efficiency is lowered. For this reason, the thickness of the well layer is preferably, for example, about 1 nm to 5 nm, and more preferably about 1.3 nm to 3 nm.
  • the thickness of the barrier layer is preferably set in the range of about 5 nm to 15 nm, for example.
  • the thickness of the well layer is set to 2 nm, and the thickness of the barrier layer is set to 10 nm.
  • the semiconductor device 100 is not limited to a configuration in which the light emitting layer 4 has a quantum well structure.
  • a double layer in which a single light emitting layer 4 is sandwiched between an n-type nitride semiconductor layer 3 and a p-type nitride semiconductor layer 5. It may be a heterostructure.
  • the p-type nitride semiconductor layer 5 has at least a p-type AlGaN layer 52.
  • the p-type nitride semiconductor layer 5 preferably includes, for example, an electron block layer 51, a p-type AlGaN layer 52, and a p-type contact layer 53.
  • the electron blocking layer 51 is preferably provided between the light emitting layer 4 and the p-type AlGaN layer 52.
  • the electron block layer 51 suppresses, among the electrons injected into the light emitting layer 4, electrons that have not been recombined with holes in the light emitting layer 4 from leaking (overflowing) to the p-type AlGaN layer 52 side. Further, it can be suitably provided between the light emitting layer 4 and the p-type AlGaN layer 52.
  • the electron block layer 51 can be composed of a p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer.
  • the Al composition ratio c of the p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer can be set to 0.9, for example.
  • the composition ratio of the p-type Al c Ga 1-c N (0 ⁇ c ⁇ 1) layer is such that the band gap energy of the electron block layer 51 is higher than the band gap energy of the p-type AlGaN layer 52 or the barrier layer. It is preferable to set. As an example, the thickness of the electron blocking layer 51 is set to 30 nm. If the thickness of the electronic block layer 51 is too thin, the effect of suppressing overflow decreases, and if the thickness is too thick, the resistance of the semiconductor device 100 may increase.
  • the thickness of the electron blocking layer 51 varies depending on values such as the Al composition ratio c and the hole concentration. Therefore, the thickness of the electron blocking layer 51 is preferably set in the range of 1 nm to 50 nm. It is more preferable to set within a range of 5 nm to 25 nm.
  • Mg is preferable.
  • the p-type AlGaN layer 52 is a layer for transporting holes to the light emitting layer 4.
  • the p-type AlGaN layer 52 is preferably composed of a p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer.
  • the composition ratio of the p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer is preferably set so that absorption of ultraviolet rays emitted from the light emitting layer 4 can be suppressed.
  • the p-type Al d Ga 1-d N (0 ⁇ d ⁇ 1) layer The Al composition ratio d can be set to 0.7, which is the same as the Al composition ratio b of the barrier layer, for example. That is, when the well layer of the light emitting layer 4 is made of an Al 0.5 Ga 0.5 N layer, the p-type AlGaN layer 52 can be constituted by, for example, a p-type Al 0.7 Ga 0.3 N layer.
  • the Al composition ratio of the p-type AlGaN layer 52 is not limited to the same as the Al composition ratio b of the barrier layer, and may be different.
  • Mg is preferable.
  • the hole concentration of the p-type AlGaN layer 52 is preferably higher in the hole concentration range where the film quality of the p-type AlGaN layer 52 does not deteriorate.
  • the hole concentration of the p-type AlGaN layer 52 is lower than the electron concentration of the n-type nitride semiconductor layer 3 in the semiconductor device 100, if the thickness of the p-type AlGaN layer 52 is too thick, Resistance becomes too large.
  • the thickness of the p-type AlGaN layer 52 is preferably 200 nm or less, and more preferably 100 nm or less. In the semiconductor device 100, as an example, the thickness of the p-type AlGaN layer 52 is set to 50 nm.
  • the semiconductor device 100 can be configured to suitably include the p-type contact layer 53 on the p-type AlGaN layer 52.
  • the p-type contact layer 53 is provided in order to reduce the contact resistance with the positive electrode 8 and obtain good ohmic contact with the positive electrode 8.
  • the p-type contact layer 53 is preferably composed of a p-type GaN layer.
  • the hole concentration of the p-type GaN layer constituting the p-type contact layer 53 is preferably higher than that of the p-type AlGaN layer 52. For example, by setting the hole concentration to about 7 ⁇ 10 17 cm ⁇ 3 , the positive electrode Good ohmic contact with 8 can be obtained.
  • the hole concentration of the p-type GaN layer may be changed as appropriate within the range of the hole concentration at which good ohmic contact with the positive electrode 8 is obtained.
  • the thickness of the p-type contact layer 53 is set to 200 nm. However, the thickness is not limited to this, and may be set, for example, in the range of 50 nm to 300 nm.
  • the semiconductor device 100 can be configured such that the nitride semiconductor layer 20 includes the buffer layer 2, the n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5 as described above.
  • the nitride semiconductor layer 20 may be provided as appropriate for the buffer layer 2, the light emitting layer 4, the electron block layer 51, and the p-type contact layer 53.
  • the nitride semiconductor layer 20 can be formed by an epitaxial growth method.
  • the nitride semiconductor layer 20 may contain impurities such as H, C, O, Si, and Fe that are inevitably mixed when the nitride semiconductor layer 20 is formed.
  • the semiconductor device 100 is removed by etching a part of the nitride semiconductor layer 20 from the surface 20a side of the nitride semiconductor layer 20 to the middle of the n-type nitride semiconductor layer 3. Thereby, the semiconductor device 100 exposes the surface 3 a of the n-type nitride semiconductor layer 3.
  • the semiconductor device 100 has the mesa structure 22 formed by etching a part of the nitride semiconductor layer 20.
  • the positive electrode 8 is formed on the surface 20 a of the nitride semiconductor layer 20, and the negative electrode 9 is formed on the surface 3 a of the n-type nitride semiconductor layer 3.
  • the surface 53 a of the p-type contact layer 53 constitutes the surface 20 a of the nitride semiconductor layer 20.
  • the positive electrode 8 is electrically connected to the p-type nitride semiconductor layer 5.
  • the positive electrode 8 is preferably electrically connected to the p-type AlGaN layer 52 through the p-type contact layer 53.
  • the positive electrode 8 includes a contact electrode 81 (hereinafter also referred to as “first contact electrode 81”) formed on the surface 5 a of the p-type nitride semiconductor layer 5 and a pad formed on the surface side of the contact electrode 81.
  • Electrode 82 (hereinafter also referred to as “first pad electrode 82”).
  • the first pad electrode 82 is formed across the first contact electrode 81 and the insulating film 10 in plan view.
  • the first contact electrode 81 is preferably formed in a shape in which the cross-sectional area gradually decreases with distance from the p-type nitride semiconductor layer 5 in the thickness direction of the p-type nitride semiconductor layer 5. More specifically, the first contact electrode 81 has a tapered side surface, so that the cross-sectional area gradually decreases with increasing distance from the p-type nitride semiconductor layer 5 in the thickness direction of the p-type nitride semiconductor layer 5. It is preferably formed in a shape.
  • the first pad electrode 82 preferably has a tapered side surface.
  • the first contact electrode 81 is a contact electrode formed on the surface 53 a of the p-type contact layer 53 in order to obtain ohmic contact with the p-type nitride semiconductor layer 5.
  • the first contact electrode 81 is formed by forming a stacked film of an Ni film and an Au film (hereinafter also referred to as “first stacked film”) on the surface 5 a of the p-type nitride semiconductor layer 5. It is formed by performing an annealing process.
  • the thickness of the Ni film is set to 30 nm
  • the thickness of the Au film is set to 200 nm.
  • the first pad electrode 82 is an external connection electrode.
  • the first pad electrode 82 is a mounting electrode. More specifically, the first pad electrode 82 is bonded to a conductive wire, a conductive bump, or the like when the semiconductor device 100 is mounted on a package, a wiring board, or the like.
  • an Au wire or the like is employed as the conductive wire.
  • the conductive bump for example, an Au bump or the like is employed.
  • the first pad electrode 82 is preferably composed of an Au layer.
  • the thickness of the Au layer constituting the first pad electrode 82 is set to 1300 nm.
  • the positive electrode 8 is preferably provided with an Al layer 83 including the first opening 12 in plan view below the first pad electrode 82.
  • the thickness of the Al layer 83 is set to 250 nm.
  • the positive electrode 8 preferably includes an upper barrier metal layer 84 in which the first pad electrode 82 is composed of an Au layer and is interposed between the first pad electrode 82 and the Al layer 83.
  • the material of the upper barrier metal layer 84 is Ti, but is not limited thereto, and may be Ta or Ni, for example.
  • the thickness of the upper barrier metal layer 84 is set to 100 nm.
  • the positive electrode 8 preferably includes a lower barrier metal layer 85 interposed between the Al layer 83 and the first contact electrode 81.
  • the material of the lower barrier metal layer 85 is Ti, but is not limited thereto, and may be Ta or Ni, for example.
  • the thickness of the lower barrier metal layer 85 is set to 100 nm.
  • the positive electrode 8 will be further described after describing a method for manufacturing the semiconductor device 100 described later.
  • the negative electrode 9 is electrically connected to the n-type nitride semiconductor layer 3.
  • the negative electrode 9 is composed of the electrode 90 as described above. Therefore, the negative electrode 9 includes a contact electrode 91 (hereinafter also referred to as “second contact electrode 91”) formed on the exposed surface 3a of the n-type nitride semiconductor layer 3, and a surface of the second contact electrode 91. And a pad electrode 92 (hereinafter also referred to as “second pad electrode 92”) formed on the side.
  • the second pad electrode 92 is formed across the second contact electrode 91 and the insulating film 10 in plan view.
  • the second contact electrode 91 is preferably formed in a shape in which the cross-sectional area gradually decreases with distance from the n-type nitride semiconductor layer 3 in the thickness direction of the n-type nitride semiconductor layer 3. More specifically, the second contact electrode 91 has a side surface tapered, so that the cross-sectional area gradually decreases as the distance from the n-type nitride semiconductor layer 3 increases in the thickness direction of the n-type nitride semiconductor layer 3. It is preferably formed in a shape.
  • the second pad electrode 92 preferably has a tapered side surface.
  • the second contact electrode 91 is a contact electrode formed on the surface 3 a of the n-type nitride semiconductor layer 3 in order to obtain ohmic contact with the n-type nitride semiconductor layer 3.
  • the second contact electrode 91 is a laminated film of an Al film, a Ni film, an Al film, a Ni film, and an Au film (hereinafter also referred to as a “second laminated film”) of the n-type nitride semiconductor layer 3. After being formed on the surface 3a, it is formed by annealing and slow cooling.
  • the thicknesses of the Al film, Ni film, Al film, Ni film, and Au film are set to 200 nm, 30 nm, 200 nm, 30 nm, and 200 nm, respectively.
  • the second contact electrode 91 is composed of a solidified structure mainly composed of Ni and Al. Therefore, the semiconductor device 100 can reduce the contact resistance between the n-type nitride semiconductor layer 3 and the second contact electrode 91.
  • the solidified structure means a crystal structure formed as a result of transformation of the molten metal into a solid.
  • the solidified structure is a molten solidified structure formed by solidification of a molten metal containing Ni and Al.
  • the solidified structure mainly composed of Ni and Al may contain, for example, Au and N as impurities.
  • the solidified structure includes a plurality of Ni primary crystals 9a in contact with the surface 3a of the n-type nitride semiconductor layer 3 and an AlNi eutectic crystal 9b in contact with the surface 3a of the n-type nitride semiconductor layer 3. It is mixed. Therefore, the semiconductor device 100 can reduce the contact resistance between the n-type nitride semiconductor layer 3 and the second contact electrode 91, and can reduce the sheet resistance (sheet ⁇ resistance) of the second contact electrode 91. It becomes. Since the AlNi eutectic 9b has an Al composition ratio of about 96 to 97 at%, it has an Al-rich structure in which Al is richer than Ni.
  • the plurality of Ni primary crystals 9a mainly contribute to the reduction of the contact resistance
  • the AlNi eutectic 9b mainly contributes to the reduction of the sheet resistance.
  • the Ni primary crystal 9a preferably contains, for example, Au and N as impurities.
  • the reason why the Ni primary crystal 9a contains N as an impurity may be an estimated mechanism in which a part of N is extracted from the n-type nitride semiconductor layer 3 and solid-dissolved when the Ni primary crystal 9a grows.
  • the AlNi eutectic 9b may contain Au as an impurity, for example. Note that the semiconductor device 100 may have a different estimation mechanism.
  • the plurality of Ni primary crystals 9a in the second contact electrode 91 preferably include Ni primary crystals 9a that satisfy the following conditions.
  • the width of the continuous region formed over the entire length of the second contact electrode 91 in the thickness direction and in contact with the n-type nitride semiconductor layer 3 in the in-plane direction of the second contact electrode 91 is Greater than thickness.
  • the semiconductor device 100 can further reduce the contact resistance between the Ni primary crystal 9a and the surface 3a of the n-type nitride semiconductor layer 3.
  • the Ni primary crystal 9a is a dendritic crystal, and the cross-sectional shape orthogonal to the thickness direction of the n-type nitride semiconductor layer 3 is preferably dendritic.
  • the semiconductor device 100 can increase the contact area between the Ni primary crystal 9 a and the surface 3 a of the n-type nitride semiconductor layer 3, and can further reduce the contact resistance.
  • the cross-sectional shape of the Ni primary crystal 9a perpendicular to the thickness direction of the n-type nitride semiconductor layer 3 is substantially the same as the dendritic shape shown in FIGS.
  • the semiconductor device 100 it is possible to reduce the operating voltage of the semiconductor device 100 by reducing the contact resistance between the n-type nitride semiconductor layer 3 and the second contact electrode 91, and to improve the emission luminance. It becomes possible to plan.
  • the second contact electrode 91 is manufactured by using Ni and Al as main components.
  • the second contact electrode 91 is made of another material containing Ti or the like as a component. It may be configured.
  • the contact between the n-type nitride semiconductor layer 3 and the second contact electrode 91 is preferably ohmic contact.
  • the ohmic contact means a contact having no current rectification caused by the direction of the applied voltage in the contact between the n-type nitride semiconductor layer 3 and the second contact electrode 91.
  • the ohmic contact is preferably substantially linear in current-voltage characteristics, and more preferably linear. Moreover, it is preferable that ohmic contact has a smaller contact resistance.
  • the current passing through the interface between the n-type nitride semiconductor layer 3 and the second contact electrode 91 surpasses the Schottky barrier. This is thought to be the sum of the electron emission current and the tunnel current passing through the Schottky barrier. For this reason, in the contact between the n-type nitride semiconductor layer 3 and the second contact electrode 91, it is considered that an ohmic contact is approximately realized when the tunnel current is dominant.
  • the second pad electrode 92 is an external connection electrode.
  • the second pad electrode 92 is a mounting electrode. More specifically, the second pad electrode 92 is joined to a conductive wire, a conductive bump, or the like when the semiconductor device 100 is mounted on a package, a wiring board, or the like.
  • the second pad electrode 92 is preferably composed of an Au layer. The thickness of the Au layer constituting the second pad electrode 92 is set to 1300 nm as an example.
  • the negative electrode 9 includes an Al layer 93 that includes the second opening 13 in a plan view below the second pad electrode 92.
  • the thickness of the Al layer 93 is set to 250 nm.
  • the negative electrode 9 preferably includes an upper barrier metal layer 94 in which the second pad electrode 92 is made of an Au layer and is interposed between the second pad electrode 92 and the Al layer 93.
  • the material of the upper barrier metal layer 94 is Ti, but is not limited thereto, and may be Ta or Ni, for example.
  • the thickness of the upper barrier metal layer 94 is set to 100 nm.
  • the negative electrode 9 preferably includes a lower barrier metal layer 95 interposed between the Al layer 93 and the second contact electrode 91.
  • the material of the lower barrier metal layer 95 is Ti, but is not limited thereto, and may be Ta or Ni, for example.
  • the thickness of the lower barrier metal layer 95 is set to 100 nm as an example.
  • the negative electrode 9 will be further described after describing the manufacturing method of the semiconductor device 100 described later.
  • the insulating film 10 is formed across a part of the upper surface 22 a of the mesa structure 22 (the surface 20 a of the nitride semiconductor layer 20), a side surface 22 c of the mesa structure 22, and a part of the surface 3 a of the n-type nitride semiconductor layer 3. It is preferable.
  • the insulating film 10 is a film having electrical insulation. As a material of the insulating film 10, SiO 2 is preferable. In short, the insulating film 10 is preferably a silicon oxide film.
  • the material of the insulating film 10 is not limited to SiO 2 , for example, Si 3 N 4 , Al 2 O 3 , TiO 2 , Ta 2 O 5 , ZrO 2 , Y 2 O 3 , CeO 2 , Nb 2 O 5, etc. It can also be adopted. As an example, the thickness of the insulating film 10 is set to 1 ⁇ m.
  • the insulating film 10 can be formed by, for example, a chemical vapor deposition (CVD) method, a vapor deposition method, a sputtering method, or the like.
  • the insulating film 10 is not limited to a single layer film, and may be a multilayer film.
  • the multilayer film provided as the insulating film 10 may be formed of a dielectric multilayer film for reflecting light (ultraviolet rays) generated in the light emitting layer 4.
  • the insulating film 10 includes a contact hole 10a that exposes the first contact electrode 81 (hereinafter also referred to as “first contact hole 10a”) and a contact hole 10b that exposes the second contact electrode 91 (hereinafter referred to as “second contact”). Hole 10b ").
  • the first contact hole 10 a is preferably formed in a shape in which the opening area gradually increases as the distance from the p-type nitride semiconductor layer 5 increases in the thickness direction of the p-type nitride semiconductor layer 5. More specifically, the first contact hole 10a has an inner surface formed in a tapered shape, so that the opening area gradually increases as the distance from the p-type nitride semiconductor layer 5 increases in the thickness direction of the p-type nitride semiconductor layer 5. It is preferable that it is formed in a shape that becomes larger. In the semiconductor device 100, it is preferable that the first contact hole 10a is larger than the first contact electrode 81 in plan view, and the inner side surface of the first contact hole 10a and the side surface of the first contact electrode 81 are separated from each other.
  • the second contact hole 10 b is preferably formed in a shape in which the opening area gradually increases as the distance from the n-type nitride semiconductor layer 3 increases in the thickness direction of the n-type nitride semiconductor layer 3. More specifically, the second contact hole 10b has an inner surface formed in a tapered shape, so that the opening area gradually increases as the distance from the n-type nitride semiconductor layer 3 increases in the thickness direction of the n-type nitride semiconductor layer 3. It is preferable that it is formed in a shape that becomes larger.
  • the second contact hole 10 b is preferably larger than the second contact electrode 91 in plan view, and the inner side surface of the second contact hole 10 b and the side surface of the second contact electrode 91 are preferably separated from each other.
  • the passivation film 11 is formed so as to cover the end portion of the first pad electrode 82, the end portion of the second pad electrode 92, and the insulating film 10. More specifically, the passivation film 11 is formed so as to cover the surface and side surfaces of the first pad electrode 82, the surface and side surfaces of the second pad electrode 92, and the insulating film 10.
  • An opening 12 (hereinafter, also referred to as “first opening 12”) that exposes the central portion of the pad electrode 82 (the central portion of the surface of the first pad electrode 82) and the central portion (the first portion of the first pad electrode 82).
  • An opening 13 (hereinafter, also referred to as “second opening 13”) that exposes the central portion of the surface of the two-pad electrode 92 is formed.
  • the passivation film 11 is formed on at least the pad electrode 92 (second pad electrode 92), and an opening that exposes the central portion of the pad electrode 92 (second pad electrode 92). 13 is formed.
  • the passivation film 11 is a protective film that is provided on the outermost layer of the semiconductor device 100 and suppresses deterioration of device characteristics due to outside air such as humidity. More specifically, the passivation film 11 is a protective film for suppressing deterioration of device characteristics of the semiconductor device 100 by protecting at least the functions of the pad electrode 92, the contact electrode 91, and the AlGaN layer 31.
  • the first opening 12 has an inner surface formed in a tapered shape so that the opening area gradually increases as the distance from the p-type nitride semiconductor layer 5 increases in the thickness direction of the p-type nitride semiconductor layer 5. Preferably it is formed.
  • the second opening portion 13 has an inner surface formed in a tapered shape so that the opening area gradually increases as the distance from the n-type nitride semiconductor layer 3 increases in the thickness direction of the n-type nitride semiconductor layer 3. Preferably it is formed.
  • the passivation film 11 is preferably a silicon nitride film, for example. Thereby, the passivation film 11 can make moisture permeability smaller than that of the silicon oxide film, and can improve moisture resistance.
  • the passivation film 11 has electrical insulation.
  • the passivation film 11 is preferably formed by a plasma CVD method. Thereby, the semiconductor device 100 can improve the step coverage of the passivation film 11 and the denseness of the passivation film 11 as compared with the case where the passivation film 11 is formed by vapor deposition or sputtering. Further, when the passivation film 11 is formed by the plasma CVD method, the semiconductor device 100 can form the passivation film 11 at a temperature sufficiently lower than the melting point of aluminum that is the material of the Al layer 93.
  • the adhesion layer 14 a is interposed between the passivation film 11 and the end portion of the first pad electrode 82.
  • the adhesion layer 14 b be interposed between the passivation film 11 and the second pad electrode 92.
  • the adhesion layers 14 a and 14 b are layers having better adhesion to the passivation film 11 than the first pad electrode 82 and the second pad electrode 92, respectively.
  • the material of the adhesion layers 14a and 14b is preferably one selected from the group consisting of Ti, Cr, Nb, Zr, TiN and TaN.
  • the wafer is a disk-shaped substrate.
  • a sapphire wafer can be adopted as a wafer.
  • the wafer is preferably formed with an orientation flat.
  • the thickness of the wafer is, for example, preferably from several hundred ⁇ m to several mm, and more preferably from 200 ⁇ m to 1 mm.
  • the diameter of the wafer is preferably 50.8 mm to 150 mm, for example.
  • the wafer preferably satisfies or complies with standards such as Japan Electronics Industry Promotion Association (JEIDA) and SEMI (Semiconductor Equipment and Materials International).
  • JEIDA Japan Electronics Industry Promotion Association
  • SEMI semiconductor Equipment and Materials International
  • the first surface of the sapphire wafer corresponds to the first surface 1 a of the substrate 1.
  • a c-plane, m-plane, a-plane, R-plane, etc. can be adopted, and the (0001) plane that is the c-plane is preferable.
  • the first surface of the sapphire wafer preferably has an off angle from the (0001) plane of 0 to 0.4 °.
  • Step of laminating nitride semiconductor layer 20 on the first surface of the wafer the nitride semiconductor layer 20 is formed by an epitaxial growth method.
  • the MOVPE method is adopted as an epitaxial growth method of the nitride semiconductor layer 20.
  • Trimethylaluminum is preferably employed as the Al source gas. Further, it is preferable to employ trimethyl gallium (TMGa) as the Ga source gas. As the N source gas, NH 3 is preferably employed. It is preferable to employ tetraethylsilane (TESi) as a source gas of Si that is an impurity imparting n-type conductivity. It is preferable to employ biscyclopentadienyl magnesium (Cp 2 Mg) as a source gas for Mg, which is an impurity contributing to p-type conductivity. For example, H 2 gas is preferably used as the carrier gas of each source gas.
  • Each source gas is not particularly limited.
  • triethylgallium (TEGa) may be used as a Ga source gas
  • a hydrazine derivative may be used as a N source gas
  • monosilane (SiH 4 ) may be used as a Si source gas.
  • the growth conditions of the nitride semiconductor layer 20 may be set as appropriate such as the substrate temperature, the V / III ratio, the supply amount of each source gas, the growth pressure, and the like.
  • the epitaxial growth method of the nitride semiconductor layer 20 is not limited to the MOVPE method, and may be, for example, an MBE method, an HVPE method, or the like.
  • Step of performing annealing for activating p-type impurities This step is performed by holding the p-type nitride semiconductor layer 5 at a predetermined annealing temperature for a predetermined annealing time in an annealing furnace of an annealing apparatus.
  • the annealing conditions are set such that the annealing temperature is 600 to 800 ° C. and the annealing time is 10 to 50 minutes. However, these values are merely examples, and are not particularly limited.
  • the annealing apparatus for example, a lamp annealing apparatus, an electric furnace annealing apparatus, or the like can be employed.
  • Step of forming mesa structure 22 a photolithography technique is used on a region of nitride semiconductor layer 20 corresponding to upper surface 22a of mesa structure 22 (surface 20a of nitride semiconductor layer 20). Thus, a first resist layer is formed.
  • the mesa structure 22 is formed by etching a part of the nitride semiconductor layer 20 from the surface 20a side to the middle of the n-type nitride semiconductor layer 3 using the first resist layer as a mask. Further, in this step, the first resist layer is removed.
  • the nitride semiconductor layer 20 is preferably etched using, for example, a dry etching apparatus. As the dry etching apparatus, for example, an inductively coupled plasma etching system is preferable.
  • a silicon oxide film that forms the basis of the insulating film 10 is formed on the entire first surface side of the wafer by, for example, PECVD (plasma-enhanced chemical vapor deposition).
  • PECVD plasma-enhanced chemical vapor deposition
  • the insulating film 10 is formed by patterning the silicon oxide film so that the first contact hole 10a and the second contact hole 10b are opened in the silicon oxide film on the first surface side of the wafer.
  • the method for forming the silicon oxide film is not limited to the PECVD method, and may be another CVD method, for example.
  • the patterning of the silicon oxide film is performed using a photolithography technique and an etching technique.
  • Step of Forming Second Contact Electrode 91 in Negative Electrode 9 first, only the region where negative electrode 9 is to be formed (that is, exposure of n-type nitride semiconductor layer 3) is performed on the first surface side of the wafer. The first step of forming a second resist layer patterned so as to expose a part of the surface 3a) is performed. In this step, a multilayer film in which an Al film, a Ni film, an Al film, a Ni film, and an Au film are sequentially stacked on the surface 3a of the n-type nitride semiconductor layer 3 from the side close to the surface 3a is deposited. The second step of forming a film is performed.
  • the vapor deposition method is preferably an electron beam vapor deposition method.
  • the method for forming the laminated film is not limited to the vapor deposition method, and may be a sputtering method, for example.
  • the third step of removing the second resist layer and the unnecessary film on the second resist layer by performing lift off is performed.
  • a fourth step of forming the second contact electrode 91 by performing an annealing process and performing slow cooling is performed.
  • the annealing treatment is preferably RTA (Rapid Thermal Annealing) in an N 2 gas atmosphere.
  • the RTA treatment conditions may be, for example, an annealing temperature of 650 ° C. and an annealing time of 1 minute.
  • the annealing temperature is preferably a temperature equal to or higher than the eutectic point (640 ° C.) of AlNi, and preferably 700 ° C. or lower.
  • the annealing temperature may be appropriately changed based on the Al composition ratio of the n-type nitride semiconductor layer 3.
  • the annealing time is preferably set in the range of about 30 seconds to 3 minutes, for example.
  • the eutectic point means a temperature at which a liquid eutectic mixture solidifies when it forms a solid phase having the same composition.
  • Slow cooling means gradual cooling.
  • the cooling rate when performing slow cooling may be, for example, 30 ° C./min.
  • the cooling rate is not limited to 30 ° C./min, and is preferably set as appropriate in the range of 20 to 60 ° C./min.
  • the infrared annealing apparatus includes an infrared lamp as a heating source, a quartz furnace for storing a work, and a vacuum pump as a pressure adjusting apparatus for adjusting the pressure in the furnace.
  • the infrared annealing apparatus is preferably a halogen lamp annealing apparatus using a halogen lamp as an infrared lamp.
  • the workpiece is a wafer-like structure in which a nitride semiconductor layer 20 having a mesa structure 22 is formed on a wafer, and a multilayer film is formed on the exposed surface 3 a of the n-type nitride semiconductor layer 3.
  • the cooling rate can be changed by adjusting the flow rate of N 2 gas flowing into the furnace.
  • the inventors of the present application considered as follows an estimated mechanism for forming the second contact electrode 91 by performing annealing treatment and slow cooling in this step. Note that the estimation mechanism may be different in the manufacturing method of the semiconductor device 100.
  • the multilayer film is melted and gradually cooled, so that the Ni primary crystal 9a is first precipitated, and then the eutectic structure of AlNi is solidified (the AlNi eutectic 9b is formed).
  • the second contact electrode 91 composed of a solidified structure mainly composed of Ni and Al can be formed. More specifically, in this step, it is possible to form the second contact electrode 91 composed of a solidified structure including a plurality of Ni primary crystals 9a and AlNi eutectic crystals 9b.
  • the Ni primary crystal 9a contains Au as an impurity.
  • the Ni primary crystal 9a contains a trace amount (ppm level) of Au as an impurity, but 99% or more is Ni. Since the Ni primary crystal 9a does not grow in the same direction (in other words, the growth rate differs depending on the direction), it grows in a dendritic shape. Moreover, the AlNi eutectic 9b contains Au as an impurity.
  • the second contact electrode 91 forms an impurity level when N dissociated from the n-type nitride semiconductor layer 3 during the annealing process is dissolved in Ni, so that an n-type nitride semiconductor layer 3 is formed by a tunnel effect. It is assumed that it becomes possible to reduce the contact resistance.
  • the second contact electrode 91 draws a part of nitrogen from the n-type nitride semiconductor layer 3 so that ohmic contact between the n-type nitride semiconductor layer 3 and the second contact electrode 91 can be realized. It is inferred. Therefore, the Ni primary crystal 9a contains N as an impurity.
  • the Au film has a function as a protective film that suppresses Ni from being oxidized by oxygen in the atmosphere before annealing, or suppresses Ni from being oxidized by residual oxygen in the furnace.
  • the annealing temperature in the step of forming the second contact electrode 91 can be lowered.
  • first contact electrode 81 is formed on surface 5a of p-type nitride semiconductor layer 5.
  • this step first, patterning is performed so that only the region where the positive electrode 8 is to be formed on the first surface side of the wafer (here, part of the surface 53a of the p-type contact layer 53) is exposed.
  • a third resist layer is formed.
  • a laminated film of a Ni film having a thickness of 30 nm and an Au film having a thickness of 200 nm is formed by electron beam evaporation, and lift-off is performed, whereby the third resist layer and the third film are formed. The unnecessary film on the resist layer is removed.
  • RTA treatment is performed in an N 2 gas atmosphere so that the contact between the first contact electrode 81 and the p-type nitride semiconductor layer 5 is an ohmic contact.
  • the RTA treatment conditions may be, for example, an annealing temperature of 500 ° C. and an annealing time of 15 minutes.
  • Step of completing the positive electrode 8 and the negative electrode 9 the lower barrier metal layers 85 and 95, the Al layers 83 and 93, and the upper barrier metal layer are utilized using photolithography technology and thin film formation technology.
  • 84, 94, a first pad electrode 82, and a second pad electrode 92 are formed.
  • a thin film forming technique for example, a vapor deposition method or the like can be employed.
  • the vapor deposition method is preferably an electron beam vapor deposition method.
  • the Al layer 83 is formed to have a size including the first contact hole 10a in plan view. “Including the first contact hole 10a in a plan view” means that the first contact hole 10a is placed in the vertical projection region of the Al layer 83 along the projection direction in the thickness direction of the p-type nitride semiconductor layer 5. Means inclusion. Further, the Al layer 93 is formed to have a size including the second contact hole 10b in plan view. “Including the second contact hole 10b in plan view” means including the second contact hole 10b in the vertical projection region of the Al layer 93 whose projection direction is along the thickness direction of the AlGaN layer 31. means.
  • a silicon nitride film that forms the basis of the passivation film 11 is formed on the entire first surface side of the wafer by, for example, a plasma CVD method.
  • the passivation film 11 is formed by patterning the silicon nitride film so that the first opening 12 and the second opening 13 are opened in the silicon nitride film on the first surface side of the wafer.
  • the method for forming the silicon nitride film is not limited to the plasma CVD method, and may be another CVD method, for example.
  • the patterning of the silicon oxide film is performed using a photolithography technique and an etching technique.
  • Step 10 Step of forming a split groove
  • a split groove reaching from the surface side of the passivation film 11 of the wafer to the middle in the thickness direction of the wafer is formed.
  • Ablation processing means laser processing under irradiation conditions that cause ablation.
  • Step of Polishing Wafer the wafer is polished from the second surface side opposite to the first surface, thereby reducing the wafer to a thickness corresponding to the predetermined thickness of the substrate 1.
  • polishing the wafer it is preferable to sequentially perform a grinding process and a lapping process.
  • a wafer on which a plurality of semiconductor devices 100 are formed is completed.
  • a wafer on which a plurality of semiconductor devices 100 are formed is completed by sequentially performing the steps (1) to (11) described above.
  • a process of dividing a wafer in which a plurality of semiconductor devices 100 are formed into individual semiconductor devices 100 is a dicing process, and a wafer in which a plurality of semiconductor devices 100 are formed is cut by a dicing saw or the like. Thus, the semiconductor device 100 is divided into individual semiconductor devices 100.
  • the semiconductor device 100 capable of improving the moisture resistance can be manufactured relatively easily.
  • the semiconductor device 100 capable of reducing the contact resistance between the n-type nitride semiconductor layer 3 and the negative electrode 9 can be manufactured relatively easily. It becomes. In the following, the reduction in contact resistance will be described and then the moisture resistance will be described.
  • the surface 3a of the n-type nitride semiconductor layer 3 is rough. That is, the surface 3a of the n-type nitride semiconductor layer 3 has a random uneven structure. For this reason, it is conceivable that sufficient contact cannot be obtained with respect to physical contact between the multilayer film and the surface 3a of the n-type nitride semiconductor layer 3 only by forming the multilayer film by vapor deposition or the like.
  • Ni has a higher work function than Ti, the resistance is higher than that of Al only by contacting the n-type nitride semiconductor layer 3.
  • the multilayer film since the multilayer film is melted, Ni reacts with N in the n-type nitride semiconductor layer 3 to form a solid solution with N, thereby reducing the contact resistance. It becomes possible.
  • the AlNi eutectic has a eutectic point of about 20 ° C. lower than that of the AlTi eutectic, and the amount of change in the melting point when the Al composition ratio deviates from the Al composition ratio in the eutectic composition is small. Therefore, in the manufacturing method of the semiconductor device 100 according to the present embodiment, it is possible to suppress variation in the electrical characteristics of the negative electrode 9 of the semiconductor device 100 for each lot, and it is possible to reduce the cost. It becomes.
  • the second contact electrode 91 having a configuration in which the plurality of Ni primary crystals 9a include the Ni primary crystals 9aa (see FIG. 3) that satisfy the following conditions. .
  • the width W1 (see FIG. 3) of the continuous region formed over the entire length of the second contact electrode 91 in the thickness direction and in contact with the n-type nitride semiconductor layer 3 in the in-plane direction of the second contact electrode 91 is It is larger than the thickness H1 (see FIG. 3) of the second contact electrode 91.
  • the second contact electrode 91 In forming the second contact electrode 91 on the surface 3 a of the n-type nitride semiconductor layer 3, Al films and Ni films are alternately stacked on the surface 3 a of the n-type nitride semiconductor layer 3. A multilayer film in which an Au film is laminated on the Ni film is formed. Thereafter, in the method for manufacturing the semiconductor device 100, the second contact electrode 91 is formed by melting the multilayer film by annealing at an annealing temperature of 640 ° C. or higher and 700 ° C. or lower and performing slow cooling. Thereby, in the manufacturing method of the semiconductor device 100, it is possible to form the second contact electrode 91 configured by a solidified structure mainly composed of Ni and Al.
  • the semiconductor device 100 it is possible to manufacture the semiconductor device 100 capable of reducing the contact resistance between the n-type nitride semiconductor layer 3 and the negative electrode 9.
  • the number of repetitions of the laminated structure of the Al film and the Ni film in the multilayer film is arbitrary as long as it is 2 or more.
  • the cooling rate when performing slow cooling is 20 to 60 ° C./min.
  • the manufacturing method of the semiconductor device 100 it is possible to form a solidified structure in which a plurality of Ni primary crystals 9a and AlNi eutectic 9b in contact with the surface 3a of the n-type nitride semiconductor layer 3 are mixed.
  • the cooling rate is slower than 20 ° C./min, the size of each Ni primary crystal 9a becomes small, and the contact between each Ni primary crystal 9a and the surface 3a of the n-type nitride semiconductor layer 3 occurs. The area will decrease.
  • the second contact electrode 91 in the semiconductor device 100 of the present embodiment described above is formed of a solidified structure mainly composed of Ni and Al.
  • the semiconductor device 100 can reduce the contact resistance between the n-type nitride semiconductor layer 3 and the negative electrode 9.
  • the contact resistance can be measured by, for example, the TLM method (Transfer length method).
  • the measurement of contact resistance by the TLM method can be performed on a sample for evaluation using, for example, a semiconductor parameter analyzer (HP4155A manufactured by Hewlett-Packard Company).
  • the evaluation sample is a sample in which a plurality of evaluation electrodes having the same specifications as the second contact electrode 91 are provided on the surface 3 a of the n-type nitride semiconductor layer 3.
  • the same specification means that the material and thickness are the same.
  • Document 2 International Publication No. WO2012 / 039442
  • an n-electrode Ti / Al / Ti / Au formed on an n - type Al x Ga 1-x N layer and an n-type Al x Ga 1-x N.
  • Reference 2 shows the result of measuring this relationship for four types of AlN molar fraction x of 0, 0.25, 0.4, and 0.6 of the n-type Al x Ga 1-x N layer. ing.
  • Document 2 describes that when the emission wavelength is shortened, that is, when the AlN molar fraction x is increased, heat treatment at a higher temperature is required.
  • the contact resistance is the lowest when the heat treatment temperature is about 950 ° C., and the minimum value of the contact resistance is about 1 ⁇ 10 ⁇ 2 ⁇ ⁇ cm 2. It is.
  • the semiconductor device 100 has a contact resistance of 5 ⁇ 10 ⁇ 3 between the negative electrode 9 and the n-type nitride semiconductor layer 3 composed of an n-type Al 0.7 Ga 0.3 N layer having a higher Al composition ratio. It can be about ⁇ cm 2 . Note that the semiconductor device 100 tends to have higher contact resistance as the Al composition ratio increases.
  • the semiconductor device of the first example is substantially the same as the semiconductor device 100, and an ultraviolet ray in which the first pad electrode 82 is directly formed on the first contact electrode 81 and the second pad electrode 92 is directly formed on the second contact electrode 91. It is a light emitting diode.
  • the semiconductor device of the second example is substantially the same as the semiconductor device 100, with only the Ti layer interposed between the first contact electrode 81 and the first pad electrode 82, and the second contact electrode 91 and the second pad electrode. This is an ultraviolet light emitting diode in which only a Ti layer is interposed between them.
  • the inventors of the present application firstly conducted a high-temperature and high-humidity energization test, an evaluation of electrical characteristics, an optical microscope, an appearance inspection using a scanning electron microscope (SEM), and the like. Went.
  • the temperature was 60 ° C.
  • the relative humidity was 80 RH%
  • the energization current was 20 mA
  • the continuous energization time was 2000 hours.
  • the inventors of the present application have found that the semiconductor device of the first example needs further improvement in moisture resistance.
  • a defect may occur in the semiconductor device of the first example during the high temperature and high humidity current test.
  • Problems include open defects, corrosion of the area immediately below the negative electrode 9 in the AlGaN layer 31, damage to the end of the second pad electrode 92, damage to the portion of the passivation film 11 on the damaged portion of the end of the second pad electrode 92 , Etc.
  • the corrosion of the region immediately below the negative electrode 9 in the AlGaN layer 31 means the oxidation of the region immediately below the second contact electrode 91 in the AlGaN layer 31 and means that Al 2 O 3 is formed.
  • the present inventors have found that the p-type contact layer 53 made of the p-type GaN layer does not corrode or the end portion of the first pad electrode 82 is damaged even when the above-described problem occurs. The knowledge that it does not occur was obtained.
  • the inventors of the present application have considered the following estimation mechanism for the mechanism of occurrence of the above-described problems in the semiconductor device of the first example.
  • moisture that has entered from defects such as pinholes and cracks in the passivation film 11 passes through crystal grain boundaries of the Au layer constituting the pad electrode 92 and defects such as pinholes and cracks. It reaches the surface 31 a of the AlGaN layer 31.
  • a current flows and holes (h + ) are generated in the AlGaN layer 31, the vicinity of the surface 31a of the AlGaN layer 31 due to AlN in the AlGaN layer 31. The following electrochemical reaction occurs.
  • N 2 is generated in the vicinity of the surface 31a of the AlGaN layer 31, and Al 2 O 3 is formed by the oxidation reaction, resulting in electrical insulation and volume expansion.
  • the current path in the AlGaN layer 31 changes, so that a region to be electrically insulated is expanded, and a region immediately below the negative electrode 9 in the AlGaN layer 31. Is electrically insulated and an open failure occurs where current does not flow.
  • the inventors of the present application conduct a high-temperature and high-humidity current test, evaluate the electrical characteristics, use an optical microscope, and SEM. Appearance inspection was conducted.
  • the inventors of the present application need to further improve the moisture resistance in the semiconductor device of the first example and the semiconductor device of the second example, whereas in the semiconductor device 100 of the embodiment, the first example.
  • the present inventors have found that the moisture resistance can be improved as compared with the semiconductor device and the semiconductor device of the second example.
  • the above-described problems occurred during the high-temperature and high-humidity current test, whereas in the semiconductor device 100 of the embodiment, the high-temperature and high-humidity The above-mentioned problems did not occur even when the current test was performed.
  • the semiconductor device 100 of the present embodiment described above includes the AlGaN layer 31, the electrode 90, the insulating film 10, and the passivation film 11.
  • the electrode 90 includes a contact electrode 91 formed on the surface 31 a of the AlGaN layer 31 and a pad electrode 92 formed on the surface side of the contact electrode 91.
  • the insulating film 10 is formed on the surface 31 a of the AlGaN layer 31 so as to surround the contact region of the contact electrode 91 with the AlGaN layer 31.
  • the passivation film 11 is formed so as to cover the insulating film 10 and the end portion of the pad electrode 92, and an opening 13 exposing the central portion of the pad electrode 92 is formed.
  • the pad electrode 92 is formed across the contact electrode 91 and the insulating film 10 in plan view.
  • the electrode 90 includes an Al layer 93 including the opening 13 in a plan view below the pad electrode 92. Therefore, the semiconductor device 100 can improve moisture resistance.
  • the semiconductor device 100 since the semiconductor device 100 includes the Al layer 93, it is possible to mitigate the impact when bonding bumps or wires to the second pad electrode 92 by the Al layer 93. It is possible to suppress the occurrence of cracks.
  • the semiconductor device 100 includes an n-type nitride semiconductor layer 3 having at least an AlGaN layer 31, a light-emitting layer 4 that is formed on the n-type nitride semiconductor layer 3 and emits light having a light emission wavelength in the ultraviolet wavelength region, and light emission It is preferable that the p-type nitride semiconductor layer 5 formed on the layer 4 is provided. Thereby, the semiconductor device 100 can improve the moisture resistance while shortening the emission wavelength of the ultraviolet light emitting element.
  • the AlGaN layer 31 is preferably an Al x Ga 1-x N (0.4 ⁇ x ⁇ 1) layer. As a result, the semiconductor device 100 can set the emission wavelength of the ultraviolet light emitting element in the UV-C wavelength region.
  • the electrode 90 in the semiconductor device 100 preferably includes an upper barrier metal layer 94 in which the pad electrode 92 is made of an Au layer and is interposed between the pad electrode 92 and the Al layer 93. Thereby, the semiconductor device 100 can suppress the diffusion between the pad electrode 92 and the Al layer 93, and can improve the reliability.
  • the material of the upper barrier metal layer 94 is preferably one selected from the group of Ti, Ta, and Ni. Thereby, the semiconductor device 100 can improve the adhesion between the upper barrier metal layer 94 and each of the pad electrode 92 and the Al layer 93.
  • the electrode 90 in the semiconductor device 100 includes a lower barrier metal layer 95 interposed between the Al layer 93 and the contact electrode 91.
  • the semiconductor device 100 can simultaneously form a portion of the positive electrode 8 other than the first contact electrode 81 and a portion of the negative electrode 9 other than the second contact electrode 91. Further, the semiconductor device 100 can suppress the diffusion between the Al layer 93 and the contact electrode 91 depending on the material of the contact electrode 91, and can improve the reliability.
  • the material of the lower barrier metal layer 95 is preferably one selected from the group of Ti, Ta, and Ni. Thereby, the semiconductor device 100 can improve the adhesion between the lower barrier metal layer 95, the Al layer 93, and the contact electrode 91.
  • the above-described semiconductor device 100 preferably further includes an adhesion layer 14b interposed between the passivation film 11 and the end portion of the pad electrode 92.
  • the adhesion layer 14 b is a layer having better adhesion with the passivation film 11 than the pad electrode 92. As a result, the semiconductor device 100 can further improve the moisture resistance.
  • the insulating film 10 is a silicon oxide film
  • the passivation film 11 is a silicon nitride film
  • the material of the adhesion layer 14b is from the group of Ti, Cr, Nb, Zr, TiN and TaN. It is preferable that it is 1 type selected. Thereby, the semiconductor device 100 can improve the moisture resistance as compared with the case where the passivation film is a silicon oxide film.
  • the positive electrode 8 in the semiconductor device 100 constituting the ultraviolet light emitting element preferably includes an Al layer 83 including the first opening 12 in a plan view below the first pad electrode 82.
  • the semiconductor device 100 can improve moisture resistance even when the p-type contact layer 53 is formed of an AlGaN layer, for example.
  • the first pad electrode 82 is composed of an Au layer.
  • the positive electrode 8 is preferably provided with an upper barrier metal layer 84 interposed between the first pad electrode 82 and the Al layer 83. Thereby, the semiconductor device 100 can simultaneously form the upper barrier metal layer 84 of the positive electrode 8 and the upper barrier metal layer 94 of the negative electrode 9.
  • the material of the upper barrier metal layer 84 is preferably one selected from the group of Ti, Ta, and Ni.
  • the positive electrode 8 may employ a configuration that does not include the upper barrier metal layer 84.
  • the structure of the positive electrode 8 is changed to that of the negative electrode 9, that is, the electrode 90.
  • a preferred embodiment is the same as the structure.
  • the ultraviolet light emitting element in the present embodiment described above is formed on the substrate 1 and the one surface (first surface) 1a side of the substrate 1, and the n-type nitride semiconductor layer 3 and the light emitting layer in order from the one surface (first surface) 1a side. 4 and a nitride semiconductor layer 20 having a p-type nitride semiconductor layer 5.
  • the ultraviolet light emitting element includes a positive electrode 8 formed on the surface 5 a of the p-type nitride semiconductor layer 5 and a negative electrode 9 formed on the exposed surface 3 a of the n-type nitride semiconductor layer 3.
  • the ultraviolet light emitting element includes an insulating film 10 and a passivation film 11.
  • the positive electrode 8 includes a first contact electrode 81 formed on the surface 5 a of the p-type nitride semiconductor layer 5 and a first pad electrode 82 formed on the surface side of the first contact electrode 81.
  • the negative electrode 9 includes a second contact electrode 91 formed on the surface 31a of the AlGaN layer 31 in the n-type nitride semiconductor layer 3, a second pad electrode 92 formed on the surface side of the second contact electrode 91, Is provided.
  • the insulating film 10 is formed on the surface 5a of the p-type nitride semiconductor layer 5 and the surface 31a of the AlGaN layer 31, and exposes the first contact hole 10a and the second contact electrode 91 that expose the first contact electrode 81.
  • a second contact hole 10b is formed.
  • the passivation film 11 is formed so as to cover the insulating film 10, the end of the first pad electrode 82, and the end of the second pad electrode 92, and the first opening that exposes the center of the first pad electrode 82.
  • a second opening 13 is formed to expose the central portion of the portion 12 and the second pad electrode 92.
  • the second pad electrode 92 is formed across the second contact electrode 91 and the insulating film 10 in plan view.
  • the negative electrode 9 includes an Al layer 93 that includes the second opening 13 in plan view below the second pad electrode 92. Thereby, the ultraviolet light emitting element can improve moisture resistance.
  • FIG. 6 is a schematic cross-sectional view of the semiconductor device 101 of the first modification.
  • the semiconductor device 101 has the same basic configuration as that of the semiconductor device 100, and only the pattern of the passivation film 11 is different.
  • the same components as those of the semiconductor device 100 are denoted by the same reference numerals and description thereof is omitted.
  • the passivation film 11 in the semiconductor device 101 is formed so as to cover the surface of the second pad electrode 92, the side surface of the second pad electrode 92, and the peripheral portion of the second pad electrode 92 on the surface of the insulating film 10. Therefore, also in the semiconductor device 101, the passivation film 11 is formed on at least the second pad electrode 92, and the opening 13 that exposes the central portion of the second pad electrode 92 is formed.
  • the semiconductor device 101 can further suppress the peeling of the passivation film 11, and can further improve the moisture resistance.
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device 102 of the second modified example.
  • the semiconductor device 102 has the same basic configuration as the semiconductor device 100, and only the pattern of the passivation film 11 is different.
  • the same components as those of the semiconductor device 100 are denoted by the same reference numerals, and the description thereof is omitted.
  • the passivation film 11 in the semiconductor device 102 is formed only on the second pad electrode 92, and an opening 13 exposing the central portion of the second pad electrode 92 is formed.
  • the semiconductor device 102 can further suppress the peeling of the passivation film 11, and can further improve the moisture resistance.
  • the semiconductor device is not limited to an ultraviolet light emitting element, and may be, for example, a GaN-based HEMT (high electron mobility mobility).
  • a GaN-based HEMT has a heterojunction composed of a GaN layer and an AlGaN layer, and a drain electrode, a source electrode, and a gate insulating film are formed on the surface of the AlGaN layer.
  • a gate electrode is formed on the substrate.
  • a gate insulating film can be formed by a part of the insulating film 10 described above, and the structure of the electrode 90 described above can be applied to a drain electrode and a source electrode. it can.
  • the semiconductor device (100, 101, 102) according to the first aspect of the present invention includes an AlGaN layer (31), an electrode (90), an insulating film (10), A passivation film (11), and the electrode (90) is formed on the surface (31a) of the AlGaN layer (31) on the surface side of the contact electrode (91) and the contact electrode (91).
  • a pad electrode (92) formed, and the insulating film (10) surrounds a contact region of the contact electrode (91) with the AlGaN layer (31).
  • the passivation film (11) is formed on at least the pad electrode (92), and the central portion of the pad electrode (92) is exposed.
  • the electrode (90) is formed so that the pad electrode (92) is formed across the contact electrode (91) and the insulating film (10) in plan view.
  • the electrode (90) includes an Al layer (93) including the opening (13) in a plan view below the pad electrode (92).
  • the semiconductor device (100, 101, 102) according to the second aspect of the present invention is the n-type nitride semiconductor layer (3) having at least the AlGaN layer (31) in the first aspect.
  • the AlGaN layer (31) is made of Al x Ga 1-x N (0.4 ⁇ x ⁇ 1). Is a layer.
  • the semiconductor device (100, 101, 102) according to the fourth aspect of the present invention is the semiconductor device (100, 101, 102) according to any one of the first to third aspects, wherein the electrode (90) is composed of the pad electrode (92) made of an Au layer. And an upper barrier metal layer (94) interposed between the pad electrode (92) and the Al layer (93).
  • the material of the upper barrier metal layer (94) is selected from the group consisting of Ti, Ta and Ni. It is a seed.
  • the electrode (90) includes the Al layer (93) and the contact electrode ( 91) and a lower barrier metal layer (95) interposed therebetween.
  • the material of the lower barrier metal layer (95) is selected from the group consisting of Ti, Ta and Ni. It is a seed.
  • the semiconductor device (100, 101, 102) according to the eighth aspect of the present invention is, in any one of the first to seventh aspects, interposed between the passivation film (11) and the pad electrode (92).
  • the adhesion layer (14b) is a layer having better adhesion to the passivation film (11) than the pad electrode (92).
  • the insulating film (10) is a silicon oxide film
  • the passivation film (11) is silicon nitride.
  • the material of the adhesion layer (14b) is a film selected from the group consisting of Ti, Cr, Nb, Zr, TiN, and TaN.
  • the passivation film is only on the pad electrode.
  • the passivation film (11) includes the insulating film (10) and the pad electrode (92). ).
  • the ultraviolet light-emitting device is formed on the substrate (1) and the one surface (1a) side of the substrate (1), and in order from the one surface (1a) side, the n-type nitride semiconductor layer (3 ), A nitride semiconductor layer (20) having a light emitting layer (4) and a p-type nitride semiconductor layer (5), and a positive electrode formed on the surface (5a) of the p-type nitride semiconductor layer (5) (8), a negative electrode (9) formed on the exposed surface (3a) of the n-type nitride semiconductor layer (3), an insulating film (10), and a passivation film (11).
  • the light emitting layer (4) is configured to emit light having a light emission wavelength in the ultraviolet wavelength region
  • the positive electrode (8) is formed on the surface of the p-type nitride semiconductor layer (5)
  • a first pad electrode (82) formed, and the negative electrode (9) is formed on a surface (31a) of an AlGaN layer (31) in the n-type nitride semiconductor layer (3).
  • a second contact hole (10b) exposing the electrode (91) is formed, the passivation film (11) is formed on at least the second pad electrode (92), and the second pad electrode ( 92)
  • An opening (13) that exposes the central portion is formed, and the negative electrode (9) has a second pad electrode (92) that is connected to the second contact electrode (91) and the insulating film (10) in plan view.
  • the negative electrode (9) includes an Al layer (93) including the opening (13) in plan view below the second pad electrode (92). .
  • the passivation film (11) is only on the second pad electrode (92).
  • the passivation film (11) covers the insulating film (10) and the second pad electrode (92).

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Abstract

　La présente invention a pour objectif d'améliorer la résistance à l'humidité d'un dispositif semiconducteur. Une électrode (90) d'un dispositif semiconducteur (100) est pourvue d'une électrode de contact (91) et d'une électrode de pastille (92) formée sur le côté recto de l'électrode de contact (91). Un film isolant (10) est présent sur le recto (31a) d'une couche d'AlGaN (31) de manière à entourer la région de l'électrode de contact (91) où un contact est établi avec la couche d'AlGaN (31). Un film de passivation (11) est formé au moins sur l'électrode de pastille (92), ledit film (11) possédant une section ouverte (13) où est exposée la section centrale de l'électrode de pastille (92). Dans l'électrode (90), l'électrode de pastille (92) est formée de manière à s'étendre sur l'électrode de contact (91) et le film isolant (10), et une couche d'Al (93) se trouve au-dessous de l'électrode de pastille (92), ladite couche d'Al (93) comprenant l'ouverture (13) dans une vue en plan.
PCT/JP2015/005210 2014-10-22 2015-10-15 Dispositif semiconducteur et élément émetteur de lumière ultraviolette WO2016063501A1 (fr)

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