WO2016056916A2

WO2016056916A2 - Self aligned low temperature process for solar cells

Info

Publication number: WO2016056916A2
Application number: PCT/NL2015/050714
Authority: WO
Inventors: Andrea INGENITO; Olindo ISABELLA; Miroslav Zeman
Original assignee: Technische Universiteit Delft
Priority date: 2014-10-10
Filing date: 2015-10-09
Publication date: 2016-04-14
Also published as: WO2016056916A3; NL2013608B1; WO2016056916A4

Abstract

The present invention is in the field of a process for making interdigitated back contacted solar cells, and interdigitated back contacted solar cells. A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence "solar"), directly into electricity by the socalled photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.

Description

Title Self aligned low temperature process for solar cells

FIELD OF THE INVENTION

The present invention is in the field of a process for making interdigitated back contacted solar cells, and in- terdigitated back contacted solar cells.

BACKGROUND OF THE INVENTION

A solar cell, or photovoltaic (PV) cell, is an elec- trical device that converts energy of light, typically sun light (hence "solar"), directly into electricity by the so- called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type to type (of cell) .

Solar cells are described as being photovoltaic ir- respective of whether the source is sunlight or an artificial light. They may also be used as photo detector.

When a solar cell absorbs light it may generate ei- ther electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are sep- arated. The separated charge carriers are "extracted" to an external circuit, typically providing a DC-current. For prac- tical use a DC-current may be transformed into an AC-current, e.g. by using a transformer.

Typically solar cells are grouped into an array of elements. Various elements may form a panel, and various pan- els may form a system.

A disadvantage of solar cells is that the conversion per se is not very efficient, typically, for Si-solar cells, limited to some 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts were moved to a rear or back side, elimi- nating shaded areas. In addition thin silicon films were ap- plied to the wafer. Solar cells also suffer from various im- perfections, such as recombination losses, reflectance loss- es, heating during use, thermodynamic losses, shadow, inter- nal resistance, such as shunt and series resistance, leakage, etc. A qualification of performance of a solar cell is the fill factor (FF) . The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is consid- ered to be a key parameter in evaluating performance. A typi- cal advanced commercial solar cell has a fill factor > 0.70, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt re- sistance; in other words less internal losses occur. Effi- ciency is nevertheless improving gradually, so every rela- tively small improvement is welcomed and of significant im- portance .

It is noted that despite technological development prior art systems are still relative expensive to manufac- ture. For instance, wafer based c-Si solar cells are fabri- cated by using a diffusion process. Such a technique is cost- effective and well known in the photovoltaic industry. In this way both front and the back side doped regions are fab- ricated in one step. When using standard diffusing processes the diffusion parameters can be tuned in order to reach doped regions with reasonable low concentration of inactive doping. However, the process occurs on both sides of the wafer and this leads to a non-optimized doped regions for the front and the back. This may lead to a low cost of ownership, but is unfavorable in terms of performances.

Some recent developments are discussed below.

In US2011/0201188 Al recites a method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is ap- plied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed.

WO2012/034993 Al recites a method for fabricating thin crystalline photovoltaic cells, comprising: providing a semiconductor substrate; forming a weakening layer in a sur- face portion of the substrate; epitaxially growing a stack of semiconductor layers on the substrate for forming an active layer of the photovoltaic cell, the one semiconductor layers of the stack having a first thermal coefficient of expansion; providing on the semiconductor layer or stack of semiconduc- tor layers a patterned contact layer for forming electrical contacts of the photovoltaic cell, the patterned contact lay- er having a second thermal coefficient of expansion different from the first thermal coefficient of expansion; and wherein providing a patterned contact layer simultaneously induces a tensile stress in the weakening layer, for example by an in- herent temperature step, resulting in a lift-off from the substrate of a structure comprising the stack of semiconduc- tor layers and the patterned contact layer. This method is considered to be still somewhat complicated in terms of num- ber of process steps. In addition certain drawbacks are still present in the devices obtained, such as a low shunt re- sistance, a low fill factor and a high leakage current (all relatively) , and as a result amongst others a low efficiency.

Haase et al. in 27^th European photovoltaic Solar En- ergy Conference and Exhibition in October 2012 Mflnchen, p. 580-585 recite some improvements relating to reduction of cell thickness for back contacted silicon solar cells.

Payo et al. in 28^th European photovoltaic Solar Ener- gy Conference and Exhibition in October 2013 Mtinchen, p. 941- 946 recite doping alternatives to a mainstream diffusion pro- cess in order to increase efficiency and reduce costs of so- lar cells.

WO2013/020868 Al recites a method which is provided for forming a pattern of differently doped regions comprising a first doped region and a second doped region at the same side of a semiconductor substrate. Ά patterned doped dielec- tric layer is provided on the surface of the semiconductor substrate at predetermined locations where the first doped region is to be formed; and the second doped region is grown epitaxially at the same side of the semiconductor substrate using the patterned doped layer as a mask, thereby driving dopants from the patterned doped layer into the semiconductor substrate and thus forming the first doped region at the predetermined locations. This saves a process step. The meth- od can advantageously be used in a fabrication process for Interdigitated Back Contact photovoltaic cells.

US 2010/108130 Ά1 recites a design and manufacturing method for an interdigitated backside contact photovoltaic (PV) solar cell less than 100 um thick. A porous silicon lay- er is formed on a wafer substrate. Portions of the PV cell are then formed using diffusion, epitaxy and autodoping from the substrate. All backside processing of the solar cell (junctions, passivation layer, metal contacts to the N+ and P+ regions) is performed while the thin epitaxial layer is attached to the porous layer and substrate. After backside processing, the wafer is clamped and exfoliated. The front of the PV cell is completed from the region of the wafer near the exfoliation fracture layer, with subsequent removal of the porous layer, texturing, passivation and deposition of an antireflective coating. During manufacturing, the cell is al- ways supported by either the bulk wafer or a wafer chuck, with no processing of bare thin PV cells.

The present invention relates to an interdigitated back contacted solar cell and various aspects thereof which over- comes one or more of the above disadvantages, without jeop- ardizing functionality and advantages.

SUMMARY OF THE INVENTION

The present invention relates in a first aspect to a process for making interdigitated back contacted devices, such as a solar cell and a light detector, according to claim 1, and in a second aspect to interdigitated back con- tacted device, such as a Si-based solar cell or light detec- tor, according to claim 14. None of the above documents re- late to the present device having amongst others at least one self-aligned ion-implant-doped region, an under-etched epi- taxial layer, and the improved performance as indicated throughout the description which may be considered to be a consequence of the present process. Also as a consequence the present device can be distinguished over the prior art cells as mentioned above by simply measuring one of the character- istics as mentioned; from a principle point of view two dif- ferent processes for manufacturing a device can never lead to the same device as the processes are different; in the pre- sent case these differences can even be measured and (thus) provide further advantages to the present device compared to the prior art devices.

The present process is based on a unique combina- tion of in-situ doped layers fabricated via epitaxy and ion

implantation. Both techniques are preferably applied to a single-side, allowing to separately optimize each doped region according to required specifications.

The present process requires a low or reduced thermal budget (T < 900 °C) to activate dopants, it pro- vides dopant regions which are virtually gap-less, and do- pant regions that are self-aligned, i.e. always in the correct position. Such is achieved by providing openings in the epitaxial layers, such as defined by a lithographic process, slightly under etching the epitaxial layer (0.2-5 μπι, preferably 0.5-2 um, more preferably 1-1.5 μπι) , and ion-implanting opposite dopants at a different cross- sectional height (see e.g. figs. 3-5) . It has been found that the present gap-less structure reduces recombination, especially recombination occurring in case of low quality passivation layer. In addition, by reducing such gap, the overall series resistance of the device is minimized. The present solution is based on the fabrication of two doped regions on two different levels (or cross-sectional height) which allows for minimization of the gap. Also im- portant is that the present process inherently avoids a direct contact between two adjacent oppositely doped re- gions. This quenches the series resistance and the leakage current between them making the shunt resistance very high leading to a high pseudo fill factor of >0.75. In a first exemplary embodiment solar cells with a conversion effi- ciency of 20.2 % have been fabricated; improving various aspects of the process and specifically various steps thereof a conversion efficiency of 22 % or more is achiev- able. Such relates to an improvement of 1-3% over prior art devices, which is a relative improvement of 5-15%. For return of investment such a difference is considered huge.

In the present process doping techniques are sin- gle-sided. It has been found that optimizing doping pro- files at a front side and back side separately minimizes overall electrical losses of a photovoltaic device. Moreo- ver, the present gap less structure with the two doped layers on different levels minimizes a leakage current be- tween two adjacent oppositely doped regions. Moreover, be- cause of the prior art diffusion technique, creating a gap between two doped regions requires at least one additional process step. It is noted that in an alternative approach of so-called fully implanted devices, both doped regions are fabricated via ion implantation. In this case, a gap- less and self-aligned structure could be fabricated. How- ever, the annealing of ion implanted boron is complicated. In particular, the activation of the boron atoms is not easy and when this is successfully achieved it requires a high thermal budget (T > 1000 °C) . On the contrary, the present solution allows for in-situ doping of boron, phos- phorous or arsenic, combined with phosphorous or arsenic implantation in order to activate the dopants at low tem- perature (T < 900 °C) . Such annealing advantageously oc- curs during the growth of the epitaxial layer; hence no extra annealing step is required.

With respect to prior art solar cells fabricated via diffusion, the present invention involves the use of doping techniques which can either accurately provide a required doping profile or overcome technical limitations of a diffusion process. In fact, in case of standard dop- ing diffusion, the doping profile is found to be limited by the solid solubility of the dopants in silicon, hence can not be optimized fully. The combination of e.g. ion implanted

phosphorous and epitaxial grown of Si doped in situ with e.g. boron enables the use of a low temperature annealing step (see e.g. fig. 2) . In addition, by using single-side doping techniques, the doping profile of each doped layer can be separately optimized. A disadvantage the present invention is that an additional doping is required with respect to a prior art IBC process and that epitaxial growth is not yet a mainstream technique in PV industry.

Thereby the present invention provides a solution to one or more of the above mentioned problems.

Advantages of the present description are detailed throughout the description. References to the figures are not limiting, and are only intended to guide the person skilled in the art through details of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates in a first aspect to a reduced temperature process for interdigitated back con- tacted solar cells according to claim 1. It is noted that in principle n-doped regions and p-doped regions may be in- terchanged throughout the invention/description. If an ep- itaxial layer is n-doped a back surface field is formed, if it is p-doped an emitter is formed. Dopant concentra- tions are in the order of 1*10¹⁷/cm³-5*10¹⁹/cm³.

In an example of the present process (see e.g. fig. 3) an acidic etching resistant layer is provided on the back side. Such a layer prevents etching of the silicon wa- fer. In an example the layer is a SiN layer.

Depending on the type of process and process equip- ment both sides of the wafer may be provided with an acidic etching resistant layer in one process step, only a back side layer may be provided, or two separate layers may be provided in two steps, one on the front side and one on the back side of the wafer.

A photo resist layer is applied on the back side etching resistant layer in order to define the self-aligned ion implant region (fig. 3) and to slightly under etch the epitaxial layer and silicon of the wafer, e.g. by using iso- tropic wet etching. The ion-implantation uses ions of oppo- site nature (n or p) compared to dopants being present in the epitaxial layer (p or n, respectively) . As such n-doped and p-doped regions are defined, which are at a different cross- sectional height (see e.g. fig. 4-6), are slightly separated from one and another, both in height and in lateral direc- tion, and are optionally separated by a dielectric material. Dopant concentrations are in the order of 1*10¹⁷/cm³- 1*10²⁰/cm³.

In an example the present process comprises the step of providing contacts to the at least one p-doped region and the at least one n-doped region (see figs. 7-10) . As such the photovoltaic energy can be harvested.

In an example of the present process contacts are provided by metal deposition and lift off of non-contact areas (see fig. 10) . Metal may be deposited using sputter- ing techniques. It is preferred to use copper, aluminum, or tungsten as metal. In an alternative, after deposition, the non-contact areas can be etched in order to remove the metal.

In an example of the present process an area of an epitaxial doped region is two- to eight- times an area of an ion-implanted doped region, preferably 3-4 times. In other words the epitaxial region is relatively larger com- pared to the ion-implanted region. From a practical pro- cess point of view such is advantageous. It has been found that such a ratio provides the best photovoltaic charac- teristics.

In an example of the present process an area of a p-doped region is two- to eight- times an area of an n- doped region. It has been found that electrical shading losses occurring in relation to the n-doped region are minimized.

In an example of the present process the epitaxi- al-doped region and ion-implant-doped region are separated by a distance of 0.1-5% relative to a length of the epi- taxial-doped region. As is detailed above such provides for improved characteristics of the present solar cell.

In an example the present process further compris- es the step of etching the acidic etching resistant lay- er (s), thereby removing said layer (s).

In an example the present process further compris- es the step ion implantation the front side of the wafer, thereby forming a front doped region, wherein the front doped region is independently selected from the back side doped region (see fig. 6) . The front doped region may form a front side field ( FSF) . By independently doping a front and a back side especially the fill factor of the solar cell can be improved.

In an example the present process further compris- es the step of passivating the front side and the back side of the wafer, such as by forming an oxide layer. Typ- ically oxidizing includes an annealing step, as the oxida- tion is carried out at elevated temperature. As an alter- native a PECVD may be used to provide an oxide layer. Al- ternatively a SiN layer may be provided. The passivation of front and back side of the wafer may be performed in . one combined step, or in two separate steps.

In an example the present process further compris- es the step of an anti-reflective coating on the pas- sivation layers of step (vi) (see fig. 7) . Such an anti- reflective coating improves light absorbance, and reduces recombination.

In an example the present process further compris- es the steps of providing a photo-resist, etching contact openings in the photo-resist, providing metal contacts in the contact openings, and optionally a forming of a layer for protecting the front side, a metal evaporation step and a metal removal step, such as by lift off of the metal layer, and a removal step of the photo resist (see fig. 10) . Thereby contacts are formed and the solar cell is ready to be used.

In an example of the present process p-doped re- gions and n-doped regions have a pitch of 0.1 mm-5 mm, such as of l-2mm. The pitch is used to describe a distance between repeated elements in a structure possessing trans- lational symmetry: in the present case, a sequence of al- ternating p-doped regions and n-doped regions. It has been found that by optimizing the pitch also characteristics of the solar cell can be optimized.

In an example of the present process at least one side of the wafer is provided with a texture, such as a microscale texture, a nanoscale texture, and combinations thereof, wherein the texture preferably has a high aspect ratio. The aspect ratio is preferably >20, such as >50. It has been found that a high aspect ratio improves energy conversion.

In an example of the present process the back side doped region and the front side doped region are differ- ent . In an example the front side doped region has a low dopant concentration of l*10¹⁷/cm³-l*10¹⁹/cm³, whereas the back side doped region is highly doped with a concentra- tion of 1+10¹⁹7cm³-1*10²⁰/cm³.

In a second aspect the present invention relates to an improved solar cell or light detector according to claim 14. It comprises at least one epitaxial-doped region and at least one self-aligned ion-implant-doped region, p- type and n-type contacts at a back side thereof, a front surface field, a back surface field, and an emitter at the backside, and wherein the least one epitaxial-doped region and the at least one ion-implant-doped region are at a different cross-sectional height and are separated by a dielectric material. Details and advantages thereof are described above.

In an example the present solar cell or light detector has an efficiency of > 21%, a series resistance of < 1 Ohm*cm, a shunt resistance of > 1000 Ohm*cm, a fill factor of > 75%, a pitch of 0.1-5 mm, wherein the epitaxi- al-doped region and ion-implant-doped region are separated by a distance of 0.1-5% relative to a length of the epi- taxial-doped region, a leakage current of < 1000 fA/cm². It preferably has a front side aspect ratio of >50.

In an example the present device has a different

FSF and BSF.

The invention is further detailed by the accompa- nying figures and examples, which are exemplary and ex- planatory of nature and are not limiting the scope of the invention. To the person skilled in the art it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, de- fined by the present claims.

SUMMARY OF FIGURES Figures 1-10 show a schematic representation of an example of the present process.

Fig. 11 shows a cross-section (SEM) of the present device.

DETAILED DESCRIPTION OF FIGURES

In the figures:

100 Si wafer

110 Epitaxial layer

120 Acidic etching protective (SiN)

130 Photoresist layer

140 BSF n-doped layer

150 FSF

160 Passivation layer (SiO2)

121 Anti-reflective coating (SiN)

131 Photoresist

170 Metal contact (A1)

The figures are further detailed in the description of the experiments below.

In figure 1 a silicon wafer 100 is provided. In figure 2 an epitaxial layer 110 (as an emitter) is deposited on the silicon wafer at a temperature of 900 °C. The epitaxial layer is deposited during 11 minutes at a rate of 90 nm/min. The silicon layer is doped with boron

(3*10¹⁹/cm³) . During deposition the dopants are activated, due to the elevated temperature used.

In figure 3 a protective SiN layer 120 is provided, on both sides of the wafer, i.e. at a bottom side on the epi- taxial layer, at a top side on the silicon surface of the wa- fer. The protective layer is resistant to acidic etching. The layer is deposited at a temperature of 400 °C using PECVD and SiH₄, NH₃, and H₂. The epitaxial layer is deposited during 10 minutes at a rate of 8 nm/min.

Further a photoresist layer 130 was applied to the

SiN layer. A mask was used to form an image in the photore- sist layer, defining opposite doped regions, in this case n- doped regions. Dry etching (C₂F₆) was used to etch the SiN layer at a pressure of 130 mTorr, during 30 seconds and at a room temperature.

In figure 4 the photoresist was stripped using a plasma O₂ stripper for 5 minutes and the silicon was etched using HNO₃/HF with ratio of 1:1. Thereby the Si is iso- tropically etched underneath (11) the SiN layer, typically about 2 urn.

In figure 5 a BSF n-doped layer 140 is fabricated via ion implantation of Phosphorus (P) . The SiN layer shields the p-doped region from the P-ions. In this way both doped regions are gap-less and self-aligned.

In figure 6 the back side and front side SiN 120 is etched in buffered HF (BHF) for 6 minutes. Ion implantation of P is performed at front side of the wafer in order to fab- ricate the FSF 150.

In figure 7 co-annealing of both BSF and FSF is per- formed at 850°C in O₂ leading to the growth of dry S1O₂160 on both sides of the wafer. PECVD SiN 121 with thicknesses around 45 run ant FS and 100 nm at BS are deposited.

In figure 8 BS of the wafer is coated with photore- sist 131 which is exposed and developed in order to define the metallization regions.

In figure 9 front side of the wafer is coated with photoresist 131 and both SiN and S1O₂ are etched in BHF for 3 minutes.

In figure 10 an Aluminum layer 170 of 2um thickness is evaporated at BS. Finally acetone is used to etch photore- sist form both sides of the wafer. During the etching metal lift-off occurs at the BS.

Fig. 11 shows a cross-section (SEM) of the present device. Therein an h+collector 110 is indicated, a SiN layer 120, an e- collector 140 and a Si wafer 100, before SiN bar- rier etching. Right to the dotted white line an under-etched area is visible. This figure shows a particular of the pre- sent self-aligned process. This step together with combina- tion of doping techniques is considered to constitute to the present invention.

EXAMPLES/EXPERIMENTS

The invention although described in detailed explana- tory context may be best understood in conjunction with the accompanying examples and figures .

It should be appreciated that for commercial appli- cation it may be preferable to use one or more variations of the present system, which would similar be to the ones dis- closed in the present application and are within the spirit of the invention.

Claims

1. Reduced temperature process at a temperature < 900 °C for activating dopants for interdigitated back contacted devices, such as a solar cell and a light detector, compris- ing the steps of

(i) providing a wafer (100), having a front side and a back side,

(ii) growing an epitaxial layer (110) on a back-side of the wafer, wherein the epitaxial layer is n-doped or p-doped by dopants,

(iii) providing openings in the epitaxial layer, wherein the epitaxial layer is under-etched,

(iv) ion implanting p-dopants (in case of an n-doped ep- itaxial layer) or n-dopants (in case of a p-doped epitaxial layer) wherein the n-doped region and p-doped region are at a different cross-sectional height of the wafer and are self- aligned, thereby forming a back side doped region.

2. Process according to claim 1, wherein after providing the epitaxial layer,

(iiia) an acidic etching resistant layer (120) is provided on the back side,

(iiib) optionally an acidic etching resistant layer (120) is provided on a front side of thl wafer,

(iiic) a photo resist layer (130) is applied on the back side etching resistant layer, and

(iiid) p-doped or n-doped regions (140) are defined with lithography, and are etched using isotropic etch- ing, thereby self-aligning the doped regions.

3. Process according to any of the preceding claims, further comprising the step of

(ix) providing contacts to the at least one p-doped region and the at least one n-doped region.

4. Process according to claim 3,

wherein contacts are provided by metal deposition and lift off thereof.

5. Process according to any of the preceding claims, wherein an area of an epitaxial doped region is two- to eight- times an area of an ion-implanted doped region.

6. Process according to any of the preceding claims, wherein an area of a p-doped region is two- to eight- times an area of an n-doped region.

7. Process according to any of the preceding claims, wherein the epitaxial-doped region and ion-implant-doped re- gion are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region.

8. Process according to any of the claims 2-7, compris- ing the steps of

(iv) etching the acidic etching resistant layer (s), and

(v) ion implantation the front side of the wafer (150), thereby forming a front doped region, wherein the front doped region is independently selected from the back side doped region.

9. Process according to claim 8, further comprising the steps of

(vi) passivating the front side (160) and the back side 121) of the wafer, and

(vii) forming an anti-reflective coating (121) on the passivation layers of step (vi) .

10. Process according to any of the preceding claims, wherein contacts are provided by

(viiia) providing a photo-resist (131),

(viiib) etching contact openings in the photo-resist,

(viiic) providing metal contacts (170) in the contact openings.

11. Process according to any of the preceding claims, wherein p-doped regions and n-doped regions have a pitch of 0.1 mm-5 mm.

12. Process according to any of the preceding claims, wherein at least one side of the wafer is provided with a texture, such as a microscale texture, a nanoscale texture, and combinations thereof, wherein the texture preferably has a high aspect ratio.

13. Process according to any of the claims 8-12, wherein the back side doped region and the front side doped region are different.

14. Improved interdigitated back contacted device, se- lected form a Si-based solar cell and a light detector, ob- tained by a method according to any of claims 1-13, compris- ing at least one under etched epitaxial-doped region and at least one self-aligned ion-implant-doped region, p-type and n-type contacts at a back side thereof, a front surface field, a back surface field, and an emitter at the backside, and wherein the least one epitaxial-doped region and the at least one ion-implant-doped region are at a different cross- sectional height and are separated by a dielectric material, having a shunt resistance of > 1000 Ohm*cm, a fill factor of > 75%, wherein the epitaxial-doped region and ion-implant- doped region are separated by a distance of 0.1-5% relative to a length of the epitaxial-doped region, and a leakage cur- rent of < 1000 fA/cm².

15. Device according to claim 14, having one or more of an efficiency of > 21%, a series resistance of < 1 Ohm*cm, and a pitch of 0.1-5 mm, a front side aspect ratio of >50, and a different front side field (FSF) and back side field (BSF) .