WO2016050879A1

WO2016050879A1 - Field-effect transistor with optimised mixed drain contact and manufacturing method

Info

Publication number: WO2016050879A1
Application number: PCT/EP2015/072624
Authority: WO
Inventors: Sylvain Delage; Bernard Carnez; Raphaël Aubry; Olivier JARDEL; Nicolas Michel; Mourad OUALLI
Original assignee: Thales
Priority date: 2014-10-03
Filing date: 2015-09-30
Publication date: 2016-04-07
Also published as: FR3026892A1; FR3026892B1; EP3201949A1; CN107078153A

Abstract

The invention relates to a field-effect transistor comprising a substrate and a semi-conductor structure having a channel area, said transistor comprising a drain contact, a source contact and a gate, said source and drain contacts making it possible to generate a flow of charge carriers in the channel area, said flow being controlled by said gate, characterised in that: said drain contact is a mixed drain contact comprising at least one elementary ohmic continuous drain contact (CD_oh) and an elementary Schottky drain contact (CD_Sch), said mixed drain contact being flush with said semiconductor structure; said elementary Schottky drain contact (CD_Sch) partially or completely overlapping said elementary ohmic drain contact (CD_oh). The invention also relates to a method for manufacturing said transistor.

Description

FIELD OF THE INVENTION Field of the invention is that of the field effect components and in particular that of the transistors whose fields of application are both those of the microwave frequencies and those of the transistor. ^power electronics. The present invention is more specifically focused on producing the contacts and access resistance of the drain contact of a field effect component while facilitating the production of components in a collective manner and which may have different characteristics, and in particular in the case of components with submicron grid sizes.

In general, the field effect transistors contact a semiconductor rod (s) using three contacts:

an ohmic source contact;

a gate corresponding to a contact which may be of Schottky type (metal-semiconductor) or a junction of a semiconductor of the opposite type to that of the semiconductor in which the carriers propagate;

an ohmic drain contact.

Figure 1 shows the block diagram of a field effect transistor. The conventional solution is to use two ohmic contacts of DC drain and CS source subjected to a voltage Vds, to inject and collect the carriers schematized by the current Ids, whose flow is controlled by the voltage Vgs carried at the gate BOY WUT.

These types of components are widely used and described in introductory books, including: "Physics of semiconductors and electronic components" Courses and exercises, Henry Mathieu, Herve Fanet Collection: Sciences Sup, Dunod 2009-5 ^th edition - EAN13 : 97810051 6438

In general, the ohmic contacts are differentiated from the so-called Schottky contacts by the function of evolution of the current as a function of the applied voltage. In the case ^of an ohmic contact, this function is linear and passes through 0, then it has a lower threshold voltage V _min for that the current is non-zero in the case of a Schottky contact. A simple ohmic contact must be made in such a way that no energy barrier opposes the crossing of the interface between the ohmic contact and the semiconductor to be contacted, which limits the access resistances.

Conventional ohmic contact fabrication solutions are based on three approaches that are not exclusive of each other. It is important to mention that some semiconductor materials do not make it easy to use all three processes for different reasons (thermal budget, unrealizable heterostructure, insufficient maximum doping, etc.).

More specifically, these methods are as follows:

the inter-diffusion of metal alloys with the semiconductor;

the very high doping of the semiconductor, which makes it possible to greatly reduce the thickness of the space charge zone and therefore the crossing of the Schottky barrier by a tunnel effect or equivalent;

the use under the metal electrode of a semiconductor alloy by engineering the energy bands, leading to the absence of a Schottky barrier at the interface.

These three approaches all require a high thermal budget, and for some semiconductor materials the contact resistances at the metal-semiconductor interface remain too high and impair the electrical performance of the devices. We are inclined to look for ways to reduce the resistance of ^access, including the drain contact. The Applicant has started from the observation that this contact resistance is lower in the case of a direct biased Schottky contact, compared to that of a conventional ohmic contact and proposed to solve the problem posed, a solution concerning an effect transistor. field, having a mixed drain contact.

It should be noted that the use of contact has already been proposed

Schottky and in particular in the articles of A Girardot, A Henkel, SL Delage, M. -A DiForte-Poisson, E. Chartier. D. Floriot, S. Cassette and PA Rolland, "High performance collector-up InGaP / GaAs heterojunction bipolar transistor with Schottky contact", Electronics Letters, Vol.35. pp.670-672, 1999, or article: Schottky Drain AIGaN / GaN HEMTs for mm-wave Applications, X. Zhao, JW Chung, H. Tang, T. Palacios, 1 - 4244-1 1 02-5 / 07 2007 IEEE. The disadvantage of this approach lies in an important waste voltage since it is necessary for the junction to go live to drive.

^For that reason, and in this context, the present invention relates to a field effect transistor comprising a substrate and a semiconductor structure having a channel region, said transistor comprising a drain contact, a source contact and a gate said source and drain contacts for generating a charge carrier stream in the channel region, said flow being controlled by said gate, characterized in that:

said drain contact is a mixed drain contact comprising at least one continuous drain ohmic elementary contact and a drain Schottky elementary contact, said mixed drain contact flush with said semiconductor structure;

said elementary Schottky drain contact partially or totally overlapping said ohmic drain elementary contact.

The use of a continuous contact allows easy manufacture with a satisfactory manufacturing yield by avoiding submicron lithographs. The fact that the contact extension Schottky is flush avoids discontinuities and potential peak effect decreasing both the effective electric field accessible and likely to increase the leakage currents of the transistor. With the remaining planar contact, it is possible to avoid etching steps as fine as 5nm critical, even in the case where etching selectivities exist between materials, the electron gas being very sensitive to the surface conditions.

In addition, the elemental Schottky drain contact partially or totally overlapping said ohmic drain elementary contact allows for reliable fabrication easily taking into account alignment and lithographic dimensional tolerances, perfect juxtaposition being impossible. The additional advantage is to easily allow a setting at the same potential of the Schottky contact to that of the ohmic drain contact. According to one variant of the invention, the source contact is a mixed contact comprising at least one source ohmic source contact and a source Schottky elementary contact.

According to a variant of the invention, the elementary Schottky drain contact and / or the source Schottky elemental contact partially overlaps the ohmic elementary drain contact and / or the source ohmic source contact. The term partial overlap means that the ohmic drain and / or source elementary contact is covered by a Schottky elementary contact of drain and / or source, said Schottky elementary contact also having a portion in contact with said substrate.

According to a variant of the invention, said gate comprises a Schottky type contact: metal / conductor.

According to one variant of the invention, said grid has a complex shape presenting:

a so-called lower part, called a gate foot, in contact with the semiconductor structure comprising the channel zone and having a first section;

a so-called high second portion, referred to as a gate cap, in contact with said lower portion and having a second section;

said first section being lower than said second section. According to a variant of the invention, the semiconductor structure comprises a set of layers of materials III-V, of which at least two materials have different forbidden bands, the largest (s) band (s) prohibited (s) for the containment of free carriers in the smallest bandgap.

According to a variant of the invention, the transistor comprises a dielectric layer covering the source contact and / or the drain contact and / or the gate.

According to a variant of the invention, the transistor further comprises a metal field plate located on said dielectric at said gate. The subject of the invention is also a component comprising a set of field effect transistors, comprising several subsets of transistors according to the invention:

a subset of transistors being characterized by a width between the gate and the mixed drain contact and a width between said gate and the ohmic elementary contact of said mixed drain contact, for each of the transistors of said subset;

said width between the gate and the mixed drain contact being different from one subset to the other;

said length between the gate and the ohmic elementary contact of said mixed drain contact being identical from one subset to the other. It should be noted that the control of the field effect transistors is generally carried out using a metal grid which can be isolated (for example MOSFET or MOSHEMT) or not (HEMT, MESFET, etc.) from the underlying semiconductor. This metal grid is all the more difficult to realize that the cutoff frequencies of power gains and power are high. Indeed, it is necessary to control a grid foot length can be below 80 nm while ensuring a profile to reduce the series resistance obtained by increasing the section at the top of the electrode.

The conventional method of producing a grid uses electronic or even optical lithographs. A stack of two different electro-sensitive resins (or even photosensitive for optical steppers) is used which makes it possible to form a metal grid of a suitable profile, generally called "mushroom".

Solutions with successive electronic or optical lithographs are also used by first opening the gate foot through a dielectric and then making a second lithography which delimits the "hat" of the grid. A metal deposit is then made which allows to "mold" a grid in the form of Gamma or T.

Due to the current reliefs related to the different topologies and the process, the calibration of the grid manufacturing processes is critical and causes dimensional, even functional, unsatisfactory variations affecting manufacturing yields and component performance.

It should be noted, more than for analog or power applications it is useful to modify certain dimensions of the components. It thus becomes very interesting to be able to have a maximum of reproducibility in the collective processes for manufacturing sets of transistors made simultaneously and collectively, the transistors within the same set being identical but different from one set to the same. other.

Using conventional manufacturing techniques, the

Applicant has detected a manufacturing performance problem when attempting to modify certain key dimensions of the devices.

The origin of the problem lies essentially in the variations of the thicknesses of the resins used to define the gate electrode during the crossing of the walkways, in this case ohmic contacts source and drain.

Figure 2 shows for this purpose, the critical parameters that define the topology ^of an elementary component, knowing that the final component often involves the parallelization of several basic components. The perpendicular dimension is not represented but it defines the total development of the transistor.

It can also be noted that linear geometries are widely used although it is also possible to use circular or polygonal geometries.

It thus appears that the following parameters have the following impacts on the operation of the component:

the gate length Lg which is related to the current transit frequency, said frequency decreasing when said gate length Lg increases;

the section of the gate cap CG making it possible to size the gate resistance, while ensuring that said gate can have a narrow foot, this section influencing the gate resistance and the gain in microwave power;

the height of the gate foot Hg which influences the gate-source capacity and the higher this height Hg, the less the coupling between the gate cap and the channel is important, allowing to increase the gain in power;

the distance Lds between source and drain which influences the breakdown voltage of the component (power) and the microwave gain (the greater the distance Ldg is large and the greater the breakdown voltage is important but at the cost of a degradation of the microwave gains);

the distance Lgs between the gate and the source which influences the series resistance Rs and the Grid-Source voltage resistance.

As mentioned above, it is however necessary to be able to define on the same semiconductor wafer components of variable topologies to obtain power levels, gains and electrical efficiencies.

To do this, the necessary optimizations are very heavy because of the thickness variations of electro-sensitive or photosensitive resins during walking.

In a conventional method the ohmic contacts are defined and then the gate contact. The indicated order is often conditioned by the high thermal budget to make the ohmic contacts (metal alloys, ion implantation anneals, etc.). To illustrate the difficulty, the annealing of the ohmic contacts in GaN technology often reaches 850 ° C for one to two minutes, ie a heat budget difficult to impose on Schottky contacts. These ohmic contacts have a thickness e_s and e_d which is close to the height of the gate foot Hg in order to have the sufficient lithographic resolution.

A conventional method of producing a grid having a CG cap is to use at least two resins:

can be deposited on one another (the cavity which defines the complex shape: foot + hat is then obtained by chemistries and sensitivities different from the insolations and the physicochemical revelations);

or two successive masks (a first resin, with etching of a dielectric to define the gate foot, followed by the use of a second resin to define the shape of the cap CG). The complex cavity being thus defined beforehand, the final filling of the cavity is carried out by a metal sandwich.

FIG. 3 shows the sectional view of a field effect transistor during the coating of the first resin. It is noted that the filling of the Lds interval is performed differently depending on the coating, viscosity and post-coating creep conditions of the resin, leaving an inherent width. The thickness of this first resin varies and it is even thicker than the length Lds is small.

According to the distance, the applicant estimated at 25% the variation of thickness when the distance Lds is modified from 10 μηι to 1, 5 μηι for an electrosensitive resin used for grids up to 0,15 μητ A consequence on the performance of manufacturing is shown as an example of 90% for standard topologies and drops to 40% for grid-source deviations of 0.5 μηι.

In concrete terms, the longer the gate length decreases, the more the optimizations of the electronic doses to define the grid (length and shape) become critical. It is necessary to define specific doses for given coating conditions for each distance of a given family and therefore dimensions Lds, Lgs, Lg desired.

Therefore, in this context, the present invention also relates to a method of manufacturing a field effect transistor according to the invention, characterized in that it comprises the following steps:

the realization of at least one source ohmic source contact and a continuous drain ohmic elementary contact on the surface of a semiconductor structure;

- the realization of a grid;

- The realization of at least one Schottky elementary drain contact so as to achieve a mixed drain contact comprising at least one ohmic elementary contact and a Schottky elementary contact.

According to a variant of the invention, the method comprises the realization of a source Schottky elementary contact so as to achieve a mixed source contact comprising at least one ohmic elementary contact and a Schottky elementary contact. According to a variant of the invention, the realization of the elementary Schottky drain and / or source contact is made by partially overlapping respectively said ohmic elementary contact drain and / or associated source.

According to a variant of the invention, the grid having:

said first section being smaller than said second section, said method comprises:

successively carrying out at least two resin deposition and photolithography steps to define said first and second portions of said grid, subsequent to the production of said ohmic source and drain contacts.

According to a variant of the invention, the realization of said elementary Schottky drain contact and / or Schottky elementary source contact is (are) carried out simultaneously with the production of said gate.

According to a variant of the invention, the realization of said elementary Schottky drain contact and / or said source Schottky elementary contact is (are) carried out simultaneously with the realization of said gate cap.

Finally, the subject of the invention is a method of collective fabrication of a set of field effect transistors, said set of transistors comprising subsets of transistors:

transistors of the same subset of transistors having a width between the gate and the identical mixed drain contact for each transistor of the same subset and different from one subset to the other;

the width between the gate and the ohmic elemental drain contact being identical from one subset to the other, characterized in that it comprises the following steps:

the realization of ohmic source and drain contacts; - the realization of the grids;

- The realization of Schottky elementary drain contacts, the widths between said grids and said elementary Schottky drain contacts being different from one subset to the other and identical for the transistors of the same subset.

The invention thus makes it possible to improve the production efficiency of the field effect transistors while improving their power efficiencies.

The invention will be better understood and other advantages will become apparent on reading the description which follows given by way of non-limiting example and by virtue of the appended figures among which:

FIG. 1 illustrates the block diagram of a field effect transistor;

FIG. 2 illustrates the technological parameters that are important for the optimization of a field effect component.

FIG. 3 illustrates the effects of the deposition of a resin with step transition between drain and source contacts for the production of a field effect transistor;

FIG. 4 illustrates a first component variant according to the invention;

FIG. 5 shows the block diagram of a transistor according to the invention comprising a mixed drain contact;

FIG. 6 illustrates a second component variant according to the invention;

FIG. 7 illustrates a third component variant according to the invention;

FIG. 8 illustrates a fourth component variant according to the invention;

FIG. 9 illustrates an exemplary component according to the invention;

FIG. 10 details the grid formed according to the example illustrated in FIG. 8;

FIG. 11 illustrates a method of collective fabrication of transistors, making it possible to produce different sizes of components, with variable dimensions of Li _G -D width between grid and mixed drain contact.

The present invention thus relates to a component in which the drain contact which is mixed combines a conventional elementary ohmic contact and a metal-semiconductor Schottky elementary contact. It thus makes it possible to have to optimize only once the lithographic profile of the grid and this for a wide range of distance between ohmic contacts drain and source, for a given gate-source distance.

It makes it possible to preserve or even improve the added power efficiencies without deterioration of the small signal gains (improved breakdown voltages, slight improvement of the series resistances).

It also makes it possible to define a precise drain contact limiting the risks of peak effect arising either from poor lithographic definition or from interdiffusions, the conventional ohmic contacts presenting in particular a risk of local fluctuation of the contact resistances and therefore the appearance of filamentation phenomena.

Using a live Schottky elemental contact to collect carriers can also improve reliability by providing a more consistent collection of carriers. In addition, in the high-voltage locked mode (low current operation lds _co and lds _C h and high voltage Vds), the Schottky contact of the mixed ohmic contact assures a role of field shield plate (Field plate) improving the voltages of breakdown of the component.

A first example of a component according to the present invention is illustrated in FIG. 4, comprising a mixed drain contact. On a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:

an ohmic contact of source C _s oh!

a gate G in the form of a mushroom;

a mixed drain contact comprising an ohmic elementary contact of drain C _D oh and a Schottky elementary contact of drain C _{D s} Thus, according to the present invention, the continuity of elementary Schottky drain contact, partially covering ^the end of the elementary contacting ohmic drain which may have imperfections, overcomes the potential defects of achieving ohmic contact. The ohmic contact is located at a sufficiently distant distance for the Schottky drain contact to cover the different spacings required for the intended applications.

When making the gate, the elementary Schottky drain contact can also be realized. The unevenness of conventional ohmic contacts crossed by the resins successively used to make the grid are therefore constant. This ensures a better manufacturing yield.

The Schottky elementary drain contact also provides the possibility of a contact with low resistance (direct-to-majority junction) above the elbow voltage of the Schottky diode. This is achieved more with a low thermal budget.

Conventional resistance in parallel on the Schottky diode governs the current from which the diode passes live. Beyond a current threshold Ids, the Schottky diode goes live and the drain resistance becomes very low. Below this threshold, the Schottky contact is blocked and makes it possible to create a field plate which can limit the maximum field at the edge of the drain contact (improvement of the reliability). The conduction threshold of the Schottky diode is reached when the following equation is obtained:

(Rco + Rsh ') ^* lds_co = Vschottky_seuil.

FIG. 5 illustrates the diagram of an ohmic drain contact by association of a conventional ohmic contact and a Schottky contact. The current lds_co (in solid lines) corresponds to the current passing conventionally via the ohmic contact.

The lds_Sch current (in dotted lines) represents the current flowing through the Schottky contact.

The resistance control associated with the traditional ohmic contact is obtained either by playing on the topology of the contact (length of the semiconductor rod to be crossed, width of the ohmic contact), or on the conductivity of the semiconductor, or by using for this plate of a Schottky junction field with a low potential barrier.

As the dimensional definition of the Schottky contacts is often better both in the plane of the surface and vertically within the materials, the breakdown voltages can be improved according to the semiconductors contacted.

FIG. 6 schematizes a second example of a component according to the present invention comprising a mixed drain contact and a mixed source contact.

For some applications, it is indeed possible to achieve the same mixed contact for the source (Schottky contact also placed close to the gate and the distant conventional ohmic contact). This symmetrical structure allows symmetrical operation. This is nevertheless achieved with an increase in the source resistance.

On a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:

a source mixed contact comprising an ohmic elementary contact of source C _{S 0} h and a Schottky elementary contact of source C _{S s} ch;

a gate G in the form of a mushroom;

a mixed drain contact comprising an ohmic elementary contact of drain C _D oh and a Schottky elementary contact of drain C _{D s}

FIG. 7 schematizes a third example of a component according to the present invention comprising a mixed drain contact. On a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:

an ohmic contact of source C _{S 0} h;

a gate G in the form of a mushroom;

The mixed drain contact is associated with a field plate to avoid electric field peaks. This field plate P _ch which can be brought to the potential of the source or of the gate is materialized by a conducting layer above a dielectric layer 2 and surrounding said gate G.

This field plate may or may not be made of the same metal as that of the Schottky elemental drain contact C _{D s}

FIG. 8 schematizes a fourth example of a component according to the present invention comprising a mixed drain contact. On a substrate 1 comprising a not shown channel that can be simple or heterostructure are produced:

an ohmic contact of source C _{S 0} h;

a gate G in the form of a mushroom;

a mixed drain contact having an ohmic drain elementary contact C _D oh and a Schottky elementary contact of drain Co sch-

The mixed drain contact is associated with a field plate P _{ch that} can be brought to the potential of the source or the gate and which is materialized by a conductive layer above a dielectric layer 2 and surrounding said gate G.

^The end of the Schottky contact vis-à-vis the gate drain comprises a protuberance on the dielectric for amplifying the drain field plate effect.

The physical simulations carried out show that the invention makes it possible to obtain, for microwave applications, preserved or even improved performances above 10 GHz, probably by reducing the resistance in dynamics of the resistance of the drain (a preliminary simulation indicates a improvement of the electrical efficiencies and power output Pout: + 2% of the power output added (RPA = [Pout - Pin] / Pdc where Pin is the RF power incident on the component and Pdc is the electrical power consumed by the component at 20GHz and + 6% power compared to a conventional 10 GHz component.) It should be noted that the modelizations do not do not take into account the improvement that can be expected in the breakdown voltages due to the presence of integrated field plate in the drain contacts.

In a simple variant, the realization of Schottky drain contacts does not require additional level of lithography. It is possible to form these contacts at other stages of the process succeeding the realization of the gate (for example during a level of the field plate type for example).

Exemplary embodiment of a field effect transistor HEMT, according to the invention.

FIG. 9 illustrates the production of a stack of layers enabling the constitution of a field effect transistor heterostructure.

On a homogeneous crystalline substrate 100 or not (SiC, Si, sapphire, GaN or composite) is carried out ^the following heterostructure by ^stacking layers below:

a nucleation layer 101 allowing growth on the heterogeneous substrate (SiC, Si, or sapphire);

a layer or set of layers 102 enabling the control of mechanical stresses;

a buffer layer 103 of GaN or doped or non-doped GaN compound allowing the confinement of the free carriers present in the layer 104;

a layer 104 of GaN semiconductor channel (which may have a thickness of 40 nm to 250 nm depending on the applications);

a barrier layer 105 in AI ₂ 5 _% Gay _5% N (which may have a thickness 25nm) or in ln _x Ali. _x N;

a doped or undoped GaN encapsulation layer 106 (which may have a thickness of 2 nm) or another dielectric.

The ohmic source contact C _{S Oh} and the elementary ohmic drain contact C _{D 0h are then made} in a known manner by diffusion from Ti / Al / Ni / Au deposits and rapid thermal annealing operation. The gate G is also produced. FIG. 10 illustrates, for this purpose, the various metallic layers constituting the gate, for example: Ni / Pt / Au, in the central cavity previously made by successive resin deposits, for example, in order to obtain the complex shape.

The Schottky elemental drain contact C _D _S ch is also made with a metal structure (not shown).

Upper layers of passivation are not shown. The first layer in contact with the GaN free surface may be silicon nitride of a hundred nanometers thick.

The dimensions of the various elements can be as follows:

the gate width Lg may typically be 0.15μηι but may vary between 0.05μηπ to several microns;

the width between the drain contact and the Ldg gate may be between 0.5μηπ and several tens of microns depending on the cut-off frequencies of the microwave gains and the targeted breakdown voltages;

the width between the gate and the source contact Lgs is generally shorter than the width Ldg but may also range from 0.5μηπ to several microns;

- The gate height Hg can typically be 0.25 μηι up to 2 μηι and beyond;

the total height of the gate may typically be 0.4 μηι, but also may be optimized from 0.1 μηη to several microns.

According to the target performance in terms ^of microwave frequencies and currents, the shape of the grid can be adjusted. Typically, the shape can be a mushroom as previously illustrated for grids shorter than Ο, δμηπ, beyond this form is not necessary. A rectangular shape can be considered also for very short grids, but this may increase the series resistance of the grid.

The thicknesses of source and drain contacts e_s and e_d can typically be 0.2μηι, this value being relatively free. According to the present invention, it is advantageous to collectively produce components having different characteristics, avoiding differentiated delicate steps to make the ohmic contacts, the most complex contacts to obtain.

Figure 1 1 illustrates such a collective method for producing a set ^of components to the surface of a substrate according to the invention. Advantageously, the step of complex realization of the set of ohmic contacts can be performed in a uniform manner.

The step of producing the Schottky drain contacts is carried out in a second step and makes it possible to achieve the desired differentiation between components having different performances and characteristics by obtaining distances between grids and elementary Schottky drain contacts (C _{D s} ch ) variables. Is thus obtained subsets of transistors ST _\, ST _{i +} comprising:

gate widths and Li _G -D mixed drain contact varying from one subset to the other, ie Li _G -D ≠ L i + 1 _G -D;

gate widths and ohmic elementary drain contact equal from one subassembly to the other, ie: Li _G -CD oh = L i + 1 _G- cD oh

The invention thus enables n ^having to optimize lithographic once the profile of the gate and for a wide range of distance between the source and drain ohmic contacts, for a given gate-source distance.

Claims

CLAIMS 1. A field effect transistor having a substrate and a semiconductor structure having a channel region, said transistor having a drain contact, a source contact, and a gate, said source and drain contacts for generating a carrier stream. charge in the channel area, said flow being controlled by said gate, characterized in that:

said drain contact is a mixed drain contact comprising at least one continuous drain ohmic elementary contact (CD oh) and a drain Schottky elementary contact (CD sch), said mixed drain contact flush with said semiconductor structure;

said elementary Schottky drain contact (CD sch) overlapping partially or totally said ohmic elementary drain contact (CD oh) -

2. Field effect transistor according to claim 1, characterized in that the source contact is a mixed contact comprising at least one source ohmic source contact (Cs oh) and a source element Schottky contact (Cs sch) -

Field effect transistor according to Claim 1 or Claim 2, characterized in that the Schottky elemental drain contact (CD sch) and / or the Schottky elementary source contact (Cs sch) overlap (s) partially the contact. resistor ohmic element (CD oh) and / or ohmic elementary source contact (Cs oh) - 4. Field effect transistor according to one of claims 1 or

3, characterized in that said grid comprises a contact of Schottky type: metal / conductor.

5. Field effect transistor according to one of claims 1 to 4, characterized in that said gate has a complex shape having: a so-called lower part, called a gate foot, in contact with the semiconductor structure comprising the channel zone and having a first section;

said first section being lower than said second section.

6. field effect transistor according to one of claims 1 to 5, characterized in that the semiconductor structure comprises a set of layers of materials III-V, at least two materials have different band gaps, the (the) largest prohibited band (s) for confinement of free carriers in the smallest bandgap.

Field effect transistor according to one of claims 1 to

6, characterized in that it comprises a dielectric layer covering the source contact and / or the drain contact and / or the gate.

8. Field effect transistor according to claim 7, characterized in that it comprises a metal field plate located on said dielectric at said gate.

9. Component comprising a set of field effect transistors, comprising several subsets of transistors according to one of claims 1 to 8:

a subset of transistors (STi) being characterized by a width between the gate and the mixed drain contact (L1 _G- D) and a width between said gate and the ohmic elementary contact (Li G-cD oh) of said contact mixed drain, for each of the transistors of said subset;

- said width between the gate and the combined drain contact (Li _G-D) being different from one subset to another;

said width between the gate and the ohmic elementary contact (Li G-CD oh) of said mixed drain contact being identical from one subset to the other.

10. A method of manufacturing at least one field effect transistor according to one of claims 1 to 8, characterized in that it comprises the following steps:

the realization of at least one source ohmic source contact (C _{s 0} h) and a continuous drain resistive elementary contact (C _{D 0} h) on the surface of a semiconductor structure;

- the realization of a grid;

the realization of at least one Schottky elementary drain contact (C _{D SC} h) so as to produce a mixed drain contact comprising at least one ohmic elementary contact (C _{D 0} h) and a Schottky elementary contact (C _{D s);} hp) -

1 1. A method of manufacturing a field effect transistor according to claim 10, characterized in that it comprises the realization of a source Schottky elementary contact (C _{s SC} h) so as to achieve a mixed source contact comprising at least one minus an ohmic elementary contact (C _{S 0} h) and a Schottky elementary contact (C _{S s} ch) -

12. A method of manufacturing a field effect transistor according to claim 1 1, characterized in that the realization of the Schottky elementary contact drain and / or source is performed by partial overlap respectively of said ohmic elementary drain contact and / or or associated source.

13. A method of manufacturing a field effect transistor according to one of claims 10 to 12, characterized in that the gate having:

said first section being smaller than said second section, said method comprises: successively carrying out at least two resin deposition and photolithography steps to define said first and second portions of said grid, subsequent to the production of said ohmic source and drain contacts.

14. A method of manufacturing a field effect transistor according to one of claims 10 to 13, characterized in that the realization of said elementary Schottky drain contact (C _{D s} ch) and / or said source Schottky elementary contact. (C _{s SC} h) is (are) performed simultaneously with the realization of said grid.

15. A method of manufacturing a field effect transistor according to claims 13 and 14, characterized in that the realization of said Schottky elementary drain contact (C _{D SC} h) and / or said source Schottky elementary contact (C _{s SC} h) is (are) performed simultaneously with the realization of said gate hat.

16. A method of collective fabrication of a set of field effect transistors, said set of transistors comprising subsets of transistors;

the transistors of the same subset of transistors (STi) having a width (L 1 _G -D) between the gate and the identical mixed drain contact for each transistor of the same subset and different from a sub - together with the other;

the width between the gate and the ohmic elemental drain contact (Li o-cD oh) being identical from one subset to the other, characterized in that it comprises the following steps:

the realization of ohmic source and drain contacts;

- the realization of the grids;

- The realization of Schottky elementary drain contacts

(C _D sch), the widths between said grids and said elementary Schottky drain contacts being different from one subset to the other and identical for the transistors of the same subset.