WO2016044980A1

WO2016044980A1 - Thread migration method, apparatus and system

Info

Publication number: WO2016044980A1
Application number: PCT/CN2014/087101
Authority: WO
Inventors: 李景超
Original assignee: 华为技术有限公司
Priority date: 2014-09-22
Filing date: 2014-09-22
Publication date: 2016-03-31
Also published as: CN105637483A; CN105637483B

Abstract

Provided are a thread migration method, apparatus and system, which determine a target processor core suitable for thread migration via a cluster controller according to state information about various processor cores in a target cluster, and sends context information about a thread to the target processor core, thereby implementing thread migration between clusters.

Description

Thread migration method, device and system

Technical field

The embodiments of the present invention relate to communication technologies, and in particular, to a thread migration method, apparatus, and system.

Background technique

In a traditional on-chip multi-processor system (hereinafter referred to as CMPs), when a thread requested by a core thread is not in a cache (Cache), the data is passed through the network on chip. Moved to the core's cache for thread access, however, when threads need continuous or frequent access to data, moving data between cores creates a large amount of traffic overhead.

In the prior art, by migrating a thread to a core in which the data requested to be accessed is stored, the data is accessed. In hardware implementation, the traffic cost caused by thread migration is much smaller than the traffic overhead caused by data handling. However, with the development of on-chip network technology, many-core architecture has become a trend for big data applications in the future. Many core architectures are clusters, each cluster contains multiple cores, and when the thread requests access data. When not in the core of the cluster, the prior art cannot implement thread migration between clusters.

Summary of the invention

Embodiments of the present invention provide a thread migration method, apparatus, and system to implement thread migration between clusters.

A first aspect of the embodiments of the present invention provides a thread migration method, which is applied to a cluster system of a many-core architecture, where the cluster system of the many-core architecture includes at least two clusters, and the two clusters are controlled by M clusters. Each of the clusters includes a plurality of processor cores, each of the cluster controllers for monitoring status information of a plurality of processor cores in the directly connected cluster, wherein the M is greater than or equal to 1 and is an integer. , the method includes:

The cluster controller receives the context information of the thread sent by the source processor core and the identifier of the target cluster, where the context information of the thread includes: a program counter value and a register value;

If the cluster controller determines that the identifier of the target cluster is directly the cluster controller An identifier of the connected cluster, the cluster controller determining, according to state information of each processor core in the target cluster, the target processor core of the thread migration;

The cluster controller sends context information of the thread to the target processor core.

With reference to the first aspect, in a first possible implementation, the cluster controller determines, according to state information of each processor core in the target cluster, the target processor core of the thread migration, including any one of the following Ways:

Determining, by the cluster controller, the target processor core of the thread migration according to status information of the memory access instruction queue of each processor core in the target cluster;

Determining, by the cluster controller, the target processor core of the thread migration according to state information of a storage unit of a thread context of each processor core in the target cluster;

The cluster controller determines the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue;

Determining, by the cluster controller, the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster, including:

The cluster controller determines, according to the number of all memory access instructions in the memory access instruction queue of each processor core in the target cluster, that the processor core with the least number of memory access instructions in the memory queue is the thread migration Target processor core.

In conjunction with the first possible implementation of the first aspect, in a third possible implementation, the storage unit of the thread context includes a plurality of entries, each of the entries is used to store context information of a thread. The state information of the storage unit of the thread context includes the number of empty storage entries of the storage unit of the thread context;

Determining, by the cluster controller, the target processor core of the thread migration according to the state information of the storage unit of the thread context of each processor core in the target cluster, including:

Determining, by the cluster controller, the processor core with the largest number of empty remaining entries in the storage unit of the thread context according to the number of empty storage entries of the storage unit of the thread context of each processor core in the target cluster Target processor core.

With reference to the first possible implementation manner of the first aspect, in a fourth possible implementation, the cluster controller is configured to: according to status information of a memory access queue of each processor core in the target cluster and a thread context The status information of the storage unit determines the target processor core of the thread migration, including:

The cluster controller allocates a first weight coefficient for the number of all the memory access instructions in the memory access instruction queue, and the cluster controller allocates a second weight to the number of the remaining space entries of the storage unit of the thread context. coefficient;

The cluster controller weights and sums the number of all fetch instructions in the fetch instruction queue of each processor core in the target cluster and the number of storage unit empty residual entries in the thread context;

The cluster controller determines the target processor core of the thread migration according to the weighted summation result.

With reference to the first aspect, or any one of the first to the fourth possible implementation manners of the first aspect, in a fifth possible implementation, the cluster controller is configured according to the target cluster Before determining the target processor core of the thread migration, the status information of each processor core further includes:

The cluster controller records, for each processor core of the target cluster, the number of all memory access instructions in the memory access instruction queue of the processor core and the storage unit of the thread context by two counters. The number of free entries.

A second aspect of the embodiments of the present invention provides a thread migration apparatus, which is applied to a cluster system of a multi-core architecture, where the cluster system of the many-core architecture includes at least two clusters, and the two clusters are controlled by M clusters. Each of the clusters includes a plurality of processor cores, each of the cluster controllers for monitoring status information of a plurality of processor cores in the directly connected cluster, wherein the M is greater than or equal to 1 and is an integer. The device includes:

a receiving port, configured to receive context information of a thread sent by the source processor core and an identifier of the target cluster, where context information of the thread includes: a program counter value and a register value;

a monitor, configured to monitor status information of each processor core in the target cluster;

a processor, configured to determine, according to the state information of each processor core in the target cluster, the target processor core of the thread migration, if the identifier of the target cluster is determined to be an identifier of the directly connected cluster;

a sending port, configured to send context information of the thread to the target processor core.

With reference to the second aspect, in a first possible implementation, the processor is specifically configured to determine, according to state information of a memory access instruction queue of each processor core in the target cluster, a target processor that is migrated by the thread Nuclear; or,

The processor is specifically configured to determine, according to state information of a storage unit of a thread context of each processor core in the target cluster, a target processor core that is migrated by the thread; or

The processor is specifically configured to determine, according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context, the target processor core of the thread migration.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner, the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue;

The processor is specifically configured to determine, according to the number of all memory access instructions in the memory access instruction queue of each processor core in the target cluster, a processor core having the least number of memory access instructions in the memory queue The target processor core for thread migration.

With reference to the first possible implementation of the second aspect, in a third possible implementation, the storage unit of the thread context includes a plurality of entries, and each of the entries is used to store context information of a thread. The state information of the storage unit of the thread context includes the number of empty storage entries of the storage unit of the thread context;

The processor is specifically configured to determine, according to the number of empty storage entries of the storage unit of the thread context of each processor core in the target cluster, the processor core with the largest number of remaining storage entries in the thread context The target processor core for thread migration.

With reference to the first possible implementation of the second aspect, in a fourth possible implementation, the processor is specifically configured to allocate a first weight coefficient for the number of all the memory access instructions in the memory access instruction queue Allocating a second weight coefficient for the number of storage unit empty table entries of the thread context; the number of all fetch instructions in the fetch instruction queue of each processor core in the target cluster and the thread context The number of empty storage table entries of the storage unit is weighted and summed; and the target processor core of the thread migration is determined according to the weighted summation result.

With reference to the second aspect or any one of the possible implementations of the first to fourth possible implementations of the second aspect, in a fifth possible implementation, the monitor is specifically configured for a pin For each processor core of the target cluster, record the number of all memory access instructions in the memory instruction fetch queue of the processor core and the memory cell empty space entries of the thread context by two counters. number.

A third aspect of the embodiments of the present invention provides a thread migration system, including:

At least two clusters are connected by the cluster controllers of any one of the possible implementations of the second aspect, each of the clusters comprising a plurality of processor cores, each of the clusters The cluster controller is configured to monitor status information of a number of processor cores in the directly connected cluster, the M being greater than or equal to 1 and being an integer.

The thread migration method, device and system provided by the embodiment of the present invention determine, by the cluster controller, a target processor core suitable for thread migration according to state information of each processor core in the target cluster, and send thread context information to the target. The processor core, thereby enabling thread migration between clusters.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any inventive labor.

1 is a schematic diagram of a cluster system 1 of a multi-core architecture of the present invention;

2 is a schematic diagram of a format of a memory access instruction queue according to the present invention;

3 is a schematic diagram of a format of a storage unit of a thread context according to the present invention;

4 is a schematic diagram of a cluster system 2 of a multi-core architecture of the present invention;

FIG. 5 is a schematic flowchart of Embodiment 1 of a thread migration method according to the present invention;

FIG. 6 is a schematic structural diagram of Embodiment 1 of a thread migration apparatus according to the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts are protected by the present invention. range.

The thread migration method of the embodiment of the present invention is applied to a cluster system of a multi-core architecture. The cluster system of the so-called multi-core architecture is shown in FIG. 1. FIG. 1 is a schematic diagram of a cluster system 1 of the multi-core architecture of the present invention, and the core architecture The cluster system includes at least two clusters (shown as two clusters in Figure 1, respectively, cluster 1 and cluster 2), each cluster containing several processor cores (shown by three processor cores in Figure 1) , respectively, processor core 1, processor core 2 and processor core 3), the number of processor cores included in each cluster may be the same or different; each cluster is connected to the cluster controller, specifically All clusters are connected to the same cluster controller, or one cluster can be connected to one cluster controller, or multiple clusters can be connected to one cluster controller; when one cluster is connected to one cluster controller, or multiple cluster connections In a cluster controller, all cluster controllers are connected according to a certain topological relationship; that is, two clusters are connected by M cluster controllers, and M is greater than or equal to 1 and is an integer ( 1 shown at M = 1), for each cluster monitor the cluster controller directly connected to several of the processor core state information. All processor cores in a cluster can access the address space of the cluster.

The status information of the processor core includes the status information of the memory access instruction queue and/or the status information of the memory unit of the thread context. The format of the memory access instruction queue is as shown in FIG. 2, and FIG. 2 is the memory access instruction of the present invention. The format diagram of the queue, the status information of the memory access instruction is used to measure the load size of the processor core, and the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue, and all memory accesses in the memory access instruction queue. The greater the number of instructions, the greater the load on the processor core. The storage unit of the thread context may be a stack, a buffer, a register file, etc., taking the stack as an example, the format of the storage unit of the thread context is as shown in FIG. 3, and FIG. 3 is a schematic diagram of the format of the storage unit of the thread context of the present invention. The storage unit of the thread context contains a plurality of entries, each of which is used to store context information of one thread. Each entry can be designed with one or more fields according to the application requirement (for example, two fields in FIG. 3 are used. The program counter value and the register value respectively, the state information of the storage unit of the thread context is used to measure the amount of context information of the thread that the processor core can store, and the state information of the storage unit of the thread context includes the storage unit of the thread context. The number of entries, the more the number of vacant entries, the more context information that the processor core can store.

When the data requested by a thread of a processor core in the cluster is not in the address space of the cluster, the data is accessed by migrating the thread to a core of the cluster in which the data resides. The method of accessing remote data has the advantages of improving bandwidth utilization and reducing delay. Therefore, the present invention provides a thread migration method to implement thread migration between clusters.

4 is a schematic diagram of a cluster system 2 of a multi-core architecture of the present invention, and FIG. 4 is a schematic diagram showing the internal structure of each processor core in more detail on the basis of FIG. 1, as shown in FIG. When a thread requests access to data, the thread sends an access request to the storage access logic module, where the access request includes address information requesting access to the data; for convenience of description, the processor core where the thread that sends the access request is called The source processor core, the cluster in which the source processor core is located is referred to as a source cluster, and the storage access logic module determines the location where the requested access data is stored according to the address information of the requested access data. Specifically, the storage access logic module may record an address space of each cluster data storage, and may determine, according to an address of the access request data, a cluster in which the address of the requesting access data belongs, and a cluster to which the address requesting the access data belongs. Called the target cluster. When the storage access logic module determines that the location of the data requested by the storage request is not in the address space of the source cluster, the storage access logic module sends a control signal to the thread migration logic module, where the control signal includes the identifier of the target cluster and the address of the data requested to be accessed, The thread migration logic module determines whether to perform thread migration. Generally, according to the historical access situation, it is determined that the data corresponding to the address requesting the access data is larger, or the data of the address accessed by the request and the data of the address space adjacent to the address accessed by the request. If it is continuous access, it is determined to perform thread migration. Otherwise, no thread migration is performed. When the thread migration logic module determines that the thread migration is performed, the thread migration unit is triggered to migrate the thread, the thread migration unit acquires the context information of the thread and the identifier of the target cluster, and the thread context information refers to information required by the execution thread, generally including The program counter and the register value, the thread migration unit sends the context information of the thread and the identifier of the target cluster to the router of the processor core, and the routers of the processor cores in the same cluster are connected according to a certain topological relationship, wherein one The router of the processor core is connected to the cluster controller, and the router of the source processor core sends the context information of the thread and the identifier of the target cluster to the cluster controller directly connected to the source cluster according to the topology relationship, and the cluster directly connected to the source cluster The controller is called a source cluster controller. The source cluster controller sends the context information of the thread and the identifier of the target cluster to the cluster controller of the target cluster according to the topology relationship between the cluster controllers, and the M cluster controllers Cluster controller directly connected to the target cluster Called the target cluster controller.

It should be noted that, in the structure of the processor core shown in FIG. 4, the thread migration logic module It can also be omitted, that is, after the storage access logic module determines the target cluster of the address of the data requested to be accessed, the thread migration unit is directly triggered to perform thread migration.

In the case of fewer processor cores in the cluster, the thread migration unit of each processor core can also directly connect to the source cluster controller without forwarding to the cluster controller through the router of each processor core. , reduce the delay.

When all clusters are connected to the same cluster controller, the source cluster controller and the target cluster controller are the same cluster controller, and the source cluster controller is omitted to send the context information of the thread according to the topology relationship of the cluster controller. The process of the target cluster controller.

After the target cluster controller receives the context information of the thread sent by the source core and the identifier of the target cluster, how to select the target processor core suitable for thread migration is described in detail in the following embodiments.

FIG. 5 is a schematic flowchart of the first embodiment of the thread migration method of the present invention. The method of the embodiment shown in FIG. 5 is applied to the cluster system of the multi-core architecture. As shown in FIG. 5, the method in this embodiment is as follows:

S501: The cluster controller receives the context information of the thread sent by the source processor core and the identifier of the target cluster.

The context information of the thread includes: a program counter value and a register value.

S502: If the cluster controller determines that the identifier of the target cluster is the identifier of the cluster directly connected to the cluster controller, the cluster controller determines the target processor core of the thread migration according to the state information of each processor core in the target cluster.

If the cluster controller determines that the identifier of the target cluster is the identifier of the cluster directly connected to the cluster controller, the cluster controller is the target cluster controller.

For different scenarios, the target cluster controller can receive the context information of the thread sent by the source processor core in different manners. One way is: when the source cluster controller and the target cluster controller are the same cluster controller, Moreover, the thread migration unit of the source processor core is directly connected to the target cluster controller, and the target cluster controller directly receives the context information of the thread from the thread migration unit of the source processor core; the other way is, when the source cluster controller When the target cluster controller is the same cluster controller, but each processor core has a processor core router, the routers of each processor core are connected according to a certain topological relationship, and one processor core is connected to the cluster controller, and the target cluster is connected. The controller receives the thread up and down through the router of the processor core connected to it Text information. Another way is: when the source cluster controller and the target cluster controller are different cluster controllers, after the source cluster controller receives the context information of the thread sent by the source processor core, according to the topology between the cluster controllers The relationship sends the thread's context information to the target cluster controller.

The cluster controller selects, according to the state information of each processor core in the target cluster, a processor core that is most suitable for running the above thread as the target processor core.

Before performing S502, the step of acquiring, by the cluster controller, status information of each processor core in the target cluster may also be included.

Specifically, the cluster controller records, for each processor core of the target cluster, the number of all the memory access instructions in the memory core instruction fetch queue of the processor core and the memory cell empty space entries in the thread context by two counters. number.

S503: The cluster controller sends the context information of the thread to the target processor core.

The cluster controller sends the context information of the thread to the target processor core, specifically, the thread migration unit sent to the target processor core, and the thread migration unit of the target processor core stores the upper and lower information of the thread in the storage unit of the thread context. In order to allow the thread to access the data requested for access in the target processor core.

In this embodiment, the cluster controller determines, according to the state information of each processor core in the target cluster, a target processor core suitable for thread migration, and sends the context information of the thread to the target processor core, thereby implementing the cluster. Thread migration between.

In the foregoing embodiment, the cluster controller determines the target processor core of the thread migration according to the state information of each processor core in the target cluster, including but not limited to the following manners:

In the first mode, the cluster controller determines the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster.

Specifically, the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue, and the more the number of memory access instructions in the memory access instruction queue, the larger the load of the processor core, therefore, the cluster control According to the number of all memory access instructions (the number of existing memory access instructions) in the memory access instruction queue of each processor core in the target cluster, the processor determines the processor with the least number of memory access instructions in the memory queue. The core is the target processor core for thread migration, that is, the processor core with the least load is selected as the target processor core of the migration. When the thread is migrated to the target processor core, the thread can be processed as early as possible.

In the second mode, the cluster controller determines the target processor core of the thread migration according to the state information of the storage unit of the thread context of each processor core in the target cluster.

The structure of the storage unit of the thread context is as shown in FIG. 3, and includes several entries, each of which is used to store context information of one thread, and the state information of the storage unit of the thread context includes the remaining entries in the storage unit of the thread context. Number. The cluster controller determines, according to the number of empty space entries of the storage unit of the thread context of each processor core in the target cluster, the processor core with the largest number of empty storage entries in the thread context is the target processor of the thread migration. nuclear.

It should be noted that, when the storage unit of the thread context of each processor core in the target cluster is full, a processor core is randomly selected as the target processor core, and the thread migration unit will have the original thread context information in the target processor core. Cut out the original way. If at least two processor cores having the largest number of slots in the storage unit of the thread context of each processor core in the target cluster have at least two, select one of the at least two processor cores according to a polling manner. Target processor core.

In the third mode, the cluster controller determines the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context.

The cluster controller allocates a first weight coefficient for the number of all the memory access instructions in the memory access instruction queue, and allocates a second weight coefficient for the number of the remaining space entries of the storage unit in the thread context, and the cluster controller processes each of the target clusters. The number of all memory access instructions in the memory fetch instruction queue and the number of memory cell empty table entries in the thread context are weighted and summed, and the cluster controller determines the target processor core of the thread migration according to the weighted summation result. Generally, the first weight coefficient is a negative number, the second weight coefficient is a positive number, and the processor core that determines the weighted summation result is the target processor core.

The present invention determines, by the cluster controller, whether the target processor core of the thread migration is not limited according to the state information of the memory access instruction queue of each processor core in the target cluster and/or the state information of the storage unit of the thread context. It is within the scope of the present invention to determine the target processor core for thread migration based on the state information of the memory access instruction queues of the processor cores in the target cluster and/or the state information of the memory cells of the thread context.

FIG. 6 is a schematic structural diagram of Embodiment 1 of a thread migration apparatus according to the present invention. The apparatus in this embodiment is a cluster controller. The apparatus in this embodiment is applied to a cluster system of a multi-core architecture, and the cluster system of the multi-core architecture includes at least two Clusters, through the M clusters between the two clusters Each of the clusters includes a plurality of processor cores, each of the cluster controllers for monitoring status information of a plurality of processor cores in the directly connected cluster, wherein the M is greater than or equal to 1 and is an integer. The device includes a receiving port 601, a monitor 602, a processor 603, and a sending port 604, where the receiving port 601 is configured to receive context information of a thread sent by the source processor core and an identifier of the target cluster, where the context information of the thread includes: a program a counter value and a register value; the monitor 602 is configured to monitor status information of each processor core in the target cluster; and the processor 603 is configured to determine, if the identifier of the target cluster is an identifier of the directly connected cluster, according to the target cluster The status information of each processor core determines the target processor core of the thread migration; the transmission port 604 is configured to send the context information of the thread to the target processor core.

In the above embodiment, the processor 603 is specifically configured to determine, according to the state information of the memory access instruction queue of each processor core in the target cluster, the target processor core of the thread migration; or

The processor 603 is specifically configured to determine, according to state information of a storage unit of a thread context of each processor core in the target cluster, the target processor core of the thread migration; or

The processor 603 is specifically configured to determine, according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context, the target processor core of the thread migration.

In the above embodiment, the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue;

The processor 603 is specifically configured to determine, according to the number of all memory access instructions in the memory access instruction queue of each processor core in the target cluster, that the processor core with the least number of memory access instructions in the memory queue is the thread. The target processor core of the migration.

In the above embodiment, the storage unit of the thread context includes a plurality of entries, each of the foregoing entries is used to store context information of a thread, and the state information of the storage unit of the thread context includes a storage unit of the thread context. The number of items;

The processor 603 is specifically configured to determine, according to the number of empty storage entries of the storage unit of the thread context of each processor core in the target cluster, that the processor core with the largest number of remaining storage entries in the thread context is a thread. The target processor core of the migration.

In the above embodiment, the processor 603 is specifically configured to be used in the cached instruction queue. The number of the memory access instruction is assigned a first weighting coefficient, and the second weighting coefficient is allocated to the number of the remaining space entries of the storage unit in the thread context; and all the accesses in the memory access instruction queue of each processor core in the target cluster The number of the stored instructions and the number of the remaining spatial entries of the storage unit of the thread context are weighted and summed; and the target processor core of the thread migration is determined according to the weighted summation result.

In the foregoing embodiment, the monitor 602 is specifically configured to record, for each processor core of the target cluster, the number of all memory access instructions in the memory access instruction queue of the processor core and the thread by using two counters. The number of empty remaining entries in the storage unit of the context.

The device of the foregoing embodiment monitors, by the monitor, status information of each processor core in the target cluster; if the processor determines that the identifier of the target cluster is the identifier of the directly connected cluster, according to each processor core in the target cluster The status information determines the target processor core of the thread migration; the sending port sends the context information of the thread to the target processor core, thereby implementing thread migration between the clusters.

The present invention further provides an embodiment of a thread migration system. The system of this embodiment includes at least two clusters, and the two clusters are connected by M cluster controllers as shown in FIG. 6, each of which includes a plurality of processor cores, each cluster controller is configured to monitor state information of a plurality of processor cores in the directly connected cluster, wherein the M is greater than or equal to 1 and is an integer, and the figure of the thread migration system embodiment can refer to the figure. 1 or Figure 2.

The system of the present embodiment can be used to implement the technical solution of the method embodiment shown in FIG. 5, and the implementation principle and technical effects are similar, and details are not described herein again.

One of ordinary skill in the art will appreciate that all or part of the steps to implement the various method embodiments described above may be accomplished by hardware associated with the program instructions. The aforementioned program can be stored in a computer readable storage medium. The program, when executed, performs the steps including the foregoing method embodiments; and the foregoing storage medium includes various media that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and are not intended to be limiting; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that The technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be equivalently replaced; and the modifications or substitutions do not deviate from the technical solutions of the embodiments of the present invention. range.

Claims

A thread migration method, characterized in that, in a cluster system applied to a many-core architecture, the cluster system of the many-core architecture includes at least two clusters, and the two clusters are connected by M cluster controllers, each Each of the clusters includes a plurality of processor cores, each of the cluster controllers for monitoring status information of a plurality of processor cores in the directly connected cluster, the M being greater than or equal to 1 and being an integer, the method include:

The cluster controller receives the context information of the thread sent by the source processor core and the identifier of the target cluster, where the cluster controller is any one of the M cluster controllers, where the context information of the thread includes: Program counter value and register value;

If the cluster controller determines that the identifier of the target cluster is an identifier of a cluster directly connected to the cluster controller, the cluster controller determines the thread according to status information of each processor core in the target cluster. The target processor core of the migration;

The cluster controller sends context information of the thread to the target processor core.
The method of claim 1 wherein

Determining, by the cluster controller, the target processor core of the thread migration according to the state information of each processor core in the target cluster, including any one of the following manners:

Determining, by the cluster controller, the target processor core of the thread migration according to status information of the memory access instruction queue of each processor core in the target cluster;

Determining, by the cluster controller, the target processor core of the thread migration according to state information of a storage unit of a thread context of each processor core in the target cluster;

The cluster controller determines the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context.
The method according to claim 2, wherein the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue;

Determining, by the cluster controller, the target processor core of the thread migration according to the state information of the memory access instruction queue of each processor core in the target cluster, including:

The cluster controller determines, according to the number of all memory access instructions in the memory access instruction queue of each processor core in the target cluster, that the processor core with the least number of memory access instructions in the memory queue is the thread migration Target processor core.
The method according to claim 2, wherein the storage unit of the thread context comprises a plurality of entries, each of the entries for storing context information of a thread, and status information of the storage unit of the thread context The number of empty remaining entries of the storage unit including the thread context;

Determining, by the cluster controller, the target processor core of the thread migration according to the state information of the storage unit of the thread context of each processor core in the target cluster, including:

Determining, by the cluster controller, the processor core with the largest number of empty remaining entries in the storage unit of the thread context according to the number of empty storage entries of the storage unit of the thread context of each processor core in the target cluster Target processor core.
The method according to claim 2, wherein the cluster controller determines the thread according to state information of a memory access instruction queue of each processor core in the target cluster and state information of a storage unit of a thread context. The target processor core for the migration, including:

The cluster controller allocates a first weight coefficient for the number of all the memory access instructions in the memory access instruction queue, and the cluster controller allocates a second weight to the number of the remaining space entries of the storage unit of the thread context. coefficient;

The cluster controller weights and sums the number of all fetch instructions in the fetch instruction queue of each processor core in the target cluster and the number of storage unit empty residual entries in the thread context;

The cluster controller determines the target processor core of the thread migration according to the weighted summation result.
The method according to any one of claims 1 to 5, wherein the cluster controller determines the target processor core that is migrated by the thread according to state information of each processor core in the target cluster. Also includes:

The cluster controller records, for each processor core of the target cluster, the number of all memory access instructions in the memory access instruction queue of the processor core and the storage unit of the thread context by two counters. The number of free entries.
A thread migration apparatus, characterized in that, in a cluster system applied to a multi-core architecture, the cluster system of the many-core architecture includes at least two clusters, and the two clusters are connected by M cluster controllers, each Each of the clusters includes a plurality of processor cores, each of the cluster controllers for monitoring status information of a plurality of processor cores in the directly connected cluster, the M The device is greater than or equal to 1 and is an integer, and the device includes:

a receiving port, configured to receive context information of a thread sent by the source processor core and an identifier of the target cluster, where context information of the thread includes: a program counter value and a register value;

a monitor, configured to monitor status information of each processor core in the target cluster;

a processor, configured to determine, according to the state information of each processor core in the target cluster, the target processor core of the thread migration, if the identifier of the target cluster is determined to be an identifier of the directly connected cluster;

a sending port, configured to send context information of the thread to the target processor core.
The apparatus according to claim 7, wherein the processor is specifically configured to determine, according to state information of a memory access instruction queue of each processor core in the target cluster, a target processor core that is migrated by the thread; or,

The processor is specifically configured to determine, according to state information of a storage unit of a thread context of each processor core in the target cluster, a target processor core that is migrated by the thread; or

The processor is specifically configured to determine, according to the state information of the memory access instruction queue of each processor core in the target cluster and the state information of the storage unit of the thread context, the target processor core of the thread migration.
The apparatus according to claim 8, wherein the status information of the memory access instruction queue includes the number of all memory access instructions in the memory access instruction queue;

The processor is specifically configured to determine, according to the number of all memory access instructions in the memory access instruction queue of each processor core in the target cluster, a processor core having the least number of memory access instructions in the memory queue The target processor core for thread migration.
The apparatus according to claim 8, wherein the storage unit of the thread context comprises a plurality of entries, each of the entries for storing context information of a thread, and status information of a storage unit of the thread context The number of empty remaining entries of the storage unit including the thread context;

The processor is specifically configured to determine, according to the number of empty storage entries of the storage unit of the thread context of each processor core in the target cluster, the processor core with the largest number of remaining storage entries in the thread context The target processor core for thread migration.
The apparatus according to claim 8, wherein the processor is specifically configured to allocate a first weight coefficient for the number of all memory access instructions in the memory access instruction queue, for the line a second weighting coefficient is allocated to the number of the remaining space entries of the storage unit of the program context; the number of all the fetch instructions in the fetch instruction queue of each processor core in the target cluster and the storage unit of the thread context The number of vacant entries is weighted and summed; the target processor core of the thread migration is determined according to the weighted summation result.
The device according to any one of claims 7 to 11, wherein the monitor is specifically configured to separately record the access of the processor core by using two counters for each processor core of the target cluster. The number of all fetch instructions in the instruction queue and the number of empty cell entries in the storage unit of the thread context.
A thread migration system, comprising:

At least two clusters connected by the cluster controllers according to any one of claims 7 to 12, each of the clusters comprising a plurality of processor cores, each of the cluster controllers For monitoring status information of several processor cores in a directly connected cluster, the M is greater than or equal to 1 and is an integer.