CN101751295B - Method for realizing inter-core thread migration under multi-core architecture - Google Patents
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Abstract
The invention relates to the field of designing multi-core hierarchical structures and aims at providing a method for realizing inter-core thread migration under a multi-core architecture. The method comprises the following steps: segmenting Cache data blocks, setting a fault mapping table and a companion mapping table, carrying out the inter-core thread migration, and completing the migration of all the Cache data blocks to an access core, thereby realizing the whole thread migration. The method has the benefits that the thread migration is realized by combining the fault mapping and the companion mapping of the Cache data blocks under the multi-core environment. The adoption of the method for retaining the Cache data blocks which are replaced in the access core rather than abandoning the Cache data blocks can improve the Cache hit ratio. The realization method can reduce the time delay of Cache access, compared with the previously proposed method of copying the Cache data blocks, the method can effectively utilize the capacity of Cache and keep the uniqueness of the Cache data blocks in the Cache.
Description
Technical field
The present invention relates to multinuclear hierarchical structure design field, particularly relate to a kind of implementation method of inter-core thread migration under multi-core architecture.
Background technology
Along with the continuous progress of science and technology, the capacity of Cache is also increasing thereupon, especially afterbody Cache.Owing to the difference of manufacture craft, tend to increase the error rate of the sram cell of forming Cache, the method for many solutions has been proposed at present; Error correcting code is one of them; It is to replace out of order unit through the unit of redundancy, but after redundant unit use is over, can only be abandoned in all the other out of order unit; This way unit that often can only remedy a mistake, it is unpractical correcting a large amount of mistakes thus.If a plurality of error unit need to correct, error correcting code just needs certain area overhead and complexity of calculation so.Also have other method, such as reduce the Cache amount of capacity through having abandoned trouble unit; Strategy abandoned in word; Position fixed policy or the like.
Time-delay is the key factor that thread migration is considered, has proposed the time-delay that many methods are used for alleviating memory access at present, particularly to afterbody Cache.The method that reduces the visit time-delay has data migtation and data to duplicate etc., but data migtation is more effective under the monokaryon situation.With under the multinuclear situation, compare, data are duplicated the uniqueness (having only the backup of an internal memory among the Cache) that can not effectively utilize the Cache capacity and can not guarantee data block.In chip multi-processor CMP; Distributed shared L2 nonuniformity visit Cache; It is more obvious that the visit time-delay shows: the needed access time of memory bank banks near visit nuclear is lacked (it is the shortest to delay time) most, grows (it is the longest to delay time) most and examine the needed access time of memory bank far away from visit.
Summary of the invention
The technical matters that the present invention will solve is that a kind of implementation method of inter-core thread migration under multi-core architecture is provided.
For solving the problems of the technologies described above, method provided by the invention may further comprise the steps:
(1) the Cache data block is cut apart:
Each Cache data block is divided into k equal portions div that equates, the size of each equal portions div is n, and the size of supposing the Cache data block is c, then c=nk;
(2) fault mapping table and companion's mapping table are set:
Each Cache data block is provided with the mapping of fault, representes that with 0 equal portions div does not have fault, can be used for storing data, representes that with 1 there is fault in equal portions div, can not be used for storing data.Each Cache data block is provided with a companion bit b, representes whether this Cache data block exists companion's piece, representes that when b=0 this Cache data block does not have companion's piece, representes that when b=1 there is companion's piece in this Cache data block.
If in a Cache group, existing the fault mapping of a Cache data block to shine upon the XOR result with the fault of another Cache data block all is 0; These two Cache data blocks just exist peer relation so, i.e. another Cache data block companion's piece that is this Cache data block.
Companion's piece determining device that all nuclear is shared is set, is used for judging whether companion bit b is 0; Each Cache group set is provided with a searcher, is used for confirming the position of companion's piece.
Each Cache group set is provided with companion's mapping table; Each Cache data block needs the log2n position to represent that the companion shines upon; N is the degree of association of Cache; If in Cache group set, there is the out of order Cache pairing of an out of order Cache data block and another, form a Cache data block that can be used for canned data, then these two out of order Cache data blocks exchange its index.
(3) in order to reduce the memory access time-delay, need carry out internuclear thread migration, its implementation process mainly is divided into following step:
Migration nuclear is meant that nuclear that thread will be moved, and visit nuclear is meant that nuclear of visit thread;
The first step: companion's piece determining device judge by in the migration nuclear the companion bit b of the Cache data block that will move whether be 0, if be 0, and change step 2 over to; If be not 0 (being b=1), and change step 5 over to;
Second step: companion's piece determining device judges whether the companion bit b of the Cache data block that will replace away in the visit nuclear is 0, if be 0, changes step 3 over to; If be 1, change step 4 over to;
The 3rd step: thread migration controller Direct Transfer Cache data block is examined to visit on the Cache data block location of displacing, and is filled into the Cache data block of from visit nuclear, displacing simultaneously and moves the position that nuclear Cache data block is moved out;
The 4th step: at first the position of its companion's piece confirmed in companion's index of the searcher utilization visit nuclear Cache data block among the Cache group set; The thread migration controller shines upon based on the fault mapping and the companion of the Cache data block that visit nuclear is displaced; Migration Cache data block is examined to visit on the active position in two Cache data blocks of displacing, and again active data in two Cache data blocks of from visit nuclear, displacing is filled into the position that migration nuclear Cache data block is moved out;
The 5th step: at first the searcher among this Cache group set is according to companion's index of migration nuclear Cache data block; Confirm the position of its companion's piece; Companion's piece determining device is judged the companion bit b of the Cache data block that will replace away in the visit nuclear simultaneously; If b=0; The thread migration controller is moved to visit nuclear with active data in two Cache data blocks, and the fault of examining two Cache data blocks of being moved out is shone upon and companion's mapping according to moving again, is filled into the Cache data block of from visit is examined, displacing to move and examines on two Cache data block location of being moved out; If b=1; The thread migration controller is moved to active data in two Cache data blocks in the visit nuclear in two Cache data blocks effectively on the position, is filled into active data in two Cache data blocks of from visit nuclear, displacing on two Cache data block location that migration nuclear moved out again.
Five step circulations more than implementing are carried out, and accomplish all Cache data blocks and are moved to visit nuclear, to realize the migration of whole thread.
Compare with background technology, the useful effect that the present invention has is:
Under multi-core environment, the fault mapping of thread migration combination Cache data block and companion are shone upon and are realized.Take to keep the method for the Cache data block of from visit nuclear, replacing away, rather than abandon the Cache data block, can improve the Cache hit rate.Implementation method of the present invention can reduce the time-delay of Cache visit, and compares the capacity and the uniqueness of maintenance Cache data block in Cache that can effectively utilize Cache with the method for the previously presented Cache of duplicating data block.
Description of drawings
Fig. 1 is the process of Cache data block migration.
Embodiment
The detailed process and the instance of this method are following:
The implementation method of inter-core thread migration under multi-core architecture comprises the steps:
(1) cutting apart the Cache data block:
Each Cache data block is divided into k equal portions div that equates, the size of each equal portions div is n, and the size of supposing the Cache data block is c, then c=nk.Suppose that Cache data block size for 32K, is divided into 4 equal portions, each equal portions size is 8K.
(2) fault mapping table and companion's mapping table:
For each Cache data block is equipped with a fault mapping; If the fault position of equal portions div is 0, just represent that these equal portions can store data, if the fault position of equal portions div is 1; Just represent that this is cut apart and to store data; Such as the fault of a Cache data block is mapped as 1010, representes that then second and the 4th can be used for storing data, and first can not be used for storing data with the 3rd.Each Cache data block is provided with a companion bit b, is used for representing whether this Cache data block exists companion's piece, in a Cache group set; The fault mapping of the fault mapping of Cache data block and interior other all the Cache data blocks of this Cache group set is XOR mutually, all is 1 if there is the result of a Cache data block XOR, and b=1 then is set; Represent that this Cache data block has companion's piece; If the result is not 1 entirely, b=0 then is set, represent that there is not companion's piece in this Cache data block.
If in a Cache group set, existing the fault mapping of a Cache data block to shine upon the XOR result with the fault of another Cache data block all is 0; These two Cache data blocks just exist peer relation so; It is companion's piece that another Cache data block is this Cache data block; For example the fault of a Cache data block is mapped as 1010; If in same Cache group set, exist the fault of another Cache data block to be mapped as 0101, the fault mapping XOR result of these two data blocks is 1111, so another Cache data block companion's piece that is this Cache data block.
Companion's piece determining device that all nuclear is shared is set, is used for judging whether companion bit b is 0; Each Cache group set is provided with a searcher, is used for confirming the position of companion's piece.
Each Cache group set is provided with companion's mapping table, and each Cache data block needs log
2nThe position representes that the companion shines upon; N is the degree of association of Cache; If in Cache group set, have an out of order Cache data block and another out of order Cache pairing (i.e. companion's piece that the Cache data block is another Cache data block); Form a Cache data block that can be used for canned data, then these two out of order its index of Cache data blocks exchange.
(3) in order to reduce the memory access time-delay, need carry out internuclear thread migration, its implementation process mainly is divided into following step:
Migration nuclear is meant that nuclear that thread will be moved, and visit nuclear is meant that nuclear of visit thread;
The first step: companion's piece determining device judge by in the migration nuclear the companion bit b of the Cache data block that will move whether be 0, if be 0, and change step 2 over to; If be not 0 (being b=1), and change step 5 over to;
Second step: companion's piece determining device judges whether the companion bit b of the Cache data block that will replace away in the visit nuclear is 0, if be 0, changes step 3 over to, if be 1, changes step 4 over to;
The 3rd step: thread migration controller Direct Transfer Cache data block is examined on the Cache data block location of displacing to visit; Promptly move trouble-free Cache data block on trouble-free Cache data block location, be filled into the position that migration nuclear Cache data block is moved out to the Cache data block of from visit nuclear, displacing simultaneously;
The 4th step: at first the searcher among the Cache group set is confirmed the position of its companion's piece: the position of finding its companion's piece through companion's mapping; The thread migration controller shines upon based on the fault mapping and the companion of the Cache data block that visit nuclear is displaced; Migration Cache data block is examined to visit on the active position in two Cache data blocks of displacing; Again active data in two Cache data blocks of from visit nuclear, displacing is filled into the position that migration nuclear Cache data block is moved out, such as moves on the active position of trouble-free Cache data block to two an out of order Cache data block;
The 5th step: at first the searcher among this Cache group set is according to companion's index of migration nuclear Cache data block; Confirm the position of its companion's piece; Companion's piece determining device is judged the companion bit b of the Cache data block that will replace away in the visit nuclear simultaneously; If b=0; The thread migration controller is moved to visit nuclear with active data in two Cache data blocks; The fault of examining two Cache data blocks of being moved out is shone upon and companion's mapping according to moving again, is filled into the Cache data block of from visit is examined, displacing to move and examines on two Cache data block location of being moved out, belongs to and moves to two out of order Cache data blocks on the trouble-free Cache data block; If b=1; The thread migration controller is moved to active data in two Cache data blocks in the visit nuclear in two Cache data blocks effectively on the position; Be filled into migration to active data in two Cache data blocks of from visit nuclear, displacing again and examine on two Cache data block location of being moved out, belong to and move to two out of order Cache data blocks on two out of order Cache data blocks.
Five step circulations more than implementing are carried out, and accomplish all Cache data blocks and are moved to visit nuclear, to realize the migration of whole thread.
Claims (1)
1. the implementation method of an inter-core thread migration under multi-core architecture may further comprise the steps:
(1) the Cache data block is cut apart:
Each Cache data block is divided into k equal portions div that equates, the size of each equal portions div is n, and the size of supposing the Cache data block is c, then c=nk;
(2) fault mapping table and companion's mapping table are set:
Each Cache data block is provided with a fault mapping table and a companion bit b, and the fault mapping table is used for representing whether each equal portions div of Cache data block can be used for storing data, and companion bit b representes whether this Cache data block exists companion's piece; If in a Cache group, existing the fault mapping of a Cache data block to shine upon the XOR result with the fault of another Cache data block all is 0; These two Cache data blocks just exist peer relation so, i.e. another Cache data block companion's piece that is this Cache data block;
Companion's piece determining device that all nuclear is shared is set, is used for judging whether companion bit b is 0;
Each Cache group set is provided with a searcher and companion's mapping table, and searcher is used for confirming the position of companion's piece, and companion's mapping table is used for confirming the position of this Cache data block companion piece; If in Cache group set, there is the out of order Cache pairing of an out of order Cache data block and another, form a Cache data block that can be used for canned data, then these two out of order Cache data blocks exchange its index;
(3) in order to reduce the memory access time-delay, need carry out internuclear thread migration, its implementation process mainly is divided into following step:
Migration nuclear is meant that nuclear that thread will be moved, and visit nuclear is meant that nuclear of visit thread;
The first step: companion's piece determining device judge by in the migration nuclear the companion bit b of the Cache data block that will move whether be 0, if be 0, change step 2 over to; If be 1, then change step 5 over to;
Second step: companion's piece determining device judges whether the companion bit b of the Cache data block that will replace away in the visit nuclear is 0, if be 0, changes step 3 over to; If be 1, change step 4 over to;
The 3rd step: thread migration controller Direct Transfer Cache data block is examined to visit on the Cache data block location of displacing, and is filled into the Cache data block of from visit nuclear, displacing simultaneously and moves the position that nuclear Cache data block is moved out;
The 4th step: at first the position of its companion's piece confirmed in companion's index of the searcher utilization visit nuclear Cache data block among the Cache group set; The thread migration controller shines upon based on the fault mapping and the companion of the Cache data block that visit nuclear is displaced; Migration Cache data block is examined to visit on the active position in two Cache data blocks of displacing, and again active data in two Cache data blocks of from visit nuclear, displacing is filled into the position that migration nuclear Cache data block is moved out;
The 5th step: at first the searcher among this Cache group set is based on companion's index of migration nuclear Cache data block; Confirm the position of its companion's piece; Companion's piece determining device is judged the companion bit b of the Cache data block that will replace away in the visit nuclear simultaneously; If b=0; The thread migration controller is moved to visit nuclear with active data in two Cache data blocks, and the fault of examining two Cache data blocks of being moved out is shone upon and companion's mapping based on moving again, the Cache data block of from visit is examined, displacing is filled into to move examines on two Cache data block location of being moved out; If b=1; The thread migration controller is moved to active data in two Cache data blocks in the visit nuclear in two Cache data blocks effectively on the position, active data in two Cache data blocks of from visit nuclear, displacing is filled on two Cache data block location that migration nuclear moved out again;
Five step circulations more than implementing are carried out, and accomplish all Cache data blocks and are moved to visit nuclear, to realize the migration of whole thread.
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| WO2016044980A1 (en) * | 2014-09-22 | 2016-03-31 | 华为技术有限公司 | Thread migration method, apparatus and system |
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| CN101504618A (en) * | 2009-02-26 | 2009-08-12 | 浙江大学 | Multi-core processor oriented real-time thread migration method |
| CN101571835A (en) * | 2009-03-26 | 2009-11-04 | 浙江大学 | Realization method for changing Cache group associativity based on requirement of program |
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| CN101504618A (en) * | 2009-02-26 | 2009-08-12 | 浙江大学 | Multi-core processor oriented real-time thread migration method |
| CN101571835A (en) * | 2009-03-26 | 2009-11-04 | 浙江大学 | Realization method for changing Cache group associativity based on requirement of program |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105204785A (en) * | 2015-10-15 | 2015-12-30 | 中国科学技术大学 | Disk array writemode selecting method based on I/O queue of disk |
| CN105204785B (en) * | 2015-10-15 | 2018-07-06 | 中国科学技术大学 | A kind of disk array WriteMode selection method based on magnetic disc i/o queue |
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