WO2016041156A1 - Procédé et appareil d'ordonnancement d'uct - Google Patents

Procédé et appareil d'ordonnancement d'uct Download PDF

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Publication number
WO2016041156A1
WO2016041156A1 PCT/CN2014/086702 CN2014086702W WO2016041156A1 WO 2016041156 A1 WO2016041156 A1 WO 2016041156A1 CN 2014086702 W CN2014086702 W CN 2014086702W WO 2016041156 A1 WO2016041156 A1 WO 2016041156A1
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storage medium
delay
delay type
access
type
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PCT/CN2014/086702
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English (en)
Chinese (zh)
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徐君
朱冠宇
王元钢
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华为技术有限公司
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Priority to PCT/CN2014/086702 priority Critical patent/WO2016041156A1/fr
Priority to CN201480036990.2A priority patent/CN105612505B/zh
Publication of WO2016041156A1 publication Critical patent/WO2016041156A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices

Definitions

  • Embodiments of the present invention relate to the field of computers, and, more particularly, to a method and apparatus for CPU scheduling.
  • a storage device connected to a Central Processing Unit (CPU) through a memory bus may include different types of storage media.
  • the access latency of the CPU is different.
  • the CPU accesses different types of storage devices through unified paths and instructions, it cannot distinguish the type of storage media to be accessed. Therefore, when the CPU chooses to wait for the currently running process, the extended storage medium during access will occupy the kernel for a long time. Resources cause a waste of CPU resources; when the CPU chooses to suspend the currently running process, the overhead of the system is too large for a storage medium with a short access time.
  • the embodiment of the invention provides a method and a device for scheduling a CPU, which can reduce the waste of CPU resources and reduce the overhead of the system.
  • the first aspect provides a method for scheduling a CPU, where the method is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, the method includes: obtaining an access address of a current access operation; The access address determines a storage medium accessed by the access operation; determines a delay type of the storage medium; and in the case where it is determined that the delay type of the storage medium is the first delay type, suspending the process of running the access operation; determining the delay of the storage medium When the type is the second delay type, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the determining a delay type of the storage medium includes: acquiring an access delay of the storage medium; if the access delay of the storage medium is greater than a preset The value of the storage medium is determined to be the first delay type. If the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the determining a delay type of the storage medium includes: obtaining a correspondence between a preset storage medium and a delay type of the storage medium According to the correspondence, the delay type of the storage medium is determined.
  • the method before determining the delay type of the storage medium, further includes: determining to wait for the access operation Whether the access data is stored in the cache; determining the type of the delay of the storage medium corresponding to the memory access address comprises: determining the type of the delay of the storage medium in the case of determining that the data to be accessed is not stored in the cache.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • a second aspect provides a device for scheduling a CPU, where the device is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, and the device includes: an acquiring module, configured to acquire a current access operation.
  • the first determining module is configured to determine, according to the access address obtained by the obtaining module, the storage medium accessed by the access operation; the second determining module is configured to determine a delay type of the storage medium; and the executing module is configured to determine the second
  • the delay type of the storage medium determined by the module is the first delay type, the process of running the access operation is aborted; when the delay type of the storage medium determined by the second determining module is the second delay type, the access operation is continued.
  • the process wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the second determining module is specifically configured to: obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determine the storage medium The delay type is the first delay type. If the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the second determining module includes: an acquiring unit, configured to acquire a correspondence between a preset storage medium and a delay type of the storage medium; And a unit, configured to determine a delay type of the storage medium according to the correspondence obtained by the obtaining unit.
  • the apparatus further includes: a third determining module, configured to determine whether the to-be-accessed data of the access operation is stored in the cache, where the second determining module is specifically configured to determine, in the third determining module, the data to be accessed In the case where it is not stored in the cache, the type of delay of accessing the storage medium is determined.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • a storage device in a third aspect, includes a controller and a plurality of different types of storage media.
  • the storage medium is configured to store data; the controller is configured to: obtain an access address of the current access operation; determine a storage medium accessed by the access operation according to the access address; determine a delay type of the storage medium; and determine a delay type of the storage medium as In the case of the first delay type, the process of running the access operation is suspended; in the case where it is determined that the delay type of the storage medium is the second delay type, the process of the access operation is continued, wherein the storage of the first delay type The access delay of the medium is greater than the access delay of the storage medium of the second delay type.
  • the controller is specifically configured to: obtain an access delay of the storage medium; and determine a delay of the storage medium if an access delay of the storage medium is greater than a preset value The type is the first delay type. If the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium is determined to be the second delay type.
  • the controller is specifically configured to: obtain a correspondence between a preset storage medium and a delay type of the storage medium; determine, according to the corresponding relationship, the storage The type of delay for the media.
  • the controller is further configured to: determine the access operation before determining the delay type of the storage medium Whether the data to be accessed is stored in the cache; in the case where it is determined that the data to be accessed is not stored in the cache, the type of delay of the storage medium is determined.
  • the first delay type storage medium comprises a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile At least one storage medium in the flash NAND flash
  • the second delay type storage medium includes at least one of a dynamic random access memory DRAM and a nonvolatile solid state memory NVM.
  • the CPU scheduling method determines the storage medium accessed by the current access operation according to the access address by obtaining the access address of the current access operation, and further determines the delay type of the storage medium.
  • the delay type of the storage medium is a type with a large delay
  • the process of performing the current access operation is suspended, and the process switching is implemented.
  • it is determined that the storage medium is of a type that is accessed less it continues to wait for the current access process to be executed. According to this manner, the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present invention.
  • FIG. 2 shows a schematic flow chart of a method of CPU scheduling according to an embodiment of the present invention.
  • FIG. 3 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 4 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 5 shows a schematic flow chart of a method for CPU scheduling according to another embodiment of the present invention.
  • FIG. 6 shows a schematic interaction process diagram of a method of CPU scheduling according to another embodiment of the present invention.
  • FIG. 7 shows a schematic block diagram of an apparatus for CPU scheduling in accordance with one embodiment of the present invention.
  • FIG. 8 shows a schematic block diagram of an apparatus for CPU scheduling according to another embodiment of the present invention.
  • Figure 9 shows a schematic block diagram of a memory device in accordance with one embodiment of the present invention.
  • FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present invention.
  • the system includes a central processing unit (CPU) (100) and a storage device (106). To connect through the memory bus.
  • the CPU integrates a CPU core (101), a Memory Management Unit (MMU) (102), a Translation Lookaside Buffer (TLB) (103), a cache (104), and a message type.
  • MMC Memory Controller
  • the storage device shown in the figure includes three different types of storage media, but the method of the embodiment of the present invention is not limited thereto, and may be one, two or more than three types of storage media. It should be understood that the storage device shown in FIG. 1 may be a Unified Access Storage (UAS), the UAS includes a controller and multiple types of storage media, and the UAS includes multiple storage media that can pass through the same memory access interface. Was visited.
  • UAS Unified Access Storage
  • the process in which the CPU core writes data to be accessed or reads data to be accessed from the storage device may include the following steps:
  • Step 1 The CPU core initiates an access request for the current access operation, where the access request includes a virtual address corresponding to the to-be-accessed data of the current access operation.
  • Step 2 The MMU queries the TLB according to the virtual address.
  • step 3 the TLB feeds back the physical address corresponding to the virtual address to the MMU.
  • step 4 the MMU feeds back the physical address corresponding to the data to be accessed to the CPU core.
  • step 5 the CPU core accesses the cache according to the physical address.
  • Step 6 When the data to be accessed is not stored in the cache, that is, in the case of a cache miss, the CPU core sends the physical address to the MMC.
  • the MMC writes or reads the data to be accessed in the corresponding storage medium in the storage device according to the physical address.
  • the storage device feeds back to the MMC that the data to be accessed has been written or read.
  • the MMC replaces the read data to be read into the cache.
  • the CPU core reads the data to be accessed from the cache or the message that the CPU core receives the MMC feedback and the data to be accessed has been written.
  • the type of the storage medium to be accessed cannot be distinguished when the CPU accesses the storage medium through a unified path and instructions, the overhead of the system cannot be reduced according to the access delay characteristic of the storage medium.
  • the CPU core accesses the cache cache according to the physical address, and when the cache stores the data to be accessed, that is, in the case of a cache hit, if the CPU core wants to write the data of the physical address.
  • the CPU core can update the data stored in the cache, or the data corresponding to the physical address that the CPU core needs to read is stored in the cache, and the CPU core can directly read from the cache according to the physical address.
  • the data That is to say, in the case of a cache hit, the CPU core does not need to access the storage medium, and the memory access request can be quickly completed in the cache, so there is no problem that the access delay is different due to different types of storage media. .
  • the CPU core accesses the cache cache according to the physical address, including: the CPU core sends a physical address to the cache; the cache receives the physical address sent by the CPU core, and determines the cache according to the physical address. Whether the data to be accessed is stored.
  • a process is the execution of a program (instructions and data) that is running.
  • the access latency of a storage medium refers to the time required for the CPU to perform a read operation on the storage medium.
  • FIG. 2 shows a schematic flow diagram of a method 200 of CPU scheduling in accordance with one embodiment of the present invention.
  • the method 200 of FIG. 2 can be applied to an integrated storage device, wherein the integrated storage device includes a plurality of different types of storage media, and the method 200 includes:
  • Step 210 Obtain an access address of the current access operation.
  • the access address may include a virtual address, a physical address, or another access address, where the virtual address is a non-physical access address in the virtual address space, and the physical address is an actual address in the physical address space.
  • the access address that is, the actual access address to which the CPU is to write data, or the actual access address at which the CPU is to read data.
  • Current access operations may include read operations, write operations, or other operations.
  • Step 220 Determine, according to the access address obtained in step 210, a storage medium accessed by the current access operation.
  • the storage medium corresponding to the physical address may be determined according to the physical address.
  • the virtual address may be determined according to the virtual address.
  • the storage medium corresponding to the access address may be determined by querying the correspondence between the access address of the storage medium stored in the local or storage device and the storage medium.
  • the access address is within a range of address spaces corresponding to a certain storage medium, it can be determined that the storage medium corresponding to the access address is the storage medium, for example, the access address obtained in step 210 is a physical address.
  • the physical address is in the range of 0-4 GB physical address space, and the physical address space of the storage medium DRAM corresponds to 0-4 GB physical address space, it can be determined that the storage medium corresponding to the physical address is DRAM.
  • the access address obtained in step 210 is virtual
  • the storage medium corresponding to the virtual address may also be determined according to this method. For the sake of brevity, no further details are provided herein.
  • Step 230 Determine a delay type of the storage medium according to the determining the storage medium in step 220.
  • the delay type of the storage medium may be determined according to the correspondence between the storage medium and the delay type of the storage medium.
  • the delay type of the storage medium corresponding to the memory access address may be determined according to the correspondence between the memory access address and the delay type of the storage medium.
  • Step 240 In a case where it is determined that the delay type of the storage medium is the first delay type, the process of running the current access operation is suspended.
  • the process of suspending the current access operation refers to a process that can suspend the current access operation, so that the process of the current access operation enters a dormant state, thereby releasing the CUP resource occupied by the current access operation process, and facilitating the process.
  • Step 250 If it is determined that the delay type of the storage medium is the second delay type, the process of performing the access operation is continued, where the access delay of the storage medium of the first delay type is greater than the storage of the second delay type. Media access latency.
  • the CPU scheduling method determines the access medium of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • it continues to wait for the current access process to be executed. According to this manner, the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • an access delay of the storage medium may be acquired; if the access delay of the storage medium is greater than a preset value, determining that the delay type of the storage medium is the first delay type; The access delay of the storage medium is not greater than a preset value, and the delay type of the storage medium is determined to be a second delay type.
  • the delay type of the storage medium is compared with the preset value, and the delay type of the storage medium is determined to be the first delay type or the second delay type.
  • the access delay of the storage medium of the delay type is greater than the access delay of the storage medium of the second delay type.
  • the comparison process may be performed only once, and the comparison result, that is, the correspondence between the storage medium and the delay type of the storage medium, is stored to the local or storage device.
  • the storage relationship may be searched directly to the local device or the storage device to determine the type of the delay of the storage medium.
  • the embodiment of the present invention is not limited thereto.
  • the CPU may also be in the CPU.
  • the preset value may be determined according to the time required for the CPU core to perform a read operation on the storage medium, and may be configured in advance.
  • the delay type of the storage medium is determined to be the first according to a relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU.
  • the delay type is still the second delay type. For example, when the access delay of the storage medium exceeds 4 times of the time resource overhead of the process switching by the CPU, it is determined that the delay type of the storage medium is the first delay type, otherwise, the delay type of the storage medium is determined to be the second time. Extension type.
  • the relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU is not limited to four times, and may be increased or decreased.
  • the present invention is implemented by way of example only. The technical methods of the examples are described without any limitation on the embodiments of the present invention.
  • determining whether the delay type of the storage medium is the first delay type or the first according to the relative proportional relationship between the access delay of the storage medium and the time resource overhead of the process switching by the CPU.
  • the process of the two-latency type may also be performed only once, and the determined result, that is, the correspondence between the storage medium and the delay type of the storage medium is stored in the local or storage device, and when the CPU core initiates the memory access request again, The storage relationship is directly searched for in the local device or the storage device, and the delay type of the storage medium is determined, but the embodiment of the present invention is not limited thereto.
  • the delay type of the storage medium when the access delay of the storage medium is greater than the preset value, the delay type of the storage medium is determined to be the first delay type; when the access delay of the storage medium is not greater than the preset value, The delay type of the storage medium is determined to be a second delay type.
  • the storage medium of the first delay type may include a hard disk drive (HDD), a solid state disk (SSD), and a non-volatile flash memory (NAND Flash).
  • the at least one storage medium, the second delay type storage medium may include at least one of a dynamic random access memory (DRAM) and a non-volatile memory (NVM).
  • DRAM dynamic random access memory
  • NVM non-volatile memory
  • non-volatile solid-state memory may include a phase change memory (PCM) and a magnetic memory (Magnetic Random Access Memory, At least one of MRAM) and Resistive Random Access Memory (RRAM), or NVM may also include other new types of memory, and embodiments of the present invention are not limited thereto.
  • PCM phase change memory
  • RRAM Resistive Random Access Memory
  • a correspondence between a preset storage medium and a delay type of the storage medium may be acquired, and then determining a delay of the storage medium according to the obtained correspondence relationship.
  • the type is the first delay type or the second delay type, where the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the correspondence between the preset storage medium and the delay type of the storage medium may be a correspondence between a storage medium pre-stored in the local or storage device and a delay type of the storage medium.
  • the method 200 further includes:
  • Step 260 Determine whether the to-be-accessed data of the current access operation is stored in the cache.
  • Step 230 In step 260, if it is determined that the to-be-accessed data is not stored in the cache, determine a delay type of the storage medium.
  • the cache may include all levels of cache cache in the CPU, a cache in the message memory controller MMC, or a cache in the cache in the software manager, and when the storage device is When the storage device UAS is integrated, it also includes the cache in the controller of the UAS. For example, in step 260, it may be determined in sequence according to the memory access address whether the data to be accessed is stored in each level of the cache in the CPU, the cache in the MMC, and the cache in the cache in the controller of the UAS, when step 260 When it is determined that the data to be accessed is not stored in any of the caches of the caches, the delay type of the storage medium is determined in step 230.
  • the to-be-accessed data when it is determined that the to-be-accessed data is stored in the cache, it may be implemented according to the prior art, that is, directly reading the to-be-accessed data from the cache or updating the to-be-accessed data. Go to the cache.
  • the to-be-accessed data when it is determined that the to-be-accessed data is stored in the cache, it may be implemented according to the prior art, that is, directly reading the to-be-accessed data from the cache or updating the to-be-accessed data. Go to the cache.
  • FIG. 4 shows a schematic flow chart of a method 300 of CPU scheduling according to another embodiment of the present invention.
  • the method 300 shown in FIG. 4 illustrates the solution of the embodiment of the present invention by taking the access address as a physical address as an example, as shown in FIG. 4 .
  • Step 310 Acquire an access address of a current access operation, where the access address is a physical address.
  • Step 320 Determine, according to the physical address obtained in step 310, a storage medium corresponding to the physical address.
  • Step 330 Determine a delay type of the storage medium according to the storage medium determined in step 320.
  • the delay type of the storage medium may be compared according to the comparison result of the storage medium, and the delay type of the storage medium may be determined according to the comparison result. For example, when the access delay of the storage medium is greater than a preset value, the The delay type of the storage medium is the first delay type. When the access delay of the storage medium is not greater than the preset value, the delay type of the storage medium may be determined to be the second delay type.
  • the preset value may be determined according to a time required by the kernel to perform a read operation on the storage medium.
  • the first preset value may be set to 100 ⁇ s-1 ms, for example, the first preset.
  • the value can be set to 500 ⁇ s, and the time for the CPU to perform a read operation on the HDD is 4 ms, which is greater than the first preset value of 500 ⁇ s. Therefore, the delay type of the HDD is the first delay type, that is, the HDD is the storage of the first delay type. medium.
  • the second preset value can be set to 600 ns-1 ⁇ s.
  • the second preset value can be set to 800 ns, and the CPU performs a read operation on the DRAM for 600 ns, which is less than the second preset value of 800 ns, so the DRAM
  • the delay type is the second delay type, that is, the DRAM is a storage medium of the second delay type.
  • the first preset value and the second preset value may be set to the same value, for example, may be set to 1 ⁇ s-100 ⁇ s, for example, may be set to 60 ⁇ s, and the CPU performs a read operation on the NVM for 300 ns, which is less than
  • the preset value is 60 ⁇ s
  • the delay type of the NVM is the second delay type, that is, the NVM is the storage medium of the second delay type
  • the time for the CPU to perform a read operation on the SSD is 70 ⁇ s, which is greater than the preset value of 60 ⁇ s
  • the delay type of the SSD is the first delay type, that is, the SSD is the storage medium of the first delay type.
  • the correspondence between the storage medium stored in the local or storage device and the delay type of the storage medium may also be obtained, and the delay type of the storage medium is determined.
  • the correspondence between the storage medium and the delay type of the storage medium can be obtained by querying a correspondence table or a document corresponding to the correspondence between the storage medium stored in the local storage device and the storage medium. And determining the type of delay of the storage medium.
  • the delay type of the storage medium and the storage medium may be obtained by querying a correspondence table or a document corresponding to a correspondence between a physical address of the storage medium stored in the local storage device and the delay type of the storage medium. The correspondence between the two, and then determine the type of delay of the storage medium.
  • the correspondence table may include: a storage medium and a delay type of the storage medium.
  • the correspondence table can be as shown in Table 1.
  • 0 can represent the second delay type
  • “1” can represent the first delay type
  • the delay type of the HDD is the first delay type
  • the delay type of the NVM is the second delay type.
  • the second delay type storage medium may be represented by "Y”.
  • "X" indicates the first delay type storage medium, or is directly expressed as "second delay type” and "first delay type” and the like.
  • the correspondence between the storage medium and the physical address space range of the storage medium may be obtained before the correspondence between the storage medium and the delay type of the storage medium is obtained, for example, It is a correspondence table as shown in Table 2.
  • the physical address space corresponding to the storage medium DRAM is in the range of 0-4 GB. It should be understood that the address space of the DRAM may be continuous or discrete, and the embodiment of the present invention is not limited.
  • the storage medium corresponding to the physical address is DRAM, and according to the correspondence between Table 1, the delay type of the DRAM is determined to be the second delay type.
  • the correspondence table may further include: a starting physical address and an ending physical address of the storage medium, for example, a physical space of a storage device including a plurality of storage media of different delays is 64M,
  • the correspondence table can be as shown in Table 3.
  • the storage medium corresponding to the physical address is DRAM
  • the delay type of the DRAM is the second delay type.
  • the delay type of the storage medium corresponding to the physical address is the second delay type. Therefore, the delay type of the storage medium corresponding to the physical address can be directly determined according to the correspondence between the physical address and the delay type of the storage medium.
  • the physical address of the storage medium shown in Table 2 and Table 3 may be determined according to the actual situation, and is only used to explain the technical solution of the embodiment of the present invention, and is not limited to the embodiment of the present invention, but needs to be pointed out.
  • the corresponding physical address space of the storage medium DRAM, HDD, SSD, NVM, etc. is a physical address space that does not overlap.
  • the physical address is taken as an example for detailed description, but the embodiment of the present invention is not limited thereto.
  • the correspondence table may also include: a virtual address, a storage medium, and a delay.
  • the virtual address can include a starting virtual address of the storage medium, ending the virtual address. For the sake of brevity, it will not be repeated here.
  • step 330 When it is determined in step 330 that the delay type of the storage medium is the first delay type, and the current access operation is a read operation, the following steps are performed:
  • Step 341a suspending the process of the current access operation, and reading the to-be-accessed data of the current access operation from the storage medium.
  • the MMC may send an interrupt request to the CPU core, where the interrupt request triggers the CPU to suspend the currently running process, that is, the CPU core can release the CPU resources occupied by the currently running process, so that Other processes that are running consume this CPU resource.
  • step 342a when the reading of the data to be accessed is completed, the process suspended before the operation is resumed.
  • the MMC can send a recovery request to the CPU core that triggers the process that was suspended before the CPU core resumes operation.
  • the process that is suspended before the recovery is resumed may be re-tuned into the ready queue for queuing, or the process may be preferentially run directly in the form of a queue.
  • step 330 When it is determined in step 330 that the delay type of the storage medium is the second delay type, and the current access When the operation is a read operation, perform the following steps:
  • Step 341b reading the data to be accessed from the storage medium.
  • step 342b when the reading of the data to be accessed is completed, the process of the current access operation is continued.
  • the third request is sent to the CPU core.
  • a message for example, can send a trigger request to the CPU core that triggers the CPU core to run the currently waiting process.
  • the currently waiting process refers to a process that occupies CPU core resources but does not run.
  • the CPU scheduling method determines the access medium of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay
  • the process of continuing to wait for execution is continued. To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the current access operation when the current access operation is a write operation, the current access operation may be implemented according to the prior art, that is, the data to be accessed may be written to the storage without determining the delay type of the storage medium corresponding to the memory access address. medium. It can also be implemented according to the process in the embodiment of the present invention, that is, it is determined in step 320 that the delay type of the storage medium is the first delay type, and when the data to be accessed is written, the CPU core can be scheduled to suspend the current operation. The process is performed, and the data to be accessed is written into the storage medium; when the writing of the data to be accessed is completed, the CPU is scheduled to resume the process that is suspended before the running, and the embodiment of the present invention is not limited thereto.
  • the technical solution in the embodiment of the present invention can also support the hyper-threading technology.
  • the two logical cores can be simulated into two physical cores by using special hardware support, so that a single processor can use the thread.
  • the characteristics of the level of parallel computing, for the storage medium of the second delay type the thread or process can be quickly switched between multiple sets of registers of the CPU, without
  • the context of a thread or process is loaded in a storage medium of a two-latency type, and the overhead of such switching is much smaller than the overhead of accessing the storage medium of the second delay type, so no CPU waits; and for the first delay
  • a type of storage medium because its access delay is long, the CPU waits to cause excessive overhead, and the context of the thread or process needs to be loaded from the storage medium of the first delay type, which requires the CPU to perform process switching, thereby reducing Overhead.
  • FIG. 5 shows a schematic flow diagram of a method 500 of CPU scheduling in accordance with another embodiment of the present invention. As shown in Figure 5,
  • Step 510 Obtain an access address of the current access operation.
  • Step 520 Determine, according to the access address obtained in step 510, whether the data to be accessed of the current access operation is stored in the cache.
  • the cache may be a cache cache of various levels in the CPU 100 in FIG. 1 .
  • Step 530a when it is determined in step 520 that the data to be accessed is not stored in the cache, determine the storage medium corresponding to the access address according to the access address obtained in step 510.
  • Step 540a Determine a delay type of the storage medium according to the storage medium determined in step 530a.
  • step 540a When it is determined in step 540a that the delay type of the storage medium is the first delay type, and the current access operation is a read operation, the following steps are performed:
  • step 541a the currently running process is suspended, and the data to be accessed is read from the storage medium.
  • step 542a when the reading of the data to be accessed is completed, the CPU kernel is scheduled to resume the process that was suspended before the operation.
  • step 540a When it is determined in step 540a that the delay type of the storage medium is the second delay type or when it is determined in step 520 that the data to be accessed is already stored in the cache, the following steps are performed:
  • Step 541b controlling to read the data to be accessed from the storage medium.
  • step 542b when the reading of the data to be accessed is completed, the CPU core is scheduled to run the currently waiting process.
  • the CPU scheduling method determines the access address of the current access operation, determines that the to-be-accessed data of the access operation is not stored in the cache according to the access address, determines the storage medium corresponding to the access address, and further determines The type of the delay of the storage medium.
  • the process of performing the current access operation is suspended, and the process switching is implemented.
  • the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby further reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 6 shows a schematic interaction process diagram of a method 600 of CPU scheduling in accordance with another embodiment of the present invention.
  • the method of FIG. 6 may be performed by a CPU, wherein a delay type of a storage medium corresponding to a physical address may be determined by a message type memory controller MMC within the CPU.
  • the method 600 shown in FIG. 6 is an example of FIG. 2, FIG. 4 or FIG. 5, as shown in FIG.
  • step 610 the CPU core sends the physical address of the current access operation to the MMC.
  • step 620 the MMC receives the physical address sent by the CPU core.
  • step 630 it is determined that the to-be-accessed data of the current access operation is not stored in the cache in the MMC.
  • Step 640 The MMC determines the delay type of the storage medium corresponding to the physical address as the first delay type by querying the corresponding relationship between the storage medium and the storage medium type.
  • the MMC can determine the delay type of the storage medium corresponding to the physical address as the first delay type by comparing the relationship between the access delay of the storage medium corresponding to the physical address and the preset value.
  • the storage medium of the first delay type may be HDD, SSD or NAND Flash.
  • step 650 the MMC sends an interrupt request to the CPU core, the interrupt request is used to instruct the CPU core to suspend the currently running process.
  • step 660 the CPU core receives the interrupt request sent by the MMC, and suspends the currently running process according to the instruction of the interrupt request.
  • Step 670 The MMC reads the data to be accessed from the storage medium corresponding to the physical address.
  • step 660 the MMC sends a recovery request to the CPU core, the recovery request is used to instruct the CPU kernel to resume the previously suspended process.
  • the MMC needs to store the to-be-accessed data read from the storage medium corresponding to the physical address into the cache, so that step 660 can be performed.
  • Step 690 The CPU core receives the recovery request sent by the MMC, and resumes the process that was suspended before the operation according to the instruction of the recovery request.
  • the CPU scheduling method determines the physical address corresponding to the physical address, and determines the storage medium corresponding to the physical address, by determining the physical address of the current access operation and determining that the to-be-accessed data of the access operation is not stored in the cache according to the physical address.
  • the delay type of the storage medium When it is determined that the delay type of the storage medium is a type with a large delay, the process of performing the current access operation is suspended. The process is now switched, which can further reduce the waste of CPU resources and reduce the overhead of the system.
  • the step 640 may include: determining, by the MMC, the delay of the storage medium by receiving an indication message that the delay type of the storage medium corresponding to the physical address fed back by the controller of the UAS is the first delay type.
  • the type is the first delay type.
  • step 630 If it is determined in step 630 that the data to be accessed is already stored in the cache in the MMC, the data to be accessed is directly read from the cache and stored in the cache, and the steps in step 640 and subsequent steps are not performed.
  • step 640 the MMC determines that the delay type of the storage medium corresponding to the physical address is the second delay type, and then the MMC sends a trigger request to the CPU core by querying the corresponding relationship between the locally stored storage medium and the storage medium type.
  • the request is used to instruct the CPU core to resume running the currently waiting process, and the CPU core receives the trigger request sent by the MMC, and resumes running the currently waiting process according to the indication of the trigger request, that is, the process of continuing the current access operation.
  • the storage device is a UAS, and the controller of the UAS has a cache. Then, after step 640, before step 650, the following steps are also performed:
  • step 641 the MMC sends a physical address to the controller of the UAS.
  • Step 642 the controller of the UAS determines, according to the physical address, whether the data to be accessed is stored in a cache in the controller of the UAS.
  • Step 643a (not shown in the figure), when the controller of the UAS determines that the data to be accessed is not stored in the cache in the controller of the UAS, the steps of step 650 and subsequent steps are performed;
  • Step 643b when the MMC determines that the data to be accessed is stored in the cache in the controller of the UAS, directly reads the data to be accessed from the cache, and stores it in the cache, no longer Step 650 and subsequent steps are performed.
  • FIG. 7 shows a schematic block diagram of an apparatus 700 for CPU scheduling in accordance with an embodiment of the present invention.
  • the device 700 is applied to an integrated storage device, where the integrated storage device includes a plurality of different types of storage media, and the device 700 includes an obtaining module 710, a first determining module 720, and a second determining module. 730 and execution module 740, wherein:
  • the obtaining module 710 is configured to obtain a memory access address of the current access operation.
  • the first determining module 720 is configured to determine an access address obtained by the obtaining module 710 to determine an access operation.
  • the storage medium to be accessed.
  • the second determining module 730 is configured to determine a delay type of the storage medium determined by the first determining module 720.
  • the execution module 740 is configured to suspend the process of running the access operation when the delay type of the storage medium determined by the second determining module 730 is the first delay type; the delay type of the storage medium determined by the second determining module 730 is When the second delay type is used, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the access delay of the storage medium of the second delay type.
  • the apparatus for scheduling a CPU core determines the storage medium accessed by the current access operation according to the access address by obtaining the access address of the current access operation, and further determines the delay type of the storage medium, when determining the storage medium.
  • the delay type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay
  • the process of continuing to wait for execution is continued.
  • the waiting time of the access operation can be reduced to some extent, and the processing efficiency of the process can be improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the second determining module 730 is specifically configured to obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determining that the delay type of the storage medium is the first The delay type is determined. If the access delay of the storage medium is not greater than a preset value, determining that the delay type of the storage medium is the second delay type.
  • the second determining module 730 is specifically configured to obtain a correspondence between the preset storage medium and a delay type of the storage medium, and determine the storage according to the correspondence acquired by the obtaining unit.
  • the type of delay for the media is specifically configured to obtain a correspondence between the preset storage medium and a delay type of the storage medium, and determine the storage according to the correspondence acquired by the obtaining unit. The type of delay for the media.
  • the storage medium of the first delay type may include at least one of a hard disk drive (HDD), a solid state disk (SSD), and a non-volatile flash memory (NAND Flash).
  • the storage medium of the second delay type may include at least one of a dynamic random access memory (DRAM) and a non-volatile memory (NVM).
  • DRAM dynamic random access memory
  • NVM non-volatile memory
  • the apparatus 700 further includes:
  • the third determining module 750 is configured to determine whether the to-be-accessed data of the access operation is stored in the cache,
  • the second determining module 730 is specifically configured to determine a delay type of the storage medium when the third determining module 750 determines that the to-be-accessed data is not stored in the cache.
  • the apparatus 700 in the CPU scheduling according to the embodiment of the present invention may correspond to the execution body of the method according to the embodiment of the present invention, and the foregoing modules of the CPU 700 are scheduled by the CPU. And other operations and/or functions, respectively, in order to implement the corresponding processes of the respective methods in FIG. 2 to FIG. 6, for brevity, no further details are provided herein.
  • the apparatus for scheduling a CPU determines the access medium of the current access operation according to the access address, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, when determining the storage medium.
  • the type of the delay type is a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the storage medium is determined to be of a type with a small delay, the process of continuing to wait for execution is continued. To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • FIG. 9 shows a schematic block diagram of a memory device 900 in accordance with an embodiment of the present invention.
  • the storage device 900 includes a controller 910 and a plurality of different types of storage media 920. among them,
  • a storage medium 920 is used to store data.
  • the storage medium 920 may be an integrated storage device UAS, and the UAS includes a plurality of different types of storage media and controllers of the UAS, and the storage media may be accessed through the same memory interface.
  • the controller 910 is configured to: obtain an access address of the current access operation; determine a storage medium accessed by the access operation according to the access address; determine a delay type of the storage medium; and determine that the delay type of the storage medium is the first delay type
  • the process of running the access operation is aborted; in the case that the delay type of the storage medium is determined to be the second delay type, the process of the access operation is continued, wherein the access delay of the storage medium of the first delay type is greater than the second The access latency of the storage medium of the delay type.
  • the controller 910 may include a core core 912, a memory management unit MMU 914, a cache cache 916, and a message memory controller MMC918.
  • the core core 912 is used to obtain the access address of the current access operation
  • the MMU 914 is configured to convert the virtual address into a corresponding physical address
  • the MMC 918 can be used to determine the storage medium accessed by the access operation according to the access address, and determine the delay type of the storage medium.
  • the kernel core 912 is further configured to: when the MMC 918 determines that the delay type of the storage medium is the first delay type, suspend the process of running the access operation; and determine, in the MMC 918, the delay type of the storage medium is the second delay type. In the case, the process of the access operation continues.
  • the storage device can obtain the access address of the current access operation, determine the storage medium accessed by the current access operation according to the access address, and further determine the delay type of the storage medium, and determine the delay of the storage medium.
  • the type is a type with a large delay
  • the process of performing the current access operation is aborted, and the process switching is implemented.
  • the process of continuing to wait for execution is continued, according to this manner, To some extent, the waiting time of the access operation is reduced, and the processing efficiency of the process is improved, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the MMC 918 can also receive the delay type of the storage medium fed back by the controller of the UAS, and the core core 912 is used to receive the delay type of the storage medium fed back by the controller of the UAS at the MMC 918.
  • the process of running the access operation is aborted; in the case where the delay type of the storage medium fed back by the controller of the UAS received by the MMC 918 is the second delay type, the process of continuing the access operation is continued. .
  • the controller 910 is specifically configured to: obtain an access delay of the storage medium; if the access delay of the storage medium is greater than a preset value, determine that the delay type of the storage medium is a first delay type; If the access delay of the storage medium is not greater than the preset value, determine that the delay type of the storage medium is the second delay type.
  • the controller 910 is specifically configured to: obtain a correspondence between a preset storage medium and a delay type of the storage medium; and determine a delay type of the storage medium according to the correspondence.
  • the controller 910 is further configured to: before determining the delay type of the storage medium, determine whether the to-be-accessed data of the current access operation is stored in the cache; and determine that the to-be-accessed data is not stored in the cache. In the case of the medium, the type of delay of the storage medium is determined.
  • the first delay type storage medium includes at least one of a hard disk drive HDD, a solid state hard disk SSD, and a nonvolatile flash NAND Flash
  • the second delay type storage medium includes dynamic randomness.
  • the storage device of the embodiment of the present invention obtains the access address of the current access operation, determines the storage medium accessed by the current access operation according to the access address, and further determines the delay type of the storage medium, and determines the delay type of the storage medium as the delay.
  • the process of executing the current access operation is aborted, and the process switching is implemented.
  • the process of continuing to wait for execution is continued, and according to this manner, the access can be reduced to some extent. Waiting time for operation In addition, improve the processing efficiency of the process, thereby reducing the waste of CPU resources and reducing the overhead of the system.
  • the controller 910 of the storage device 900 may correspond to an execution body of the method according to the embodiment of the present invention, and the controller 910 of the storage device 900 may implement The corresponding processes of the respective methods in FIG. 2 to FIG. 6 are not described herein again for the sake of brevity.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.

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Abstract

La présente invention concerne un procédé et un appareil d'ordonnancement d'une UCT. Le procédé consiste à : (210) acquérir une adresse d'accès d'une opération d'accès en cours ; (220) selon l'adresse d'accès, déterminer un support d'informations auquel a accédé l'opération d'accès ; (230) déterminer un type de retard temporel du support d'informations ; (240) dans le cas où le type de retard temporel du support d'informations est déterminé comme étant un premier type de retard temporel, arrêter un processus exécutant l'opération d'accès ; (250) et dans le cas où le type de retard temporel du support d'informations est déterminé comme étant un second type de retard temporel, exécuter en continu le processus de l'opération d'accès. Selon le procédé, lorsqu'il est déterminé que le type de retard temporel du support d'informations est un type d'un retard temporel supérieur, le processus exécutant l'opération d'accès est arrêté de sorte à mettre en œuvre la commutation de processus, et lorsqu'il est déterminé que le type de retard temporel du support d'informations est un type d'un retard temporel inférieur, il est mis en attente et l'exécution du processus d'accès est effectuée en continu. Ainsi, le temps d'attente de l'opération d'accès peut être réduit dans une certaine mesure, et l'efficacité de traitement de processus est améliorée, de sorte à réduire le gaspillage des ressources de l'UCT et le surdébit du système.
PCT/CN2014/086702 2014-09-17 2014-09-17 Procédé et appareil d'ordonnancement d'uct WO2016041156A1 (fr)

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