WO2016020098A1

WO2016020098A1 - Generating an identifier for a circuit

Info

Publication number: WO2016020098A1
Application number: PCT/EP2015/063806
Authority: WO
Inventors: Kai Fischer; Erwin Hess; Dominik Merli; Andreas Mucha; Fabian Riess
Original assignee: Siemens Aktiengesellschaft
Priority date: 2014-08-05
Filing date: 2015-06-19
Publication date: 2016-02-11
Also published as: DE102014215467A1

Abstract

The invention relates to a circuit for generating an identifier for the circuit, said identifier functioning as a physically unclonable function and providing at least one bit as a measurement result, wherein an identifier of the circuit is generated solely from the measurement result or in connection with other measurement values. The circuit has at least two switching stages, each of which comprises at least two switching stage elements. Switching stage elements of successive switching stages can be assigned to one another using a permutation instruction which can be assigned to each switching stage element. Furthermore, an interface unit for an initialization unit is provided, said initialization unit being suitable for specifying a determined value as the output value of the respective output of the switching stage elements of the switching stages such that the circuit can be kept in an unstable state during an active phase of the initialization unit. After the active phase has ended, the circuit is designed to assume a state which characterizes the circuit dependent on the permutation instruction. A detection unit for detecting at least one bit within the circuit in the characteristic state is provided for generating the identifier.

Description

description

Generating an identifier for a circuit in the industrial and in the private sphere electronic devices, integrated circuits, or embedded Gerä ^¬ te, so-called embedded devices, are used. These devices, that is, the physical objects or the hardware on which at ^¬ play, an embedded system is realized, are for many different applications can be ^¬ fied or authenticated clearly identi. Moreover, for applications in the security environment cryptographic Keüs ^¬ sel be protected against unauthorized access stored on the devices described or used. There is often an interest in physical attacks on ^¬ be used cryptographic keys, these keys to ver ^¬ nieces.

It is known to use the principle of physically unclonable functions, so-called physical unclonable functions, in short PUFs, whereby a complex behavior of a physical system is analyzed. The behavior is determined by factors that are neither directly observable, modifiable or reproducible by the manufacturer of the system nor by anyone else, in particular an attacker. It is assumed that a manufacturer of a hardware may not be able to produce a hardware with given physically unclonable properties. A PUF maps input values or challenges to output values or responses in a manner determined by the complex behavior. The picture by the PUF is present at every physi ^¬ rule specimen, also known as instance, different and random for all practical purposes, for the single copy but stable.

Thus, authentication by means of the physically unclonable function can be achieved by measuring the intrinsic physical property of the hardware and by ne derived information is used as an identifier. A physically unklonbaren function can be tested, if it is in a device or a semiconductor circuit to an original product, such as a response or measurement is evaluated here as well, which are not on a replica or manipu ^¬ profiled device or semiconductor circuit can be generated. If the number of possible PUF Challenge Response Pairs is so large that it is impractical for an attacker to learn a significant proportion of them, even if they have physical access to the object, it is called a Strong PUF.

A specific expression of a Strong PUF has been reported in Chen et al. "The bistable ring PUF: A new architecture for strong Physical Unclonable Functions" (2011 IEEE International Sym ^¬ sium on hardware Oriented Security and Trust (HOST), 134- 141. IEEE, 2011) presented here is a bistable ring PUF. BRPUF, which consists of a ring-connected even number of identical stages of digital circuit elements, each implementing the logical Ne ^¬ cation, eg inverter .. Because of this structure, the ring has two stable states At the stage of the ring, the outputs of the inverters can either have the pattern 0101 or 1010. The random variations in the characteristics of integrated circuits and their elements due to fabrication influence for each physical instance of a BRPUF which of the two stable states the ring occupies. The information which of the two states is present corresponds to a PUF response from a B it. exist to achieving a challenge-response formalism within each stage two parallel signal paths, wherein confi gured ^¬ as an active element of the ring about a Challenge one of the two paths, while the other is disabled. The bit length of the challenge corresponds to the number of stages of the ring, that is, each bit of the challenge determines the Configu ^¬ ration of the signal path in a stage. To re-off ^¬ read the response for a new challenge to allow temporarily forced by a reset signal of the ring in an unstable state in which all the steps in the same state, 0 or 1, are. After canceling the reset state, the ring falls after one settling time in one of the two stable states. Unfortunately, real implementations of a BRPUF often provide the same response regardless of the challenge. Ideally ^¬ case a uniform distribution of the responses is desired.

It is from the dissertation "Attacking and Protecting Ring Oscillator Physical Unclonable Functions and Code Offset

Fuzzy Extract "by D. Merli, 2013, known to use a so-called Twisted Bistable Ring PUF, where a Challenge bit is no longer used to disable one path element and to activate another, but to swap two path elements made within a ring. Thus, getting all the path elements in the ring and the annular ^combustion length remains constant. a path element only changes the position within the ring. There is a need, formality for a circuit with PUF functionalities as many challenge response hold to provide pairs available and at the same time evenly distributed Responses to he ^¬. This object is solved by the independent claims of the application ahead ^¬. advantageous embodiments are specified in the dependent claims.

According to the invention, a circuit is provided for generating an identifier for the circuit, with

at least two switching stages, the switching stages each comprising at least two switching stages ^¬ weils elements, the Minim ^¬ are formed so than two switching stages, that respective ge output values at respective outputs of the at least two switching stages elements of a preceding switching stage jeweili ^¬ gen inputs of the at least two switching stages elements of a following switching stage are alternatively fed;

wherein by a respective step element switching denbare permutation zuor- an assignment of a jeweili ^¬ gen input of the respective switching stage member is followed ^¬ the switching stage to exactly one output of a Schaltstufenele ^¬ mentes the preceding switching stage be fixed;

with an interface unit to an initialization, the initialization unit as the output value of a respective From ^¬ gear, so that the circuit in an unstable state can be kept suitable for setting a predetermined value of the switching stages elements of the switching stages during an active phase of the initialization;

wherein after termination of the active phase, the circuit is set up to take a characteristic of the circuit ^¬ rule state as a function of the permutation rule;

at least one detection unit for detecting at least ei ^¬ nes bits at least one position within the scarf ^¬ tion, wherein by detecting the at least one bit within the circuit in the characteristic state using the at least one bit of the identifier can be generated.

The circuit acts as a physically unklonbare radio ^¬ tion and provides, as a measurement result at least one bit, from which alone or in conjunction with other measured values an identifier of the circuit is produced. The identifier may, in particular, be a bit pattern. This bit pattern is characteristic and uniquely identifies a specific copy of the circuit. A replica or a forgery of the circuit or a further copy of the circuit provides a different identifier with identical measurement of the circuit. The circuit is, for example, an integrated circuit ^¬ circuit, in particular a digital circuit, an FPGA or an ASIC. In particular, the circuit is only a cut or a subarea on an integrated circuit or FPGA or ASIC. For example, only this section has a PUF functionality. This section is then used for the generation of the identifier, for example for the verification of identity of a present circuit with an original circuit.

If, for example, an access to the original circuit does not exist, for example because a present circuit to be tested is another device or another example of the circuit, or if a modified, manipulated or reconstructed circuit is present, then it can the identifier can not be determined by means of the physically unclonable function.

The switching stage is understood to mean a block of at least two switching stage elements. The logical grouping of a plurality of shift stage elements to the block arises from the fact that all alternative shift stage elements, to which a respective output value can be supplied, are logically combined. This means that a potentially pro in the circuit ^¬ pagierender signal change happened a switching stage element of a spe ^¬-specific switching stage and then the next shift stage is fed to a causal conditional by this signal change signal another shift stage element of this specific shift stage or the same switching stage element only after a Circulation time can pass through all existing switching stages again. A switching stage element is understood to mean a functional element which implements a logic function. In particular, it is inverter, which outputs the logical negati ^¬ on an input signal as an output signal. In particular ^¬ sondere used digital circuit elements to implement the desired logic function. On reprogrammable digital components, so-called Field Programmable Gate Arrays, short FPGAs, for example, the inversion ^¬ function particularly favorable by so-called look-up tables, short LUTs, to be realized. LUTs can implement any logic ^¬ functions within their available input and output signals, as can be stored in them in the form of a table of values for every possible combination of input signals an associated output value. In particular, in the switching step elements to the functional elements, which have two inputs and in depen ^¬ dependence acting from a fixed present at one of the inputs an input signal for signals at the other input the inverted ter, for example, NOR gate.

The interconnection between two switching stages is provided such that only one of a plurality of inputs of a switching stage element is connected to an output of a switching stage element of the preceding switching stage. When using a multiplexer which is ^preceded by a switching stage ^element , the multiplexer selects one of possible connections of outputs of preceding switching stage elements to inputs of subsequent switching stage elements. At the same time, only one output of the previous switching stage is supplied to a switching stage element, so that an interconnection of switching stage elements of the previous switching stage to switching stage elements of the subsequent switching stage is permuted with respect to the assignment of the respective switching stage elements to one another. In this case, two assignments or more can be interchanged, ie all achievable by permutation combinations of interconnections can be accepted.

The permutation rule specifies the interconnection with the outputs of each switching stage element of a switching stage

Switching stage elements of the previous switching stage fixed. In ^¬ play inputs of the respective Schaltstufenele ^¬ elements are activated by the permutation, and an output of a switching element of a stage previous study programs fe is only one switching element of the following stages

Switching stage fed. In particular, a permutation ^rule prescribes the assignment for all the switching stage elements of a switching stage together. Each shift stage will be at the Choice of Permutationsvorschrift all taken into account for the permutation ^¬ seen switching stage elements. Thus, ei ^¬ ne double assignment of multiple outputs of switching stage elements of previous switching stages to an input of a switching stage element is advantageously avoided. In one ^variant , switching stage elements can be provided which are not configured via the permutation rule but have invariable connections to previous or subsequent switching stages. The number of the permutation participating ligter switching step elements match in neighboring Schaltstu ^¬ fen. The permutation rule can be understood as a sequence for measuring the circuit acting as a PUF. In particular, a depending ^¬ stays awhile permutation is provided for all the switching stages of the circuit, so that a maxi ^¬ male number of different interconnections of shift stages elements of the respective switching stages to one another is possible.

In order to place the circuit in an unstable state, which determines output values of the respective outputs of the switching stage elements independently of an interconnection of the switching stage elements and independently of a production-related characteristic of the installed components, an interface device to an initialization unit is provided. The interface device can be configured in such a way that, in particular, an input is provided for all switching stage elements of a switching stage and for each of the built-in switching stages, to which a value predeterminable by the initialization unit is permanently applied, so that a value independent of the respective other input, by the switching stage element, which receives the output signal of the upstream circuit element is output. Thus, for example, the inverting function of the switching stage ^¬ elements is suppressed during the active phase of the initialization and there is no signal change due to the implemented logic function of the switching stage element instead of. Once the active phase is complete, ie when at ^¬ play, the triggered by the initialization input of a switching stage member is busy such that the switching stages element images an image of the value at the other input, regardless of the area occupied by the initialization input, the circuit leaves the unstable Status. Thus, a reset function is incorporated by the initialization unit, which inde ^¬ gig momentarily displaced from an existing condition in the circuit, the circuit in an unstable state and takes no longer affect the state after the completion of the active phase. After leaving the unstable Zustan- of the outputs of the switching stages elements may show partly chaotic oscillatory behavior, which eventually ends up in the circuit a certain time period when a stable state is entered by the circuit which of the permutation and its indi ^¬ vidual, copy -specific properties is determined. The circuit may also remain in a non-stable state for a predetermined period of time. Then there is the characteristic state that currently none of it is assumed in ^¬ the stable states. An identifier can also be derived from this information, for example by evaluating multi-bit responses which, in addition to the two possible stable states, also detect the unstable state as a characteristic state.

The permutation rule determines the configuration of the circuit, ie the position of switching elements within the circuit. Configuration of the complete circuit, there is determined, and in particular it is determined which switching stages elements are located within a bistable ring and in particular a common bistable ^¬ len ring. As a result of the permutation rule, it is simultaneously determined how many rings result from the interconnection of the respective shift stage elements. Furthermore, the permutation rule determines how many potentially stable rings are formed. Beispielswei- se a bistable ring is formed which has all the scarf ^¬ processing elements. In another variant, two bistable rings are formed. It is also possible that one or more bistable rings are formed by the permutation rule and an unstable ring, eg an oscillating circuit.

The interface device consists in particular of an interface of all switching stage elements located in the circuit to form an initialization unit which uniformly predefines the output value for all switching stages. Preprinting by an output value at a position within the circuit which predetermines the assumption of one of the two bistable states is thus avoided.

If there is the permutation, that is, a permu ^¬ tationsvorschrift was selected and was the Permutationsvor ^¬ record of units, such as multiplexers transmitted to the respective switching stages elements, so that the supply order could be each made, can, via the interface device, an initialization signal, ie, a predetermined value can be specified, which specifies fixed output values of the switching stage elements. The circuit is now kept in an unstable state, so that previously assumed values within the circuit no longer have any influence on the unstable state. The active phase of the initialization unit is then terminated and one or more of the bistable states or an unstable state is now assumed in the one or more bistable ring circuits.

The selected state of the rings is characteristic for the realization or for the copy of the circuit configured via the permutation regulation and can be read out with the aid of a detection unit which is provided at at least one position of the circuit, for example in each bistable closed ring. The detection unit detects a bit or a multi-bit pattern as a response to the chosen permutation rule, ie the chosen challenge. Is detected one bit at a location within a bistable ge ^¬ closed ring, which registers the logical value at this point, it is clearly determined which of the two bistable states was adopted. The identifier can now be formed, for example, from a read-out bit if a single ring has been formed by the configuration. A multi-bit Response to Be ^¬ mood one of the three possible characteristic states - stable 0101 ... or 1010 ... stable or unstable - is analogous to the data forming the Identifizieres. If multiple rings have been formed, the bits representing the state in each of the rings may be combined to produce the identifier. In particular, a bit from a short formed ring may be included in the generation of the identifier to prevent challenge-response behavior of the short ring with manageable challenge-response space. The permutation rule provides a multiplicity of possible interconnections, which leads to a multiplicity of different configurations. The configurations differ both in the number of rings formed and in the shape of the rings, ie the position of individual switching stage elements within the circuit. The ge ^¬ selected permutation can be regarded as a challenge, which is given to the circuit and from which there is a configuration of the circuit. Thus, a very large challenge space is available, which is determined by the number of possible permutations of respective shift stage elements of respective shift stages. For a number L of successive switching stages, each with a number N of different switching stage elements results in a number of ^¬ N! ^L possible configurations. The identifier can be considered a response. For a copy of a circuit, a response to a given challenge is unpredictable, since the assumption of one of the two stable states is due to production-related variables. ration of the hardware, which are neither reproducible nor foreseeable by the manufacturer in hardware.

The challenge-response behavior of the circuit is therefore neither predictable nor reproducible and the identifier generated is thus able to provide information about the originality of a circuit. If the circuit has been manipulated, this can also be detected via a challenge-response behavior in which responses to selected challenges do not match the responses made by a manufacturer or a trusted entity at a time when no manipulation has been secured has taken place. The circuit shows a favorable response behavior, which, avoids excessive tendency to a fixed Response un ^¬ dependent on the applied Challenge. The strong mixing of the signal paths by choosing the configuration by means of the permutation rule and variation of the ring lengths as a function of the challenge results in a greater variance of the internal circuit parameters, which ensures a balanced response behavior. Due to the large in ^¬ ternal complexity so-called Machine Learning are attacks on the PUF, which attempt to predict based on the known subset of challenge-response pairs, the responses of the PUF for any other challenges more difficult. The cost of circuit resources and thus the costs in the implementation are low. According to one embodiment, by supplying respective outputs of switching stage elements of a following switching stage to respective inputs of switching stage elements of a preceding switching stage, at least one bistable closed ring can be constructed. This means that the switching stages can be closed to a ring, is placed firmly ^¬ by the permutation which switching stages elements are connected to the rear Kopp ^¬ switching center together. The assignment of switching stage elements to each other thus takes place at each point within the ring in an analogous manner. Through the interaction of all Permutationsvorschriften, ie all assignments to the built-shift levels, the behavior of the circuit is determined in terms of the number of rings. Only when the permutation rule at all switching stages, which are designed configurable, is fixed and specified, the configuration of the entire circuit is fixed. According to one embodiment, three or more switching stages are provided, whose respective switching stage elements in each case interconnected via the Permutationsvorschrift according to claim 1 ^¬ , so that at least one bistable closed ring can be constructed.

In this case, both the total number of switching stages provided is variable, as well as the number of different shift stage elements per shift stage. It can be provided in the circuit ne ^¬ ben the configurable switching stages and switching stages, which are not changeable via a permutation with respect to their interconnection within the circuit. Thus, it may be advantageous to balance between the overhead of additional circuit resources and the ability to vary the configuration of the circuit.

According to one embodiment at least one Schaltstu ^¬ fenelement comprises a plurality of signal paths, wherein one of the plurality Sig ^¬ nalpfade is activated by a selection rule. For the derivation of the identifier is then next to the Challenge, which determines the interconnection of the switching stage elements for selected switching stages, also another challenge each

Switch stage element is applied, which individually selects one of the two or more signal paths for each Schaltstufenele ^¬ ment with multiple signal paths for forwarding and processing the signal in the circuit. Thus, even more variants than possible configurations can be chosen. Both challenges are specified for setting the configuration, whereupon the active phase of the initialization unit is started. After completing the active phase, the one or more responses can then be evaluated.

According to one embodiment, the circuit further comprises a respective detection unit in each of the bistable closed rings constructed by means of the Per ^¬ mutationsvorschrift for detecting at least one respective bit, wherein from several bits of the respective bits of the identifier can be derived. Advantageously, a respective detection unit is provided in each track, wherein the number of tracks is defined by the number of switching stage elements per switching ^¬ stage. Depending on the configuration, only a portion of the installed detection units is required for detecting at least one respective bit, ie a respective characteristic state in a ring. The maximal

Number of constructible rings is determined by the number of tracks, i. at switching stage elements per switching stage, specified.

According to one embodiment, the permutation rule can be specified as a challenge, which defines the assignment for each switching stage ^{element of} the switching stage. The challenge is specified for each shift stage the shift stage elements, wherein for two consecutive over Challenges responsive shift stages, the same number of shift stage elements per shift stage is permuted. For another pair aufeinan ^¬ derfolgender switching stages a different number of switching elements per stage switching stage on the permutation ^¬ regulations can be interconnected. In particular, the challenge is multi-bit, that is to say comprises more than one bit, and can thus contain information about the input to be selected per switching stage element.

According to one embodiment, the at least one bit represents a response as a function of the challenge, and the response is characteristic of a copy of the circuit. Depending on the number of rings formed is the response in egg ^¬ ner information on the adopted characteristic state of each bistable closed ring. The response In particular, it can be formed from a combination of the respectively detected bits and form the identifier for the circuit. According to one embodiment, the response is unanimous or multi-bit. In this case, it can already be predetermined for a given challenge from the configuration selected thereby how many bits the response comprises. The evaluation of a detected in egg ^¬ nem ring bits or bit pattern can be carried out depending on the Challenge. If the configuration of the tracks was such that only one ring is formed, the state of a ^specific stage is used as a one-bit response. If several rings arise, their responses can be handled in exactly the same way as when these responses are taken from separately implemented PUF circuits. Several bits can be output in response to the number of rings. Alternatively, a linking and processing of the states takes place in a common response of one or more bits, for example by a combinatorial circuit. The identifier can be formed from one or more responses. Depending on how Clearly ^¬ or statement is strong, the presence of a response for a authenticatio ^¬ tion or key derivation, a composite of any number of detectable responses

Identifiers are formed.

According to one embodiment, the circuit further comprises a unit for evaluating the response regarding a stabilization property. The temporal behavior of the stabilization process can be included in the evaluation of the bits detected from ^different rings. For example, for each ring in addition to the detected bit and the required time from the exit of the initialization state or reset state is detected until reaching the assumed stable state. Based on this information, one or more bits of the individual rings may be output for output or further processing, the stabilization time of which satisfies predetermined conditions. In particular, tet a long stabilization time out that is not very pronounced in ^¬ trinsische tendency of a ring to one of the two possible stable end states. Thus, for example, the responses always become different

Challenges selected, whose stabilization times were the long ^¬ th, so it is expected that overall results in a more balanced distribution of oil responses. This is advantageous when a light guessing or Vorhersag ^¬ bility of a response should be avoided. At the same time, a fast stabilization process points to a strong intrinsic tendency to one of the stable states, which suggests that even under changing environmental conditions and under the influence of physical noise, which is unavoidable in real implementations, the identical applied challenge always leads to the same response. Again, this is desirable in terms of reliability and accuracy of Challenge Response methods on PUFs. These two aspects can be taken into account in order to select a favorable evaluation or a favorable selection criterion for the responses, depending on the requirement for the response. The unit may also be advantageously used to establish a period of time within which a condition in a bistable ring must be assumed to be recognized as a stable condition. If the time span is exceeded and no stable state has been assumed, the characteristic state is considered to be unstable.

According to one embodiment the unit comprises a Zeiterfas ^¬ sungseinheit, in particular a counter, and / or a selection unit for selecting and Responses to Weiterlei ^¬ th to an output unit. Thus, the stabilization property can be technically determined such that a counter in a ring counts the periods of a clock signal. Thus, it is detected how long a respective ring formed by the configuration takes until it assumes a stable state or assumes a stable state. The off ^¬ selection unit may be predetermined thresholds which indicate for which a required interval Stability 1 b

lisierungszeit a detected bit in a ring should be selected as a response. For example, the selected response is sent directly as an identifier of an output unit be placed riding ^¬. Alternatively, multiple responses are forwarded to the display unit off and there directly or after the on ^¬ a join function call einbittig or mehrbittig output.

According to one embodiment, the circuit further comprises an evaluation circuit for detecting the characteristic state, the evaluation circuit suitable for detecting a temporally stable alternating pattern along the step circuits. The evaluation circuit in particular carries out cross-over of the track and reconstructs the signal course along the rings. If a time-stable alternie ^¬ rendes pattern of the states 0 and 1 along the step scarf ^¬ obligations within one track, that is, belonging to a ring, so the stabilization process is completed, the ring has assumed a steady state and a response can be evaluated. It can be advantageously determined the time required minimum that is necessary for creating the identifier particularly to have to wait without an unnecessarily long wait ^¬ sen. The evaluation circuit may further specify a period of time within which the assumption of a stable state is expected. If no stable state has been assumed until then, the characteristic state is detected as unstable.

The invention further relates to a method for generating an identifier for a circuit having at least two switching stages, the switching stages each comprising at least two switching stage elements,

- wherein respective output values at respective outputs of the at least two switching stages elements of a preceding switching stage respective inputs supplied alternatively ^¬ leads of the at least two switching elements of a ^step-¬ following switching stage; - wherein by a respective step element switching denbare permutation zuor- an assignment of a jeweili ^¬ gen input of the respective switching stage member will follow ^¬ the switching stage to exactly one output of a switching element of the preceding stage shift stage set;

- wherein a festgeleg ^¬ ter value is set as an initial value of a respective output of the switching stages of the switching stages elements by means of an initialization unit, so that the circuit is held in an unstable state during an active phase of the initialization;

- After completion of the active phase, the circuit occupies a characteristic state for the circuit in response to the Permutationsvorschrift and is detected by means of a detection unit of at least one bit at least one position within the circuit in the characteristic state for generating the identifier.

The invention further relates to a method for generating an identifier for a circuit comprising the steps of: providing a circuit having at least two switching ^stages , the switching stages each comprising at least two switching stage elements, wherein the at least two switching stages are designed such that respective output values at each ^¬ mean outputs of the at least two switching stage elements of a preceding switching stage respective inputs of the at least two switching stage elements of a subsequent switching stage are fed alternatively;

- Applying a challenge by means of a permutation rule, wherein a connection of a respective input of the respective switching stage element of the following switching stage to exactly one output of a switching stage element of the preceding switching stage is determined by the permutation rule;

- Specifying a predetermined value as the output value of a respective output of the switching stage elements of the Schaltstu ^¬ fen for holding an unstable state of the circuit during an active phase; - detecting a response after completion of the active phase, wherein the response is formed from at least one tapped at least one Po ^¬ sition of the circuit in a characteristic state of the circuit and bit depends on the Challenge and characteristic of a specimen of the circuit.

The invention further relates to a computer program product with a computer program, which has means for carrying out the method according to one of the preceding claims, when the computer program is executed on a program-controlled device.

The invention will be explained in more detail by means of exemplary embodiments with the aid of the figures. Show it:

Figure 1 is a schematic representation of a circuit for

Generating an identifier for the circuit according to a first embodiment of the invention;

Figure 2 is a schematic representation of a circuit for

Generating an identifier for the circuit according to a second embodiment of the invention;

Figure 3 is a schematic representation of a circuit for

Generating an identifier for the circuit according to a third embodiment of the invention;

Figure 4 is a schematic representation of a switching stage egg ner circuit according to a fourth embodiment of the invention.

1 shows a circuit 1 is shown, which is a digital integrated circuit at ^¬ play, with four switch circuits 10, 20, 30, 40, each of the four switching stages 10, 20, 30, 40 each consist of two switching stage elements 100, 101, 200, 201, 300, 301, 400, 401.

Each output of the switching stage elements 100, 101 of a preceding switching stage 10 is alternatively supplied to a respective input of all switching stage elements 200, 201 of the subsequent switching stage 20. The circuit is so ^{ausgebil ¬} det that for two switching stage elements in a switching stage, all interconnections are possible, ie both a connection between a first switching stage element 100 of the previous switching stage 10 with the first switching stage element 200 of the subsequent switching stage 20 and with the second switching stage element 201 of subsequent switching stage 20. a depending ^¬ weiliges switching stage element can always be gear connected to an output of a previous shift stage member over only a single. All possible alternative combinations are shown in FIG.

It is also shown schematically how a respective challenge C10, C20, C30, C40 is applied for each switching stage 10, 20, 30, 40. One of the challenges C10, C20, C30, C40 leg ^¬ constitutes as information the permutation, which may in particular einbittig for this embodiment and for both switching stages elements of a switching stage jointly for the shift stage at which the respective Challenge located on ^¬, one at specifies the incoming input. The two combinatorial ways of connecting the two switching stage elements of the two adjacent switching stages can be specified via the challenge. Predetermining the challenge can in particular for all the switching stages 10, 20, 30, 40 analogous ^¬ SUC gene. At least one point within the circuit is a detection unit E provided which detects a logic state value at this point of the circuit. Despite the linear application of the switching stages, all illustrated switching stages within circuit 1 are equivalent. ^Accordingly , the detection unit E can also be usefully installed between all switching stages shown and in all tracks. A track within the circuit is formed by a juxtaposition of shift stage elements of respective successive shift stages. For example, if all challenges CIO, C20, C30, C40 respectively specify to select the upper input illustrated in the drawing, two parallel tracks are formed. Thus, all the shift stage elements of the shift stage depicted in the upper row and in each case all the lower shift stage elements each form one track. The designation of an interconnection as a track or as a signal course within a track is arbitrary, but can be chosen so meaningful, for example, that the shortest signal paths are selected to mark a track. The detection unit E checks whether a stable state of the circuit was adopted, in particular the fact that for a long enough time remains a logical value of the detection unit is present and gives these logi ^¬ rule value as response. The identifier I can be generated from the response. If two bistable rings are formed by the challenge, the respective response is generated in both tracks by the detection unit, at the same or different logical location within the circuit. If the challenge has been selected, ie the configuration of the circuit 1 is made, then the circuit 1 is first put in an unstable state.

The provision of an initialization unit for holding the in ^¬ stable state is shown in Figure 2.

In all figures, functionally identical elements are provided with the same reference numerals, unless stated otherwise.

Figure 2 shows schematically how an interface device is provided with an initialization unit R with interfaces to al ^¬ len switching stage elements of all switching stages. The switching stage elements are, for example, NOR gates or look-up tables or so-called Look-up tables, which implement the logic function of a NOR gate in software.

To set the configuration via respective permutation rules at the switching stages, three challenges were chosen. Specifically, the first Challenge CIO the first switching circuit 10, the second Challenge C20 of the second switching stage 20 and the fourth ^¬ Challenge C40 of the fourth switching ^¬ stage 40 is chosen such that no lane change is carried out by the interconnection. ^By contrast, the third challenge C30, which is present at the third switching stage 30, has been selected such that a permutation occurs between the second switching stage 20 and the third switching stage 30. A signal at the output of the switching stage member 201 of the upper track the input of the switching stage member 300 of the unte ^¬ ren track is accordingly supplied. This assignment causes a long ring of length 2x4, ie 8, arises and that all Schaltstu ^¬ fenelemente the circuit are interconnected within this ring.

For the sake of clarity, only the activated interconnections, that is to say the connections selected via the challenges, are shown in FIG. For the initialization of the circuit 1 is at each

Interface input of each switching stage element to the ini ^¬ tialisierungseinheit R, for example, the value 1 or logical HIGH fixed, so that regardless of the logical value, which is present at the selected via the Permutationsvorschrift input of a switching stage element, always a logical 0 or logic LOW is applied to the output of each switching stage element , The assumption of the logical value 0 is thus enforced by the initialization unit at each point of the scarf ^¬ tion 1, ie between all switching stages and in all tracks or rings.

To derive the response that is associated with the challenge applied via the permutation ^rule , the Interface input of each switching stage element to the initialization unit R set to the value of logic 0. The switching stage elements now each act as inverters and provide the logical negation of the logic value applied to the input selected via the permutation ^rule at its respective output.

After completion of the active phase of initialization in which an unstable state at all positions within the circuit is assumed now turn off all switching stages elements according to their logically negating functiona ^¬ notes, and theoretically the same time. By manufacturing ^¬ related differences from the cycle time of the individual switching stage elements or by temporal variations and delays in the implementation of the logical function using built-look-up tables one of the bistabi ^¬ len states within the ring, which depends on the hardware for the Circuit 1 characteristic tendency towards a bit pattern expression 0101 or 1010, etc. depends. For capturing the bit pattern in time-sequential measurements, an identical position between two inverters should be chosen to ensure comparability. Alternatively, an identical logical position may be useful, ie, for example, a position offset by two inverters compared to the original position, so that the bit pattern appears equal again due to the two intervening negations.

FIG. 3 shows diagrammatically how the number of rings formed can change when an adjacent challenge is changed. In this third embodiment takes place both between the first switching stage 10 and the second switching stage 20 and between the third switching stage 30 and the fourth switching stage 40, a permutation of the tracks. Now the tracks intersect at two points, so that the effect of the track change after the straight ^¬ number of permutations, namely two permutations, is repealed. Thus, a signal at the output of fourth switching stage 40 is potentially fed back to the input of that switching stage element, from which the signal from a previous pass has already been started. With regard to a signal curve, two rings are formed, each of which has an even number of switching stages. In each ring four shift stage elements are included, wel ^¬ che, however, come from different tracks. Accordingly, by applying a logically negated challenge, it can also be achieved that two bistable closed rings exist, with just each switching stage element being supplied with the respective other switching stage element of the adjacent switching stage in comparison to the previous configuration. Thus, by applying various challenges, the affiliation of shift stage elements to tracks or rings and thus the influence of individual shift stage elements in the ^¬ sen rings can be changed. Unique tendencies, which drive the assumption of one of the possible stable states, are suppressed by permuting at different positions within the circuit, for example in different rings.

For clarity, the initialization with the respective was here on a draw ^¬

Interfaces omitted.

Figure 4 schematically shows again a plurality of signal paths may be provided according to a fourth embodiment of the invention within a Schaltstufenele ^¬ mentes which is provided on a further Challenge per switching stage element upstream, which is actively connected to the two or more signal paths. For a switching stage element 100 of the first switching stage 10, it is shown, for example, how two NOR gates or two NOR look-up tables are installed parallel to one another and another or inner Challenge C100 prescribes a selection rule for selecting the signal paths. Similarly, in a further switching stage element 101 of the first switching stage 10 via an inner Chal ^¬ lenge C101 also another variation of the selected Sig- default path. Alternatively, the controllable by the Challenge switching a delay path in one of the switching stage elements is possible and provides a great deal of circuit complexity, a variation of the circuit properties.

The inner challenge C100 or C101 is applied in particular to ei ^¬ nen multiplexer as a control signal which determines which input of the multiplexer is selected, ie which of the two NOR function elements is selected to the signal from this function element path to the output of the switching ^¬ stage element pass.

By combining the outer challenge to determine the permutation with the inner challenge to select parallel alternative paths, an even larger number of challenge-response pairs are created and thus the challenge space is increased again advantageously. Introducing alterna tive ^¬ signal paths which are selected by the inner Challenge as ak ^¬ tively, may be provided for individual switching stages elements or a plurality of switching elements of one stage or more stages of various stages and in particular for all switching stages elements.

The embodiments are limited to variants of the circuit according to the invention, which have a manageable number of switching stages, namely four switching stages, and a small number of switching stage elements per switching stage, namely two switching stage elements. The examples were chosen to ensure readability in the figures. Advantageously, a plurality of switching elements per stage shift stage is provided so that a plurality Moegli ^¬ cher interconnections of shift stages elements of two adjacent switching stages is configurable with one another, namely at a number of switching stages N elements N! possible permutations. In this case, it is also possible to use circuits with an odd number of switching stages, since the configuration of the circuit can be predetermined by means of a suitable permutation rule in such a way that a ring of even numbers The number of switching stage elements is created by interconnecting an even multiple of adjacent tracks. , In a case an odd number of shift stages at ^¬ elements left which can not be closed to form a bistable ring, these can be ignored in the evaluation. Overall, an even number of switching stage elements, taking into account all switching stages, before, the longest constructible ring is always determined by the total number of switching stage elements.

For reasons of readability, the detection unit has been dispensed with in FIGS. 2 to 4. This can be seen superiors in all lanes at a common position within the circuit or for different tracks at different? ^¬ chen positions. Furthermore, the detection unit can be installed in combination with an evaluation circuit which, for example, picks off a bit behind each stage circuit for recognizing the time-stable alternating pattern. Also, the evaluation circuit is preferably provided in all tracks of the circuit, so that regardless of the number of rings formed the appropriate time for reading the response can be detected. Depending on the application the reali ^¬ catalyzed by the circuit physically unklonbare function is used as key storage or authenticity verification. The derived identifier serves, for example, to form a cryptographic key which is stored in a non-readable form on a hardware and can only be generated on this hardware provided for this purpose. For an authenticity check, the identifier may enter into a response which a validator of a device expects from the circuit.

In order to further increase the quality of the response data, in a learning phase, in which challenge-response pairs can be collected, which further for authentication or are used to generate a cryptographic key, such challenges are sorted out, which indicate a strong predistinction of the response. In particular, the time required for the PUF to reach a stable state is measured per challenge. Challenges below a certain threshold will not be used in the future. This ensures that a Respon ^¬ se can not be guessed or not meaningful is recognized as belonging to a challenge.

The functional elements within a switching stage can be chosen arbitrarily be ^¬. If the invention is implemented within a reprogrammable digital module, ie field programmable gate arrays, in short FPGAs, the selection, inversion and reset function can be realized in a particularly favorable manner jointly by so-called look-up tables. Look-up tables can realize any logic functions within the scope of their available input and output signals, since a corresponding output value can be stored in the form of a value table for each possible combination of input signals.

Claims

claims

1. A circuit (1) for generating an identifier (I) for the circuit (1), with

at least two switching stages (10, 20), the switching stages (10, 20) each comprising at least two switching stage ^elements (100, 101, 200, 201),

wherein the at least two switching stages (10, 20) such out forms ^¬ that respective output values of the respective off transitions of the at least two switching stages elements (100, 101) of a preceding switching stage (10), respective inputs of the at least two switching stages elements (200, 201) a follow ^¬ the switching stage (20) can be fed alternatively;

wherein an assignment of a respective input of the respective switching stage element (200, 201) of the following switching stage (20) to exactly one ^{output of} a switching stage element (100, 101) of the preceding switching stage (10 ) is definable;

- an interface device to an initialization unit (R), the initialization unit (R) suitable for specifying a predetermined value as the output value of a respective output of ^{¬ the} output stage elements (100, 101, 200, 201) of the switching stages (10, 20), so that the Circuit (1) is stable in an unstable state during an active phase of the initialization unit;

wherein after termination of the active phase, the circuit is arranged to assume a characteristic of the circuit (1) state in dependence on the Permutationsvor- script;

- at least one detection unit (E) for detecting Minim ^¬ least one bit in at least one position within the circuit,

wherein by detecting the at least one bit within the circuit (1) in the characteristic state using the at least one bit of the identifier (I) can be generated.

2. The circuit (1) according to claim 1, wherein by supplying respective outputs of switching stage elements (200, 201) of a subsequent switching stage (20) to respective inputs of switching ^¬ stage elements (100, 101) of a preceding switching stage (10) at least one bistable closed Ring is constructible.

3. The circuit (1) according to claim 1 or 2, wherein three or more switching stages (10, 20, 30, ...) are provided, whose respective switching stage elements (100, 101, 200, 201, 300, 301, ... ) are each interconnected via the permutation rule according to claim 1, so that at least one bistable closed ring can be constructed.

4. The circuit (1) according to any one of the preceding claims, wherein at least one switching stage element (100) comprises a plurality of signal paths and wherein one of the plurality of signal paths can be activated via a selection rule.

A circuit (1) according to any one of the preceding claims, further comprising a respective detection unit (E) in each of the bistable closed rings constructed by the permutation rule for detecting at least one respective bit, the bit (I) consisting of a plurality of bits of the respective bits. is derivable.

6. The circuit (1) according to any one of the preceding claims, wherein the permutation rule as a challenge (C10, C20) can be predetermined, which determines the assignment for each switching stage element (100, 101) of the switching stage (100).

7. The circuit of claim 6, wherein the at least one bit represents a response in response to the challenge and the response is characteristic of an instance of the circuit.

8. The circuit (1) according to claim 7, wherein the response is single-bit or multi-bit.

9. Circuit (1) according to one of the preceding claims, further comprising a unit for evaluating the response towards ^¬ a stabilization property.

10. The circuit (1) according to claim 9, wherein the unit has a time recording unit, in particular a counter, and / or a selection unit for selecting responses and for forwarding to an output unit.

11. The circuit according to claim 1, further comprising an evaluation circuit for detecting the characteristic state, the evaluation circuit suitable for detecting a temporally stable alternating pattern along the step circuits.

12. A method for generating an identifier for a circuit having at least two switching stages, the switching stages comprising at least two switching stage elements, - wherein respective output values at respective outputs of the at least two switching stage elements of a preceding switching stage respective inputs of the at least two switching ^¬ stage elements of a subsequent switching stage alternatively supplied ^¬ be led;

- wherein by a respective step element switching denbare permutation zuor- an assignment of a jeweili ^¬ gen input of the respective switching stage member will follow ^¬ the switching stage to exactly one output of a Schaltstufenele ^¬ mentes the preceding switching stage set;

- wherein a festgeleg ^¬ ter value is set as an initial value of a respective output of the switching stages of the switching stages elements by means of an initialization unit, so that the circuit is held in an unstable state during an active phase of Initiali ^¬ sierungseinheit; - After terminating the active phase, the circuit occupies a characteristic state of the circuit in dependence on the permutation rule and by means of a detection unit of at least one bit on at least one Position within the circuit in the characteristic state is detected to generate the identifier.

13. A method of generating an identifier for a circuit comprising the steps of:

- Providing a circuit having at least two switching stages, the switching stages comprising at least two switching stage elements, wherein the at least two switching stages are formed such that respective output values at respective outputs of the at least two switching stage elements of a preceding switching stage respective inputs of the at least two switching stage elements of a subsequent switching stage alternatively be supplied;

- Creating a challenge by means of a Permutationsvor- script, wherein the permutation rule an interconnection of a respective input of the respective switching stage element of the following switching stage is set to exactly one output of a switching stage element of the previous switching stage;

- Specifying a predetermined value as the output value of a respective output of the switching stage elements of the Schaltstu ^¬ fen for holding an unstable state of the circuit during an active phase;

- detecting a response after completion of the active phase, WO at the response from at least one tapped at least one Po ^¬ sition of the circuit in a stable state of the circuit bit is formed and is dependent on the Challenge and characteristic of a specimen of the circuit.

14. The method of claim 13, wherein three or more switching stages are provided, the respective switching elements are interconnected stages 13, so that at least one bistable closed ring is configured in each case on the permutation according to ^¬ demanding.

15. Computer program product with a computer program having means for carrying out the method according to one of the preceding claims, when the computer program on a program-controlled device is executed.