WO2016008403A1 - 移动终端的控制装置、控制方法及其移动终端 - Google Patents

移动终端的控制装置、控制方法及其移动终端 Download PDF

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Publication number
WO2016008403A1
WO2016008403A1 PCT/CN2015/083970 CN2015083970W WO2016008403A1 WO 2016008403 A1 WO2016008403 A1 WO 2016008403A1 CN 2015083970 W CN2015083970 W CN 2015083970W WO 2016008403 A1 WO2016008403 A1 WO 2016008403A1
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Prior art keywords
signal
module
mobile terminal
gate
display module
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English (en)
French (fr)
Inventor
兰永城
张胜利
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/72—Mobile telephones; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selection
    • H04M1/725—Cordless telephones

Definitions

  • the present invention relates to the field of mobile communications technologies, and in particular, to a control device, a control method, and a mobile terminal thereof for a mobile terminal.
  • the Liquid Crystal Display Module has always been an important device for mobile terminals, and its working status directly affects the user experience.
  • smart mobile terminals generally adopt large-sized display modules, taking mobile phones as an example.
  • the display screen is usually 4.5'q HD (Quarter High Definition), 5.0' HD (High Definition) display, and the like. Coupled with the ultra-thin design trend of smart mobile terminals, the harsh use environment brings higher requirements for the display module's Electro-Static discharge (ESD) capability.
  • ESD Electro-Static discharge
  • FPC flexible printed circuit board
  • the long pin feet of the FPC make the implementation of the ESD protection of the display module increasingly difficult.
  • the present invention provides a control device, a control method and a mobile terminal of the mobile terminal, which can automatically eliminate the interference of the static electricity on the display module.
  • the present invention provides a control device for a mobile terminal, the mobile terminal comprising a display module, a status register and a processor, the control device comprising a detection module and a response Module
  • a detecting module configured to send an abnormality signal to the response module when detecting that the flag signal of the status register and/or any working status signal of the display module is abnormal;
  • the response module is configured to send a reset signal to the processor when the abnormality signal of the detection module is received, so that the processor resets the display module.
  • the response module is specifically timing
  • the detecting module is specifically a logic control circuit
  • the logic control circuit is configured to send a stop count reset signal to the timer when detecting that the flag signal of the status register and/or any working status signal of the display module is abnormal, so that The timer count overflows;
  • the timer is configured to send a reset signal to the processor after the overflow occurs, so that the processor resets the display module.
  • the working state signals are a line sync signal, a frame sync signal, a gate scan signal, an energy enable signal, a source scan signal, and each internal clock drive. Any of a signal, panel drive signal.
  • the logic control circuit includes an AND gate, and the display module includes a working module that outputs the working state signal;
  • At least one of the working modules is connected in one-to-one correspondence with at least one input end of the AND gate, and a flag signal output end of the status register is connected to another input end of the AND gate, and the output end of the AND gate is connected a reset end of the timer;
  • An output of the timer is coupled to the processor.
  • the logic control circuit includes an OR gate, and the display module includes a working module that outputs the working state signal;
  • At least one of the working modules is connected in one-to-one correspondence with at least one input end of the OR gate, and a flag signal output end of the status register is connected to another input end of the OR gate, and an output end of the OR gate is connected a reset end of the timer;
  • An output of the timer is coupled to the processor.
  • the logic control circuit includes a NAND gate, and the display module includes a working module that outputs the working state signal;
  • At least one of the working modules is connected in one-to-one correspondence with at least one input end of the NAND gate, and a flag signal output end of the status register is connected to another input end of the NAND gate, the NAND gate The output end is connected to the reset end of the timer;
  • An output of the timer is coupled to the processor.
  • the logic control circuit includes a NOR gate, and the display module includes a working module that outputs the working state signal;
  • At least one of the working modules is connected in one-to-one correspondence with at least one input end of the NOR gate, and a flag signal output end of the status register is connected to another input end of the NOR gate, and the NOR gate The output end is connected to the reset end of the timer;
  • An output of the timer is coupled to the processor.
  • the display module includes a driving IC module, and the control device is disposed inside the driving IC module.
  • the present invention further provides a mobile terminal, comprising: a display module, a status register, and a processor, which further includes a mobile terminal according to any one of the foregoing aspects. Control device.
  • the present invention further provides a method for controlling a mobile terminal, where the mobile terminal includes a display module, a status register, and a processor, and the control method includes:
  • a reset signal is sent to the processor to cause the processor to reset the display module.
  • control device the control method and the mobile terminal of the mobile terminal according to the present invention have the following advantages:
  • the detecting module is configured to detect a flag signal of the status register and an operating status signal of the display module, and respond when the flag signal of the status register and/or any working status signal of the display module is abnormal.
  • the module receives the abnormal signal sent by the detecting module, and sends a reset signal to the processor actively, and the processor resets the display module, and can effectively and effectively remove the static interference received by the display module, thereby avoiding the processor actively detecting the display.
  • the operating state of the module occupies system resources and affects system operation efficiency.
  • FIG. 1 is a circuit block diagram of an embodiment of a control apparatus for a mobile terminal according to the present invention
  • FIG. 2 is a timing diagram of a normal operation of a watchdog module in an embodiment of a method for controlling a mobile terminal according to the present invention
  • FIG. 3 is a timing chart when the operating state signal is abnormal in the embodiment corresponding to FIG. 2;
  • FIG. 4 is a timing chart when the flag signal is abnormal in the embodiment corresponding to FIG. 2;
  • FIG. 5 is a circuit block diagram of another embodiment of a control apparatus for a mobile terminal according to the present invention.
  • FIG. 6 is a timing diagram of a normal operation of a monitoring module in a control method corresponding to the control device of FIG. 5;
  • Fig. 7 is a timing chart showing a case where the line synchronizing signal is abnormal and the pixel clock signal is normal in the operating state signal in the control method corresponding to the control device of Fig. 5.
  • FIG. 1 is a schematic diagram of an embodiment of a control device for a mobile terminal according to the present invention.
  • the mobile terminal includes a display module, a status register, and a processor 2, and the control device includes a detection module and a response module.
  • a detecting module configured to send an abnormality signal to the response module when detecting that the flag signal of the status register and/or any working status signal of the display module is abnormal;
  • the response module is configured to send a reset signal to the processor 2 when the abnormality signal of the detection module is received, so that the processor 2 resets the display module.
  • the display module includes a driving IC module, and the working state signal output by the driving IC module is a frame synchronization signal.
  • the control device comprises a monitoring module 1 which is arranged inside the driving IC module.
  • the monitoring module 1 comprises a timer 12 and a logic control circuit.
  • the response module is specifically the timer 12 of the monitoring module 1
  • the detection module is specifically the logic control circuit of the monitoring module 1 .
  • the working state signal detected by the detecting module is preferably a frame synchronization signal.
  • the monitoring module is disposed inside the driving IC module, on the one hand, the circuit board arrangement space can be saved, and on the other hand, the frame synchronization signal inside the driving IC module can be directly outputted to the monitoring module, and the circuit is optimized. Layout while avoiding external interference due to circuit extraction.
  • the logic control circuit is configured to send a stop count reset signal to the timer 12 when detecting that the flag signal of the status register and/or any working status signal of the display module is abnormal, so that The timer count overflows;
  • the timer is configured to send a reset signal to the processor 2 after the count overflows, so that the processor 2 resets the display module.
  • the logic control circuit collects the working state signal of the display module and the flag signal of the status register in real time, and outputs a reset signal to the timer after the logic judgment, and when the display module is abnormal, the working state signal level An abnormality or a level inversion of the identification signal occurs, the logic control circuit outputs a stop count reset signal, and the timer value of the timer 12 overflows the preset value due to the inability to reset, so that the level of the timer 12 output is inverted.
  • the processor 2 detects that the level of the timer 12 is reversed, the processor 2 performs a forced reset operation on the display module.
  • the detection process of the static electricity of the invention is automatic detection, and when the display module is abnormal, the timer 12 actively issues a reset signal.
  • the detection process of the static electricity of the invention is automatic detection, and when the display module is abnormal, the timer 12 actively issues a reset signal.
  • the processor does not need to allocate resources separately to actively detect the state of the display module, and the implementation method is simple, and does not occupy processor resources.
  • the logic control circuit includes an AND gate 11, the AND gate 11 includes two input terminals, and the display module includes a working module that outputs the working state signal;
  • One of the working modules is connected to an input end of the AND gate 11, the flag signal output end of the status register is connected to another input end of the AND gate 11, and the output end of the AND gate 11 is connected a reset end of the timer 12, the reset end is configured to receive the stop count reset signal;
  • the output of the timer 12 is connected to the processor 2.
  • the working state signal may be any one of a line sync signal, a frame sync signal, a gate scan signal, an exercise energy signal, a source scan signal, each internal clock drive signal, and a panel drive signal.
  • the working module may be a driving IC module such as an output frame synchronization signal.
  • the timer further includes a working control end, and when the working control end of the timer receives the working signal, the timer enters a working state.
  • the mobile terminal includes a display module, a status register, and a processor 2, and further includes the control device of the mobile terminal described above.
  • the mobile terminal The display module, the status register and the processor 2 are included, and the control method includes:
  • a reset signal is sent to the processor 2 to cause the processor 2 to reset the display module.
  • the working state signal is any one of a line synchronization signal, a frame synchronization signal, a gate scan signal, an exercise energy signal, a source scan signal, each internal clock drive signal, and a panel drive signal.
  • the timer 12 further includes a working control end. When the working control end of the timer 12 receives the working signal, the timer enters an active state.
  • the logic control circuit is an AND gate having two input ends, and the working state signal and the flag signal are input in one-to-one correspondence with the input terminals of the gate, and the stop counting reset signal is output by the AND gate output terminal.
  • the A signal is used to represent a certain working state signal, which exhibits a continuous high and low level alternating during normal operation
  • the B signal is used to represent the flag signal during normal operation.
  • the continuous high level is presented, and the reset signal is represented by RESET.
  • the signal is determined by the AND signal logic operation of the A signal and the B signal, and the EN signal is used to represent the working signal input to the timer working control terminal.
  • the EN signal is continuously high level, and the Y signal is used to represent the timer output level. When the display module is working normally, the timer outputs a high level.
  • the flag signal is abnormal, that is, the B signal is inverted from the high level to the low level
  • RESET is continuously operated low by the AND gate logic operation, and the timer overflows due to receiving the stop count reset signal signal.
  • the Y signal has a flipping process from high level to low level, and the processor resets the display module.
  • the A signal exhibits a continuous low power in the latter stage due to an abnormal operating signal. Ping, RESET and the gate logic operation to obtain a continuous low level, the timer can not be received by the count reset signal, it can be regarded as accepting the stop count reset signal signal and overflow, the Y signal appears from high level to low level During the flipping process, the processor resets the display module.
  • the logic control circuit may be an OR gate, and an input of the working module and the OR gate of the display module End connection, the flag signal output end of the status register is connected to another input end of the OR gate, the output end of the OR gate is connected to the reset end of the timer; Stop counting the reset signal; the output of the timer is coupled to the processor.
  • the OR gate When the OR gate receives the working state signal and the flag signal are both at a low level, determining that the working state signal and the flag signal are abnormal, and the processor performs a reset action on the display module.
  • the logic control circuit may be a NAND gate, and one of the working modules of the display module and the NAND gate An input terminal is connected, a flag signal output end of the status register is connected to another input end of the NAND gate, and an output end of the NAND gate is connected to a reset end of the timer; And configured to receive the stop count reset signal; an output of the timer is coupled to the processor.
  • the NAND gate When the NAND gate receives the working state signal and the flag signal are both at a high level, determining that the working state signal and the flag signal are abnormal, and the processor performs a resetting operation on the display module.
  • the logic control circuit may be a NOR gate, and one of the working modules of the display module and the NOR gate An input terminal is connected, a flag signal output end of the status register is connected to another input end of the NOR gate, and an output end of the NOR gate is connected to a reset end of the timer; And configured to receive the stop count reset signal; an output of the timer is coupled to the processor.
  • the monitoring module determines that the working state signal and the flag signal are abnormal, and the processor performs a resetting operation on the display module.
  • FIG. 5 is another embodiment of a control apparatus for a mobile terminal according to the present invention.
  • the display module outputs two operational status signals to the AND gate 11, such as an A signal characterizing the line sync signal and a C signal characterizing the pixel clock signal; the B signal is identical to the first embodiment and still characterizes the flag signal.
  • the working principle of the forced reset operation on the display module is the same as that in the first embodiment. The difference is that the high level is output only when the A signal, the B signal, and the C signal are different.
  • the monitoring module determines that the working state signal and the flag signal are abnormal, and the processor resets the display module.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).
  • the logic control circuit is not limited to the AND gate, and may further include one or a combination of an OR gate, a NOT gate, a NAND gate, and a NOT gate, and the operation state signals are a line synchronization signal, a frame synchronization signal, a gate scan signal, Any one of the energy signal, the source scan signal, the internal clock drive signal, and the panel drive signal, any control signal that can characterize the state of the current display module can be used as the working state signal. Any technical deduction or substitution made with the method, structure, etc. of the present invention, or similar to the inventive concept, should be regarded as the scope of protection of the present invention.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Debugging And Monitoring (AREA)
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Abstract

本发明涉及移动通信技术领域，尤其涉及一种移动终端的控制装置、控制方法及其移动终端。移动终端的控制装置，所述移动终端包括显示模组、状态寄存器和处理器，所述控制装置包括检测模块和响应模块；检测模块，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述响应模块发送异常信号；响应模块，用于接收到所述检测模块的所述异常信号时，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。本发明实施例还提供了一种移动终端的控制方法及移动终端，采用本发明实施例可自动消除静电对显示模组的干扰。

Description

移动终端的控制装置、控制方法及其移动终端
相关申请的交叉引用
本申请主张在2014年7月16日在中国提交的中国专利申请号No.201410338790.4的优先权，其全部内容通过引用包含于此。
技术领域
本发明涉及移动通信技术领域，尤其涉及一种移动终端的控制装置、控制方法及其移动终端。
背景技术
显示模组(Liquid Crystal Display Module，LCM)一直是移动终端的重要设备，其工作的状态直接影响到用户的使用体验；目前智能移动终端开始普遍采用大尺寸的显示模组，以手机为例，其显示屏通常为4.5’qHD(Quarter High Definition)、5.0’HD(High Definition)显示屏等。加上智能移动终端的超薄设计趋势，恶劣的使用环境给显示模组抗静电(Electro-Static discharge，ESD)能力带来更高的要求。然而，显示模组的印刷电路板(Flexible Printed Circuit board，FPC)的排布空间受限，以及FPC的较长的pin脚等因素，使得对显示模组的抗ESD保护的实现日益困难。
发明内容
为了解决移动终端显示模组受静电干扰显示异常的技术问题，本发明提供一种移动终端的控制装置、控制方法及其移动终端，可自动消除静电对显示模组的干扰。
第一方面，作为本发明的第一种实施方案，本发明提供了一种移动终端的控制装置，所述移动终端包括显示模组、状态寄存器和处理器，所述控制装置包括检测模块和响应模块；
检测模块，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述响应模块发送异常信号；
响应模块，用于接收到所述检测模块的所述异常信号时，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
结合第一种实施方案，作为第二种实施方案，所述响应模块具体为定时 器，所述检测模块具体为逻辑控制电路；
所述逻辑控制电路，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述定时器发送停止计数复位信号，以使所述定时器计数溢出；
所述定时器，用于在计数溢出后，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
结合第二种实施方案，作为第三种实施方案，所述工作状态信号为行同步信号、帧同步信号、栅(gate)扫描信号、行使能信号、源(source)扫描信号、各内部时钟驱动信号、面板(panel)驱动信号中的任一项。
结合第三种实施方案，作为第四种实施方案，所述逻辑控制电路包括与门，所述显示模组包括输出所述工作状态信号的工作模块；
至少一所述工作模块与所述与门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述与门的另一输入端连接，所述与门的输出端连接所述定时器的重置端；
所述定时器的输出端连接所述处理器。
结合第三种实施方案，作为第五种实施方案，所述逻辑控制电路包括或门，所述显示模组包括输出所述工作状态信号的工作模块；
至少一所述工作模块与所述或门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述或门的另一输入端连接，所述或门的输出端连接所述定时器的重置端；
所述定时器的输出端连接所述处理器。
结合第三种实施方案，作为第六种实施方案，所述逻辑控制电路包括与非门，所述显示模组包括输出所述工作状态信号的工作模块；
至少一所述工作模块与所述与非门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述与非门的另一输入端连接，所述与非门的输出端连接所述定时器的重置端；
所述定时器的输出端连接所述处理器。
结合第三种实施方案，作为第七种实施方案，所述逻辑控制电路包括或非门，所述显示模组包括输出所述工作状态信号的工作模块；
至少一所述工作模块与所述或非门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述或非门的另一输入端连接，所述或非门的输出端连接所述定时器的重置端；
所述定时器的输出端连接所述处理器。
结合第一至七中任一种实施方案，作为第八种实施方案，所述显示模组包括一驱动IC模块，所述控制装置设于驱动IC模块内部。
第二方面，本发明还提供了一种移动终端，所述移动终端包括显示模组、状态寄存器和处理器，它还包括上述第一方面中任一种实施方案所述的一种移动终端的控制装置。
第三方面，本发明还提供了一种移动终端的控制方法，所述移动终端包括显示模组、状态寄存器和处理器，所述控制方法包括：
检测所述显示模组的工作状态信号和所述状态寄存器的标识信号是否有异常；
在检测到所述标识信号异常时和/或任一所述工作状态信号异常时，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
本发明所述的一种移动终端的控制装置、控制方法及其移动终端具有如下优点：
所述检测模块用于对状态寄存器的标志信号和显示模组的工作状态信号进行检测，当所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，响应模块接收到检测模块发出的异常信号，并主动向处理器发送复位信号，处理器对显示模组复位，能有及时有效的清除显示模组受到的静电干扰，避免因处理器主动检测所述显示模组的运行状态而占用系统资源，影响系统运行效率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明所述移动终端的控制装置的一个实施例的电路原理框图；
图2是本发明所述移动终端的控制方法的一个实施例中监视(watchdog)模块正常工作的时序图；
图3是图2对应的实施例中工作状态信号异常时的时序图；
图4是图2对应的实施例中标志信号异常时的时序图；
图5是本发明所述移动终端的控制装置的另一个实施例的电路原理框图；
图6是图5所述控制装置对应的控制方法中监视模块正常工作的时序图；
图7是图5所述控制装置对应的控制方法中工作状态信号中行同步信号异常而像素时钟信号正常时的时序图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示为本发明所述一种移动终端的控制装置的一个实施例，所述移动终端包括显示模组、状态寄存器和处理器2，所述控制装置包括检测模块和响应模块；
检测模块，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述响应模块发送异常信号；
响应模块，用于接收到所述检测模块的所述异常信号时，向所述处理器2发送复位信号，以使所述处理器2对所述显示模组复位。
在本实施例中，所述显示模组包括一驱动IC模块，驱动IC模块输出的工作状态信号为帧同步信号。所述控制装置包括一监视模块1，所述监视模块1设于驱动IC模块内部，所述监视模块1包括定时器12和逻辑控制电路。所述响应模块具体为监视模块1的所述定时器12，所述检测模块具体为监视模块1的所述逻辑控制电路。
其中，检测模块检测的工作状态信号优选帧同步信号。此时将所述监视模块设于驱动IC模块内部，一方面可以节省电路板排布空间，另一方面可以将所述驱动IC模块内部的帧同步信号在其内直接输出至监视模块，优化电路布局，同时避免电路引出而受到外部干扰。
所述逻辑控制电路，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述定时器12发送停止计数复位信号，以使所述定时器计数溢出；
所述定时器，用于在计数溢出后，向所述处理器2发送复位信号，以使所述处理器2对所述显示模组复位。
所述逻辑控制电路实时采集显示模组的工作状态信号和状态寄存器的标志信号，并经过逻辑判断后向定时器输出计数复位信号，当判断显示模组异常时，所述工作状态信号的电平出现异常或标识信号的电平翻转，所述逻辑控制电路输出停止计数复位信号，定时器12的计时数值因无法重置而溢出预设值，使得定时器12输出的电平翻转。处理器2在检测到定时器12的电平翻转时，对显示模组进行强制复位操作。本发明对静电的检测过程为自动检测，当显示模组异常时，定时器12主动发出复位信号。
本发明对静电的检测过程为自动检测，当显示模组异常时，定时器12主动发出复位信号。不需要处理器单独分配资源对显示模组的状态进行主动检测，实现方法简单，不占用处理器资源。
所述逻辑控制电路包括与门11，所述与门11包括两个输入端，所述显示模组包括输出所述工作状态信号的工作模块；
其中一所述工作模块与所述与门11的一输入端连接，所述状态寄存器的标志信号输出端与所述与门11的另一输入端连接，所述与门11的输出端连接所述定时器12的重置端，所述重置端用于接收所述停止计数复位信号；
所述定时器12的输出端连接所述处理器2。
其中，工作状态信号可以为行同步信号、帧同步信号、栅(gate)扫描信号、行使能信号、源(source)扫描信号、各内部时钟驱动信号、面板(panel)驱动信号中的任一项。工作模块可以是如输出帧同步信号的驱动IC模块。
所述定时器还包括一工作控制端，当定时器的工作控制端接收到工作信号时，定时器进入工作状态。
作为本发明所述一种移动终端的一个实施例，所述移动终端包括显示模组、状态寄存器和处理器2，还包括上述所述的移动终端的控制装置。
作为本发明所述一种移动终端的控制方法的一个实施例，所述移动终端 包括显示模组、状态寄存器和处理器2，所述控制方法包括：
检测所述显示模组的工作状态信号和所述状态寄存器的标识信号是否有异常；
在检测到所述标识信号异常时和/或任一所述工作状态信号异常时，向所述处理器2发送复位信号，以使所述处理器2对所述显示模组复位。
所述方法中，所述工作状态信号为行同步信号、帧同步信号、栅扫描信号、行使能信号、源扫描信号、各内部时钟驱动信号、面板驱动信号中的任一项。
所述定时器12还包括一工作控制端，当定时器12的工作控制端接收到工作信号时，定时器进入工作状态。
在本方法实施例中，所述逻辑控制电路为具有两个输入端的与门，所述工作状态信号和标志信号由与门输入端一一对应输入，停止计数复位信号由与门输出端输出。
如图2、图3、图4所示，用A信号表征某一工作状态信号，其在正常工作时呈现持续性的高、低电平交替，用B信号表征标志信号，其在正常工作时呈现持续性高电平，用RESET表征计数复位信号，其信号由A信号和B信号通过与门逻辑运算决定，用EN信号表征输入到定时器工作控制端的工作信号，在定时器工作时，所述EN信号呈现持续性高电平，用Y信号表征定时器输出电平，显示模组正常工作时定时器输出高电平。
如图2所示，由于显示模组工作正常，RESET持续表现为与A信号相同的高、低电平交替，故逻辑控制电路(此实施例中为与门)持续输出计数复位信号(当RESET为高电平时输出)，计时器中的计时数值持续重置，计时器不会溢出，从而Y信号始终表现为高电平，不呈现电平翻转，处理器不对显示模组进行复位动作。
如图3所示，由于标志信号异常，即B信号从高电平翻转到低电平，RESET经与门逻辑运算得到持续的低电平，计时器由于接受到停止计数复位信号信号而溢出，Y信号出现由高电平到低电平的翻转过程，处理器对显示模组进行复位动作。
如图4所示，由于工作状态信号异常，A信号在后段呈现出持续的低电 平，RESET经与门逻辑运算得到持续的低电平，计时器由于无法接收到计数复位信号，即可视为接受到停止计数复位信号信号而溢出，Y信号出现由高电平到低电平的翻转过程，处理器对显示模组进行复位动作。
作为本发明所述一种移动终端的控制方法的另一种实现方式，所述逻辑控制电路可以为一或门，所述显示模组的其中一所述工作模块与所述或门的一输入端连接，所述状态寄存器的标志信号输出端与所述或门的另一输入端连接，所述或门的输出端连接所述定时器的重置端；所述重置端用于接收所述停止计数复位信号；所述定时器的输出端连接所述处理器。
当所述或门接收到所述工作状态信号和所述标志信号均为持续低电平时，判断所述工作状态信号和所述标志信号异常，处理器对显示模组进行复位动作。
作为本发明所述一种移动终端的控制方法的另一种实现方式，所述逻辑控制电路可以为一与非门，所述显示模组的其中一所述工作模块与所述与非门的一输入端连接，所述状态寄存器的标志信号输出端与所述与非门的另一输入端连接，所述与非门的输出端连接所述定时器的重置端；所述重置端用于接收所述停止计数复位信号；所述定时器的输出端连接所述处理器。
当所述与非门接收到所述工作状态信号和所述标志信号均为持续高电平时，判断所述工作状态信号和所述标志信号异常，处理器对显示模组进行复位动作。
作为本发明所述一种移动终端的控制方法的另一种实现方式，所述逻辑控制电路可以为一或非门，所述显示模组的其中一所述工作模块与所述或非门的一输入端连接，所述状态寄存器的标志信号输出端与所述或非门的另一输入端连接，所述或非门的输出端连接所述定时器的重置端；所述重置端用于接收所述停止计数复位信号；所述定时器的输出端连接所述处理器。
当所述工作状态信号和所述标志信号不同时输出低电平并持续一定时间后，监视模块判断所述工作状态信号和所述标志信号异常，处理器对显示模组进行复位动作。
如图5所示为本发明所述一种移动终端的控制装置的另一个实施例，如图5所示，与本发明所述一种移动终端的控制装置的前述实施例不同的是， 所述显示模组输出两个工作状态信号至与门11，例如表征行同步信号的A信号和表征像素时钟信号的C信号；B信号与实施例一相同，仍表征标志信号。
如图6和图7所示，其对显示模组进行强制复位操作工作原理与实施例一中的方法相同，不同的是，仅当A信号、B信号、C信号不同时输出高电平并持续一定时间时，监视模块才判断所述工作状态信号和所述标志信号异常，处理器对显示模组进行复位动作。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(RandomAccess Memory，RAM)等。
如上所述是结合具体内容提供的多种实施方式，并不认定本发明的具体实施只局限于这些说明。如所述逻辑控制电路不仅限于与门，还可包括或门、非门、与非门、或非门之一或其组合等，工作状态信号为行同步信号、帧同步信号、栅扫描信号、行使能信号、源扫描信号、各内部时钟驱动信号、面板驱动信号中的任一项，任何能表征当前显示模组状态的控制信号均可作为工作状态信号等。凡与本发明方法、结构等近似、雷同，或是对于发明构思前提下做出若干技术推演或替换，都应当视为本发明的保护范围。

Claims (10)

  1. 一种移动终端的控制装置，所述移动终端包括显示模组、状态寄存器和处理器，其中，所述控制装置包括检测模块和响应模块；
    检测模块，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述响应模块发送异常信号；
    响应模块，用于接收到所述检测模块的所述异常信号时，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
  2. 如权利要求1所述的移动终端的控制装置，其中，所述响应模块具体为定时器，所述检测模块具体为逻辑控制电路；
    所述逻辑控制电路，用于在检测到所述状态寄存器的标志信号和/或所述显示模组的任一工作状态信号有异常时，向所述定时器发送停止计数复位信号，以使所述定时器计数溢出；
    所述定时器，用于在计数溢出后，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
  3. 如权利要求2所述所述的移动终端的控制装置，其中，所述工作状态信号为行同步信号、帧同步信号、栅扫描信号、行使能信号、源扫描信号、各内部时钟驱动信号、面板驱动信号中的任一项。
  4. 如权利要求3所述的移动终端的控制装置，其中，所述逻辑控制电路包括与门，所述显示模组包括输出所述工作状态信号的工作模块；
    至少一所述工作模块与所述与门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述与门的另一输入端连接，所述与门的输出端连接所述定时器的重置端；
    所述定时器的输出端连接所述处理器。
  5. 如权利要求3所述的移动终端的控制装置，其中，所述逻辑控制电路包括或门，所述显示模组包括输出所述工作状态信号的工作模块；
    至少一所述工作模块与所述或门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述或门的另一输入端连接，所述或门的输出端连接所述定时器的重置端；
    所述定时器的输出端连接所述处理器。
  6. 如权利要求3所述的移动终端的控制装置，其中，所述逻辑控制电路包括与非门，所述显示模组包括输出所述工作状态信号的工作模块；
    至少一所述工作模块与所述与非门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述与非门的另一输入端连接，所述与非门的输出端连接所述定时器的重置端；
    所述定时器的输出端连接所述处理器。
  7. 如权利要求3所述的移动终端的控制装置，其中，所述逻辑控制电路包括或非门，所述显示模组包括输出所述工作状态信号的工作模块；
    至少一所述工作模块与所述或非门的至少一输入端一一对应连接，所述状态寄存器的标志信号输出端与所述或非门的另一输入端连接，所述或非门的输出端连接所述定时器的重置端；
    所述定时器的输出端连接所述处理器。
  8. 如权利要求1至7之一所述的移动终端的控制装置，其中，所述显示模组包括一驱动IC模块，所述控制装置设于驱动IC模块内部。
  9. 一种移动终端，所述移动终端包括显示模组、状态寄存器和处理器，其中，还包括如权利要求1-8任一项所述的移动终端的控制装置。
  10. 一种移动终端的控制方法，所述移动终端包括显示模组、状态寄存器和处理器，其中，所述控制方法包括：
    检测所述显示模组的工作状态信号和所述状态寄存器的标识信号是否有异常；
    在检测到所述标识信号异常时和/或任一所述工作状态信号异常时，向所述处理器发送复位信号，以使所述处理器对所述显示模组复位。
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