WO2016002380A1 - Storage device, information processing system, and method for controlling storage device - Google Patents

Abstract

The purpose of the present invention is to store control codes for controlling a non-volatile memory in the non-volatile memory and to improve the storage reliability thereof. A control code memory stores the control codes for controlling the non-volatile memory. A reading control unit reads the control codes from the control code memory prior to the operation of the non-volatile memory. An error correction unit corrects an error in the read control codes. A working memory holds the error-corrected control codes. A control unit controls the non-volatile memory on the basis of the control codes held in the working memory and outputs a command to request that the control code memory be rewritten with the control codes held in the working memory. A refresh control unit carries out the rewriting on the basis of the control code rewriting request command.

Description

Storage device, information processing system, and storage device control method

The present technology relates to a storage device, an information processing system, and a storage device control method. Specifically, the present invention relates to a storage device, an information processing system, and a storage device control method for storing startup data in a nonvolatile memory and correcting an error of the startup data.

In order to use non-volatile memory such as NAND flash memory and ReRAM (resistance random access memory), a control code for operating the built-in control circuit is required. High reliability is required for storing the control code, and an OTP (one-time programming) memory using an antifuse arranged in the nonvolatile memory is used. However, as the nonvolatile memory capacity increases, the capacity of the control code also increases, and a large-capacity OTP memory is required. Since the OTP memory has a larger cell area per capacity than a memory cell of a nonvolatile memory, for example, ReRAM, an increase in the capacity of the OTP memory leads to an increase in the size of the nonvolatile memory chip.

An area for storing the control code is provided in the memory cell of the nonvolatile memory, and the OTP memory described above becomes unnecessary by storing the control code therein. On the other hand, ReRAM, which is a nonvolatile memory, has a problem that a bit error occurs and the reliability of data storage is lower than that of an OTP memory. Adding complicated ECC processing to increase the reliability of storage causes problems such as an increase in cost and an increase in startup time.

On the other hand, a memory system has been proposed in which a plurality of control codes are stored in a non-volatile memory, and when the control codes are read, a majority operation is performed for each bit of these control codes to correct the control code error. (For example, refer to Patent Document 1). Since the majority decision operation has a small circuit size and operates at a high speed, an increase in cost and an increase in start-up time can be avoided.

JP 2010-225259 A

In the above-described prior art, even if a control code error occurs, error correction is possible by majority operation. However, no measures are taken to prevent the accumulation of errors, and if a large number of errors are accumulated, there is a risk that the correction of the errors may be impossible.

The present technology has been created in view of such a situation, and an object thereof is to improve the storage reliability of the control code by rewriting the control code in which the error is corrected in the nonvolatile memory as the storage location.

The present technology has been made to solve the above-described problems. The first aspect of the present technology is a control code memory for storing a control code for controlling the nonvolatile memory, and before the operation of the nonvolatile memory. A read control unit that reads the control code from the control code memory, an error correction unit that performs error correction of the read control code, a working memory that holds the control code in which the error is corrected, and the working memory A control unit that controls the nonvolatile memory based on the control code held in the memory and outputs an instruction for requesting the control code memory to rewrite the control code held in the working memory; and And a refresh control unit that performs the above rewriting based on the storage device. As a result, the corrected control code is rewritten in the control code memory.

Further, in the first aspect, a deterioration state detection unit that detects a deterioration state indicating the necessity of rewriting the control code, and control code deterioration information that holds the detected deterioration state as control code deterioration information A holding unit, and the control unit may output the instruction based on the control code deterioration information. Thereby, the deterioration state of the control code is detected, and rewriting is performed based on this.

In the first aspect, the deterioration state detection unit may detect the deterioration state by detecting that the error correction has occurred in the error correction unit. This brings about the effect of detecting the deterioration of the control code by detecting the error occurrence of the control code.

In the first aspect, the memory device further includes a counting unit that counts the number of times the power is turned on or off in the memory, and the deterioration state detecting unit is configured such that the number of times counted by the counting unit reaches a predetermined number. Therefore, the deterioration state may be detected. This brings about the effect of detecting the deterioration of the control code by detecting that the number of times of turning on or off the power has reached a predetermined number.

In this first aspect, the control unit may read the held control code deterioration information and output the instruction based on the read control code deterioration information. As a result, the control unit reads out the control code deterioration information and outputs an instruction to rewrite the control code.

In addition, in the first aspect, a control code deterioration information supply unit that supplies the control code deterioration information to the memory controller is further provided, and the control unit is configured to perform the control based on the supplied control code deterioration information. The instruction may be output based on a request for rewriting issued from the memory controller. As a result, the control code is rewritten via the memory controller.

In the first aspect, the control code memory further includes a parity generation unit that generates a parity for correcting an error in the control code, and the control code memory further includes an area for storing the parity. The unit may perform the error correction using the parity, and the refresh control unit may rewrite the corresponding parity in the code memory together with the control code in which the error is corrected. This brings about the effect that the error of the control code is corrected using the parity.

Further, in this first aspect, the control code memory stores the control code in a plurality of areas, and the error correction unit detects that the corresponding values in the plurality of control codes do not match. The error correction may be performed by correcting the bit. As a result, an error is corrected by a plurality of control codes.

In this first aspect, the error correction unit may perform the error correction by performing a majority operation on the mismatched bits to correct the mismatched bits. As a result, the error of the control code is corrected by the majority operation.

In the first aspect, the error correction unit may perform the error correction by performing a logical sum operation on the mismatched bits to correct the mismatched bits. This brings about the effect that the error of the control code is corrected by the logical sum operation.

Further, according to the first aspect, a control code memory for storing a control code for controlling the nonvolatile memory, a read control unit for reading the control code from the control code memory before the operation of the nonvolatile memory, and the reading An error correction unit that performs error correction of the control code, a working memory that holds the control code in which the error is corrected, and the necessity to rewrite the control code held in the working memory in the control code memory. A deterioration state detection unit that detects the deterioration state indicated, a control code deterioration information holding unit that holds the detected deterioration state as control code deterioration information, and a control code that supplies the control code deterioration information to the memory controller Request the rewriting based on the deterioration information supply unit and the supplied control code deterioration information A memory controller that issues a quest, and a control unit that controls the nonvolatile memory based on the control code held in the working memory and outputs an instruction to request the rewrite based on the issued request. And a refresh control unit that performs the rewriting based on the instruction. As a result, the control code is rewritten via the memory controller.

A second aspect of the present technology includes a control code memory that stores a control code for controlling the nonvolatile memory, a read control unit that reads the control code from the control code memory before the nonvolatile memory is operated, An error correction unit that performs error correction of the read control code, a working memory that holds the control code in which the error is corrected, and the control code held in the working memory needs to be rewritten in the control code memory A deterioration state detection unit that detects a deterioration state that indicates the characteristics, a control code deterioration information holding unit that holds the detected deterioration state as control code deterioration information, and supplies the control code deterioration information to the memory controller A control code deterioration information supply unit and a request for rewriting based on the supplied control code deterioration information. A memory controller that issues an est; a control unit that controls the nonvolatile memory based on the control code held in the working memory and outputs an instruction to request the rewrite based on the issued request; An information processing system comprising: a storage device including a refresh control unit that performs the rewriting based on the instruction; and a host computer that accesses the storage device via the memory controller. As a result, the control code is rewritten via the memory controller.

In addition, according to a third aspect of the present technology, a read procedure for reading a control code for controlling the nonvolatile memory from the control code memory before the operation of the nonvolatile memory, and an error correction for correcting the error of the read control code are performed. A control procedure for controlling the nonvolatile memory based on the control code in which the error is corrected, and outputting an instruction for requesting the control code memory to rewrite the control code in which the error is corrected; And a refresh control procedure for performing the rewriting based on the instruction. The control code is rewritten.

According to the present technology, the control code can be stored in the non-volatile memory, and an excellent effect of increasing the storage reliability can be obtained. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure showing an example of composition of an information processing system in an embodiment of this art. It is a figure showing an example of a functional block of a storage unit in a 1st embodiment of this art. It is a figure showing an example of composition of a memory in a 1st embodiment of this art. It is a figure showing an example of data arrangement of a control code memory in a 1st embodiment of this art. It is a figure showing an example of a processing procedure of power-on processing in a 1st embodiment of this art. It is a figure showing an example of a processing procedure of memory starting processing in a 1st embodiment of this art. It is a figure which shows an example of the process sequence of the reading of the control code in 1st Embodiment of this technique, and an error correction process. It is a figure showing an example of a processing procedure of control code reading processing in a 1st embodiment of this art. It is a figure which shows an example of the process sequence of the control code rewriting process in 1st Embodiment of this technique. It is a figure showing an example of a processing procedure of read-out of a control code and error correction processing in a modification of the first embodiment of the present technology. It is a figure showing an example of composition of a memory in a 2nd embodiment of this art. It is a figure explaining OR operation in a 2nd embodiment of this art. It is a figure which shows an example of the process sequence of the reading of the control code in 2nd Embodiment of this technique, and an error correction process. It is a figure showing the example of composition of the memory in a 3rd embodiment of this art. It is a figure showing an example of a processing procedure of power-on processing in a 4th embodiment of this art. It is a figure showing an example of a processing procedure of control code rewriting processing in a 4th embodiment of this art. It is a figure showing an example of a functional block diagram of a storage unit in a 5th embodiment of this art. It is a figure showing an example of a processing procedure of control part starting processing in a 5th embodiment of this art.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First embodiment (an example of performing ECC encoding and majority operation)
2. Second embodiment (example of performing logical sum operation)
3. Third Embodiment (Example in which deterioration of control code is determined based on the number of times power is turned on or off)
4). Fourth Embodiment (Example in which a memory controller issues a request for rewriting)
5. Fifth embodiment (an example of rewriting without a memory controller)

<1. First Embodiment>
[Example of ECC encoding and majority operation]
FIG. 1 is a diagram illustrating a configuration example of an information processing system according to an embodiment of the present technology. The information processing system according to the embodiment of the present technology includes a host computer 100 and a storage device 200. The host computer 100 writes data to or reads data from the storage device 200. The host computer 100 writes and reads data by outputting a command requesting writing or reading to the storage device 200.

The storage device 200 stores data. The storage device 200 includes a memory controller 210, a power control unit 201, and a memory 220. The memory controller 210 interprets a command output from the host computer 100 and controls the memory 220 based on the command. This control is performed by issuing a request to the memory 220. The memory controller 210 also exchanges data with the host computer 100. The memory controller 210 includes an ECC processing unit 211. The ECC processing unit 211 performs encoding that adds a parity to data output from the host computer 100 to form an ECC code, and decoding that extracts the original data from the ECC code. During this decoding, data error correction is performed. The power control unit 201 controls on / off of power supplied to the memory 220. The power controller 201 is controlled by the memory controller 210.

The memory 220 stores data transferred from the host computer 100 via the memory controller 210. The memory 220 includes a control unit 221 and a memory cell array 270. The control unit 221 controls the entire memory 220. The memory cell array 270 includes memory cells configured by a non-volatile memory arranged two-dimensionally and is a main data storage unit. As the nonvolatile memory, for example, ReRAM can be used. In addition, the memory 220 includes a circuit for driving the memory cell array 270. Details of these will be described later.

The memory cell array 270 includes a control code memory 280. That is, a part of the memory cell group constituting the memory cell array 270 is allocated as the control code memory 280. The control code memory 280 stores control codes. The first example of the control code is firmware for controlling the memory cell array 270 that is a nonvolatile memory. More specifically, it is firmware for operating a drive circuit attached to the memory cell array 270, and the control unit 221 performs control based on this control code. A second example of the control code is a control parameter of the nonvolatile memory. This is a unique value such as a voltage applied to the nonvolatile memory cell and an application time thereof. The control unit 221 determines a voltage to be applied to the memory cell array based on this parameter. Further, as a third example of the control code, defective address information may be included. This is address information of a memory area determined to be defective at the time of factory shipment. The control unit 221 refers to the defective address information and performs a replacement process for the defective memory area. Note that memory cells other than the memory cells assigned to the control code memory 280 in the memory cell array 270 are areas for storing data output from the memory controller. Details of the memory 220 and the memory cell array 270 will be described later.

The exchange among the host computer 100, the memory controller 210, and the memory 220 will be described taking data writing as an example. First, a command requesting data writing is issued from the host computer 100 to the memory controller 210 together with the data. The memory controller 210 interprets this and encodes data. Thereafter, the memory controller 210 issues a request for writing data to the memory 220 together with the encoded data. The memory 220 interprets this request and stores the encoded data in the memory cell array 270. In this way, data is written by exchanging commands and requests.

[Functional block diagram in the first embodiment of the present technology]
FIG. 2 is a diagram illustrating an example of functional blocks of the storage device according to the first embodiment of the present technology. In the figure, the components of the memory controller 210 and the memory 220 included in the storage device 200 are divided into functional blocks. The storage device 200 in the figure includes a memory controller 210, a control code memory 280, a read control unit 222, an error correction unit 230, and a work memory 223. The storage device 200 also includes a refresh control unit 224, a control unit 221, a degradation state detection unit 225, a control code degradation information holding unit 226, and a control code degradation information supply unit 227. The control code memory 280 and the memory controller 210 are the same as those described with reference to FIG.

The read control unit 222 reads the control code from the control code memory 280. This reading is performed before power is turned on to the memory 220 and the memory 220 becomes accessible from the memory controller 210. The error correction unit 230 performs error correction on the control code read from the control code memory 280. This error correction will be described later. The work memory 223 holds a control code in which an error is corrected. As the working memory 223, a volatile memory capable of high-speed operation, for example, an SRAM can be used. The control unit 221 controls the entire memory 220 as described above. Further, the control unit 221 interprets the request issued by the memory controller 210 and performs processing such as data writing. The control unit 221 operates based on the control code held in the work memory 223. The refresh control unit 224 rewrites the control code in which the error held in the work memory 223 is corrected in the control code memory 280. This rewriting is performed based on an instruction for requesting rewriting output from the control unit 221.

The deterioration state detection unit 225 detects a deterioration state of the control code stored in the control code memory 280. Here, the deterioration state of the control code represents a state in which a bit error has occurred in a part of the control code stored in the nonvolatile memory or a bit error can occur. Even when the control code is deteriorated, it is possible to extract the original control code by performing error correction. However, if bit errors accumulate, error correction becomes impossible. For this reason, when the control code is in a deteriorated state, it is necessary to rewrite the control code in the control code memory 280. In the first embodiment of the present technology, a state in which error correction by the error correction unit 230 is performed on a control code in which a bit error has occurred is defined as a deterioration state of the control code.

The control code deterioration information holding unit 226 holds the deterioration state of the control code detected by the deterioration state detection unit 225 as control code deterioration information. The control code deterioration information holding unit 226 can be configured by a register, for example. In the embodiment of the present technology, the control code deterioration information holding unit 226 will be described as being configured by a 1-bit register corresponding to the control code deterioration information. In the initial state, the value of this register is “0”. The control code deterioration information is set by setting a value “1” in this register.

The control code deterioration information supply unit 227 supplies the control code deterioration information held in the control code deterioration information holding unit 226 to the memory controller 210. The control code deterioration information supply unit 227 can use, for example, a signal line connected to the memory controller 210 in order to output the contents of the register constituting the control code deterioration information holding unit 226. Further, for example, a circuit having a function of interpreting a request for requesting supply of control code deterioration information issued by the memory controller 210 and outputting the control code deterioration information to the memory controller 210 can be used. The memory controller 210 supplied with the control code deterioration information issues a request for requesting rewriting of the control code. Based on this request, the control unit 221 outputs an instruction for requesting the above-described rewriting.

[Memory configuration]
FIG. 3 is a diagram illustrating a configuration example of the memory according to the first embodiment of the present technology. The memory 220 includes a power-on reset unit 252, a control unit 221, a read control unit 222, a control code deterioration information holding unit 226, a control signal generation unit 243, a work memory 223, and an error correction unit 230. . The memory 220 includes a parity generation unit 254, a memory interface 251, a selection unit 255, a memory cell array 270, a data buffer 256, and data buses 257 to 259. The memory cell array 270 includes a control code memory 280. Note that the error correction unit 230 in FIG. 3 includes an ECC decoding unit 231 and a majority operation unit 232. The majority decision calculation unit 232 includes the deterioration state detection unit 225 described with reference to FIG. Similarly, the control unit 221 in FIG. 3 includes the refresh control unit 224 and the control code deterioration information supply unit 227 described in FIG.

The control code memory 280 stores a plurality of control codes. In these, control codes having the same contents are written in different areas of the control code memory 280 at the time of factory shipment. An odd number of control codes are stored in the control code memory 280 in order to perform a majority operation described later. In the first embodiment of the present technology, control codes having the same contents are stored in three locations. The control code memory 280 also stores parity for each of the plurality of control codes. This parity will be described later. In addition to these, the memory 220 also includes a sense amplifier, a driver, and an address decoder for driving the memory cell array 270 (not shown).

The memory interface 251 exchanges data with the memory controller 210. The memory interface 251 transfers the request output from the memory controller 210 to the inside of the memory 220 and exchanges data bidirectionally with the memory controller 210. The power-on reset unit 252 generates a reset signal when the power is turned on. The power-on reset unit 252 starts operation when a power supply voltage is applied to the memory 220 and turns on the reset signal. After that, it is detected that the power supply voltage of the memory 220 has reached a specified value, for example, 90% of the power supply voltage in a steady state, and the reset signal is turned off.

The parity generation unit 254 generates parity for performing error detection and error correction of the control code. For example, a Hamming code method can be used for generating the parity. The error correction unit 230 corrects an error in the control code. The error correction unit 230 in FIG. 3 includes an ECC decoding unit 231 and a majority operation unit 232. The ECC decoding unit 231 performs control code decoding. The ECC decoding unit 231 detects control code errors and corrects errors using the above-described parity. Since there are three control codes, the ECC decoding unit 231 decodes each control code.

The majority operation unit 232 performs majority operation on the control code decoded by the ECC decoding unit 231. Here, the majority operation is to use a plurality of data (control codes) and determine the value of each bit in the data by majority. Specifically, the more “0” or “1” is the control code value in each bit. In the first embodiment of the present technology, control codes are provided at three locations, and correction is possible when a bit error occurs in any one of the corresponding three bits. . The majority operation unit 232 detects a deterioration state of the control code when an error in the control code is corrected during the calculation process. Specifically, when a mismatch between the control codes is detected, it is corrected by a majority operation, and the read control unit 222 is notified that the control code is in a degraded state. As described above, the majority decision calculation unit 232 includes the deterioration state detection unit 225. Upon receiving the notification, the read control unit 222 sets the value “1” in the control code deterioration information holding unit 226. These procedures will be described later.

Read control unit 222 reads the control code from the control code memory 280. The read control unit 222 in FIG. 3 includes an address counter for accessing the control code memory 280. The read control unit 222 is reset by the reset signal output from the power-on reset unit 252. At this time, the address counter is also initialized. When the reset signal is turned off, the read control unit 222 starts operation. First, the read control unit 222 increments the address counter, reads the control code and parity in units of one word, and transfers them to the ECC decoding unit 231. Next, the control code decoded by the ECC decoding unit 231 is transferred to the majority operation unit 232. Finally, the operation result in the majority operation unit 232 is transferred to the work memory 223 and held. By repeating these, the control code is read out.

The control unit 221 interprets the request issued by the memory controller 210 and controls the entire memory 220. This will be described in detail by taking the case of writing data as an example. The control unit 221 that has received a request to write data interprets this request and controls the control signal generation unit 243. The control signal generator 243 outputs a control signal to the address decoder and driver. Further, data relating to a request for writing that is issued by the memory controller 210 is transferred to the data buffer 256 and then supplied to the memory cell array 270 to be written. The control unit 221 also has a function of rewriting the control code in which the error is corrected in the control code memory 280 when receiving a request for rewriting the control code. As described above, the control unit 221 includes the function of the refresh control unit 224.

In order to perform this rewriting, the control unit 221 has a built-in address counter for accessing the control code memory 280. The control unit 221 rewrites the control code in units of words while incrementing the address counter. At this time, the control unit 221 also rewrites the parity corresponding to this one-word control code. That is, the control code is encoded and rewritten. For this reason, the control unit 221 transfers a one-word control code to the parity generation unit 254 to generate parity. Note that the control unit 221 according to the first embodiment of the present technology transfers the control code from the work memory 223 to the memory controller 210 based on a request for reading out the control code issued from the memory controller 210. Thereafter, the control code is rewritten based on the request for rewriting the control code issued from the memory controller 210 and the control code issued accompanying the request. These procedures will be described later. Further, the control unit 221 has a function of reading the control code deterioration information held in the control code deterioration information holding unit 226 and outputting the control code deterioration information to the memory controller 210 when receiving a request for reading the control code deterioration information. Have. As described above, the control unit 221 includes the function of the control code deterioration information supply unit 227.

The control signal generator 243 outputs a control signal to the sense amplifier, driver, and address decoder according to an instruction from the controller 221 or the read controller 222. The data buffer 256 temporarily holds data to be written to the memory cell array 270 and data read from the memory cell array 270. Data buses 257 to 259 are signal lines for transmitting data and the like bidirectionally. The data bus 257 is disposed between the memory interface 251 and the selection unit 255, and the data bus 259 is disposed between the data buffer 256 and the selection unit 255. The data bus 258 is selected with the control unit 221, the read control unit 222, the control code degradation information holding unit 226, the control signal generation unit 243, the working memory 223, the ECC decoding unit 231, the majority decision operation unit 232, and the parity generation unit 254. It arrange | positions between the parts 255. The selection unit 255 selects a data bus. The selection unit 255 exchanges data and the like between the data buses 257 to 259 in accordance with an instruction from the control unit 221 or the read control unit 222. The control code deterioration information holding unit 226 and the work memory 223 are the same as those described with reference to FIG. The parity generation unit 254 is an example of a parity generation unit described in the claims.

FIG. 4 is a diagram illustrating an example of control code arrangement in the control code memory according to the first embodiment of the present technology. This figure shows an example of control code arrangement in the control code memory 280. In the first embodiment of the present technology, three control codes are stored in the control code memory. For this reason, the control code memory 280 is also divided into three areas. This corresponds to the first to third regions in FIG. In these areas, data 281, 283 and 285 and parities 282, 284 and 286 of each data are stored. The control code and parity are n words in size and are stored in memory cells assigned addresses 1 to n, respectively.

[Error correction of control code]
Thus, in the first embodiment of the present technology, three control codes are used, and ECC encoding and majority calculation are performed on these three control codes. Error detection and error correction are performed. That is, the control code error correction process is performed twice. As described above, the majority operation can correct an error when one bit error occurs for each of the three corresponding bits. On the other hand, when two or more bit errors occur, error correction cannot be performed. However, by duplicating the error correction processing, it is possible to avoid such a state that error correction cannot be performed, and to improve control code storage reliability. Note that the control code storage reliability can be further improved by performing ECC decoding and majority operation using five control codes.

[Power-on processing procedure]
FIG. 5 is a diagram illustrating an example of a processing procedure of power-on processing according to the first embodiment of the present technology. This figure shows a processing procedure of power-on processing of the memory 220 by the memory controller 210. The memory controller 210 controls the power supply control unit 201 to turn on the power supply voltage to be applied to the memory 220 (step S901). Thereafter, the process waits until the startup process in the memory 220 is completed (step S902). When the activation process in the memory 220 is completed (step S902: Yes), the control code deterioration information holding unit 226 is read (step S903). This is performed by, for example, issuing a request for requesting the memory 220 to read the control code deterioration information holding unit 226. As a result, when the value of the control code deterioration information holding unit 226 is 1 (step S904: Yes), the memory controller 210 determines that the control code has deteriorated, and performs the refresh process (step S905). .

First, the control code is read (step S906). This is done by issuing a request to the memory 220 for requesting reading of the control code. Based on this request, the control code is read and transferred from the memory 220 to the memory controller 210. Next, the read control code is written (step S907). This is performed by issuing a request for writing the control code to the memory 220 and transferring the control code read in step S907 to the memory 220. Thereafter, the power-on process is terminated. On the other hand, when the value of the control code deterioration information holding unit is 0 (step S904: No), the memory controller 210 determines that the control code has not deteriorated, and ends the power-on process.

[Processing procedure for memory startup processing]
FIG. 6 is a diagram illustrating an example of a processing procedure of the memory activation process according to the first embodiment of the present technology. The process shown in the figure corresponds to the activation process of the memory 220 described in step S902 of the power-on process in FIG. In the first embodiment of the present technology, the read control unit 222 has an error occurrence flag indicating whether or not an error has occurred in the control code. When this flag is 1, the read control unit 222 determines that an error has occurred.

First, a power-on reset (step S931) is performed. This is done by turning on the reset signal by the power-on reset unit 252 and initializing the address counter built in the read control unit 222 to a value indicating the head of the control code memory 280. In the first embodiment of the present technology, the value of the address counter is initialized to 1. At this time, the values of the control code deterioration information holding unit 226 and the error occurrence flag are also initialized to 0.

When the reset signal is turned off, the read control unit 222 starts processing. First, control code reading and error correction processing are performed (step S940). As a result, one word of data (control code of one word) is selected and output from the control code. The selected data is transferred to the work memory 223 (step S934). When reading is completed for all the words of the control code (step S935: Yes), the process proceeds to the next process (step S937). When reading of the control code is not completed (step S935: No), the address counter is incremented (step S936), and the processing from step S940 is executed again. Thereafter, the error occurrence flag is checked, and when this value is 1 (step S937: Yes), the value of the control code deterioration information holding unit 226 is set to 1 (step S938). Thereafter, the memory activation process is terminated. On the other hand, if the value of the error occurrence flag is not 1 (step S937: No), the memory activation process is terminated.

[Procedure for reading control code and error correction]
FIG. 7 is a diagram illustrating an example of a processing procedure of control code reading and error correction processing according to the first embodiment of the present technology. First, the control code is read (step S941). This is done by reading the control code and parity from the memory cells of the control code memory 280. At this time, the control code and parity in word units are read from the memory cell at the address designated by the address counter. In the first embodiment of the present technology, three control codes and three parities are stored in the memory cells with the same address. For this reason, the control code and parity of 3 words are read out. Next, the control code is decoded (step S942). This is done by transferring the read control code and parity of one word to the ECC decoding unit 231 and decoding. This decoding is also performed for each control code of 3 words.

Next, the majority calculation of the control code is performed (step S943). This is performed by transferring the three decoded one-word control codes to the majority operation unit 232 and performing the majority operation for each bit in the majority operation unit 232. In this majority decision operation, when the values of all three bits of the control code of one word match (step S944: Yes), no error has occurred, and the process proceeds to the next process (step S946). On the other hand, when there is a bit unit mismatch in the three 1-word control codes (step S944: No), the read control unit 222 sets the error occurrence flag to 1 (step S945). Thereafter, the result of the majority operation is set as selection data (step S946), the control code is read, and the error correction process is terminated.

[Control code read processing]
FIG. 8 is a diagram illustrating an example of a processing procedure of a control code reading process according to the first embodiment of the present technology. This process is a process in the memory 220 corresponding to a request for reading the control code issued by the control code reading process (step S906) in the power-on process described with reference to FIG. Accordingly, the control unit 221 starts processing when a request for reading the control code is issued. The control unit 221 interprets the request and transmits the control code held in the work memory 223 to the memory controller 210 (step S951). Thereafter, the process ends.

[Control code rewriting process]
FIG. 9 is a diagram illustrating an example of a processing procedure of a control code rewriting process according to the first embodiment of the present technology. This process is a process in the memory 220 corresponding to the request for requesting the writing of the control code issued by the control code writing process (step S907) in the power-on process described with reference to FIG. Therefore, the control unit 221 starts processing when a request for writing the control code is issued. The control unit 221 interprets the request and receives a control code from the memory controller 210. Thereafter, the received control code is transferred to the work memory 223 (step S961). Next, an initial value is set in the address counter built in the control unit 221 (step S962). In the first embodiment of the present technology, the value of the address counter is initialized to 1.

Next, a control code for one word is taken out from the transferred control code and encoded (step S963). This encoding is performed by transferring the control code for one word to the parity generation unit 254 and adding the generated parity to the control code for one word. Next, the control code encoded in the control code memory 280 is rewritten (step S964). At this time, rewriting is performed on the memory cell at the address designated by the address counter. The control code and parity for one word are rewritten in each of the three areas of the memory cell. That is, the control code and parity for 3 words are rewritten. When rewriting has been completed for all words of the control code (step S965: Yes), the control code rewriting process is terminated. If the rewriting of the control code has not ended (step S965: No), the address counter is incremented (step S966), and the processing from step S963 is executed again.

As described above, according to the first embodiment of the present technology, it is possible to avoid error accumulation by performing error correction of the control code and rewriting the corrected control code in the control code memory which is the storage area. Therefore, the storage reliability of the control code can be improved. In the first embodiment of the present technology, double error correction by ECC encoding and majority voting is performed to further increase the storage reliability of the control code. In addition, in the first embodiment of the present technology, the control code is rewritten via the memory controller 210. For this reason, the memory controller 210 can adjust the timing of rewriting the control code, and can easily manage the schedule of the entire storage device.

[Modification]
In the first embodiment of the present technology, control code deterioration is determined when a control code mismatch occurs in the majority operation. However, deterioration of the control code may be determined when error correction is performed in ECC decoding. This is because it is possible to determine the deterioration of the control code at an earlier stage as compared with the method of determining the deterioration based on the mismatch of the majority of the control codes after the error correction is performed. As a result, the storage reliability of the control code can be further improved. The modification of the first embodiment of the present technology is different from the first embodiment of the present technology in that the deterioration of the control code is determined when error correction is performed in ECC decoding.

The ECC decoding unit 231 according to the modification of the first embodiment of the present technology determines that the control code is in a deteriorated state when the control code error is detected and error correction is performed in the decoding process. Notify As described above, the ECC decoding unit 231 includes the function of the deterioration state detection unit 225 described with reference to FIG. Since the other configuration of the storage device is the same as that of the storage device 200 described in the first embodiment of the present technology, the description thereof is omitted.

FIG. 10 is a diagram illustrating an example of a processing procedure of control code reading and error correction processing according to a modification of the embodiment of the present technology. First, the control code is read (step S971). This is performed by reading three control codes and parity from the memory cells of the control code memory 280, respectively. Next, the control code is decoded (step S972). This is performed by transferring the read control code and parity of one word to the ECC decoding unit 231 and decoding them by the ECC decoding unit 231. This decoding is also performed for each of the three control codes. In this ECC decoding, when error correction of the control code is not performed (step S974: Yes), the process proceeds to the next process (step S973). On the other hand, when the error correction of the control code is performed (step S974: No), the read control unit 222 sets the error occurrence flag to 1 (step S975). Thereafter, a majority operation is performed (step S973). The result of the majority operation is used as selection data (step S976), and the control code reading and error correction processing are terminated. Since other processing procedures are the same as those of the storage device 200 according to the first embodiment of the present technology, description thereof is omitted.

<2. Second Embodiment>
[Example of logical OR operation]
In the first embodiment of the present technology, error correction is performed by ECC decoding and majority operation. On the other hand, in the second embodiment of the present technology, error correction by logical sum operation is performed.

FIG. 11 is a diagram illustrating a configuration example of a memory according to the second embodiment of the present technology. The memory 220 in the figure includes an error correction unit 230 including a logical sum operation unit 233. On the other hand, the parity generation unit 254 need not be provided. Further, the memory cell array 270 uses a memory cell array composed of ReRAM. The other configuration is the same as that of the memory 220 described with reference to FIG.

[OR operation]
FIG. 12 is a diagram illustrating a logical sum operation according to the second embodiment of the present technology. This figure explains the logical sum operation performed in the logical sum operation unit 233. An example of performing a logical sum operation on the first to third control codes (read data) will be described. The logical sum operation unit 233 calculates and outputs a logical sum for each bit of each read data. Here, the logical sum is an operation that outputs “0” when all the values of each bit are “0”, and outputs “1” when at least one bit has a value of “1”.

[Characteristics of non-volatile memory]
A ReRAM memory cell performs a storage operation by applying a voltage to a resistance change layer and utilizing a change in the resistance value. The resistance change layer has a two-layer structure including an insulating layer and a metal ion supply layer including chalcogenide, and can perform a memory operation by changing a resistance value by applying a voltage. The variable resistance layer in the initial state immediately after manufacture is in a high resistance state. In order to make this usable as a memory, forming is performed before shipment from the factory. This forming is performed by applying a voltage (hereinafter referred to as a forming voltage), whereby metal ions supplied from the metal ion supply layer enter the insulating layer to form a filament that is a conductive path. Thus, a low resistance state is obtained. When this reverse voltage is applied, the metal ions forming the filament return from the insulating layer to the metal ion supply layer side, and thus return to a high resistance state. When a voltage is applied again, the state transitions to a low resistance state, but can be transitioned to a low resistance state by applying a voltage lower than the forming voltage.

In the second embodiment of the present technology, the high resistance state corresponds to the logical state “0”, and the low resistance state corresponds to the logical state “1”. The variable resistance layer before forming maintains a high resistance state, and maintains this logic state “0” unless a forming voltage is applied. Therefore, no deterioration occurs. On the other hand, the resistance change layer of the memory cell that is set to the logic state “1” by forming may cause a transition to the logic state “0” due to deterioration.

[Control code storage and error correction in non-volatile memory]
In the second embodiment of the present technology, control codes are stored and errors are corrected by using the properties of the ReRAM. The ReRAM memory cell in the initial state is in the logic state “0”. Thereafter, the control code is written by applying the forming voltage only to the bit to which the logic state “1” is written. As described above, since it is only necessary to consider the transition from the logical state “1” to the logical state “0”, the error can be corrected by the logical sum operation. In FIG. 12, the bits of the control code value “0” are not deteriorated, and therefore all the three bits are maintained at “0”. The result of the logical sum operation is also “0”. On the other hand, a bit whose control code value is “1” may be “0” due to deterioration. However, the error can be corrected to “1” by performing a logical sum operation.

[Procedure for reading control code and error correction]
FIG. 13 is a diagram illustrating an example of a processing procedure of control code reading and error correction processing according to the second embodiment of the present technology. This process is a process called in step S940 of the memory activation process described with reference to FIG. First, the control code is read (step S811). This is performed by reading the control code from the memory cell of the control code memory 280. At this time, a word-unit control code is read from the memory cell at the address designated by the address counter. In the second embodiment of the present technology, a control code of 3 words is read.

Next, a logical OR operation of the control code (step S813) is performed. This is performed by transferring three read control codes of one word to the logical sum operation unit 233 and performing a logical sum operation for each bit. In this logical sum operation, when the values of all three bits of the control code of one word match (step S814: Yes), no error has occurred, and the process proceeds to the next process (step S816). On the other hand, when there is a bit unit mismatch in the three 1-word control codes (step S814: No), the read control unit 222 sets the error occurrence flag to 1 (step S815). Thereafter, the result of the logical sum operation is set as selection data (step S816), and the control code reading and error correction processing are terminated. Note that other processing procedures are the same as those in the first embodiment of the present technology, and a description thereof will be omitted.

As described above, according to the second embodiment of the present technology, the control code writing process can be simplified by writing the control code in parallel with the forming. Further, simple error correction processing can be realized by performing error correction by logical sum operation using the characteristics of the nonvolatile memory.

<3. Third Embodiment>
[Example of judging deterioration of control code based on the number of power on / off times]
In the first embodiment of the present technology, the deterioration of the control code is determined when an error is corrected. On the other hand, in the third embodiment of the present technology, the deterioration is determined when the number of power on / off times reaches a predetermined number, and the control code is rewritten.

FIG. 14 is a diagram illustrating a configuration example of a memory according to the third embodiment of the present technology. The memory 220 in the figure includes a count unit 261. The count unit 261 includes a deterioration state detection unit 225. The count unit 261 measures the number of times power is turned on or off in the memory 220. In addition, the count unit 261 can be configured by, for example, a nonvolatile memory that stores the number of times of power-on. The measurement in the count unit 261 can be performed by incrementing the number of times of power-on stored in the nonvolatile memory as the activation process after reset by the power-on reset unit 252. Further, when the number of power-on times reaches a set value, for example, 1000 times, the read control unit 222 is notified that the control code is in a degraded state. Thus, the count unit 261 includes the function of the deterioration state detection unit 225. In the third embodiment of the present technology, deterioration information is set when an error correction is performed in the majority voting unit 232 and when the number of power-on times reaches a set value. The other configuration of the memory 220 is the same as that of the memory 220 described with reference to FIG.

As described above, in the third embodiment of the present technology, in addition to the case where the error correction of the control code is performed, the number of times of turning on or off the power in the memory 220 reaches a predetermined number. Then, the control code deterioration is detected and rewritten. Thereby, the storage reliability of the control code can be further increased.

<4. Fourth Embodiment>
[Example where the memory controller issues a request to rewrite]
In the first embodiment of the present technology, the memory controller rewrites the control code by issuing a request for requesting reading and writing of the control code. On the other hand, in the fourth embodiment of the present technology, the memory controller rewrites the control code by issuing a request for rewriting.

The storage device according to the fourth embodiment of the present technology may have the same configuration as the storage device 200 described in FIG. The control unit 221 is different in that it interprets a request for rewriting issued from the memory controller and rewrites the control code. Since other than this is the same as that of the storage device 200, the description thereof is omitted.

[Power-on processing procedure]
FIG. 15 is a diagram illustrating an example of a processing procedure of power-on processing according to the fourth embodiment of the present technology. The memory controller 210 controls the power supply control unit 201 to turn on the power supply voltage applied to the memory 220 (step S991). Thereafter, the process waits until the activation process in the memory 220 is completed (step S992). When the activation process in the memory 220 is completed (step S992: Yes), the control code deterioration information holding unit 226 is read (step S993). As a result, when the value of the control code deterioration information holding unit 226 is 1 (step S994: Yes), the memory controller 210 determines that the control code has deteriorated, and performs the refresh process (step S995). . This is performed by issuing a request for refreshing to the memory 220 (step S996). Thereafter, the power-on process is terminated. On the other hand, when the value of the control code deterioration information holding unit is 0 (step S994: No), the memory controller 210 determines that the control code has not deteriorated and ends the power-on process.

[Control code rewriting process]
FIG. 16 is a diagram illustrating an example of a processing procedure of control code rewriting processing. This process is started when a request for rewriting the control code is issued. The control unit 221 interprets the request and sets an initial value in an address counter built in the control unit 221 (step S802). Next, a control code for one word is extracted from the control code held in the work memory 223 and encoded (step S803). This encoding is performed by transferring a control code for one word to the parity generation unit 254 and adding the parity generated by the parity generation unit 254. Next, the control code encoded in the control code memory 280 is rewritten (step S804). At this time, rewriting is performed on the memory cell at the address designated by the address counter. If rewriting has not been completed for all words of the control code (step S805: No), the address counter is incremented (step S806), and the processing from step S803 is executed again. When rewriting is completed for all the words of the control code (step S805: Yes), the control code rewriting process is terminated. Note that the other processing procedures are the same as those of the storage device 200 according to the first embodiment of the present technology, and thus the description thereof is omitted.

As described above, according to the fourth embodiment of the present technology, the memory controller 210 can rewrite the control code by issuing only a request for requesting rewriting of the control code, and rewrite the control code. Processing can be simplified.

<5. Fifth embodiment>
[Example of rewriting without a memory controller]
In the first embodiment of the present technology, the memory controller supplied with the control code deterioration information issues a request and rewrites the control code. On the other hand, in the fifth embodiment of the present technology, the control unit 221 acquires the control code deterioration information and rewrites the control code without any memory controller.

FIG. 17 is a diagram illustrating an example of a functional block diagram of the storage device according to the fifth embodiment of the present technology. The storage device in the figure is configured by removing the memory controller 210 and the control code deterioration information supply unit 227 from the storage device described in FIG. Also, the control unit 221 directly acquires the control code deterioration information held in the control code deterioration information holding unit 226 and outputs a rewrite instruction. Since the configuration of the other functional blocks is the same as that of the storage device described with reference to FIG. Note that the memory 220 according to the fifth embodiment of the present technology may have the same configuration as the memory 220 in FIG. However, the control unit 221 reads the control code deterioration information holding unit 226 after the power-on process is completed. As a result, if the deterioration of the control code is set, the control code rewriting process described later is performed. Rewrite the control code. The other configuration of the memory 220 is the same as that of the memory 220 described with reference to FIG.

[Power-on processing procedure]
The power-on procedure by the memory controller 210 in the fifth embodiment of the present technology is as follows. First, the memory controller 210 turns on the power of the memory module. Next, it waits for the memory activation to end. Thereafter, the processing is terminated and normal processing is performed. Compared with the processing procedure described in FIG. 15, the control code deterioration information holding unit read process (step S993) and the subsequent processes are not performed. Thereafter, memory activation processing, control code reading, and error correction processing in the memory 220 are sequentially performed. These are the same as the processes described with reference to FIGS.

[Control procedure startup procedure]
FIG. 18 is a diagram illustrating an example of a processing procedure of a control unit activation process according to the fifth embodiment of the present technology. After the control code reading process by the reading control unit 222 is completed, the control unit 221 performs this process. First, the control unit 221 reads the control code deterioration information holding unit 226 (step S823). As a result, when the value of the control code deterioration information holding unit 226 is 0 (step S824: No), the control unit 221 ends the control unit activation process. On the other hand, when the value of the control code deterioration information holding unit 226 is 1 (step S824: Yes), the control unit 221 determines that the control code has deteriorated, and performs control code rewriting processing (step S830). carry out. Thereafter, the control unit activation process is terminated.

[Procedure for rewriting control code]
The processing procedure of the control code rewriting process in the fifth embodiment of the present technology may be the same processing procedure as the control code rewriting process described in FIG. However, it is different in that it is called in step S830 in the above-described control unit activation process. Other than this, the processing is the same as that described in FIG.

As described above, according to the fifth embodiment of the present technology, it is possible to simplify the processing of the memory controller by judging the deterioration of the control code and rewriting without the intervention of the memory controller 210. it can.

As described above, in the embodiment of the present technology, error correction is performed on the control code stored in the control code memory which is a nonvolatile memory. Thereafter, by rewriting the control code in which the error is corrected in the control code memory, accumulation of errors can be prevented, and the storage reliability of the control code can be improved.

The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

Further, the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described in this specification are merely examples, and are not limited, and other effects may be obtained.

In addition, this technique can also take the following structures.
(1) a control code memory for storing a control code for controlling the nonvolatile memory;
A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
An error correction unit that performs error correction of the read control code;
A working memory holding the control code in which the error is corrected;
A control unit that controls the nonvolatile memory based on the control code held in the working memory and outputs an instruction to request rewriting of the control code held in the working memory with respect to the control code memory;
And a refresh control unit that performs the rewriting based on the instruction.
(2) a deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code;
A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
The storage device according to (1), wherein the control unit outputs the instruction based on the control code deterioration information.
(3) The device according to (2), wherein the deterioration state detection unit detects the deterioration state by detecting that the error correction has occurred in the error correction unit.
(4) further comprising a counting unit that counts the number of times power is turned on or off in the memory;
The memory according to (2), wherein the deterioration state detection unit detects the deterioration state when the number of times counted by the counting unit reaches a predetermined number.
(5) The control unit according to any one of (2) to (4), wherein the held control code deterioration information is read and the instruction is output based on the read control code deterioration information Storage device.
(6) further comprising a control code deterioration information supply unit that supplies the control code deterioration information to the memory controller;
The control unit according to (2) to (4), wherein the control unit outputs the instruction based on a request for requesting the rewriting issued from the memory controller based on the supplied control code deterioration information. Any storage device.
(7) further comprising a parity generator for generating parity for correcting an error in the control code;
The control code memory further includes an area for storing the parity,
The error correction unit performs the error correction using the parity,
The storage device according to any one of (1) to (6), wherein the refresh control unit rewrites a corresponding parity in the code memory together with the control code in which the error is corrected.
(8) The control code memory stores the control code in a plurality of areas,
The memory according to any one of (1) to (6), wherein the error correction unit performs the error correction by correcting a bit when corresponding values in the plurality of control codes do not match each other. apparatus.
(9) The storage device according to (8), wherein the error correction unit performs the error correction by performing a majority operation on the mismatched bits for correction.
(10) The storage device according to (8), wherein the error correction unit performs the error correction by performing an OR operation on the mismatched bits to correct the mismatched bits.
(11) a control code memory for storing a control code for controlling the nonvolatile memory;
A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
An error correction unit that performs error correction of the read control code;
A working memory holding the control code in which the error is corrected;
A deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code held in the working memory in the control code memory;
A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
A control code deterioration information supply unit for supplying the control code deterioration information to the memory controller;
A memory controller that issues a request for requesting the rewriting based on the supplied control code deterioration information;
A control unit that controls the nonvolatile memory based on the control code held in the working memory, and outputs an instruction to request the rewriting based on the issued request;
And a refresh control unit that performs the rewriting based on the instruction.
(12) a control code memory for storing a control code for controlling the nonvolatile memory;
A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
An error correction unit that performs error correction of the read control code;
A working memory holding the control code in which the error is corrected;
A deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code held in the working memory in the control code memory;
A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
A control code deterioration information supply unit for supplying the control code deterioration information to the memory controller;
A memory controller that issues a request for requesting the rewriting based on the supplied control code deterioration information;
A control unit that controls the nonvolatile memory based on the control code held in the working memory, and outputs an instruction to request the rewriting based on the issued request;
A storage device including a refresh control unit that performs the rewriting based on the instruction;
An information processing system comprising: a host computer that accesses the storage device via the memory controller.
(13) a reading procedure for reading a control code for controlling the nonvolatile memory from the control code memory before the operation of the nonvolatile memory;
An error correction procedure for performing error correction of the read control code;
A control procedure for controlling the nonvolatile memory based on the control code in which the error is corrected, and outputting an instruction for requesting rewriting of the control code in which the error is corrected with respect to the control code memory;
And a refresh control procedure for performing the rewriting based on the instruction.

DESCRIPTION OF SYMBOLS 100 Host computer 200 Memory | storage device 201 Power supply control part 210 Memory controller 211 ECC processing part 220 Memory 221 Control part 222 Read control part 223 Work memory 224 Refresh control part 225 Degradation state detection part 226 Control code deterioration information holding part 227 Control code deterioration information Supply unit 230 Error correction unit 231 ECC decoding unit 232 Majority calculation unit 233 OR operation unit 243 Control signal generation unit 251 Memory interface 252 Power-on reset unit 254 Parity generation unit 255 Selection unit 256 Data buffer 257 to 259 Data bus 261 Count unit 270 Memory cell array 280 Control code memory 281 Data 282 Parity

Claims (13)

1. A control code memory for storing a control code for controlling the nonvolatile memory;
   A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
   An error correction unit that performs error correction of the read control code;
   A working memory holding the control code in which the error is corrected;
   A control unit that controls the nonvolatile memory based on the control code held in the working memory and outputs an instruction to request rewriting of the control code held in the working memory with respect to the control code memory;
   And a refresh control unit that performs the rewriting based on the instruction.
2. A deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code;
   A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
   The storage device according to claim 1, wherein the control unit outputs the instruction based on the control code deterioration information.
3. 3. The storage device according to claim 2, wherein the deterioration state detection unit detects the deterioration state by detecting that the error correction has occurred in the error correction unit.
4. A counter for counting the number of times power is turned on or off in the memory;
   The storage device according to claim 2, wherein the deterioration state detection unit detects the deterioration state when the number of times counted by the counting unit reaches a predetermined number.
5. The storage device according to claim 2, wherein the control unit reads the held control code deterioration information and outputs the instruction based on the read control code deterioration information.
6. A control code deterioration information supply unit for supplying the control code deterioration information to the memory controller;
   The storage device according to claim 2, wherein the control unit outputs the instruction based on a request for requesting the rewrite issued from the memory controller based on the supplied control code deterioration information.
7. A parity generator for generating parity for correcting an error in the control code;
   The control code memory further includes an area for storing the parity,
   The error correction unit performs the error correction using the parity,
   The storage device according to claim 1, wherein the refresh control unit rewrites a corresponding parity in the code memory together with the control code in which the error is corrected.
8. The control code memory stores the control code in a plurality of areas,
   The storage device according to claim 1, wherein the error correction unit performs the error correction by correcting a bit when corresponding values in the plurality of control codes do not match.
9. The storage device according to claim 8, wherein the error correction unit performs the error correction by performing a majority operation on the mismatched bits to correct the mismatched bits.
10. The storage device according to claim 8, wherein the error correction unit performs the error correction by performing a logical sum operation on the mismatched bits to correct the mismatched bits.
11. A control code memory for storing a control code for controlling the nonvolatile memory;
    A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
    An error correction unit that performs error correction of the read control code;
    A working memory holding the control code in which the error is corrected;
    A deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code held in the working memory in the control code memory;
    A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
    A control code deterioration information supply unit for supplying the control code deterioration information to the memory controller;
    A memory controller that issues a request for requesting the rewriting based on the supplied control code deterioration information;
    A control unit that controls the nonvolatile memory based on the control code held in the working memory, and outputs an instruction to request the rewriting based on the issued request;
    And a refresh control unit that performs the rewriting based on the instruction.
12. A control code memory for storing a control code for controlling the nonvolatile memory;
    A read controller that reads the control code from the control code memory before the operation of the nonvolatile memory;
    An error correction unit that performs error correction of the read control code;
    A working memory holding the control code in which the error is corrected;
    A deterioration state detection unit for detecting a deterioration state indicating the necessity of rewriting the control code held in the working memory in the control code memory;
    A control code deterioration information holding unit for holding the detected deterioration state as control code deterioration information;
    A control code deterioration information supply unit for supplying the control code deterioration information to the memory controller;
    A memory controller that issues a request for requesting the rewriting based on the supplied control code deterioration information;
    A control unit that controls the nonvolatile memory based on the control code held in the working memory, and outputs an instruction to request the rewriting based on the issued request;
    A storage device including a refresh control unit that performs the rewriting based on the instruction;
    An information processing system comprising: a host computer that accesses the storage device via the memory controller.
13. A reading procedure for reading out a control code for controlling the nonvolatile memory from the control code memory before the operation of the nonvolatile memory;
    An error correction procedure for performing error correction of the read control code;
    A control procedure for controlling the nonvolatile memory based on the control code in which the error is corrected, and outputting an instruction for requesting rewriting of the control code in which the error is corrected with respect to the control code memory;
    And a refresh control procedure for performing the rewriting based on the instruction.

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