WO2015190218A1 - Cyanide electrolytic gold plating bath and bump formation method using same - Google Patents

Cyanide electrolytic gold plating bath and bump formation method using same Download PDF

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WO2015190218A1
WO2015190218A1 PCT/JP2015/063991 JP2015063991W WO2015190218A1 WO 2015190218 A1 WO2015190218 A1 WO 2015190218A1 JP 2015063991 W JP2015063991 W JP 2015063991W WO 2015190218 A1 WO2015190218 A1 WO 2015190218A1
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gold
plating bath
film
gold plating
electrolytic gold
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PCT/JP2015/063991
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French (fr)
Japanese (ja)
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誠人 古川
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メタローテクノロジーズジャパン株式会社
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Priority to KR1020197014454A priority Critical patent/KR20190057163A/en
Priority to CN201580022227.9A priority patent/CN106460213B/en
Priority to KR1020167031053A priority patent/KR20170016823A/en
Publication of WO2015190218A1 publication Critical patent/WO2015190218A1/en

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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/48Electroplating: Baths therefor from solutions of gold
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48After-treatment of electroplated surfaces
    • C25D5/50After-treatment of electroplated surfaces by heat-treatment
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Definitions

  • the organic acid conductive salt at least oxalate is used.
  • the oxalate include potassium oxalate, sodium oxalate, and ammonium oxalate.
  • the blending amount of oxalate is 2.5 to 50 g / L as oxalic acid, and preferably 10 to 30 g / L. If it is less than 2.5 g / L, plating penetration occurs, and if it exceeds 100 g / L, the plating appearance tends to be poor.
  • organic acid conductive salts other than oxalate include citrate and formate. Examples of the citrate and formate include potassium citrate and potassium formate. These may be used alone or in combination of two or more.

Abstract

The present invention provides a cyanide electrolytic gold plating bath that: comprises gold cyanide as a gold source at a gold concentration of 0.1 - 15 g/L, an oxalate at 2.5 - 50 g/L of oxalic acid, 5 - 100 g/L of an inorganic acid conducting salt, 0.1 - 50 g/L of water soluble sugars, and a crystal modifier at a metal concentration of 0.1 - 100 mg/L; and is able to form gold bumps for which the film hardness after heat treatment is 70 - 120 HV.

Description

シアン系電解金めっき浴及びこれを用いるバンプ形成方法Cyan-based electrolytic gold plating bath and bump forming method using the same
 本発明は、シアン系電解金めっき浴に関する。また、パターニングされた半導体ウエハ上に、該シアン系電解金めっき浴を用いて所定硬度の金バンプを形成するバンプ形成方法に関する。 The present invention relates to a cyan electrolytic gold plating bath. The present invention also relates to a bump forming method for forming gold bumps having a predetermined hardness on a patterned semiconductor wafer using the cyan electrolytic gold plating bath.
 半導体ウエハをプリント配線基板に取り付ける方法として、電極接合方法がある。電極接合方法は、半導体ウエハの集積回路に形成される金バンプとプリント配線基板上に形成される基板電極とを接続する方法である。図2は、半導体チップが電極接合方法によって取り付けられているプリント配線基板の構造の一例を示す断面図である。 There is an electrode bonding method as a method for attaching a semiconductor wafer to a printed wiring board. The electrode bonding method is a method of connecting gold bumps formed on an integrated circuit of a semiconductor wafer and substrate electrodes formed on a printed wiring board. FIG. 2 is a cross-sectional view showing an example of the structure of a printed wiring board to which a semiconductor chip is attached by an electrode bonding method.
 図2において、10はプリント配線基板、16は半導体チップである。プリント配線基板10は、硬質基板11の表面に基板配線パターン12及び基板電極14が積層されている。半導体チップ16は、半導体ウエハ1の表面に回路層1’及びAl(アルミニウム)電極2、パッシベーション膜3が順次積層されている。Al電極2の表面におけるパッシベーション膜3の開口部には、TiWスパッタ膜4、金スパッタ膜5、金バンプ7が順次積層されている。 In FIG. 2, 10 is a printed wiring board, and 16 is a semiconductor chip. In the printed wiring board 10, a board wiring pattern 12 and a board electrode 14 are laminated on the surface of a hard board 11. In the semiconductor chip 16, a circuit layer 1 ′, an Al (aluminum) electrode 2, and a passivation film 3 are sequentially stacked on the surface of the semiconductor wafer 1. In the opening of the passivation film 3 on the surface of the Al electrode 2, a TiW sputtered film 4, a gold sputtered film 5, and a gold bump 7 are sequentially laminated.
 プリント配線基板10の基板電極14と半導体チップ16の金バンプ7とは電気的に接合されている。電気的な接合としては、異方性導電接着剤20を用いる方法や共晶接合が挙げられる。異方性導電接着剤とは、Ni/Auめっき層により被覆された樹脂粒子がエポキシ樹脂等の熱硬化性樹脂に均一に分散している接着剤をいう。共晶接合とは、熱圧着や超音波により共晶を形成させて基板電極と金バンプとを接合する電極接合をいう。図2においては、プリント配線基板10の基板電極14と半導体チップ16の金バンプ7とは異方性導電接着剤20を介して電気的に接合されている。 The substrate electrode 14 of the printed wiring board 10 and the gold bump 7 of the semiconductor chip 16 are electrically joined. Examples of electrical bonding include a method using an anisotropic conductive adhesive 20 and eutectic bonding. An anisotropic conductive adhesive refers to an adhesive in which resin particles coated with a Ni / Au plating layer are uniformly dispersed in a thermosetting resin such as an epoxy resin. Eutectic bonding refers to electrode bonding in which a eutectic is formed by thermocompression bonding or ultrasonic waves to bond a substrate electrode and a gold bump. In FIG. 2, the substrate electrode 14 of the printed wiring board 10 and the gold bump 7 of the semiconductor chip 16 are electrically bonded via an anisotropic conductive adhesive 20.
 金バンプ7の熱処理後の皮膜硬度は、60HV以下である。金バンプ7の熱処理後の皮膜硬度は、異方性導電接着剤20に含まれる導電粒子の硬度や基板電極14の材質等に応じて60HV以下の範囲において適宜調整される。 The film hardness of the gold bump 7 after the heat treatment is 60HV or less. The film hardness after the heat treatment of the gold bump 7 is appropriately adjusted within a range of 60 HV or less in accordance with the hardness of the conductive particles contained in the anisotropic conductive adhesive 20 and the material of the substrate electrode 14.
 近年、携帯電話やノートパソコン等の電子機器の軽量化、小型化、高性能化が進むに従い、電子部品の小型化が求められている。小型化された電子部品においては、回路の集積密度の高度化及びファインピッチ化が進んでいる。電極間のピッチ幅が5~20μmである狭い回路が設けられたプリント配線基板と半導体ウエハとを電気的に接合する場合、隣接する金バンプ同士が接触する不具合が生じている。その原因は、基板電極とバンプとの熱圧着時に、金バンプが面方向に変形するためと考えられる。従来の皮膜硬度が60HV以下の金バンプは、皮膜硬度が低過ぎる。そのため、ピッチ幅が狭い回路が設けられているプリント配線基板との接合には適さない。したがって、従来製造される金バンプよりも高い皮膜硬度を有する金バンプを形成することが求められている。 In recent years, as electronic devices such as mobile phones and notebook computers become lighter, smaller, and have higher performance, there is a demand for smaller electronic components. In miniaturized electronic components, the integration density of circuits and the fine pitch have been advanced. When a printed wiring board provided with a narrow circuit having a pitch width between electrodes of 5 to 20 μm is electrically bonded to a semiconductor wafer, there is a problem that adjacent gold bumps are in contact with each other. The cause is considered to be that the gold bump is deformed in the surface direction at the time of thermocompression bonding between the substrate electrode and the bump. A conventional gold bump having a film hardness of 60 HV or less has a film hardness that is too low. Therefore, it is not suitable for joining with a printed wiring board provided with a circuit having a narrow pitch width. Therefore, it is required to form a gold bump having a higher film hardness than a conventionally manufactured gold bump.
 金バンプを形成する際に用いる電解金めっき浴としては、亜硫酸金を金源とする非シアン系電解金めっき浴と、シアン化金を金源とするシアン系電解金めっき浴と、がある。非シアン系電解金めっき浴においては、皮膜硬度が高い金バンプを形成する方法が公知である(特許文献1)。特許文献1には、ポリアルキレングリコール及び/又は両性界面活性剤が添加された非シアン系電解金めっき浴が開示されている。この非シアン系電解金めっき浴は、金皮膜中に不純物が取り込まれ、金皮膜の再結晶化が阻害される。その結果、高硬度の金皮膜を形成することができる。 Electrolytic gold plating baths used for forming gold bumps include a non-cyan electrolytic gold plating bath using gold sulfite as a gold source and a cyan electrolytic gold plating bath using gold cyanide as a gold source. In non-cyan electrolytic gold plating baths, a method for forming gold bumps with high film hardness is known (Patent Document 1). Patent Document 1 discloses a non-cyan electrolytic gold plating bath to which a polyalkylene glycol and / or an amphoteric surfactant is added. In this non-cyan electrolytic gold plating bath, impurities are taken into the gold film, and recrystallization of the gold film is inhibited. As a result, a high hardness gold film can be formed.
特開2009-57631号公報JP 2009-57631 A
 特許文献1に開示される非シアン系電解金めっき浴は、シアン系電解金めっき浴と比較して薬品コストが高い。また、金めっき浴の安定性が低いため、浴管理が困難である。そのため、低コスト化の要請、浴管理の容易性、シアン系電解金めっき浴でのファインパターニングに適したフォトレジストの改良が進んだこと等により、シアン系電解金めっき浴を使用したいと考える事業者が増加している。 The non-cyan electrolytic gold plating bath disclosed in Patent Document 1 has a higher chemical cost than the cyan electrolytic gold plating bath. Moreover, since the stability of the gold plating bath is low, bath management is difficult. Therefore, businesses that want to use cyan electrolytic gold plating baths due to demands for cost reduction, ease of bath management, and improvements in photoresists suitable for fine patterning in cyan electrolytic gold plating baths. The number of people is increasing.
 しかし、シアン系電解金めっき浴に、非シアン系電解金めっき浴と同様に有機添加剤を添加しても、形成される金皮膜には不純物がほとんど共析しない。したがって、形成される金皮膜の金純度が高いため、熱処理後に軟らかくなる。即ち、高硬度の金皮膜を形成することができるシアン系電解金めっき浴は、未だ実用化されていない。 However, even if an organic additive is added to the cyan electrolytic gold plating bath in the same manner as the non-cyan electrolytic gold plating bath, impurities are hardly co-deposited in the formed gold film. Therefore, since the gold film formed has a high gold purity, it becomes soft after heat treatment. That is, a cyan electrolytic gold plating bath that can form a high-hardness gold film has not yet been put into practical use.
 本発明の目的は、熱処理後の皮膜硬度が高い金バンプを形成することができるシアン系電解金めっき浴を提供することにある。 An object of the present invention is to provide a cyan electrolytic gold plating bath capable of forming gold bumps having high film hardness after heat treatment.
 本発明者らは、鋭意研究の結果、シアン系電解金めっき浴にシュウ酸塩及び水溶性多糖類を添加することにより、皮膜硬度が高い金バンプを形成できることを見出し、本発明を完成するに至った。上記課題を解決する本発明は、以下に記載するものである。 As a result of intensive studies, the present inventors have found that gold bumps with high film hardness can be formed by adding oxalate and water-soluble polysaccharides to a cyan electrolytic gold plating bath, and to complete the present invention. It came. The present invention for solving the above problems is described below.
 [1] 金源としてのシアン化金塩を金濃度で0.1~15g/Lと、
 シュウ酸塩をシュウ酸として2.5~50g/Lと、
 無機酸伝導塩を5~100g/Lと、
 水溶性多糖類を0.1~50g/Lと、
 結晶調整剤を金属濃度で1~100mg/Lと、
を含有するシアン系電解金めっき浴。
[1] Gold cyanide salt as a gold source is 0.1 to 15 g / L in gold concentration,
2.5 to 50 g / L of oxalate as oxalic acid,
5 to 100 g / L of inorganic acid conductive salt,
0.1 to 50 g / L of water-soluble polysaccharide,
The crystal modifier is 1 to 100 mg / L in metal concentration,
A cyan electrolytic gold plating bath containing
 [2] 前記水溶性多糖類が、デキストリン、α-シクロデキストリン、β-シクロデキストリン及びデキストランから選択される1種又は2種以上である[1]に記載のシアン系電解金めっき浴。 [2] The cyan electrolytic gold plating bath according to [1], wherein the water-soluble polysaccharide is one or more selected from dextrin, α-cyclodextrin, β-cyclodextrin and dextran.
 [3] 前記結晶調整剤が、Tl化合物、Pb化合物及びAs化合物から選択される1種又は2種以上である[1]に記載のシアン系電解金めっき浴。 [3] The cyan electrolytic gold plating bath according to [1], wherein the crystal modifier is one or more selected from a Tl compound, a Pb compound, and an As compound.
 [4] パターニングされた半導体ウエハ上に、[1]乃至[3]に記載のシアン系電解金めっき浴を用いて電解金めっきを行った後、200~300℃で5~600分間熱処理することにより、皮膜硬度が70~120HVの金バンプを形成する、バンプ形成方法。 [4] Electrolytic gold plating is performed on the patterned semiconductor wafer using the cyan electrolytic gold plating bath described in [1] to [3], followed by heat treatment at 200 to 300 ° C. for 5 to 600 minutes. To form a gold bump having a film hardness of 70 to 120 HV.
 本発明のシアン系電解金めっき浴を用いて形成された金バンプは、皮膜硬度が70~120HVであり、ファインピッチの電子部品における半導体ウエハと基板との電気的接合に適する。また、本発明の電解金めっき浴は、シアン化金塩を用いるため、非シアン系の電解金めっき浴と比較して浴管理が容易である。本発明のシアン系電解金めっき浴を用いると、高硬度の金バンプを低コストで形成することができる。したがって、本発明は、小型の電子部品の生産コスト低減に寄与する。 The gold bump formed using the cyan electrolytic gold plating bath of the present invention has a film hardness of 70 to 120 HV and is suitable for electrical bonding between a semiconductor wafer and a substrate in a fine pitch electronic component. Moreover, since the electrolytic gold plating bath of the present invention uses a gold cyanide salt, the bath management is easier as compared with a non-cyan electrolytic gold plating bath. When the cyan electrolytic gold plating bath of the present invention is used, high-hardness gold bumps can be formed at low cost. Therefore, the present invention contributes to reducing the production cost of small electronic components.
本発明のシアン系電解金めっき浴を用いて形成された金バンプの一例を示す断面図である。It is sectional drawing which shows an example of the gold bump formed using the cyan-type electrolytic gold plating bath of this invention. プリント配線基板に半導体チップを取り付けた状態の一例を示す断面図ある。It is sectional drawing which shows an example of the state which attached the semiconductor chip to the printed wiring board.
 本発明のシアン系電解金めっき浴は、金源としてのシアン化金塩と、シュウ酸塩と、無機酸伝導塩と、水溶性多糖類と、結晶調整剤とを含有する。本発明のシアン系電解金めっき浴を用いて形成される金バンプは、熱処理後の皮膜硬度が70~120HVである。以下、本発明のシアン系電解金めっき浴を構成する各成分について説明する。 The cyan electrolytic gold plating bath of the present invention contains a gold cyanide salt as a gold source, an oxalate, an inorganic acid conductive salt, a water-soluble polysaccharide, and a crystal modifier. Gold bumps formed using the cyan electrolytic gold plating bath of the present invention have a film hardness of 70 to 120 HV after heat treatment. Hereinafter, each component constituting the cyan electrolytic gold plating bath of the present invention will be described.
 [シアン化金塩]
 本発明のシアン系電解金めっき浴には、金源として公知のシアン化金塩を制限することなく使用することができる。シアン化金塩としては、シアン化金カリウム、シアン化金ナトリウム、シアン化金アンモニウムが例示される。
[Gold cyanide]
In the cyan electrolytic gold plating bath of the present invention, a known gold cyanide salt can be used without limitation as a gold source. Examples of the gold cyanide salt include potassium gold cyanide, sodium gold cyanide, and ammonium gold cyanide.
 シアン化金塩の配合量は、金濃度として、0.1~15g/Lであり、4~15g/Lが好ましい。金濃度が0.1g/L未満である場合、陰極電流効率が低く、金膜厚が不均一になったり、所望の金膜厚を得られなくなったりする。なお、金膜厚は10~20μmであることが好ましい。金濃度が15g/Lを超える場合、陰極電流効率が金イオン濃度に比例して増大しなくなるため効率的でない。また、めっき液の持ち出しによる金メタルのロスが大きくなる。そのため、生産コストが上昇する。 The compounding amount of the gold cyanide salt is 0.1 to 15 g / L as gold concentration, and preferably 4 to 15 g / L. When the gold concentration is less than 0.1 g / L, the cathode current efficiency is low, the gold film thickness becomes non-uniform, or a desired gold film thickness cannot be obtained. The gold film thickness is preferably 10 to 20 μm. When the gold concentration exceeds 15 g / L, the cathode current efficiency does not increase in proportion to the gold ion concentration, which is not efficient. Further, the loss of gold metal due to taking out of the plating solution increases. As a result, production costs increase.
 [伝導塩]
 本発明のシアン系電解金めっき浴は、無機酸伝導塩と、少なくともシュウ酸塩を含む有機酸伝導塩とが併用される。シュウ酸塩を用いない場合、フォトレジストとウエハとの間にめっきが潜り込み、パターン外析出が起こるため好ましくない。即ち、めっき潜り込みの分だけ金スパッタ膜のめっき皮膜が厚くなり、金めっき後のUBM層のエッチング処理工程で除去しきれずに導通不良となることがある。無機酸伝導塩を用いない場合、バンプ高さのバラツキが大きくなり好ましくない。
[Conductive salt]
In the cyan electrolytic gold plating bath of the present invention, an inorganic acid conductive salt and an organic acid conductive salt containing at least oxalate are used in combination. When oxalate is not used, plating sinks between the photoresist and the wafer, and deposition outside the pattern occurs, which is not preferable. That is, the plating film of the gold sputtered film is thickened by the amount of penetration of the plating, and may not be completely removed in the etching process of the UBM layer after gold plating, resulting in poor conduction. When an inorganic acid conductive salt is not used, the bump height varies greatly, which is not preferable.
 無機酸伝導塩としては、リン酸塩を用いる。リン酸塩としては、リン酸ナトリウム、リン酸カリウム、リン酸マグネシウム、リン酸アンモニウムが例示され、リン酸カリウムを用いることが好ましい。無機酸伝導塩の配合量は5~100g/Lであり、10~80g/Lであることが好ましく、20~70g/Lであることがより好ましい。 As the inorganic acid conductive salt, phosphate is used. Examples of the phosphate include sodium phosphate, potassium phosphate, magnesium phosphate, and ammonium phosphate, and potassium phosphate is preferably used. The compounding amount of the inorganic acid conductive salt is 5 to 100 g / L, preferably 10 to 80 g / L, and more preferably 20 to 70 g / L.
 有機酸伝導塩としては、少なくともシュウ酸塩を用いる。シュウ酸塩としては、シュウ酸カリウム、シュウ酸ナトリウム、シュウ酸アンモニウムが例示される。シュウ酸塩の配合量は、シュウ酸として2.5~50g/Lであり、10~30g/Lが好ましい。2.5g/L未満である場合、めっき潜り込みが発生し、100g/Lを超える場合、めっき外観が不良になりやすくなる。シュウ酸塩以外の有機酸伝導塩としては、クエン酸塩、ギ酸塩が例示される。クエン酸塩、ギ酸塩としては、クエン酸カリウム、ギ酸カリウムが例示される。これらは単独で用いても良く、2種以上を併用しても良い。有機酸伝導塩の配合量は、5~150g/Lであり、20~140g/Lであることが好ましく、30~130g/Lであることがより好ましい。伝導塩の配合量が上記の範囲を超える場合、つきまわり性が悪化したり、金めっき皮膜にやけを生じたりする場合がある。 As the organic acid conductive salt, at least oxalate is used. Examples of the oxalate include potassium oxalate, sodium oxalate, and ammonium oxalate. The blending amount of oxalate is 2.5 to 50 g / L as oxalic acid, and preferably 10 to 30 g / L. If it is less than 2.5 g / L, plating penetration occurs, and if it exceeds 100 g / L, the plating appearance tends to be poor. Examples of organic acid conductive salts other than oxalate include citrate and formate. Examples of the citrate and formate include potassium citrate and potassium formate. These may be used alone or in combination of two or more. The compounding amount of the organic acid conductive salt is 5 to 150 g / L, preferably 20 to 140 g / L, and more preferably 30 to 130 g / L. When the blending amount of the conductive salt exceeds the above range, throwing power may be deteriorated or the gold plating film may be burned.
 [水溶性多糖類]
 本発明のシアン系電解金めっき浴においては、公知の水溶性多糖類を用いることができる。入手容易性の観点からは、デキストリン、α-シクロデキストリン、β-シクロデキストリン、デキストランを例示することができる。これらの水溶性多糖類は、単独で用いても良く、2種類以上を併用しても良い。
[Water-soluble polysaccharide]
A known water-soluble polysaccharide can be used in the cyan electrolytic gold plating bath of the present invention. From the viewpoint of availability, dextrin, α-cyclodextrin, β-cyclodextrin and dextran can be exemplified. These water-soluble polysaccharides may be used alone or in combination of two or more.
 熱処理後の金バンプの皮膜硬度を70~120HVの高硬度にする場合、水溶性多糖類の配合量は、0.1~50g/Lが好ましく、0.5~30g/Lがより好ましい。配合量が0.1g/L未満である場合、熱処理後の金バンプの皮膜硬度が60HV未満になる。そのような金バンプは、基板と半導体ウエハとの熱圧着により変形しやすい。半導体ウエハ上の回路がファインピッチで形成されている場合、変形した金バンプ同士が接触して接合に不具合が出るおそれがある。また、異方性導電接着剤中の導電粒子の硬度に対して金バンプの皮膜硬度が低過ぎると、熱圧着工程で導電粒子が金バンプ中に埋没する。その結果、金バンプと基板電極との間で導電粒子が熱圧着されない。配合量が50g/Lを超える場合、ヤケめっきが発生して外観不良となる。 When the film hardness of the gold bump after heat treatment is set to a high hardness of 70 to 120 HV, the blending amount of the water-soluble polysaccharide is preferably 0.1 to 50 g / L, more preferably 0.5 to 30 g / L. When the blending amount is less than 0.1 g / L, the film hardness of the gold bump after the heat treatment becomes less than 60 HV. Such gold bumps are easily deformed by thermocompression bonding between the substrate and the semiconductor wafer. When the circuit on the semiconductor wafer is formed at a fine pitch, the deformed gold bumps may come into contact with each other, resulting in a problem in bonding. On the other hand, if the coating hardness of the gold bump is too low with respect to the hardness of the conductive particle in the anisotropic conductive adhesive, the conductive particle is buried in the gold bump in the thermocompression bonding step. As a result, the conductive particles are not thermocompression bonded between the gold bump and the substrate electrode. If the blending amount exceeds 50 g / L, burnt plating occurs, resulting in poor appearance.
 上記の水溶性多糖類を含有する本発明のシアン系電解金めっき浴を用いて、後に詳説する方法でめっきを行うことにより、熱処理後の皮膜硬度が70~120HVの金バンプを形成することができる。 By using the cyan electrolytic gold plating bath of the present invention containing the above-mentioned water-soluble polysaccharide and performing plating by a method described in detail later, a gold bump having a film hardness of 70 to 120 HV after heat treatment can be formed. it can.
 熱処理後の金バンプの皮膜硬度は、水溶性多糖類の種類や配合量を調節することにより制御することができる。その理由は明らかでないが、上記の所定の水溶性多糖類が、金皮膜中に不純物として取り込まれやすい性質を有するためと推察される。すなわち、シアン系電解金めっき浴中に配合される水溶性多糖類は金皮膜中に共析されることで、熱処理後の金の再結晶化を抑制する。これにより、熱処理後の皮膜硬度が高い金バンプを形成することができると考えられる。 The film hardness of the gold bump after the heat treatment can be controlled by adjusting the type and blending amount of the water-soluble polysaccharide. The reason is not clear, but it is presumed that the predetermined water-soluble polysaccharide has the property of being easily incorporated as an impurity in the gold film. That is, the water-soluble polysaccharide blended in the cyan electrolytic gold plating bath is co-deposited in the gold film, thereby suppressing recrystallization of gold after the heat treatment. Thereby, it is considered that gold bumps having high film hardness after heat treatment can be formed.
 金バンプの皮膜硬度は、導電粒子の種類や相手金属の硬度との相対性、回路のピッチ幅等種々の条件を考慮して選択される。 The film hardness of the gold bump is selected in consideration of various conditions such as the type of conductive particles, the relativity with the hardness of the counterpart metal, and the pitch width of the circuit.
 [結晶調整剤]
 本発明のシアン系電解金めっき浴においては、結晶調整剤としてTl化合物、Pb化合物又はAs化合物を添加する。Tl化合物としては、ギ酸タリウム、マロン酸タリウム、硫酸タリウム、硝酸タリウムが例示される。Pb化合物としては、クエン酸鉛、硝酸鉛、硫酸鉛が例示される。好ましくは硝酸鉛が用いられる。As化合物としては、三酸化二ヒ素が例示される。これらのTl化合物、Pb化合物及びAs化合物は単独で使用しても良いし、2種以上を併用しても良い。
[Crystal modifier]
In the cyan electrolytic gold plating bath of the present invention, a Tl compound, Pb compound or As compound is added as a crystal modifier. Examples of the Tl compound include thallium formate, thallium malonate, thallium sulfate, and thallium nitrate. Examples of the Pb compound include lead citrate, lead nitrate, and lead sulfate. Preferably, lead nitrate is used. An arsenic trioxide is illustrated as an As compound. These Tl compounds, Pb compounds and As compounds may be used alone or in combination of two or more.
 結晶調整剤の配合量は、本発明の目的を損なわない範囲で適宜定めることができる。通常、金属濃度として0.1mg~100mg/Lであり、0.5~50mg/Lが好ましく、1~30mg/Lがより好ましい。配合量が100mg/Lを超える場合、めっき付きまわりが悪化するおそれがある。また、得られる金めっき皮膜の外観にムラが生じる。配合量が0.1mg/L未満である場合、得られる金めっき皮膜にヤケが生じる。 The compounding amount of the crystal modifier can be appropriately determined within a range not impairing the object of the present invention. Usually, the metal concentration is 0.1 mg to 100 mg / L, preferably 0.5 to 50 mg / L, more preferably 1 to 30 mg / L. When the blending amount exceeds 100 mg / L, there is a possibility that the area with plating may deteriorate. Moreover, unevenness occurs in the appearance of the obtained gold plating film. If the blending amount is less than 0.1 mg / L, the resulting gold plating film will be burned.
 [その他の成分]
 本発明のシアン系電解金めっき浴においては、上記の成分の他に、本発明の目的を損なわない範囲でpH調整剤等の成分を含有させることができる。pH調整剤としては、水酸化ナトリウム、水酸化カリウム、水酸化アンモニウム及びリン酸、クエン酸、シュウ酸が例示される。
[Other ingredients]
In the cyan electrolytic gold plating bath of the present invention, in addition to the above components, components such as a pH adjusting agent can be contained within a range not impairing the object of the present invention. Examples of the pH adjuster include sodium hydroxide, potassium hydroxide, ammonium hydroxide, phosphoric acid, citric acid, and oxalic acid.
 [金バンプの形成方法]
 本発明のシアン系電解金めっき浴を用いて、常法に従ってめっき操作を行うことにより、皮膜硬度が70~120HVで、膜厚が10~50μmの金皮膜を形成することができる。本発明のシアン系電解金めっき浴を用いて、半導体ウエハ上に金バンプを形成する方法を図1を参照しながら説明する。
[Gold bump formation method]
By performing a plating operation according to a conventional method using the cyan electrolytic gold plating bath of the present invention, a gold film having a film hardness of 70 to 120 HV and a film thickness of 10 to 50 μm can be formed. A method for forming gold bumps on a semiconductor wafer using the cyan electrolytic gold plating bath of the present invention will be described with reference to FIG.
 (1) 積層工程
 図1は、本発明のシアン系電解金めっき浴を用いて形成された金バンプの一例を示す断面図である。先ず、半導体ウエハ1の回路層1’が形成された面にAl電極2が形成される。次に、回路層1’の表面に、回路層1’及びAl電極2を被覆するパッシベーション膜3が成膜される。パッシベーション膜3には、Al電極2の一部を露出させる位置に開口部3aが設けられる。パッシベーション膜3の表面には、TiWスパッタ膜4が成膜される。パッシベーション膜3及びパッシベーション膜3の開口部3aから露出するAl電極2は、TiWスパッタ膜4により被覆される。TiWスパッタ膜4の表面には、Auスパッタ膜5が成膜される。TiWスパッタ膜4及びAuスパッタ膜5は、Under Bump Metal(UBM)層6を構成する。UBM層6の表面には、レジスト膜8が成膜され、マスキングされる。レジスト膜8には、Auスパッタ膜5の一部を露出させる開口部8aが設けられる。レジスト膜8の開口部8aは、レジスト膜8の下層においてAl電極2が位置する領域に設けられる。レジスト膜8の材料としては、ネガ型フォトレジスト等を用いることが好ましい。
(1) Lamination process FIG. 1: is sectional drawing which shows an example of the gold bump formed using the cyan-type electrolytic gold plating bath of this invention. First, the Al electrode 2 is formed on the surface of the semiconductor wafer 1 on which the circuit layer 1 ′ is formed. Next, a passivation film 3 that covers the circuit layer 1 ′ and the Al electrode 2 is formed on the surface of the circuit layer 1 ′. In the passivation film 3, an opening 3 a is provided at a position where a part of the Al electrode 2 is exposed. A TiW sputtered film 4 is formed on the surface of the passivation film 3. The Al film 2 exposed from the passivation film 3 and the opening 3 a of the passivation film 3 is covered with a TiW sputtered film 4. An Au sputtered film 5 is formed on the surface of the TiW sputtered film 4. The TiW sputtered film 4 and the Au sputtered film 5 constitute an under bump metal (UBM) layer 6. A resist film 8 is formed on the surface of the UBM layer 6 and masked. The resist film 8 is provided with an opening 8 a that exposes a part of the Au sputtered film 5. The opening 8 a of the resist film 8 is provided in a region where the Al electrode 2 is located in the lower layer of the resist film 8. As a material for the resist film 8, it is preferable to use a negative photoresist or the like.
 (2) 電解金めっき工程
 積層構造が形成された半導体ウエハ1を被めっき物として、pHや液温、電流密度が適宜調整された本発明のシアン系電解金めっき浴を用いて所望の膜厚になるまで電解金めっきを行う。本発明の金めっき浴は、素地がメタライズされ、導電性の高いものであれば、被めっき物を選ばない。特に、レジスト膜8を使用してパターンニングしたシリコンウエハの回路上や、GaAsウエハなどの化合物ウエハの回路上における金バンプ形成に好適である。
(2) Electrolytic gold plating step Using the semiconductor wafer 1 having a laminated structure as an object to be plated, a desired film thickness using the cyan electrolytic gold plating bath of the present invention in which pH, liquid temperature, and current density are appropriately adjusted. Electrolytic gold plating is performed until. As long as the gold plating bath of the present invention is metallized and has high conductivity, any object to be plated can be used. In particular, it is suitable for forming gold bumps on a silicon wafer circuit patterned using the resist film 8 or a compound wafer circuit such as a GaAs wafer.
 本発明のシアン系電解金めっき浴は、pH4.0~8.0で使用することが好ましく、pH5.0~7.0で使用することがより好ましい。pHが4.0未満である場合、陰極電流効率が低下し、得られる金皮膜が十分な膜厚にならない。pHが8.0を超える場合、得られる金皮膜の外観が赤色化する。 The cyan electrolytic gold plating bath of the present invention is preferably used at pH 4.0 to 8.0, and more preferably at pH 5.0 to 7.0. When pH is less than 4.0, cathode current efficiency falls and the gold film obtained does not become a sufficient film thickness. When pH exceeds 8.0, the appearance of the obtained gold film turns red.
 本発明のシアン系電解金めっき浴の液温は、30~80℃が好ましく、40~70℃がより好ましい。めっき浴の液温が上記の範囲を外れると、陰極電流効率が低下したり、金めっき浴の安定性を損なったりするため好ましくない。 The liquid temperature of the cyan electrolytic gold plating bath of the present invention is preferably 30 to 80 ° C, more preferably 40 to 70 ° C. If the temperature of the plating bath is out of the above range, it is not preferable because the cathode current efficiency is lowered or the stability of the gold plating bath is impaired.
 本発明のシアン系電解金めっき浴を用いる場合の電流密度は、めっき液の組成や液温、その他の条件を勘案して設定される。したがって、一義的には決められないが、例えば、金濃度が8g/Lのめっき液を液温55℃で使用する場合、電流密度は0.5~1.0A/dmに設定することが好ましい。適切な電流密度に設定されない場合、めっき外観やめっき皮膜の特性に異常が生じるおそれがある。また、めっき浴が不安定になり、めっき液成分の分解が生じる場合がある。 The current density when using the cyan electrolytic gold plating bath of the present invention is set in consideration of the composition of the plating solution, the solution temperature, and other conditions. Therefore, although not uniquely determined, for example, when a plating solution having a gold concentration of 8 g / L is used at a liquid temperature of 55 ° C., the current density may be set to 0.5 to 1.0 A / dm 2. preferable. If the current density is not set appropriately, the appearance of plating and the characteristics of the plating film may be abnormal. In addition, the plating bath may become unstable and decomposition of the plating solution component may occur.
 電解金めっき後、半導体ウエハ1のレジスト膜8は、溶剤によって溶解除去される。レジスト膜8が除去されることにより、金バンプ7で被覆されていない領域のUBM層6が露出する。露出したUBM層6はエッチング等により除去される。これにより、金バンプ7で被覆されていない領域ではパッシベーション膜3が露出する。金バンプ7で被覆されているUBM層6はこの工程で除去されることなく、積層構造が維持される。 After the electrolytic gold plating, the resist film 8 on the semiconductor wafer 1 is dissolved and removed with a solvent. By removing the resist film 8, the UBM layer 6 in a region not covered with the gold bump 7 is exposed. The exposed UBM layer 6 is removed by etching or the like. Thereby, the passivation film 3 is exposed in a region not covered with the gold bumps 7. The UBM layer 6 covered with the gold bumps 7 is not removed in this step, and the laminated structure is maintained.
 (3) 熱処理工程
 UBM層6とレジスト膜8とが除去された後、金バンプ7が形成された半導体ウエハ1は、200~300℃で熱処理される。熱処理時間は5分間以上であり、30~600分間であることが好ましい。熱処理には、ファインオーブン等が使用される。ファインオーブンは、熱処理に必要な時間、チャンバー内部を設定温度に一定時間保持できるため、該熱処理に適している。熱処理後、半導体ウエハ1は自然冷却される。温度低下の過程で、金が再結晶化することにより皮膜硬度が変化する。上記の形成方法により得られる金バンプの皮膜硬度は70~120HVであり、従来の金バンプより高硬度である。
(3) Heat Treatment Step After the UBM layer 6 and the resist film 8 are removed, the semiconductor wafer 1 on which the gold bumps 7 are formed is heat treated at 200 to 300 ° C. The heat treatment time is 5 minutes or more, preferably 30 to 600 minutes. A fine oven or the like is used for the heat treatment. The fine oven is suitable for the heat treatment because the inside of the chamber can be maintained at a set temperature for a certain time for the time required for the heat treatment. After the heat treatment, the semiconductor wafer 1 is naturally cooled. In the process of lowering the temperature, the film hardness changes due to recrystallization of gold. The film hardness of the gold bump obtained by the above forming method is 70 to 120 HV, which is higher than that of the conventional gold bump.
 本発明のシアン系電解金めっき浴は、金源やめっき液を構成する成分を補充管理することにより、2ターン以上使用することができる。「1ターン」とは金めっき浴中の金がすべてめっきに消費された状態をいう。 The cyan electrolytic gold plating bath of the present invention can be used for two or more turns by replenishing and managing the components constituting the gold source and the plating solution. “One turn” means a state in which all gold in the gold plating bath is consumed for plating.
 以下、実施例によって本発明を具体的に説明する。本発明はこれらの実施例に限定されるものではない。 Hereinafter, the present invention will be specifically described with reference to examples. The present invention is not limited to these examples.
 被めっき物として、素地断面組成がAu/TiW/SiOのシリコンウエハを用いた。シリコンウエハのレジスト膜には、ネガ型フォトレジスト(JSR社製品名:THB-121N)を使用した。レジスト膜には、配置ピッチ20μmでパターニングされた開口部を2つ設けた。一つの開口部の開口形状は、短辺が20μm、長辺が100μmの長方形である。もう一つの開口部の開口形状は、1辺が100μmの正方形である。 As the object to be plated, a silicon wafer having a substrate cross-sectional composition of Au / TiW / SiO 2 was used. A negative photoresist (JSR product name: THB-121N) was used for the resist film of the silicon wafer. The resist film was provided with two openings patterned at an arrangement pitch of 20 μm. The opening shape of one opening is a rectangle having a short side of 20 μm and a long side of 100 μm. The opening shape of the other opening is a square having a side of 100 μm.
 表1-2に記載する組成で、実施例1~12、比較例1~5のめっき液を調製した。調製されためっき液1L中に被めっき物を浸漬し、表1-2に記載する条件下で、金膜厚が15μmになるまで電解めっき操作を行い、その後熱処理を行った。得られた金バンプの物性を、以下に記載する方法で測定した。測定結果は表1-2に記載した。 The plating solutions of Examples 1 to 12 and Comparative Examples 1 to 5 were prepared with the compositions described in Table 1-2. An object to be plated was immersed in 1 L of the prepared plating solution, and an electroplating operation was performed until the gold film thickness became 15 μm under the conditions described in Table 1-2, followed by heat treatment. The physical property of the obtained gold bump was measured by the method described below. The measurement results are shown in Table 1-2.
 〔皮膜硬度(ビッカース硬さ;HV)〕
 被めっき物上に形成された2つの金バンプのうち、一辺が100μmの正方形金バンプを用いて、熱処理前及び250℃で30分間熱処理した後の金バンプの硬度を測定した。測定は、ミツトヨ社製微小硬さ試験機HM-221を用いて行った。測定条件は、測定圧子を25gf荷重で10秒保持した。
[Film hardness (Vickers hardness; HV)]
Of the two gold bumps formed on the object to be plated, square gold bumps with a side of 100 μm were used to measure the hardness of the gold bumps before heat treatment and after heat treatment at 250 ° C. for 30 minutes. The measurement was performed using a micro hardness tester HM-221 manufactured by Mitutoyo Corporation. The measurement conditions were that the measurement indenter was held for 10 seconds at a load of 25 gf.
 〔浴安定性〕
 被めっき物に電解金めっきを施した後、金めっき浴の様子を目視で観察した。
 ○:金めっき浴に分解や沈殿が観察されない。
 ×:金めっき浴に分解や沈殿が観察される。
[Bath stability]
After electrolytic gold plating was applied to the object to be plated, the state of the gold plating bath was visually observed.
○: No decomposition or precipitation is observed in the gold plating bath.
X: Decomposition and precipitation are observed in the gold plating bath.
 〔めっき皮膜外観〕
 被めっき物に形成された金バンプの表面外観を顕微鏡を用いて観察し、色調、ムラ、表面粗さを目視で評価した。
 ○:色調、ムラに異常が観察されない。
 ×:色調、ムラに異常が観察される。
[Appearance of plating film]
The surface appearance of the gold bump formed on the object to be plated was observed using a microscope, and the color tone, unevenness, and surface roughness were visually evaluated.
○: No abnormality is observed in color tone and unevenness.
X: Abnormalities are observed in color tone and unevenness.
 〔めっき潜り込み〕
 被めっき物に形成された金バンプの表面外観を顕微鏡を用いて観察し、めっきの潜り込みを目視で評価した。
 ○:めっき潜り込みが観察されない。
 ×:めっき潜り込みが観察される。
[Plating penetration]
The surface appearance of the gold bump formed on the object to be plated was observed using a microscope, and the penetration of the plating was visually evaluated.
○: Plating penetration is not observed.
X: Plating penetration is observed.
Figure JPOXMLDOC01-appb-T000001
 
Figure JPOXMLDOC01-appb-T000001
 
Figure JPOXMLDOC01-appb-T000002
 
Figure JPOXMLDOC01-appb-T000002
 
 実施例1~12で形成された金バンプは、熱処理後の皮膜硬度がいずれも70~120HVの範囲内であり高硬度であった。いずれの金バンプも、色調はレモンイエローで、ムラがなく半光沢~無光沢の良好な外観が得られた。浴安定性も良好であった。 The gold bumps formed in Examples 1 to 12 each had a high hardness because the film hardness after the heat treatment was in the range of 70 to 120 HV. All of the gold bumps were lemon yellow in color and had a good appearance with no unevenness and a semi-gloss to matte appearance. The bath stability was also good.
 比較例1で形成された金バンプは、熱処理後の皮膜硬度が70HV未満であり低硬度であった。色調はレモンイエローで、ムラがなく半光沢~無光沢の良好な外観であった。浴安定性は良好であった。 The gold bump formed in Comparative Example 1 had a low hardness with a film hardness after heat treatment of less than 70 HV. The color tone was lemon yellow and there was no unevenness and it was a semi-gloss to matte appearance. The bath stability was good.
 比較例2で形成された金バンプは、熱処理後の皮膜硬度が70HV未満であり低硬度であった。また、フォトレジストとウエハとの間にめっきの潜り込みが見られた。得られたバンプの外観は、ムラがなく、半光沢~無光沢の良好な外観であった。浴安定性は良好であった。 The gold bumps formed in Comparative Example 2 had a low hardness with a film hardness after heat treatment of less than 70 HV. Moreover, the penetration of plating was observed between the photoresist and the wafer. The appearance of the obtained bumps was uniform and had a good appearance that was semi-glossy to matte. The bath stability was good.
 比較例3で形成された金バンプは、熱処理後の皮膜硬度が90HVであり高硬度であった。しかし、フォトレジストとウエハとの間にめっきの潜り込みが見られた。得られたバンプの外観は、ムラがなく、半光沢~無光沢の良好な外観であった。浴安定性は良好であった。 The gold bump formed in Comparative Example 3 had a high hardness of 90 HV after the heat treatment. However, there was a dip in the plating between the photoresist and the wafer. The appearance of the obtained bumps was uniform and had a good appearance that was semi-glossy to matte. The bath stability was good.
 比較例4で形成された金バンプは、熱処理後の皮膜硬度が70HV未満であり低硬度であった。また、フォトレジストとウエハとの間にめっきの潜り込みが見られた。得られたバンプの外観は、ムラがなく、半光沢~無光沢の良好な外観であった。浴安定性は良好であった。 The gold bump formed in Comparative Example 4 had a low hardness with a film hardness after heat treatment of less than 70 HV. Moreover, the penetration of plating was observed between the photoresist and the wafer. The appearance of the obtained bumps was uniform and had a good appearance that was semi-glossy to matte. The bath stability was good.
 比較例5で形成された金バンプは、熱処理後の皮膜硬度が90HVであり高硬度であった。また、フォトレジストとウエハとの間にめっきの潜り込みが見られた。得られたバンプの外観は、ムラがあった。浴安定性は良好であった。 The gold bump formed in Comparative Example 5 had a high hardness of 90 HV after heat treatment. Moreover, the penetration of plating was observed between the photoresist and the wafer. The appearance of the obtained bump was uneven. The bath stability was good.
 1   半導体ウエハ
 1’  回路層
 2   Al電極
 3   パッシベーション膜
 3a  パッシベーション膜の開口部
 4   TiWスパッタ膜
 5   金スパッタ膜
 6   UBM層
 7   金バンプ
 7a  金バンプの表面
 8   レジスト膜
 8a  レジスト膜の開口部
10   プリント配線基板
11   硬質基板
12   基板配線パターン
14   基板電極
16   半導体チップ
18   封止材
20   異方性導電接着剤
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1 'Circuit layer 2 Al electrode 3 Passivation film 3a Passivation film opening 4 TiW sputter film 5 Gold sputter film 6 UBM layer 7 Gold bump 7a Gold bump surface 8 Resist film 8a Resist film opening 10 Print wiring Substrate 11 Hard substrate 12 Substrate wiring pattern 14 Substrate electrode 16 Semiconductor chip 18 Sealing material 20 Anisotropic conductive adhesive

Claims (4)

  1.  金源としてのシアン化金塩を金濃度で0.1~15g/Lと、
     シュウ酸塩をシュウ酸として2.5~50g/Lと、
     無機酸伝導塩を5~100g/Lと、
     水溶性多糖類を0.1~50g/Lと、
     結晶調整剤を金属濃度で0.1~100mg/Lと、
    を含有することを特徴とするシアン系電解金めっき浴。
    Gold cyanide salt as a gold source at a gold concentration of 0.1 to 15 g / L,
    2.5 to 50 g / L of oxalate as oxalic acid,
    5 to 100 g / L of inorganic acid conductive salt,
    0.1 to 50 g / L of water-soluble polysaccharide,
    The crystal modifier is a metal concentration of 0.1 to 100 mg / L,
    A cyan electrolytic gold plating bath comprising:
  2.  前記水溶性多糖類が、デキストリン、α-シクロデキストリン、β-シクロデキストリン及びデキストランから選択される1種又は2種以上である請求項1に記載のシアン系電解金めっき浴。 The cyan electrolytic gold plating bath according to claim 1, wherein the water-soluble polysaccharide is one or more selected from dextrin, α-cyclodextrin, β-cyclodextrin and dextran.
  3.  前記結晶調整剤が、Tl化合物、Pb化合物及びAs化合物から選択される1種又は2種以上である請求項1に記載のシアン系電解金めっき浴。 The cyan electrolytic gold plating bath according to claim 1, wherein the crystal modifier is one or more selected from a Tl compound, a Pb compound, and an As compound.
  4.  パターニングされた半導体ウエハ上に、請求項1乃至3のいずれか1項に記載のシアン系電解金めっき浴を用いて電解金めっきを行った後、200~300℃で5~600分間熱処理することにより、皮膜硬度が70~120HVの金バンプを形成する、バンプ形成方法。 Electrolytic gold plating is performed on the patterned semiconductor wafer using the cyan electrolytic gold plating bath according to any one of claims 1 to 3, followed by heat treatment at 200 to 300 ° C for 5 to 600 minutes. To form a gold bump having a film hardness of 70 to 120 HV.
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