WO2015186533A1

WO2015186533A1 - Image sensor, electronic apparatus, ad conversion device, and drive method

Info

Publication number: WO2015186533A1
Application number: PCT/JP2015/064675
Authority: WO
Inventors: 延幸嶋村
Original assignee: ソニー株式会社
Priority date: 2014-06-04
Filing date: 2015-05-22
Publication date: 2015-12-10
Also published as: JP2015231096A

Abstract

　The present technique pertains to an image sensor, an electronic apparatus, an AD conversion device, and a drive method that make it possible to reduce noise. An amplification unit outputs an amplified reference signal in which a reference signal varying in level is amplified at a K-fold amplification rate greater than or equal to x1. An attenuation unit attenuates the amplified reference signal at a 1/K-fold attenuation rate, and outputs an attenuated reference signal. An AD conversion unit compares the attenuated reference signal and an electric signal outputted from a pixel, thereby converting the electric signal from analog to digital (performing AD conversion). The present technique can be applied to cases in which, e.g., the electric signal outputted from a pixel is AD-converted.

Description

Image sensor, electronic device, AD converter, and driving method

The present technology relates to an image sensor, an electronic device, an AD converter, and a driving method, and more particularly, to an image sensor, an electronic device, an AD converter, and a driving method that can reduce noise, for example.

Recently, in digital cameras such as digital video cameras and digital still cameras, for example, CMOS (Complementary Metal Oxide Semiconductor) image sensors are used as solid-state imaging devices for capturing images.

In the analog front end of the CMOS image sensor, a reference signal to be compared with an electrical signal obtained from a pixel is shared by a plurality of ADCs (Analog-to-Digital Converter), and an electrical signal obtained from a plurality of pixels such as pixels on one horizontal line. Parallel AD conversion is performed in which the AD conversion is performed in parallel (see, for example, Patent Document 1).

Patent No. 4,470,700

In column parallel AD conversion, for example, a reference signal is shared by a plurality of ADCs that perform AD conversion of electrical signals obtained from pixels of one horizontal line. Therefore, if the noise (random noise) included in the reference signal is not sufficiently small compared to the noise (random noise) included in the electrical signal obtained from the pixel, in the image obtained from the CMOS image sensor in the horizontal line direction. Correlated horizontal stripe noise appears to such an extent that it can be visually observed, and the image quality deteriorates.

In order to prevent such deterioration in image quality, it is necessary to reduce the noise of the reference signal (noise included in the reference signal) by an order of magnitude less than the noise of the electric signal obtained from the pixel (noise included in the electric signal). is there.

However, in recent years, the noise of the electrical signal obtained from the pixel has been remarkably improved to a few e ⁻ (e represents the elementary electric quantity), and the specifications required for the noise allowed for the reference signal have become stricter. Yes.

The present technology has been made in view of such a situation, and makes it possible to reduce noise of a reference signal.

An image sensor according to an embodiment of the present technology includes a photoelectric conversion element that performs photoelectric conversion, a pixel that outputs an electrical signal, a reference signal output unit that outputs a reference signal whose level changes, and the reference signal that is one or more times higher An amplification unit that outputs an amplified reference signal amplified at an amplification factor of K, an attenuation unit that attenuates the amplified reference signal at an attenuation factor of 1 / K and outputs an attenuation reference signal, and is output from the pixel And an AD converter that performs AD (Analog-to-Digital) conversion of the electrical signal by comparing the electrical signal with the attenuated reference signal.

An image sensor driving method according to an embodiment of the present technology includes a photoelectric conversion element that performs photoelectric conversion, the image sensor including a pixel that outputs an electrical signal and a reference signal output unit that outputs a reference signal whose level changes. An amplified reference signal obtained by amplifying the reference signal with an amplification factor of 1 or more times K is output, the amplified reference signal is attenuated by an attenuation factor of 1 / K, and an attenuated reference signal is output from the pixel. The driving method includes a step of performing AD (Analog-to-Digital) conversion of the electrical signal by comparing the output electrical signal with the attenuated reference signal.

An electronic apparatus according to an embodiment of the present technology includes an optical system that collects light and an image sensor that receives light and picks up an image. The image sensor includes a photoelectric conversion element that performs photoelectric conversion, and outputs an electrical signal. A reference signal output unit that outputs a reference signal whose level changes, an amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more, and the amplification reference The signal is attenuated by an attenuation factor of 1 / K times, and an attenuation unit that outputs an attenuation reference signal is compared with the electric signal output from the pixel and the attenuation reference signal. And an AD converter that performs AD (Analog-to-Digital) conversion.

An AD conversion apparatus of the present technology, a reference signal output unit that outputs a reference signal whose level changes, an amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times, and The AD conversion apparatus includes an attenuator that attenuates the amplified reference signal at an attenuation factor of 1 / K and outputs an attenuated reference signal, an electric signal, and a comparator that compares the attenuated reference signal.

In the present technology, an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more is output, and the amplified reference signal is attenuated by an attenuation factor of 1 / K, so that an attenuated reference signal is obtained. Is output. Then, AD conversion of the electrical signal is performed by comparing the electrical signal with the attenuated reference signal.

Note that the image sensor and the AD conversion device may be independent devices or may be internal blocks constituting one device.

According to the present technology, the noise of the reference signal can be reduced.

It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram which shows the structural example of one Embodiment of the digital camera to which this technique is applied. 2 is a block diagram illustrating a configuration example of an image sensor 2. FIG. It is a circuit diagram which shows the structural example of the pixel _{11m, n} . It is a block diagram showing a configuration example of ADC 31 _n. It is a block diagram showing a configuration example of the comparator 61 _n. It is a wave form diagram which shows the example of a VSL signal and a reference signal. It is a figure explaining the noise contained in a reference signal. It is a figure explaining the noise contained in a reference signal. It is a block diagram which shows the 1st structural example of the column parallel AD conversion part 22 which reduces reference signal noise RN_REF. It is a block diagram which shows the 2nd structural example of the column parallel AD conversion part 22 which reduces reference signal noise RN_REF. 6 is a flowchart for explaining an example of the operation of the column parallel AD conversion unit 22. It is a circuit diagram showing a configuration example of the attenuation section 111 _n. 3 is a circuit diagram illustrating a first configuration example of a reference signal output unit 33. FIG. 6 is a circuit diagram illustrating a second configuration example of a reference signal output unit 33. FIG. It is a wave form diagram which shows the example of a reference signal, an amplification reference signal, and an attenuation | damping reference signal. It is a figure which shows the example of the relationship between the ISO sensitivity set to the digital camera, and the amplification attenuation parameter K. It is a flowchart explaining the example of the process which sets the amplification attenuation parameter K according to ISO sensitivity. It is a block diagram which shows the structural example of one embodiment of a computer.

FIG. 1 is a block diagram illustrating a configuration example of an embodiment of a digital camera to which the present technology is applied.

Note that the digital camera can capture both still images and moving images.

1, the digital camera includes an optical system 1, an image sensor 2, a memory 3, a signal processing unit 4, an output unit 5, and a control unit 6.

The optical system 1 has, for example, a zoom lens, a focus lens, a diaphragm, and the like (not shown), and makes light from the outside enter the image sensor 2.

The image sensor 2 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor that receives incident light from the optical system 1, performs photoelectric conversion, and outputs image data corresponding to the incident light from the optical system 1. To do.

The memory 3 temporarily stores image data output from the image sensor 2.

The signal processing unit 4 performs processing such as noise removal and white balance adjustment as signal processing using the image data stored in the memory 3 and supplies the processed signal to the output unit 5.

The output unit 5 outputs the image data from the signal processing unit 4.

That is, the output unit 5 has a display (not shown) made of, for example, liquid crystal, and displays an image corresponding to the image data from the signal processing unit 4 as a so-called through image.

The output unit 5 includes a driver (not shown) that drives a recording medium such as a semiconductor memory, a magnetic disk, or an optical disk, and records the image data from the signal processing unit 4 on the recording medium.

The control unit 6 controls each block constituting the digital camera in accordance with a user operation or the like.

In the digital camera configured as described above, the image sensor 2 receives incident light from the optical system 1 and outputs image data according to the incident light.

The image data output from the image sensor 2 is supplied to and stored in the memory 3. The image data stored in the memory 3 is subjected to signal processing by the signal processing unit 4, and the resulting image data is supplied to the output unit 5 and output.

FIG. 2 is a block diagram showing a configuration example of the image sensor 2 of FIG.

2, the image sensor 2 includes a pixel array 10, a control unit 20, a pixel driving unit 21, a column parallel AD conversion unit 22, and an output unit 23.

The pixel array 10 includes M ×

N pixels

11 _1,1 , 11 _1,2 ,..., 11 _{1, N} , 11 _2,1,. _{_{_{11 2,2, ···, 11 2,}}} N, ···, 11 M, 1, 11 M, 2, ···, 11 M, has a _N, imaging unit for capturing an image (image pickup device) Function as.

M × N pixels 11 _1,1 to 11 _{M, N} are arranged in a matrix (lattice) of M rows and N columns on a two-dimensional plane.

N pixels 11 _{m, 1} to 11 _{m, N} arranged in the row direction (lateral direction) of the m-th row (m = 1, 2,..., M) (from the top) of the pixel array 10 include: pixel control line 41 _m extending in the row direction are connected.

Further, (left) n-th column (n = 1,2, ···, N ) M pixels _{11 1} arranged in the column direction (vertical direction) _{of, n} to _{11 M,} the _n, the column direction An extending VSL (Vertical Signal Line) 42 _n is connected.

The pixels 11 _{m and n} perform photoelectric conversion of light (incident light) incident thereon. Furthermore, the pixel 11 _{m, n} is the voltage corresponding to the charges obtained by photoelectric conversion (electrical signal), from the pixel driver 21, under the control of via the pixel control line 41 _m, the current source 43 _n is connected Is output on the VSL 42 _n .

Note that the pixels 11 _{m, n} can perform photoelectric conversion of light of a predetermined color that enters through a color filter (not shown) such as a Bayer array.

The control unit 20 controls the pixel driving unit 21, the column parallel AD conversion unit 22 (the auto zero control unit 32, the reference signal output unit 33, and the like) and other necessary blocks according to a predetermined logic or the like.

Pixel driver 21, under the control of the control unit 20, via the pixel control line 41 _m, to the pixels _{11 m, 1} not connected to the pixel control line 41 _m _{11 m,} and controls the _N (drive).

The column parallel AD converter 22 is connected to each of the pixels 11 _{m, 1} to 11 _{m, N} arranged in a row via the VSLs 42 ₁ to 42 _N , and therefore the pixels 11 _{m, n} are output on the VSL 42 _n. An electrical signal (voltage) (hereinafter also referred to as a VSL signal) is supplied to the column parallel AD conversion unit 22.

The column parallel AD conversion unit 22 performs parallel AD conversion of VSL signals supplied from the pixels 11 _{m, 1} to 11 _{m, N} arranged in a row via the VSLs 42 ₁ to 42 _N in parallel. The digital data obtained as a result of AD conversion is supplied to the output unit 23 as pixel values (pixel data) of the pixels 11 _{m, 1} to 11 _{m, N.}

Here, the column parallel AD conversion unit 22 performs AD conversion of all the electric signals of _N pixels 11 _{m, 1} to 11 _{m, N} arranged in a row in parallel, and also the N pixels 11 _{m, 1.} _Furthermore, AD conversion of electrical signals of one or more pixels of less than N out of 11 _{m and N} can be performed in parallel.

However, in the following, in order to simplify the description, the column parallel AD conversion unit 22 performs AD conversion of all VSL signals of _N pixels 11 _{m, 1} to 11 _{m, N} arranged in a row in parallel. To do.

The column parallel AD conversion unit 22 performs N ADC (Analog to Digital Converter) 31 in order to perform AD conversion of all the VSL signals of _N pixels 11 _{m, 1} to 11 _{m, N} arranged in a row in parallel. ₁ to 31 _N.

Further, the column parallel AD conversion unit 22 includes an auto zero control unit 32, a reference signal output unit 33, and a clock output unit 34.

Auto-zero control unit 32 includes the ADC 31 _n, the auto-zero pulse is a signal for controlling the autozero process described later comparator 61 _n, via the auto-zero control line 32A, is supplied (output) to the ADC 31 ₁ through 31 _N .

The reference signal output unit 33 is composed of, for example, a DAC (Digital to Analog Converter), and the level (voltage) changes from a predetermined initial value to a predetermined final value with a constant slope like a ramp signal. A reference signal having a period is supplied (output) to the ADCs 31 ₁ to 31 _N via the reference signal line 33A.

The clock output unit 34 supplies (outputs) a clock having a predetermined frequency to the ADCs 31 ₁ to 31 _N via the clock line 34A.

The ADC 31 _n is connected to the VSL 41 _n , and therefore, the ADC 31 _n is supplied with a VSL signal (electric signal) output from the pixel 11 _m, _n on the VSL 41 _n .

The ADC 31 _n performs AD conversion of the VSL signal output from the pixels 11 _{m and n} using the reference signal from the reference signal output unit 33 and the clock from the clock output unit 34, and further performs CDS (Correlated Double Sampling). ) To obtain digital data as pixel values.

Here, the ADC 31 _n compares the VSL signal of the pixel 11 _{m, n} with the reference signal from the reference signal output unit 33 until the level of the VSL signal of the pixel 11 _{m, n} matches the level of the reference signal. By counting the time required for the change in the level of the reference signal (until the magnitude relationship between the VSL signal and the reference signal is reversed), AD conversion of the VSL signal of the pixels 11 _{m and n} is performed.

In the ADC 31 _n , the time required to change the level of the reference signal until the level of the VSL signal of the pixel 11 _{m, n} matches the level of the reference signal is counted by counting the clock from the clock output unit 34. Is called.

In addition, the N ADCs 31 ₁ to 31 _N receive the VSL signals of _{the N} pixels 11 _{m, 1} to 11 _{m, N in} the _first to Mth rows of the pixel array 10, for example, the first row. Are sequentially supplied, and AD conversion and CDS of the VSL signal are performed in units of rows.

The output unit 23 selects the column n from which the pixel value is read, and reads the AD conversion (and CDS) result of the pixel 11 _{m, n} obtained by the ADC 31 _n as the pixel value from the ADC 31 _{n of} the column n. And output to the outside (in this embodiment, the memory 3 (FIG. 1)).

Here, the ADC 31 _n performs CDS in addition to AD conversion. However, the ADC 31 _n performs only AD conversion, and CDS can be performed by the output unit 23.

In the following, explanation of CDS will be omitted as appropriate.

FIG. 3 is a circuit diagram showing a configuration example of the pixels _{11m, n} in FIG.

In FIG. 3, the pixel 11 _{m, n} includes a PD 51 and four NMOS (negative channel MOS) FETs (Field Effect Transistors) 52, 54, 55, and 56.

Further, in the pixel 11m _{, n} , the drain of the FET 52, the source of the FET 54, and the gate of the FET 55 are connected, and an FD (Floating Diffusion) (capacitance) for converting charges into voltage is connected to the connection point. ) 53 is formed.

The PD 51 is an example of a photoelectric conversion element that performs photoelectric conversion, and performs photoelectric conversion by receiving incident light and charging a charge corresponding to the incident light.

The anode of the PD 51 is connected (grounded) to the ground, and the cathode of the PD 51 is connected to the source of the FET 52.

The FET 52 is an FET for transferring the charge charged in the PD 51 from the PD 51 to the FD 53, and is also referred to as a transfer Tr 52 hereinafter.

The source of the transfer Tr 52 is connected to the cathode of the PD 51, and the drain of the transfer Tr 52 is connected to the source of the FET 54 via the FD 53.

The gate of the transfer Tr52 is connected to the pixel control line 41 _m, the gate of the transfer Tr52 via the pixel control line 41 _m, the transfer pulse TRG is supplied.

Here, the pixel driving unit 21 (FIG. 2), via a pixel control line 41 _m, the pixel _{11 m, n} and for driving (control), the control signal to be supplied to the pixel control line 41 _m, the transfer pulse In addition to TRG, there are a reset pulse RST and a selection pulse SEL which will be described later.

The FD 53 is a region that converts charges into voltage like a capacitor formed at the connection point of the drain of the transfer Tr 52, the source of the FET 54, and the gate of the FET 55.

The FET 54 is an FET for resetting the charge (voltage (potential)) charged in the FD 53, and is also referred to as a reset Tr 54 hereinafter.

The drain of the reset Tr54 is connected to the power supply Vdd.

The gate of the reset Tr54 is connected to the pixel control line 41 _m, the gate of the reset Tr54, via a pixel control line 41 _m, the reset pulse RST is supplied.

The FET 55 is an FET for buffering the voltage of the FD 53, and is hereinafter also referred to as an amplifying Tr 55.

The gate of the amplification Tr55 is connected to the FD 53, and the drain of the amplification Tr55 is connected to the power supply Vdd. The source of the amplifying Tr 55 is connected to the drain of the FET 56.

The FET 56 is an FET for selecting an output of an electric signal (VSL signal) to the VSL 42 _n , and is hereinafter also referred to as a selection Tr 56.

The source of the selection Tr 56 is connected to the VSL 42 _n .

The gate of the selection Tr56 is connected to the pixel control line 41 _m, the gate of the selection Tr56, via a pixel control line 41 _m, a selection pulse SEL is supplied.

Here, the source of the amplifying Tr 55 is connected to the current source 43 _n via the selection Tr 56 and the VSL 42 _n , so that the SF (Source Follower) (circuit) is configured by the amplifying Tr 55 and the current source 43 _n . Therefore, the FD 53 is connected to the VSL 42 _n via the SF.

Note that the pixels 11 _{m and n} can be configured without the selection Tr 56.

Further, as the configuration of the pixels 11 _{m, n,} a configuration of a shared pixel in which the FD 53 or the selection Tr 56 is shared by the plurality of PDs 51 and the transfer Tr 52 can be employed.

In the pixel 11m _{, n} configured as described above, the PD 51 receives light incident thereon and performs photoelectric conversion, thereby starting charge charging according to the amount of received incident light. Here, in order to simplify the description, it is assumed that the selection pulse SEL is at the H level and the selection Tr 56 is in the ON state.

When a predetermined time (exposure time) has elapsed since the start of charge charging in the PD 51, the pixel drive unit 21 (FIG. 2) temporarily transfers the transfer pulse TRG (from the L (Low) level). Set to H (High) level.

When the transfer pulse TRG temporarily becomes H level, the transfer Tr 52 is temporarily turned on.

When the transfer Tr 52 is turned on, the charge charged in the PD 51 is transferred to the FD 53 via the transfer Tr 52 and charged.

The pixel driving unit 21 temporarily sets the reset pulse RST to the H level before temporarily setting the transfer pulse TRG to the H level, whereby the reset Tr 54 is temporarily turned on.

When the reset Tr 54 is turned on, the FD 53 is connected to the power supply Vdd via the reset Tr 54, and the charge in the FD 53 is swept out to the power supply Vdd via the reset Tr 54 and reset.

Here, as described above, when the FD 53 is connected to the power supply Vdd and the charge in the FD 53 is reset, the pixels 11 _{m and n} are reset.

After the charge of the FD 53 is reset, the pixel driving unit 21 temporarily sets the transfer pulse TRG to the H level as described above, and thereby the transfer Tr 52 is temporarily turned on.

When the transfer Tr 52 is turned on, the charge charged in the PD 51 is transferred to the FD 53 after reset via the transfer Tr 52 and charged.

A voltage (potential) corresponding to the electric charge charged in the FD 53 is output on the VSL 42 _n as the VSL signal via the amplification Tr 55 and the selection Tr 56.

In VSL42 _n in the connected ADC 31 n _(Fig. 2), the reset level is VSL signal immediately after the pixel 11 _m, reset _n has been performed is AD converted.

Further, in the ADC 31 _n , the signal level (the reset level, the pixel value, and the VSL signal (the voltage corresponding to the charge charged in the PD 51 and transferred to the FD 53) after the transfer Tr 52 is temporarily turned on) Are converted to AD.

In the ADC 31 _n , the CDS for obtaining the difference between the AD conversion result of the reset level (hereinafter also referred to as reset level AD value) and the AD conversion result of the signal level (hereinafter also referred to as signal level AD value) as a pixel value. Is done.

FIG. 4 is a block diagram illustrating a configuration example of the ADC 31 _n of FIG.

The ADC 31 _n includes a comparator 61 _n and a counter 62 _n , and performs reference signal comparison AD conversion and CDS.

The comparator 61 _n has two input terminals, an inverting input terminal (−) and a non-inverting input terminal (+).

One of the input terminals inverting input terminal of the two input terminals of the comparator 61 _n (-), the reference signal from the reference signal output unit 33, and the pixel 11 _{m, n} VSL signal (reset level, For example, a reference signal is supplied. The non-inverting input terminal (+) which is the other input terminal of the two input terminals of the comparator 61 _n is connected to the reference signal from the reference signal output unit 33 and the VSL signals of the pixels 11 _{m and n} . The other, for example, a VSL signal is supplied.

The comparator 61 _n compares the reference signal supplied to the inverting input terminal with the VSL signal supplied to the non-inverting input terminal, and outputs the comparison result.

That is, the comparator 61 _n is one of the H and L levels when the reference signal supplied to the inverting input terminal is larger than the VSL signal supplied to the non-inverting input terminal, for example, the L level. Is output.

Further, the comparator 61 _n sets the H level, which is the other of the H and L levels, when the VSL signal supplied to the non-inverting input terminal is larger than the voltage of the reference signal supplied to the inverting input terminal. Output.

Note that an auto zero pulse is supplied from the auto zero control unit 32 to the comparator 61 _n via the auto zero control line 32A. The comparator 61 _n performs auto zero processing according to the auto zero pulse from the auto zero control unit 32.

Here, in the auto zero process, the comparator 61 _n, 2 two input signals being given currently to the comparator 61 _n, i.e., a signal that is currently supplied to the inverting input terminal of the comparator 61 _n, to the non-inverting input terminal The comparator 61 _n is set so that a comparison result indicating that the currently supplied signal matches is obtained.

The counter 62 _n is supplied with the output of the comparator 61 _n and the clock from the clock output unit 34.

For example, the counter 62 _n starts counting the clock from the clock output unit 34 at the timing when the reference signal (level) supplied from the reference signal output unit 33 to the comparator 61 _n starts to change, and the comparator 61 _n For example, when the level of the reference signal supplied to the inverting input terminal of the comparator 61 _n is equal to the level of the VSL signal supplied to the non-inverting input terminal (reference signal). When the magnitude relationship between the VSL signal and the VSL signal is reversed), the clock count from the clock output unit 34 is terminated.

Then, the counter 62 _n outputs the clock count value as the AD conversion result of the VSL signal supplied to the non-inverting input terminal of the comparator 61 _n .

Here, the reference signal output unit 33 outputs, for example, a signal having a slope (slope-shaped waveform) in which the voltage decreases at a constant rate from a predetermined initial value to a predetermined final value as the reference signal. .

In this case, the counter 62 _n counts the time from the start of the slope until the reference signal changes to a voltage matching the VSL signal supplied to the non-inverting input terminal of the comparator 61 _n , and is obtained by the count. count value is an AD conversion result of the VSL signal supplied to the non-inverting input terminal of the comparator 61 _n.

The ADC 31 _n obtains the reset level as a VSL signal supplied from the pixel 11 _{m, n} to the non-inverting input terminal of the comparator 61 _n and the AD conversion result of the signal level. Then, the ADC 31 _n performs CDS for obtaining a difference between the AD conversion result (signal level AD value) of the signal level and the AD conversion result (reset level AD value) of the reset level, and the difference obtained by the CDS is calculated as a pixel. Output as 11 _{m, n} pixel values.

Note that in the ADC 31 _n , the CDS is performed by actually executing a calculation for obtaining a difference between the signal level AD value and the reset level AD value, and for example, by controlling the clock count in the counter 62 _n. be able to.

That is, in the counter 62 _n , for example, for the reset level, the clock is counted while the count value is decremented by one, and for the signal level, the count value is set with the clock count value for the reset level as an initial value. Contrary to the case of the reset level, by counting the clock while incrementing by one, the AD conversion of the reset level and the signal level is performed, and the signal level (the AD conversion result) and the reset level ( CDS can be performed to obtain the difference from the AD conversion result.

In this embodiment, a ramp signal having a slope that decreases at a constant rate is employed as the reference signal. However, for example, the reference signal has a slope that increases at a constant rate. A ramp signal or the like can be employed.

Figure 5 is a block diagram showing a configuration example of the comparator 61 _n of FIG.

The comparator 61 _n includes

capacitor circuits

71 and 72, a differential amplifier 73, and an output amplifier 74.

Capacitor circuits

71 and 72 are capacitors used for auto-zero processing.

One end of the capacitor as the capacitor circuit 71 is connected to the gate of FET81 of the differential amplifier 73, the other end, an inverting input terminal IN1 of the comparator 61 _n - is connected to ().

One end of the capacitor as the capacitor circuit 72 is connected to the gate of FET82 of the differential amplifier 73, the other end is connected to the non-inverting input terminal IN2 of the comparator 61 _n (+).

In the auto-zero processing, the

capacitor circuits

71 and 72 have the same voltage as the signal supplied to the gate of the FET 81 via the capacitor circuit 71 and the signal supplied to the gate of the FET 82 via the capacitor circuit 72. As such, charge is charged.

The capacitor circuit 71 offsets the signal (reference signal) supplied from the inverting input terminal IN1 by a voltage corresponding to the charge charged during the auto-zero process, and supplies it to the gate of the FET 81. Similarly, the capacitor circuit 72 offsets the signal (VSL signal) supplied from the non-inverting input terminal IN2 by a voltage corresponding to the charge charged during the auto-zero process and supplies the signal to the gate of the FET 82.

A reference signal is supplied to the differential amplifier 73 via the inverting input terminal IN1 and the capacitor circuit 71, and a VSL signal is supplied via the non-inverting input terminal IN2 and the capacitor circuit 72. .

The differential amplifier 73 outputs a comparison result signal representing a comparison result obtained by comparing the reference signal, which is the two signals supplied thereto, and the VSL signal to the output amplifier 74 as a differential output. That is, the differential amplifier 73 outputs a signal corresponding to the difference between the reference signal and the VSL signal as a differential output.

The output amplifier 74 functions as a buffer that buffers the differential output in order to output the differential output (comparison result signal) output from the differential amplifier 73 to a circuit at the subsequent stage at an appropriate level.

That is, the output amplifier 74 amplifies the differential output (comparison result signal) output from the differential amplifier 73 with a predetermined gain, and outputs a signal obtained as a result of the amplification as an amplifier output.

The amplifier output of the output amplifier 74 is supplied to the counter 62 _n (FIG. 4) as a final output signal of the comparator 61 _n representing the comparison result obtained by comparing the reference signal and the VSL signal.

As described above, the counter 62 _n counts the clock from the clock output unit 34 and ends the clock counting according to the output of the comparator 61 _n . Then, the counter 62 _n outputs the count value of the clock as the AD conversion result of the VSL signal supplied to the comparator 61 _n (the differential amplifier 73).

Here, in FIG. 5, the differential amplifier 73 includes

FETs

81, 82, 83, and 84, switches 85 and 86, and a current source 89.

FET 81 and FET 82 are NMOS (Negative Channel Channel MOS) FETs, and their sources are connected to each other. Further, the connection point between the sources of the FET 81 and the FET 82 is connected to the other end of the current source 89 whose one end is grounded. The FET 81 and FET 82 constitute a so-called differential pair.

The gate of the FET 81 is connected to the inverting input terminal IN1 of the comparator 61 _n (differential amplifier 73) through the capacitor circuit 71, and the gate of the FET 82 is connected to the comparator 61 _n (differential amplifier 73 through the capacitor circuit 72). ) Is connected to the non-inverting input terminal IN2.

As described above, the comparator 61 _n has a differential pair composed of the FET 81 and the FET 82 in the input stage.

FET 83 and FET 84 are PMOS (Positive Channel MOS) FETs, and their gates are connected to each other.

Further, the sources of the FET 83 and the FET 84 are connected to the power source Vdd, and the connection point between the gates of the FET 83 and the FET 84 is connected to the drain of the FET 83. Therefore, the FET 83 and the FET 84 constitute a current mirror.

Of the FET 83 and FET 84 constituting the current mirror, the drain of the FET 83 is connected to the drain of the FET 81, and the drain of the FET 84 is connected to the drain of the FET 82.

The connection point between the drains of the FET 82 and the FET 84 is connected to the output terminal OUTd of the differential amplifier 73.

The switch 85 and the switch 86 are switches composed of, for example, FETs, and are turned on or off according to the auto zero pulse supplied from the auto zero control unit 32.

That is, the switch 85 is turned on or off so as to connect or disconnect between the gate and drain of the FET 81 according to the auto-zero pulse. The switch 86 is turned on or off to connect or disconnect the gate and drain of the FET 82 in response to the auto-zero pulse.

5, the output amplifier 74 includes

FETs

91 and 92, a switch 93, and a capacitor 94.

The FET 91 is a PMOS FET, and its gate is connected to the output terminal OUTd of the differential amplifier 73. The source of the FET 91 is connected to the power supply Vdd, and the drain is connected to the drain of the FET 92.

FET 92 is an NMOS FET and functions as a current source. The gate of the FET 92 is connected to one end of the capacitor 94, and the source is grounded.

The switch 93 is a switch composed of, for example, an FET or the like, and is turned on or off according to the auto zero pulse supplied from the auto zero control unit 32.

That is, the switch 93 is turned on or off so as to connect or disconnect between the gate and the drain of the FET 92 according to the auto-zero pulse.

One end of the capacitor 94 is connected to the gate of the FET 92, and the other end is grounded.

The connection point between the drain of the FET 91 and the drain of the FET 92 is connected to the output terminal OUT1 of the output amplifier 74, and the voltage at the connection point between the drain of the FET 91 and the drain of the FET 92 is output from the output terminal OUT1 to the amplifier output. Is output as

In the comparator 61 _n configured as described above, the current i ₁ corresponding to the gate voltage of the FET 81 flows through the FET 81 (from the drain to the source) of the differential amplifier 73, and the FET 82 (from the drain to the source) A current i ₂ corresponding to the gate voltage of the FET 82 flows.

Further, the same current as the current i ₁ flowing in the FET 81 flows in the FET 83 and the FET 84 (from the source to the drain) constituting the current mirror.

The voltage applied to the gate of the FET 81 from the inverting input terminal IN1 through the capacitor circuit 71 (the gate voltage of the FET 81) is applied to the gate of the FET 82 from the non-inverting input terminal IN2 through the capacitor circuit 72 (of the FET 82). If it is greater than the gate voltage), the current i ₁ flowing through the FET 81 is larger than the current i ₂ flowing through the FET 82.

In this case, the same current as the current i ₁ flowing through the FET 81 flows through the FET 84, but the current i ₂ flowing through the FET 82 connected to the FET 84 is smaller than the current i _1. In order to increase i ₂ , the drain-source voltage increases.

As a result, the differential output of the output terminal OUTd, which is the connection point between the

FETs

82 and 84, becomes H level.

On the other hand, when the gate voltage of the FET 82 is larger than the gate voltage of the FET 81, the current i ₂ flowing through the FET 82 becomes larger than the current i ₁ flowing through the FET 81.

In this case, the same current as the current i ₁ flowing through the FET 81 flows through the FET 84, but the current i ₂ flowing through the FET 82 connected to the FET 84 is larger than the current i _1. The drain-source voltage is decreased in an attempt to decrease i ₂ .

FETs

82 and 84, becomes L level.

The differential output of the output terminal OUTd is supplied to the gate of the FET 91 of the output amplifier 74.

In the output amplifier 74, the FET 92 functions as a current source, and when the differential output supplied to the gate of the FET 91 is at the H level, the FET 91 is turned off.

When the FET 91 is off, the drain of the FET 91 is at L level, and therefore the amplifier output at the output terminal OUT1 is at L level.

On the other hand, when the differential output supplied to the gate of the FET 91 is at the L level, the FET 91 is turned on.

When FET 91 is on, the drain of FET 91 is at H level, and therefore the amplifier output at output terminal OUT1 is at H level.

From the above, the reference signal supplied to the inverting input terminal IN1, than VSL signal supplied to the non-inverting input terminal IN2, when the voltage is high, the amplifier output of the output terminal OUT1, i.e., the comparator 61 _n output Becomes L level.

On the other hand, VSL signal supplied to the non-inverting input terminal IN2 is than the reference signal supplied to the inverting input terminal IN1, when the voltage is high, the amplifier output of the output terminal OUT1 (output of the comparator 61 _n) is Become H level.

Here, the

switches

85, 86, and 93 are turned on or off according to the auto-zero pulse.

The auto zero pulse is, for example, a pulse that temporarily changes from the L level to the H level, and the

switches

85 and 86 are turned off when the auto zero pulse is at the L level, and are turned on when the auto zero pulse is at the H level. become.

When the

switches

85 and 86 are turned on, the gate and drain of the FET 81 are connected, the gate and drain of the FET 82 are connected, and the gate voltages of the

FETs

81 and 82 are the same.

Therefore, when the auto-zero pulse becomes H level, the voltage applied to the gate of the FET 81 from the inverting input terminal IN1 through the capacitor circuit 71 (the gate voltage of the FET 81), and the voltage from the non-inverting input terminal IN2 through the capacitor circuit 72. Thus, the

capacitor circuits

71 and 72 are charged with electric charges so that the voltage applied to the gate of the FET 82 (the gate voltage of the FET 82) matches.

When the auto zero pulse becomes L level, the connection between the gate and drain of the FET 81 is disconnected and the connection between the gate and drain of the FET 82 is disconnected. In the

capacitor circuits

71 and 72, the electric charge charged when the auto-zero pulse is at the H level is maintained.

As a result, the comparator 61 _n (the differential amplifier 73) has two input signals given to the comparator 61 _n when the auto zero pulse is at the H level (when the auto zero pulse falls), that is, a reference signal being supplied to the inverting input terminal IN1 of the comparator 61 _n, the non-inverting input VSL signal supplied to the terminal IN2 and the comparison result indicating that a match is set so as to obtain.

The setting of the comparator 61 _n as described above is performed in the auto zero process.

According to the auto zero process, differential amplifier 73, thus, the comparator 61 _n, when the auto-zero process, a voltage which has been applied to the inverting input terminal IN1 of the comparator 61 _n, voltage and which has been applied to the non-inverting input terminal IN2 Can be determined based on the fact that they match each other as a reference between the voltage applied to the inverting input terminal IN1 and the voltage applied to the non-inverting input terminal IN2.

In the output amplifier 74, as in the

switches

85 and 86, the switch 93 is turned off when the auto zero pulse is at the L level and turned on when the auto zero pulse is at the H level.

When the switch 93 is turned on, the capacitor 94 is charged to a voltage equal to the drain voltage of the FET 92. After that, when the switch 93 is turned off, the voltage of the capacitor 94 is applied to the gate of the FET 92, and the FET 92 functions as a current source for supplying the same current as that flowing when the switch 93 is turned on.

FIG. 6 is a diagram for explaining the operation of the image sensor 2 (FIG. 2).

In FIG. 6, the horizontal axis represents time, and the vertical axis represents voltage.

6, the image sensor 2, the pixel _{11 m,} from _n, VSL42 through _n, ADC 31 _n of the comparator 61 the non-inverting input terminal IN2 (+) VSL signal is an electrical signal supplied to the (a voltage of the _n ) And a reference signal (voltage) supplied from the reference signal output unit 32 to the inverting input terminal IN1 (−) of the comparator 61 _n of the ADC 31 _n via the reference signal line 33A. is there.

In FIG. 6, together with the VSL signal and the reference signal, the transfer pulse TRG given to the transfer Tr 52 (FIG. 3) (the gate thereof), the reset pulse RST given to the reset Tr 54, the auto zero control unit 32 to the comparator 61 _n ( The auto zero pulse given to the

switches

85, 86 and 93 in FIG. 5), the differential output of the output terminal OUTd of the differential amplifier 73 (FIG. 5), and the amplifier output of the output terminal OUT1 of the output amplifier 74 are It is shown.

In FIG. 6, the VSL signal indicates the voltage applied to the gate of the FET 81 of the comparator 61 _n (FIG. 5) (not the voltage itself on the VSL 42 _n ). rather than voltage itself on 34A,) it shows a voltage applied to the gate of FET82 comparator 61 _n. The same applies to the drawings described later.

In the image sensor 2, the reset pulse RST is temporarily set to the H level, whereby the pixels _{11m and n} are reset.

In resetting the pixel 11 _{m, n} , as described with reference to FIG. 3, the FD 53 is connected to the power source Vdd via the reset Tr 54, and the charge in the FD 53 is reset, so that the pixel 11 _{m, n} is output. In the pixel 11 _{m, n} , the voltage of the VSL signal on the VSL 42 _n output from the FD 53 via the amplification Tr 55 and the selection Tr 56 rises, and at time t ₁ , the voltage corresponding to the power supply Vdd Become.

VSL signal while the FD53 is connected to the power supply Vdd, and maintains a voltage corresponding to the power supply Vdd, then, at time t _2, the reset pulse RST becomes L level, the pixel 11 _m, some within _n As a result of the movement of the electric charge, a slight charge enters the FD 53, and as a result, the VSL signal drops slightly.

In FIG. 6, from time t ₂ when the reset pulse RST becomes L level to subsequent time t ₃ , the VSL signal slightly decreases due to the movement of charges generated in the pixels 11 _{m and n} .

As described above, the drop in the VSL signal that occurs after the pixels 11m _{, n} are reset may be referred to as reset feedthrough.

After the pixel 11 _{m, n} is reset (or during reset), the auto zero control unit 32 changes the auto zero pulse from the L level to the H level, thereby starting the auto zero processing of the comparator 61 _n (FIG. 4). .

6, at time t ₄ after the reset feedthrough occurs, the auto-zero pulse is from H level to L level, Odozero processing of the comparator 61 _n is started. Thereafter, at time t _5, by auto-zero pulse is from H level to L level, the auto zero processing of the comparator 61 _n is finished (completed).

According to such auto-zero processing, on the basis that the VSL signal applied to the comparator 61 _n matches the reference signal at time t ₅ which is the timing of the falling edge of the auto-zero pulse, The comparator 61 _n (differential amplifier 73) is set so that the magnitude relationship with the reference signal can be determined (compared).

In FIG. 6, the auto zero process is completed after the pixels 11 _{m, n} are reset.

In this case, the magnitude relationship between the VSL signal and the reference signal is determined based on the fact that the reference signal and the voltage lowered by the reset feedthrough from the VSL signal during reset of the pixels 11 _{m and n} match. as can be, the comparator 61 _n is set.

As a result, the reference signal (waveform thereof) is arranged at a position based on the voltage that is lowered by the reset feedthrough from the VSL signal during resetting of the pixels 11m _{, n} .

Reference signal output unit 33 (FIG. 4) at time t ₆ after the auto zero processing is completed (end), the reference signal is increased by a predetermined voltage.

Here, the time t ₆ after the auto zero process has finished, a reference signal, to be raised by a predetermined voltage, hereinafter also referred to as start offset.

Further, the reference signal output unit 33 reduces the voltage of the reference signal at a constant rate for AD conversion of the VSL signal, but the voltage of the reference signal decreases at a constant rate. The portion of the reference signal is also called a slope.

Reference signal output unit 33 at time t _6, a reference signal, and the direction of the slope (direction in which the voltage of the reference signal will change) in the reverse direction to perform the starting offset to be offset by a predetermined voltage.

Then, the reference signal output section 33, a certain period from time t ₇ to the time t _9, the voltage of the reference signal, (gradually lowered) gradually reduced at a constant rate.

Therefore, the reference signal in the period from the time t ₇ to the time t ₉ forms a slope.

Slope of the reference signal in the period from the time t ₇ to the time t _9, the reset level (pixel 11 _{m, n} reset immediately after the VSL signal (pixel 11 m of the VSL _{signal, n} is reset, by the reset feedthrough the VSL signal)) after the voltage drop has occurred is the slope for AD conversion, below, the duration of the slope (the period from time t ₇ to the time t _9), also referred to as P (Preset) phase. The slope of the P phase is also referred to as the P phase slope.

Here, the comparator 61 _n is set so that the VSL signal and the reference signal at the time of auto-zero processing coincide with each other by the auto-zero processing after resetting the pixels 11 _{m, n} , and thus the auto-zero processing is completed. At time t ₆ after the reference signal is, according to the starting offset is increased by a predetermined voltage, the reference signal voltage is greater than VSL signal (reset level). Therefore, the comparator 61 _n outputs a comparison result indicating that the reference signal is larger than the VSL signal at the P-phase start time t ₇ .

That is, the differential output of the differential amplifier 73 becomes H level, and the amplifier output of the output amplifier 74 becomes L level.

For example, the counter 62 _n of the ADC 31 _n (FIG. 4) starts clock counting from the start time t ₇ of the P-phase slope.

In the P phase, the reference signal (voltage) is gradually reduced, in FIG. 6, the magnitude of the at time t ₈ the P phase, the VSL signal as the reference signal and the reset level is matched, the reference signal and VSL signal The relationship is reversed from the beginning of phase P.

As a result, the comparison result output from the comparator 61 _n is reversed from the start of the P phase, and the comparator 61 _n starts outputting the comparison result indicating that the VSL signal as the reset level is larger than the reference signal. To do.

That is, the differential output of the differential amplifier 73 becomes L level, and the amplifier output of the output amplifier 74 becomes H level.

When the comparison result output by the comparator 61 _n is reversed, that is, when the amplifier output of the output amplifier 74 that is the output of the comparator 61 _n becomes H level, the counter 62 _n of the ADC 31 _n (FIG. 4) counts the clock. Then, the count value of the counter 62 _{n at} that time becomes the AD conversion result (reset level AD value) of the reset level.

After the end of the P phase, in the image sensor 2, the transfer pulse TRG is changed from the L level to the H level from time t ₁₀ to t ₁₁ , and as a result, in the pixel 11 _{m, n} (FIG. 3), photoelectric conversion is performed. The charge charged in the PD 51 is transferred to the FD 53 via the transfer Tr 52 and charged.

By charge from the PD51 to the FD 53 is charged, the voltage of the VSL signal corresponding to the electric charges charged in the FD 53 is lowered at time t _11, the transfer pulse TRG changes from the H level to the L level, the PD51 FD 53 When the transfer of the charge to the FD 53 ends, the VSL signal becomes a signal level (voltage) corresponding to the charge charged in the FD 53.

Also, after the end of the P phase, the reference signal output unit 33 (FIG. 4) raises the reference signal to the same voltage as at the start of the P phase, for example.

As described above, when the VSL signal becomes a voltage corresponding to the charge charged in the FD 53, or when the reference signal rises to the same voltage as that at the start of the P phase, the magnitude of the reference signal and the VSL signal is increased. The relationship is reversed again.

As a result, the differential output of the differential amplifier 73 becomes H level, and the amplifier output of the output amplifier 74 becomes L level.

Reference signal output unit 33 (FIG. 4) is a reference signal, after raising the beginning and the same voltage of the P phase, from a period of time (time t ₇ from the time t ₁₂ to time t ₁₄ to time t ₉ The reference signal voltage is decreased (decreased) at the same rate of change as in the case of the P phase.

Therefore, the reference signal during a period from the time t ₁₂ to time t _14, as well as the reference signal in the period from the time t ₇ to the time t _9, to form a slope.

Slope of the reference signal during a period from the time t ₁₂ to time t _14, in the signal level (pixel 11 m of the VSL _{signal, n (FIG.} 3), immediately after the charge from PD51 to FD53 transfer occurred the VSL signal) and the slope for AD conversion, below, the duration of the slope (during a period from the time t ₁₂ to time t _14), also referred to as D (Data) phase. The slope of D phase is also referred to as D phase slope.

Here, in the starting time t ₁₂ in the D phase, as in the case of starting time t ₇ in the P phase, the reference signal will greater than (voltage) of the VSL signal. Accordingly, the comparator 61 _n is the starting time t ₁₂ in the D phase, the reference signal, and outputs the comparison result indicating the larger than VSL signal.

Counter 62 _n of ADC 31 _n (Fig. 4) is, for example, from the start time t ₁₂ the D-phase slope starts counting the clock.

In the D phase, the reference signal (voltage) is gradually reduced, the magnitude of 6, at time t ₁₃ in the D phase, the VSL signal as the reference signal and the signal level matches the reference signal and VSL signal The relationship is reversed from the beginning of phase D.

As a result, the comparison result of the comparator 61 _n outputs, reversed from the start of the D-phase, comparator 61 _n is, VSL signal as a signal level, starting the comparison indicating than the reference signal is greater result output To do.

When the comparison result output from the comparator 61 _n is reversed and becomes H level, the counter 62 _n of the ADC 31 _n (FIG. 4) ends the clock counting. Then, the count value of the counter 62 _{n at} that time becomes a signal level AD conversion result (signal level AD value).

As described above, when the reset level AD value is obtained in the P phase and the signal level AD value is obtained in the D phase, the image sensor 2 obtains the difference between the reset level AD value and the signal level AD value. And the difference obtained as a result of the CDS is output as a pixel value.

7 and 8 are diagrams illustrating noise included in the reference signal.

FIG. 7 is a block diagram showing a configuration example of the column parallel AD conversion unit 22 in FIG.

In the figure, portions corresponding to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

7 shows the column parallel AD conversion unit 22 of FIG. 2 in a simplified manner.

That is, in FIG. 7, the auto zero control unit 32, the auto zero control line 32A, the clock output unit 34, and the clock line 34A are not shown, and the ADC 31 _n , the reference signal output unit 33, and the reference signal line 33A It is shown in the figure.

As shown in FIG. 7, the column parallel AD conversion unit 22 performs a plurality of AD conversions of VSL signals obtained from a plurality of pixels such as _N pixels 11 _{m, 1} to 11 _{m, N,} etc., for example, in one horizontal line. The reference signals output from the reference signal output unit 33 are shared among the N ADCs 31 ₁ to 31 _N.

In other words, the N ADCs 31 ₁ to 31 _N commonly use the reference signal supplied from the reference signal output unit 33 via the reference signal line 33A and use the N pixels _{11m, 1} to AD conversion of the VSL signal supplied from 11 _{m, N} via the VSL 42 ₁ to 42 _N is performed.

Therefore, when the noise (random noise) included in the reference signal is not sufficiently smaller than the noise (random noise) included in the VSL signal obtained from the pixels 11 _{m, n} , an image obtained from the image sensor 2 is obtained. In FIG. 2, horizontal streak-like noise correlated in the horizontal line direction appears to the extent that it can be visually observed, and the image quality deteriorates.

FIG. 8 is a block diagram illustrating a configuration example of the column parallel AD conversion unit 22 that schematically represents noise related to the column parallel AD conversion unit 22.

In FIG. 8, portions corresponding to those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

Also in FIG. 8, the column parallel AD conversion unit 22 is shown in a simplified manner as in FIG.

In FIG. 8, RN_REF represents noise (hereinafter also referred to as reference signal noise) included in the reference signal supplied from the reference signal output unit 33 to the ADCs 31 ₁ to 31 _N , and RN_SIG (n) represents the nth column. It represents noise (hereinafter also referred to as pixel noise) included in the VSL signal supplied from the pixels 11 _{m, n} to the ADC 31 _n .

Note that there is no correlation between the pixel noise RN_SIG (n) in a certain n-th column and the pixel noise RN_SIG (n ′) in another n′-th column.

As shown in FIG. 8, the ADC 31 _n, the reference signal including reference signal noise RN_REF, the VSL signal containing pixel noise RN_SIG (n) are supplied. Then, the ADC 31 _n performs AD conversion of the VSL signal using the reference signal.

In order to make the above-described horizontal streak noise generated in the image obtained from the image sensor 2 inconspicuous, generally, the level of the reference signal noise RN_REF is made smaller by about one digit than the level of the pixel noise RN_SIG (n). There is a need.

For example, since the reference signal is generated by the DAC constituting the reference signal output unit 33 built in the image sensor 2 constituted by one chip, the reference signal noise RN_REF included in the reference signal is the heat of the output of the DAC. Noise becomes dominant.

Therefore, as a method of reducing the reference signal noise RN_REF, there is a method of reducing the thermal noise of the DAC output. However, when the thermal noise of the DAC output is reduced, the current consumption of the DAC tends to increase.

Further, in the column-parallel AD converting unit 22, on the reference signal line 33A is a wiring path from the reference signal output section 33 to the ADC 31 _n, disturbance noise (coupling noise, etc.), which may be superimposed on the reference signal . Therefore, the reference signal noise RN_REF may include disturbance noise as described above in addition to random noise that is dominated by the thermal noise of the DAC output. Therefore, a design with great care is required.

Further, in recent years, the pixel noise RN_SIG (n) has been remarkably improved to about several e ⁻ , and the level allowed for the reference signal noise RN_REF has become severe.

FIG. 9 is a block diagram illustrating a first configuration example of the column parallel AD conversion unit 22 that reduces the reference signal noise RN_REF.

In FIG. 9, parts corresponding to those in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

Also in FIG. 9, the column parallel AD conversion unit 22 is shown in a simplified manner as in FIG.

The column parallel AD conversion unit 22 of FIG. 9 is common to the case of FIG. 8 in that it includes an ADC 31 _n , a reference signal output unit 33, and a reference signal line 33A.

However, the column parallel AD conversion unit 22 of FIG. 9 is different from the case of FIG. 8 in that an amplification unit 101 and an attenuation unit 102 are newly provided.

9, the amplification unit 101 is built in the reference signal output unit 33, and a reference signal (before the reference signal noise RN_REF is superimposed) is supplied to the amplification unit 101.

The amplifying unit 101 amplifies the reference signal supplied thereto at an amplification factor of K (> = 1) times, and outputs an amplified reference signal that is a reference signal after the amplification on the reference signal line 33A.

The attenuating unit 102 attenuates the amplified reference signal supplied from the amplifying unit 101 via the reference signal line 33A with an attenuation factor of 1 / K times the inverse of the amplification factor K, and the amplified reference signal after the attenuation. A certain attenuation reference signal is output on the reference signal line 33A.

Here, in FIG. 9, the attenuation unit 102 is provided immediately before the reference signal line 33A branches to the _N ADCs 31 ₁ to 31 _N , and the attenuation reference signal output by the attenuation unit 102 onto the reference signal line 33A. Is commonly supplied to _N ADCs 31 ₁ to 31 _N.

Therefore, in FIG. 9, the attenuation unit 102 is shared by _N ADCs 31 ₁ to 31 _N.

Comparative From the above, in FIG. 9, the damping unit 102 is a position on the reference signal line 33A that can be shared by the N ADC 31 ₁ through 31 _N, the VSL signal in the N ADC 31 ₁ through 31 _N It can be said that the amplified reference signal has been attenuated to the attenuated reference signal at a position immediately before being performed.

In the column parallel AD conversion unit 22 configured as described above, a reference signal is generated in the reference signal output unit 33, and the amplification unit 101 amplifies the reference signal with an amplification factor K, and the amplified reference obtained as a result The signal is output on the reference signal line 33A.

The amplified reference signal output from the amplification unit 101 onto the reference signal line 33A is supplied to the attenuation unit 102.

The attenuating unit 102 attenuates the amplified reference signal supplied thereto with an attenuation factor 1 / K, and outputs the attenuated reference signal obtained as a result on the reference signal line 33A.

The attenuation reference signal output from the attenuation unit 102 onto the reference signal line 33A is supplied in common to the _N ADCs 31 ₁ to 31 _N and is used for AD conversion of the VSL signal.

In other words, the ADC 31 _n compares the VSL signal output from the pixel 11 _{m, n} with the attenuated reference signal supplied from the attenuating unit 102, and attenuates the reference signal until the VSL signal and the attenuated reference signal match. The AD conversion of the VSL signal is performed by counting the time required for the change.

FIG. 10 is a block diagram illustrating a second configuration example of the column parallel AD conversion unit 22 that reduces the reference signal noise RN_REF.

In FIG. 10, portions corresponding to those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Also in FIG. 10, the column parallel AD conversion unit 22 is shown in a simplified manner as in FIG.

The column parallel AD conversion unit 22 of FIG. 10 is common to the case of FIG. 9 in that it includes an ADC 31 _n , a reference signal output unit 33, a reference signal line 33A, and an amplification unit 101.

However, the column parallel AD conversion unit 22 of FIG. 10 is different from the case of FIG. 9 in that _N attenuation units 111 ₁ to 111 _N are provided instead of the attenuation unit 102.

That is, in FIG. 9, one attenuating unit 102 is provided so that the one attenuating unit 102 is shared by _N ADCs 31 ₁ to 31 _{N. In} FIG. 10, N attenuating units 102 are provided. Units 111 ₁ to 111 _N are provided in such a manner that each attenuation unit 111 _n is independently assigned to each ADC 31 _n .

The attenuation section 111 _n, amplified reference signal amplifying unit 101 outputs on the reference signal line 33A is supplied.

The attenuating unit 111 _n attenuates the amplified reference signal supplied thereto with an attenuation factor of 1 / K times that is the inverse of the amplification factor K, and converts the attenuated reference signal, which is the amplified reference signal after the attenuation, to the ADC 31 _n. To supply.

Here, in FIG. 10, the attenuation unit 111 _n is provided immediately before the ADC 31 _n . Therefore, in FIG. 10, the attenuating unit 111 _n attenuates the amplified reference signal to the attenuated reference signal at a position on the reference signal line 33A immediately before the ADC 31 _n compares with the VSL signal. it can.

The amplified reference signal output from the amplifying unit 101 onto the reference signal line 33A is supplied to the attenuating units 111 ₁ to 111 _N.

The attenuating unit 111 _n attenuates the amplified reference signal supplied thereto with the attenuation rate 1 / K, and supplies the attenuated reference signal obtained as a result to the ADC 31 _n .

In the ADC 31 _n , the VSL signal output from the pixel 11 _{m, n} is compared with the attenuation reference signal supplied from the attenuation unit 111 _n , and the attenuation reference signal until the VSL signal and the attenuation reference signal match is compared. The AD conversion of the VSL signal is performed by counting the time required for the change.

FIG. 11 is a flowchart for explaining an example of the operation of the column parallel AD conversion unit 22 in FIGS. 9 and 10.

In step S11, the reference signal output unit 33 generates a reference signal and supplies the reference signal to the amplification unit 101.

In step S12, the amplification unit 101 amplifies the reference signal generated by the reference signal output unit 33 with an amplification factor K, and outputs the amplified reference signal obtained as a result on the reference signal line 33A.

The amplified reference signal output from the amplifying unit 101 onto the reference signal line 33A is supplied to the attenuating unit 102 or the N attenuating units 111 ₁ to 111 _N.

In step S13, the attenuating unit 102 or the attenuating units 111 ₁ to 111 _N attenuates the amplified reference signal supplied thereto with the attenuation rate 1 / K, and the resultant attenuated reference signal is converted to the ADC 31 ₁ to 31. _N.

In step S14, the ADC 31 _n, to the pixel _{11 m,} and VSL signal outputted from the _n, compares the attenuation reference signal supplied from the damping unit 102 or 111 _n, and damping reference signal and VSL signal matches The AD conversion of the VSL signal is performed by counting the time required for the change of the attenuation reference signal.

As described above, the column parallel AD conversion unit 22 in FIGS. 9 and 10 outputs an amplified reference signal obtained by amplifying the reference signal with the amplification factor K, and the amplified reference signal is supplied with an attenuation factor 1 which is the reciprocal of the amplification factor K. Since the signal is attenuated by / K and an attenuated reference signal is output, the reference signal noise RN_REF included in the (amplified) reference signal can be efficiently reduced.

That is, if the reference signal that does not include the reference signal noise RN_REF is represented by S_REF, the amplified reference signal is represented by S_AMP, and the attenuated reference signal is represented by S_ATT, the amplified reference signal S_AMP is the K signal of the reference signal S_REF, and the reference Since it includes the signal noise RN_REF, it can be expressed by the equation S_AMP = K × S_REF + RN_REF.

Since the attenuation reference signal S_ATT is a 1 / K signal of the amplified reference signal S_AMP, it is expressed by the expression S_ATT = 1 / K × S_AMP = S_REF + 1 / K × RN_REF.

Therefore, the reference signal noise included in the attenuated reference signal S_ATT can be reduced to about 1 / K of the original reference signal noise RN_REF.

Here, the rate at which the reference signal noise included in the attenuated reference signal such as about 1 / K is reduced from the original reference signal noise is referred to as a noise attenuation rate.

Since the attenuated reference signal is obtained by multiplying the amplified reference signal by K times the reference signal by 1 / K times, the dynamic range of the original reference signal is maintained as it is as the dynamic range of the attenuated reference signal.

Therefore, in the ADC 31 _n , even when AD conversion is performed using the attenuated reference signal, AD conversion of the VSL signal can be performed with the same dynamic range as when AD conversion is performed using the reference signal.

Furthermore, as described above, the dynamic range of the attenuated reference signal is maintained as it is, while the reference signal noise included in the attenuated reference signal is the original reference signal noise RN_REF. S / N (SignalSignto Noise Ratio) can be greatly improved for the attenuated reference signal.

Note that the reference signal noise RN_REF may depend on the dynamic range of the amplified reference signal depending on the circuit configuration of the reference signal output unit 33 (DAC) that generates the reference signal. In such a case, depending on the circuit configuration, Noise attenuation rate is different.

Here, hereinafter, K representing the amplification factor K of the amplification unit 101 and the attenuation factors 1 / K of the attenuation units 102 and 111 _n is also referred to as an amplification attenuation parameter K.

Also, a process of obtaining an amplified reference signal obtained by amplifying a reference signal and attenuating the amplified reference signal to an attenuated reference signal is also referred to as an amplification attenuation process.

According to the amplification attenuation process, as described above, the reference signal noise included in the attenuation reference signal is reduced. Therefore, it can be said that the amplification attenuation process has a noise reduction function.

FIG. 12 is a circuit diagram illustrating a configuration example of the attenuation unit 111 _n of FIG.

The attenuation unit 111 _n can be realized by, for example, a switched capacitor circuit having a capacitor.

When the attenuating unit 111 _n is realized by a switched capacitor circuit having a capacitor, a switched capacitor circuit serving as the attenuating unit 111 _n can be newly provided.

Note that the attenuation unit 102 in FIG. 9 can also be configured in the same manner as the attenuation unit 111 _n .

Further, for the attenuating unit 111 _n of FIG. 10, the capacitor circuit 71 used for the auto-zero process can be configured to function also as the attenuating unit 111 _n .

FIG. 12 shows a configuration example of the capacitor circuit 71 that also functions as the attenuation unit 111 _n .

In FIG. 12, the capacitor circuit 71 includes K unit capacitors C _1,1 to C _{1, K} and K-1 switches 131 ₁ to 131 _K-1 .

It is no unit capacitor C _{1, 1} C _{1, K} is a capacitor used for the auto-zero process of (hereinafter also referred to as auto-zero process capacitor), a capacitor connected to an inverting input terminal IN1 of the comparator 61 _n into K In the divided capacitor, the unit capacitor C _{1, k} has a capacity of 1 / K of the auto zero processing capacitor.

One end of each of the _K unit capacitors C _1,1 to C _{1, K} is connected to the differential amplifier 73 (the gate of the FET 81).

Further, to the K units capacitor C _{1, 1} not of the C _{1, K,} 1 to K-1 th unit capacitor C _{1, 1} to the other end of the C _{1, K-1} is to switch 131 ₁ to 131 _K-1, are connected, the other end of the K-th unit capacitor C _{1, K} is connected to the inverting input terminal IN1.

The switch 131 _k is switched so as to connect the other end of _{the k-th} unit capacitor C1 _{, k} to GND (ground) or the inverting input terminal IN1.

Switching of the switch 131 _k is performed, for example, under the control of the image sensor 2 by the control unit 6 (Figure 1).

In the capacitor circuit 71 configured as described above, when auto-zero processing is performed, the switches 131 ₁ to 131 _K-1 connect the other ends of the unit capacitors C _{1, k} to C _{1, K-1} to GND, Alternatively, they are switched so as to be connected to the inverting input terminal IN1.

When 0 or more i switches among the _K-1 switches 131 ₁ to 131 _K−1 are switched to the inverting input terminal IN1, the attenuation rate is (i + 1) / K. .

That is, for example, when the 1st to i-th i switches 131 ₁ to 131 _i are switched to the inverting input terminal IN1, the amplification reference signal is supplied to the inverting input terminal IN1. The reference signals are i + 1 to (K-1) th Ki-1 unit capacitors C1 _{, i + 1} to C1 _{, K-1} and 1st to ith ith unit capacitors C1,1 _. The total of ₁ to C _{1, i} and the Kth unit capacitor C _{1, K} is divided by i + 1 unit capacitors to attenuate (i + 1) / K times. .

In FIG. 12, since all of the switches 131 ₁ to 131 _K-1 are switched to the GND side and the number i of the switches 131 _k switched to the inverting input terminal IN1 side is 0, the amplification reference The signal is attenuated by 1 / K times in the capacitor circuit 71 that also functions as the attenuating unit 111 _n .

As described above, in the capacitor circuit 71 that also functions as the attenuating unit 111 _n , the attenuation rate of how many times the amplified reference signal is increased is variably set to an arbitrary value by switching the switches 131 ₁ to 131 _K−1. can do.

Further, according to the capacitor circuit 71 also functions as a damping unit 111 _n, as the attenuation unit 111 _n, it is not necessary to provide a separate new circuits, to suppress an increase in circuit scale, realizing the damping unit 111 _n can do.

In FIG. 12, the connection from the balance between the capacitor circuit 71, the capacitor constituting the capacitor circuit 72, like the capacitor circuit 71, of the capacitor auto-zero process, a non-inverting input terminal IN2 of the comparator 61 _n The capacitor is divided into _K unit capacitors C _2,1 to C _{2, K.}

However, the capacitor constituting the capacitor circuit 72 is not necessary to divide the capacitor connected to the non-inverting input terminal IN2 of the comparator 61 _n to the K units capacitor C _2,1 is not in the C _{2, K.}

FIG. 13 is a circuit diagram illustrating a first configuration example of the reference signal output unit 33 including the amplification unit 101.

In FIG. 13, the reference signal output unit 33 includes a current source 141 and a resistor 142.

The current source 141 is configured by a current mirror circuit, for example, and allows a predetermined current to flow through the resistor 142.

Here, with respect to the current mirror circuit constituting the current source 141, the current flowing through the mirror source can be switched by switching the number of transistors (such as FETs) constituting the mirror destination through which the current according to the current flowing through the mirror source flows. The mirror ratio, which is the ratio of the current flowing through the mirror tip, can be changed, whereby the current source 141 can change the current flowing through the resistor 142.

The resistor 142 functions as a DAC. That is, a current flowing through the current source 141 flows through the resistor 142, and a current (flow) generated in the resistor 142 due to the current flowing through the resistor 142 is obtained as a result of DA conversion of the current flowing through the current source 141. Output as a signal.

In the reference signal output unit 33 configured as described above, the current source 141 or the resistor 142 can function as the amplification unit 101.

That is, in the current source 141, by changing the mirror ratio, the current flowing through the resistor 142 is adjusted to, for example, K times that when the (original) reference signal is obtained. It also functions as an amplifying unit 101 that amplifies K times.

Further, by adjusting the resistance value of the resistor 142 to, for example, K times when obtaining the reference signal, the resistor 142 also functions as the amplifying unit 101 that amplifies the reference signal by K times.

Note that, as a mounting method of the amplifying unit 101, any of a method of adjusting the current of the current source 141 and a method of adjusting the resistance value of the resistor 142 to a large value can be employed. However, when the resistance value of the resistor 142 is adjusted to be large, thermal noise increases in the voltage generated by the resistor 142, and a switch for switching the resistance value is required.

Further, the current source 141 can be configured by a switched capacitor circuit (current source that operates for a discrete time) or the like in addition to a current mirror circuit. When the current source 141 is configured by a switched capacitor circuit, the current flowing through the resistor 142 is changed by adjusting the capacitance of the capacitor that configures the switched capacitor circuit and the frequency for switching the connection to the capacitor. be able to.

Here, when the resistance value of the resistor 142 is increased, thermal noise increases in the reference signal as a voltage generated in the resistor 142. From the viewpoint of reducing the reference signal noise, generally, the resistance value of the resistor 142 is reduced. Need to be small.

When the resistance value of the resistor 142 is reduced, it is necessary to increase the current of the current source 141. In this case, the power consumption of the reference signal output unit 33 is increased.

However, the column-parallel AD converting unit 22, the attenuation section 102 or 111 _n, amplified reference signal is attenuated by the attenuation factor 1 / K, since the reference signal noise is reduced, in that the damping unit 102 or 111 _n In consideration of the reduction of the reference signal noise, the resistance value of the resistor 142 can be designed to a somewhat large resistance value. By designing the resistance value of the resistor 142 to be a large resistance value, the current of the current source 141 can be suppressed to a small current, and as a result, the power consumption of the reference signal output unit 33 can be reduced.

FIG. 14 is a circuit diagram illustrating a second configuration example of the reference signal output unit 33 including the amplification unit 101.

In the figure, portions corresponding to those in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

14, the reference signal output unit 33 is common to the case of FIG. 13 in that it has a current source 141.

However, in FIG. 14, the reference signal output unit 33 is different from the case of FIG. 13 in that an operational amplifier 151 and a capacitor 152 are provided instead of the resistor 142.

The inverting input terminal (-) of the operational amplifier 151 is connected to the current source 141 and one end of the capacitor 152, and the non-inverting input terminal (+1) is grounded (connected to GND). The output terminal of the operational amplifier 151 is connected to the other end of the capacitor 152.

Therefore, the operational amplifier 151 and the capacitor 152 constitute an integrator and function as a DAC.

That is, in the integrator composed of the operational amplifier 151 and the capacitor 152, the current flowing through the current source 141 is integrated, and a voltage proportional to the integral value of the current is obtained as a result of DA conversion of the current flowing through the current source 141. A signal is output from the output terminal of the operational amplifier 151.

In the reference signal output unit 33 configured as described above, the integrator configured by the current source 141 or the operational amplifier 151 and the capacitor 152 can function as the amplification unit 101.

That is, as described with reference to FIG. 13, in the current source 141, the current source 141 adjusts the current flowing through the current source 141 to, for example, K times that for obtaining the reference signal, so that the current source 141 increases the reference signal by K times. It also functions as the amplification unit 101 that amplifies the signal.

Further, by adjusting the capacitance (capacitance) of the capacitor 152 constituting the integrator to, for example, 1 / K times that for obtaining the reference signal, the integrator serves as the amplification unit 101 that amplifies the reference signal by K times. Also works.

Note that, as a mounting method of the amplifying unit 101, any of a method of adjusting the current of the current source 141 and a method of adjusting the capacitance of the capacitor 152 can be employed. However, when adjusting the capacity of the capacitor 152, a switch for switching the capacity is required.

Here, in the reference signal output unit 33 of FIG. 14, since the operational amplifier 151 is used, the power consumption can be reduced. However, the operational amplifier 151 potentially has a large internal thermal noise, and therefore the reference signal noise becomes large.

However, in the column parallel AD conversion unit 22, the amplified reference signal is attenuated by the attenuation factor 1 / K and the reference signal noise is reduced in the attenuation unit 102 or 111 _n , so that low power consumption can be achieved. By using the operational amplifier 151, it is possible to improve that the reference signal noise becomes large.

FIG. 15 is a waveform diagram showing examples of a reference signal, an amplified reference signal, and an attenuated reference signal.

FIG. 15A is a waveform diagram illustrating an example of an original reference signal (original reference signal) generated by the reference signal output unit 33 and an amplified reference signal obtained by amplifying the reference signal by the amplification unit 101 K times. is there.

If the dynamic range of the (reference) reference signal is expressed as Dorg and the dynamic range of the amplified reference signal is expressed as Damp, the dynamic range Damp of the amplified reference signal is K times the dynamic range Dorg of the original reference signal. It is expressed by the formula Damp = K × Dorg.

FIG. 15B is a waveform diagram showing an example of an attenuated reference signal obtained by attenuating the amplified reference signal by 1 / K times by the attenuating unit 102 or 111 _n .

If the dynamic range of the attenuated reference signal is expressed as Datt, the dynamic range Datt of the attenuated reference signal is 1 / K times the dynamic range Damp of the amplified reference signal, and the formula Datt = 1 / K × Damp = 1 It is expressed as / K × K × Dorg.

Therefore, the dynamic range Datt of the attenuated reference signal matches the dynamic range Dorg of the original reference signal.

Since the attenuated reference signal is a signal obtained by attenuating the amplified reference signal by 1 / K times, the reference signal noise contained in the attenuated reference signal is approximately 1 / K times the reference signal noise contained in the amplified reference signal. Reduced.

In the present embodiment, it is assumed that the column parallel AD conversion unit 22 is a so-called single slope type AD conversion device. Therefore, the reference signal has a slope which is a ramp signal that decreases with a constant slope. This technology, however, is a single slope AD conversion that performs AD conversion by counting the time required for the level of the reference signal to change until the level of the electrical signal subject to AD conversion matches the level of the reference signal. In addition to the device, the AD conversion device that performs AD conversion based on the potential difference between the electric signal to be converted and the reference signal, and other AD conversion by comparing the electric signal with the reference signal using the reference signal The present invention can be applied to an AD converter having an arbitrary configuration.

That is, the present technology can be applied to, for example, pipeline-type, ΔΣ-type, flash-type AD converters in addition to single-slope AD converters.

FIG. 16 is a diagram showing an example of the relationship between the ISO sensitivity set in the digital camera (FIG. 1) and the amplification attenuation parameter K.

As described above, according to the amplification attenuation process in which the amplified reference signal obtained by amplifying the reference signal is obtained and the amplified reference signal is attenuated to the attenuated reference signal, the dynamic range is the same as the original reference signal, and the reference signal noise is reduced. A reduced attenuated reference signal can be obtained.

Incidentally, in the amplification attenuation process, the reference signal is amplified K times according to the amplification attenuation parameter K in the amplification unit 101 of the reference signal output unit 33.

Therefore, when the amplification attenuation process is performed, the power consumption of the reference signal output unit 33 (which constitutes the DAC) may increase.

In actual implementation, the reference signal output unit 33 is configured using a transistor such as an FET, and the FET needs to operate in a saturation region. However, if the dynamic range of the original reference signal is somewhat large, it may be difficult to ensure the operation of the FET in the saturation region when the reference signal is amplified to a K-fold amplified reference signal. is there.

Thus, in the amplification attenuation process, the amplification attenuation parameter K representing the amplification factor K for amplifying the reference signal and the attenuation factor 1 / K for attenuating the amplification reference signal is the ISO sensitivity set for the digital camera, and thus the image sensor. 2 can be set according to the analog gain.

Here, the setting of the amplification attenuation parameter K according to the ISO sensitivity is performed by the control unit 6 (FIG. 1), for example.

FIG. 16A shows a first setting method for setting the amplification attenuation parameter K in accordance with the ISO sensitivity set in the digital camera.

16A (the same applies to B of FIG. 16), the horizontal axis represents the ISO sensitivity (or analog gain), and the vertical axis represents the amplification attenuation parameter K. Furthermore, Gmin represents the minimum value of ISO sensitivity, and Gmax represents the maximum value of ISO sensitivity.

In A of FIG. 16, when the ISO sensitivity is a value in the range from the minimum value Gmin to the predetermined threshold TH, the amplification attenuation parameter K is set to 1, and the ISO sensitivity is increased from the predetermined threshold TH to the maximum. When the value is in the range up to the value Gmax, the amplification attenuation parameter K is set to a predetermined value P greater than 1.

Here, when the amplification attenuation parameter K is 1, the amplification attenuation process is substantially invalid because the amplification reference signal obtained by amplifying the reference signal by 1 is attenuated by 1/1. Become.

That is, the amplification attenuation process is substantially effective when the amplification attenuation parameter K is larger than 1.

When the ISO sensitivity is a value in the range from the minimum value Gmin to the predetermined threshold TH, and is so-called low ISO sensitivity (low analog gain), the slope of the slope of the reference signal becomes large, and the reference signal output unit 33 The current that flows to generate the reference signal becomes large.

So, if the ISO sensitivity is low ISO sensitivity, set the amplification attenuation parameter K to 1 and disable the amplification attenuation processing with noise reduction function, the noise reduction function will be turned off, but amplification An increase in power consumption of the reference signal output unit 33 due to the attenuation process can be prevented, and an operation in the saturation region of the FET constituting the reference signal output unit 33 can be ensured.

On the other hand, when the ISO sensitivity is a value in the range from the predetermined threshold TH to the maximum value Gmax, so-called high ISO sensitivity (high analog gain), the slope of the slope of the reference signal becomes small, and the reference signal output unit In 33, the current passed to generate the reference signal is reduced.

Therefore, when the ISO sensitivity is high ISO sensitivity, the amplification attenuation parameter K is set to a value P greater than 1 and the amplification attenuation processing is enabled to turn on the noise reduction function and to achieve high ISO sensitivity. While reducing the reference signal noise which becomes a problem at the time of sensitivity, while suppressing the increase in the power consumption of the reference signal output part 33 by performing an amplification attenuation process, in the saturation area | region of FET which comprises the reference signal output part 33 Operation can be ensured.

That is, at the time of high ISO sensitivity, since the current that is passed to generate the reference signal in the reference signal output unit 33 is small, even if the amplification attenuation process is performed according to the amplification attenuation parameter K set to a value P greater than 1. The power consumption of the reference signal output unit 33 does not increase so much by the amplification and attenuation process. Furthermore, at the time of high ISO sensitivity, since the slope of the slope of the reference signal is small and the dynamic range is also small, even when the amplification attenuation process is performed according to the amplification attenuation parameter K set to a value P greater than 1, The operation of the FET constituting the reference signal output unit 33 in the saturation region can be ensured.

And at the time of high ISO sensitivity, there is a tendency for horizontal stripes in the image caused by the reference signal noise to stand out, but by performing amplification attenuation processing according to the amplification attenuation parameter K set to a value P greater than 1, It is possible to reduce reference signal noise and suppress horizontal stripes in the image. That is, for example, when shooting in a dark place, the ISO sensitivity is set to a high ISO sensitivity, but the image quality of an image shot in such a dark place can be improved.

FIG. 16B shows a second setting method for setting the amplification attenuation parameter K according to the ISO sensitivity set in the digital camera.

In FIG. 16B, when the ISO sensitivity is a value in the range from the minimum value Gmin to the predetermined threshold TH1, the amplification attenuation parameter K is set to 1. When the ISO sensitivity is a value in a range from the predetermined threshold TH1 to the predetermined threshold TH2 (> TH1), the amplification attenuation parameter K is set to a predetermined value P1 greater than 1, and the ISO sensitivity is When the value is in the range from the predetermined threshold value TH2 to the maximum value Gmax, the amplification attenuation parameter K is set to a predetermined value P2 that is larger than the predetermined value P1.

Therefore, in FIG. 16B, when the ISO sensitivity is a value in the range from the minimum value Gmin to the predetermined threshold TH1, and when the ISO sensitivity is low, the amplification attenuation parameter K is set to 1, and as a result, The amplification and attenuation process is substantially disabled, and the noise reduction function is turned off.

On the other hand, if the ISO sensitivity is a value in the range from the predetermined threshold TH1 to the maximum value Gmax, and the ISO sensitivity is high, the amplification attenuation parameter K is set to a value P1 or P2 greater than 1, and the result The amplification attenuation process is enabled and the noise reduction function is turned on.

In FIG. 16B, when the ISO sensitivity is a value in the range from the predetermined threshold TH1 to the predetermined threshold TH2, the amplification attenuation parameter K is set to a value P1 greater than 1, and the ISO sensitivity is When the value is in the range from the predetermined threshold value TH2 to the maximum value Gmax, the amplification attenuation parameter K is set to a value P2 larger than the value P1.

When the amplification attenuation parameter K is set to the value P1, the reference signal noise is reduced to about 1 / P1 times in the amplification attenuation process. When the amplification attenuation parameter K is set to the value P2, the reference signal noise is further reduced by about 1 / P2 (<1 / P1) times in the amplification attenuation process.

As described above, the amplification attenuation process is performed according to the ISO sensitivity set at the time of photographing with the digital camera, thereby suppressing an increase in power consumption of the reference signal output unit 33 due to the amplification attenuation process, The reference signal noise can be reduced while ensuring the operation of the FET constituting the reference signal output unit 33 in the saturation region.

In FIG. 16, the amplification attenuation parameter (the noise reduction function) is disabled or enabled by setting the amplification attenuation parameter K to 1 or a value larger than 1, but the amplification attenuation When invalidating the processing, it is possible not to actually perform the amplification attenuation processing.

In FIG. 16, one or two threshold values are adopted as the ISO sensitivity threshold value, but the number of ISO sensitivity threshold values may be three or more. The same applies to the number of amplification attenuation parameters K.

Further, in FIG. 16, the amplification attenuation parameter K is set discretely according to the ISO sensitivity, but the amplification attenuation parameter K can be set to a continuous value according to the ISO sensitivity. It is.

FIG. 17 is a flowchart for explaining an example of processing for setting the amplification attenuation parameter K according to the ISO sensitivity in accordance with the second setting method.

In step S21, the control unit 6 (FIG. 1) determines whether or not an operation for changing the ISO sensitivity of the digital camera has been performed by the user or the like.

If it is determined in step S21 that the operation for changing the ISO sensitivity has not been performed, the process proceeds to step S22, the control unit 6 maintains the current amplification attenuation parameter K as it is, and the process proceeds to step S21. Return to.

If it is determined in step S21 that an operation for changing the ISO sensitivity has been performed, the process proceeds to step S23, and the control unit 6 determines that the changed ISO sensitivity is smaller (or less) than the threshold value TH1. Determine if it exists.

If it is determined in step S23 that the ISO sensitivity is smaller than the threshold value TH1, the process proceeds to step S24, and the control unit 6 sets the amplification attenuation parameter K to 1, thereby performing the amplification attenuation process. After invalidating, the process returns to step S21.

If it is determined in step S23 that the ISO sensitivity is not lower than the threshold value TH1, the process proceeds to step S25, and the control unit 6 determines that the changed ISO sensitivity is equal to or higher than the threshold value TH1 (or higher). It is determined whether it is present and smaller (or less) than the threshold value TH2.

If it is determined in step S25 that the ISO sensitivity is greater than or equal to the threshold TH1 and less than the threshold TH2, the process proceeds to step S26, and the control unit 6 sets the amplification attenuation parameter K to a value P1 greater than 1. After setting, the process returns to step S21.

In step S25, when it is determined that the ISO sensitivity is equal to or higher than the threshold TH1 and is not lower than the threshold TH2, that is, when the changed ISO sensitivity is equal to or higher than the threshold TH2 (or higher), the process is as follows. Proceeding to step S27, the control unit 6 sets the amplification attenuation parameter K to a value P2 larger than the value P1, and the process returns to step S21.

Next, a series of processing performed by the control unit 6 can be performed by hardware or can be performed by software. When a series of processing is performed by software, a program constituting the software is installed in a computer such as a microcomputer.

Therefore, FIG. 18 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.

The program can be recorded in advance in a hard disk 205 or ROM 203 as a recording medium built in the computer.

Alternatively, the program can be stored (recorded) in the removable recording medium 211. Such a removable recording medium 211 can be provided as so-called package software. Here, examples of the removable recording medium 211 include a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, and a semiconductor memory.

The program can be installed on the computer from the removable recording medium 211 as described above, or downloaded to the computer via a communication network or a broadcast network, and installed on the built-in hard disk 205. That is, the program is transferred from a download site to a computer wirelessly via a digital satellite broadcasting artificial satellite, or wired to a computer via a network such as a LAN (Local Area Network) or the Internet. be able to.

The computer incorporates a CPU (Central Processing Unit) 202, and an input / output interface 210 is connected to the CPU 202 via the bus 201.

When a command is input by the user operating the input unit 207 via the input / output interface 210, the CPU 202 executes a program stored in a ROM (Read Only Memory) 203 according to the command. . Alternatively, the CPU 202 loads a program stored in the hard disk 205 into a RAM (Random Access Memory) 204 and executes it.

Thereby, the CPU 202 performs processing according to the flowchart described above or processing performed by the configuration of the block diagram described above. Then, the CPU 202 outputs the processing result as necessary, for example, via the input / output interface 210, from the output unit 206, or from the communication unit 208, and further recorded in the hard disk 205.

Note that the input unit 207 includes a keyboard, a mouse, a microphone, and the like. The output unit 206 includes an LCD (Liquid Crystal Display), a speaker, and the like.

Here, in the present specification, the processing performed by the computer according to the program does not necessarily have to be performed in chronological order in the order described as the flowchart. That is, the processing performed by the computer according to the program includes processing executed in parallel or individually (for example, parallel processing or object processing).

Further, the program may be processed by one computer (processor), or may be distributedly processed by a plurality of computers.

Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

That is, the present technology can be applied to any electronic device equipped with a function of capturing an image, such as a mobile terminal such as a smartphone having a function of capturing an image by mounting an image sensor in addition to a digital camera.

Further, in the digital camera, the analog gain of the image sensor 2 may be changed for each color according to the white balance, but as such, according to the analog gain for each color changed according to the white balance. The amplification attenuation parameter K can be set.

Furthermore, in this embodiment, as the attenuation factor of the attenuation section 102 or 111 _n, has been decided to adopt the inverse 1 / K of the amplification factor K of the amplifier 101, as the attenuation factor of the attenuation section 102 or 111 _n is A value different from the reciprocal 1 / K of the amplification factor K of the amplification unit 101 can be adopted. However, if a value different from the inverse 1 / K of the amplification factor K is used as the attenuation factor, the dynamic range of the attenuation reference signal used for AD conversion will not match the dynamic range of the original reference signal. , You need to be careful about that.

Further, the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

In addition, this technique can take the following structures.

<1>
A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An image sensor including: an AD conversion unit that performs AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel with the attenuated reference signal.
<2>
The image sensor according to <1>, wherein the attenuation unit attenuates the amplified reference signal immediately before being compared with the electrical signal in the AD conversion unit.
<3>
The attenuation unit is a capacitor circuit having a capacitor,
The image sensor according to <1> or <2>, wherein the capacitor circuit attenuates the amplified reference signal by dividing the amplified signal with a capacitor.
<4>
The capacitor circuit is:
Having a plurality of capacitors and a switch for switching the connection of the plurality of capacitors;
The image sensor according to <3>, wherein the attenuation rate 1 / K for attenuating the amplified reference signal is changed by switching connection of a capacitor with the switch.
<5>
The image sensor according to <3> or <4>, wherein the capacitor is a capacitor used for auto-zero processing.
<6>
The image sensor according to any one of <1> to <5>, wherein an amplification attenuation process for attenuating the amplified reference signal obtained by amplifying the reference signal is performed according to an ISO sensitivity at the time of shooting.
<7>
When the ISO sensitivity is a high ISO sensitivity equal to or higher than a predetermined threshold, the amplification attenuation process is enabled, and when the ISO sensitivity is a low ISO sensitivity not higher than the predetermined threshold, the amplification attenuation process is disabled <6 The image sensor described in>.
<8>
The image sensor according to <6> or <7>, wherein an amplification attenuation parameter K representing the amplification factor K and the attenuation factor 1 / K of the amplification attenuation process is set according to the ISO sensitivity.
<9>
By setting the amplification attenuation parameter to a value greater than 1, the amplification attenuation processing is enabled,
The image sensor according to <8>, wherein the amplification attenuation parameter is disabled by setting the amplification attenuation parameter to 1.
<10>
The reference signal output unit is
A current source through which current flows and a resistor through which the current flows;
A voltage generated by the current flowing through the resistor is output as the reference signal;
The image sensor according to any one of <1> to <9>, wherein the current source functions as the amplifying unit by adjusting the current.
<11>
The reference signal output unit is
A current source for supplying current, an operational amplifier and a capacitor for integrating the current,
The voltage obtained by integrating the current is output as the reference signal,
The image sensor according to any one of <1> to <9>, wherein the current source functions as the amplifying unit by adjusting the current.
<12>
A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
An image sensor including a reference signal output unit that outputs a reference signal whose level changes,
An amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K is output,
The amplified reference signal is attenuated by an attenuation factor of 1 / K, and an attenuated reference signal is output.
A driving method including a step of performing AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel and the attenuated reference signal.
<13>
An optical system that collects the light;
An image sensor that receives light and captures an image,
The image sensor is
A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An electronic device comprising: an AD conversion unit that performs AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel with the attenuated reference signal.
<14>
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An AD converter comprising: an electric signal; and a comparator that compares the attenuated reference signal.

DESCRIPTION OF SYMBOLS 1 Optical system, 2 Image sensor, 3 Memory, 4 Signal processing part, 5 Output part, 6 Control part, 10 Pixel array, 11 ₁ , _{1 thru |} or 11 _{M, N} pixel, 20 Control part, 21 Pixel drive part, 22 columns Parallel AD conversion unit, 31 ₁ to 31 _N ADC, 32 auto zero control unit, 32A auto zero control line, 33 reference signal output unit, 33A reference signal line, 34 clock output unit, 34A clock line, 41 ₁ to 41 _M pixel control line , 42 ₁ to 42 _N VSL, 43 ₁ to 43 _N current source, 51 PD, 52 transfer Tr, 53 FD, 54 reset Tr, 55 amplifying Tr, 56 selection Tr, 61 ₁ to 61 _N comparator, 62 ₁ to 62 _N Counter, 63 ₁ to 63 _N comparator, 64 ₁ to 64 _N counter, 71, 72 capacitor circuit, 73 differential amplifier, 74 output amplifier, 81 to 84 FET, 85, 86 switch, 89 current source, 91, 92 FET, 93 switch, 94 capacitor, 101 amplifying unit, 102, 111 ₁ to 111 _N attenuating unit, 131 ₁ to 131 _K-1 Switch, 141 current source, 142 resistor, 151 operational amplifier, 152 capacitor, 201 bus, 202 CPU, 203 ROM, 204 RAM, 205 hard disk, 206 output unit, 207 input unit, 208 communication unit, 209 drive, 210 I / O interface, 211 Removable recording media

Claims

A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An image sensor including: an AD conversion unit that performs AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel with the attenuated reference signal.
The image sensor according to claim 1, wherein the attenuation unit attenuates the amplified reference signal immediately before being compared with the electrical signal in the AD conversion unit.
The attenuation unit is a capacitor circuit having a capacitor,
The image sensor according to claim 2, wherein the capacitor circuit attenuates the amplified reference signal by dividing the amplified signal with a capacitor.
The capacitor circuit is:
Having a plurality of capacitors and a switch for switching the connection of the plurality of capacitors;
The image sensor according to claim 3, wherein an attenuation factor 1 / K for attenuating the amplified reference signal is changed by switching connection of a capacitor with the switch.
The image sensor according to claim 3, wherein the capacitor is a capacitor used for auto-zero processing.
The image sensor according to claim 3, wherein an amplification attenuation process for attenuating the amplified reference signal obtained by amplifying the reference signal is performed according to an ISO sensitivity at the time of shooting.
The amplification attenuation process is enabled when the ISO sensitivity is a high ISO sensitivity equal to or higher than a predetermined threshold, and the amplification attenuation process is disabled when the ISO sensitivity is a low ISO sensitivity not higher than a predetermined threshold. 6. The image sensor according to 6.
The image sensor according to claim 6, wherein an amplification attenuation parameter K representing an amplification factor K and an attenuation factor 1 / K of the amplification attenuation process is set according to the ISO sensitivity.
By setting the amplification attenuation parameter to a value greater than 1, the amplification attenuation processing is enabled,
The image sensor according to claim 8, wherein the amplification attenuation process is invalidated by setting the amplification attenuation parameter to 1. 9.
The reference signal output unit is
A current source through which current flows and a resistor through which the current flows;
A voltage generated by the current flowing through the resistor is output as the reference signal;
The image sensor according to claim 3, wherein the current source functions as the amplifying unit by adjusting the current.
The reference signal output unit is
A current source for supplying current, an operational amplifier and a capacitor for integrating the current,
The voltage obtained by integrating the current is output as the reference signal,
The image sensor according to claim 3, wherein the current source functions as the amplifying unit by adjusting the current.
A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
An image sensor including a reference signal output unit that outputs a reference signal whose level changes,
An amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K is output,
The amplified reference signal is attenuated by an attenuation factor of 1 / K, and an attenuated reference signal is output.
A driving method including a step of performing AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel and the attenuated reference signal.
An optical system that collects the light;
An image sensor that receives light and captures an image,
The image sensor is
A pixel having a photoelectric conversion element for performing photoelectric conversion and outputting an electrical signal;
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An electronic device comprising: an AD conversion unit that performs AD (Analog to Digital) conversion of the electrical signal by comparing the electrical signal output from the pixel with the attenuated reference signal.
A reference signal output unit that outputs a reference signal whose level changes;
An amplification unit that outputs an amplified reference signal obtained by amplifying the reference signal at an amplification factor of 1 or more times K;
Attenuating the amplified reference signal with an attenuation factor of 1 / K, and outputting an attenuated reference signal;
An AD converter comprising: an electric signal; and a comparator that compares the attenuated reference signal.