WO2015185750A1 - Croissance par fusion de structures semi-conductrices d'alliage monocristallin et ensembles semi-conducteurs incorporant de telles structures - Google Patents

Croissance par fusion de structures semi-conductrices d'alliage monocristallin et ensembles semi-conducteurs incorporant de telles structures Download PDF

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WO2015185750A1
WO2015185750A1 PCT/EP2015/062623 EP2015062623W WO2015185750A1 WO 2015185750 A1 WO2015185750 A1 WO 2015185750A1 EP 2015062623 W EP2015062623 W EP 2015062623W WO 2015185750 A1 WO2015185750 A1 WO 2015185750A1
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semiconductor
optionally
seed
main body
substrate
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PCT/EP2015/062623
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English (en)
Inventor
Frederic Yannick GARDES
Graham Trevor REED
Callum George LITTLEJOHNS
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University Of Southampton
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Priority claimed from GB1410106.7A external-priority patent/GB2526880A/en
Application filed by University Of Southampton filed Critical University Of Southampton
Priority to EP15727645.2A priority Critical patent/EP3152780B1/fr
Priority to US15/316,555 priority patent/US11198951B2/en
Publication of WO2015185750A1 publication Critical patent/WO2015185750A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

Definitions

  • the present invention relates to the melt-growth of single-crystal alloy semiconductor structures, especially to structures fabricated on an insulator, and semiconductor assemblies incorporating such structures.
  • the present invention typically has application in electronic, photovoltaic and photonic devices, such as wavelength-sensitive devices x - 2 , photodetectors, mid- infrared waveguides and high-mobility complementary metal oxide semiconductor (CMOS) devices and circuits, and also, for example, in the fabrication of QCSE optical modulators and detectors and Franz Keldysh optical modulators.
  • CMOS complementary metal oxide semiconductor
  • the present invention also has application in, and lattice matching for, epitaxial III-V growth 3 ⁇ 4 .
  • SiGe which has application, for example, in a SiGe-on-insulator (SGOI) device or circuit.
  • Other alloy semiconductors include GeSi, GaAs and GaSb 5 .
  • RMG rapid melt-growth technique
  • LPE liquid phase epitaxy
  • RMG is attractive for the heterogeneous integration of SiGe-based devices on insulator for electronics, photovoltaics and photonics because it is possible to grow defect-free single-crystal material. This can lead to significant improvements in device characteristics, such as high mobility, low leakage current and high quantum efficiency.
  • the present inventors have devised a method, using tailored designs, of controlling inter-diffusion at the growth front in a melt-growth process, which yields a more consistent composition concentration within the resulting structure.
  • the present invention provides a method of fabricating at least one single-crystal alloy semiconductor structure, comprising : forming at least one seed on a substrate for growth of at least one single-crystal alloy semiconductor structure, the at least one seed containing an alloying material; providing at least one structural form on the substrate which is crystallized to form the at least one single-crystal alloy semiconductor structure, the at least one structural form being formed of a host material and comprising a main body which extends from the at least one seed and a plurality of elements which are connected in spaced relation to the main body; heating the at least one structural form such that the material of the at least one structural form has a liquid state; and cooling the at least one structural form, such that the material of the at least one structural form nucleates at the least one seed and crystallizes as a single crystal to provide at least one single-crystal alloy semiconductor structure, with a growth front of the single crystal propagating in the main body of the respective structural form away from the respective seed; wherein the plurality of elements of each structural
  • the present invention provides a semiconductor pre-form from which at least one single-crystal semiconductor structure is fabricated, the semiconductor pre-form comprising : a substrate; at least one seed on the substrate for growth of at least one single-crystal alloy semiconductor structure, the at least one seed containing an alloying material; at least one structural form on the substrate which, when crystallized, forms the at least one single-crystal alloy semiconductor structure, the at least one structural form being formed of a host material and comprising a main body which extends from the at least one seed and a plurality of elements which are connected in spaced relation to the main body; wherein the plurality of elements of each structural form provide reservoirs of the alloying material in liquid state when heated to a temperature above the melting point of the material of the at least one structural form, such that successive ones of the plurality of elements act to maintain during fabrication, in liquid state, an available supply of the alloying material to a growth front of a single crystal in the main body of the respective structural form.
  • the present invention provides a semiconductor assembly, comprising : a substrate; and at least one single-crystal semiconductor structure on the substrate, the at least one semiconductor structure being formed of an alloy of a host material and an alloying material and comprising a main body and a plurality of elements which extend in spaced relation to the main body.
  • successive ones of reservoirs act to maintain, in liquid phase, an available supply of the alloying material, in one embodiment Si, to the growth front in the main body, in one embodiment GeSi, such as to prevent the complete consumption of the alloying material before complete crystallisation of the main body has occurred, and therefore maintain a given concentration of the alloying material within the fabricated alloy semiconductor.
  • the liquid phase at the reservoirs provides for a substantially greater rate of cooling, which provides that the segregation rate of the alloying material at the growth front is substantially reduced, thereby limiting the change in the alloying material concentration along the growth front.
  • the present invention provides a fabrication technology that enables the fabrication of electronic, photovoltaic and photonic devices on a common substrate, typically a wafer, such as a Si wafer or silica (S1O2) wafer.
  • a wafer such as a Si wafer or silica (S1O2) wafer.
  • the present invention provides a single-crystal, defect-free material which has a generally-uniform composition.
  • the present invention enables the fabrication of a plurality of structures requiring different alloy composition on the same substrate using a single deposition step and a single annealing step through control of the annealing temperature and the material design, enabling a composition to be dictated by structural design and not by the deposition or growth mechanism.
  • the present invention has particular application to the fabrication of SiGe.
  • SiGe has a number of attractive characteristics.
  • SiGe possesses full miscibility across its entire composition range which allows for bandgap tuning for wavelength- sensitive devices, and lattice matching, whereby the lattice constant can be perfectly matched to other materials, enabling it to act as a substrate for epitaxial growth of the lattice-matched material, e.g. GaAs.
  • SiGe compounds can be either optically absorbing or transparent at telecommunication wavelengths (approximately 1550 nm or 1310 nm), thus enabling the fabrication of active devices for both optical modulation 29-32 and detection 33,34 .
  • SiGe has a higher hole and electron mobility as compared to Si, meaning that it will ultimately lead to faster devices, e.g. transistors, and is also fully compatible with current CMOS processes, and therefore avoids the contamination issues associated with III-V materials.
  • Figure 1 illustrates a plan view of a semiconductor assembly in accordance with a first embodiment of the present invention, with the capping insulation removed for purposes of illustration;
  • Figure 2 illustrates a sectional view (along section I-I in Figure 1) of the semiconductor assembly of Figure 1;
  • Figure 3 illustrates a sectional view (along section I-I in Figure 1) of a semiconductor assembly in accordance with a second embodiment of the present invention
  • Figure 4 illustrates a sectional view (along section I-I in Figure 1) of a semiconductor assembly in accordance with a third embodiment of the present invention
  • Figures 5(a) to (e) illustrate the operative steps in the fabrication of the semiconductor assembly of Figures 1 and 2;
  • Figure 6 illustrates the phase diagram for the alloy GeSi
  • Figure 7 illustrates plots of the concentration of the host material as a function of distance from the seed for a semiconductor assembly (Sample #1) having a structure comprising only a main body and no radiating elements, and a semiconductor assembly (Sample #2) of Figures 1 and 2 having a structure comprising a main body and radiating elements, both annealed at a temperature of 955 °C;
  • Figure 8 illustrates a plot of the concentration of the host material as a function of the distance from the seed for the main body and the branch or radiating elements (Branches #1-8, with Branch #1 being closest to the seed) of Sample
  • Figure 9 illustrates plots of the concentration of the host material as a function of distance from the seed for three semiconductor assemblies of Figures 1 and 2, annealed at temperatures of 955 °C, 1027 °C and 1101 °C, respectively
  • Figure 10 illustrates an electon back-scatter diffraction (EBSD) scan on a structure of a semiconductor assembly of Figures 1 and 2;
  • EBSD electon back-scatter diffraction
  • Figure 11 illustrates transmission electron microscope (TEM) images of the interface between a seed at the surface of the substrate body and a structure of a semiconductor assembly of Figures 1 and 2;
  • Figure 12 illustrates a plan view of a semiconductor assembly in accordance with a fourth embodiment of the present invention, with the capping insulation removed for purposes of illustration;
  • TEM transmission electron microscope
  • Figure 13 illustrates plots of the concentration of the host material at spaced locations along a length of the second section of each of the main bodies of the semiconductor structures of Figure 12;
  • Figure 14 illustrates a plan view of a semiconductor assembly in accordance with a fifth embodiment of the present invention, with the capping insulation removed for purposes of illustration;
  • Figure 15 illustrates a plan view of a semiconductor assembly in accordance with a sixth embodiment of the present invention, with the capping insulation removed for purposes of illustration;
  • Figure 16 illustrates a plan view of a semiconductor assembly in accordance with a sixth embodiment of the present invention, with the capping insulation removed for purposes of illustration.
  • Figures 1 and 2 illustrate an alloy semiconductor assembly in accordance with a first embodiment of the present invention.
  • the semiconductor assembly comprises a substrate 3, at least one seed 7 which is provided for growth of a single-crystal alloy semiconductor material, in this embodiment epitaxial in relation to the at least one seed 7, as will be described in more detail hereinbelow, at least one semiconductor structure 11 which is formed of an alloy semiconductor material and extends from the at least one seed 7, and a capping layer 15, in this embodiment an insulating layer, which encapsulates the at least one semiconductor structure 11.
  • the substrate 3 comprises a substrate body 17, here a wafer, and an insulating layer 19 which is formed over the substrate body 17 and includes at least one aperture 21, with the substrate body 17 at the at least one aperture 21 providing the at least one seed 7.
  • the layers 15, 19 are formed of Si0 2 , but in alternative embodiments could be formed of any suitable insulator, typically oxides or nitrides.
  • the semiconductor assembly comprises a single seed 7 from which a single semiconductor structure 11 is formed.
  • the semiconductor assembly comprises a plurality of seeds 7 from which a plurality of semiconductor structures 11 are formed.
  • the substrate body 17 is formed of a first material, here Si, which is a component of the alloy semiconductor material.
  • the substrate body 17 is a single-crystal wafer of Si.
  • the insulating layer 19 could omit the at least one aperture 21, and the at least one seed 7 provided on the substrate body 17, typically by patterning a layer which is formed on the substrate body 17.
  • the at least one seed 7 could be formed of poly-Si.
  • the at least one seed 7 could be formed of poly-SiGe or poly GeSi.
  • the substrate body 17 could be formed of an insulating material and the insulting layer 19 omitted, and the at least one seed 7 provided on the substrate body 17, typically by patterning a layer which is formed on the substrate body 17.
  • the at least one seed 7 could be formed of poly-Si.
  • the at least one seed 7 could be formed of poly-SiGe or poly-GeSi.
  • the insulating material of the substrate body 17 could comprise Si0 2 , but in alternative embodiments could be formed of any suitable insulator, typically oxides or nitrides.
  • the at least one semiconductor structure 11 comprises a main body 31 and a plurality of branch or radiating elements 33 which extend outwardly, and in spaced relation, from the main body 31.
  • the radiating elements 33 provide reservoirs or pools of the semiconductor material in a liquid state when the assembly is processed at an annealing temperature, thereby providing available supplies of the alloying material, in this embodiment Si, to the growth front in the main body 31.
  • the main body 31 comprises an elongate element, here a strip.
  • the main body 31 is a layer, here planar in form.
  • the main body 31 has a width w m of 5 pm. In preferred embodiments the main body 31 has a width w m of less than 10 pm, optionally not more than about 5 pm. In this embodiment the main body 31 has a depth d m of 400 nm. In preferred embodiments the main body 31 has a depth d m of less than 10 pm, optionally not more than about 5 pm.
  • the main body 31 and the radiating elements 33 extend in a single plane, with the radiating elements 33 radiating outwardly in relation to the main body 31, here radiating laterally in substantially parallel relation to the main body 31.
  • the radiating elements 33 extend substantially in orthogonal relation to the main body 31.
  • the radiating elements 33 have a width w r of 5 pm. In preferred embodiments the radiating elements 33 have a width w r of less than 10 pm, optionally not more than about 5 pm.
  • the radiating elements 33 have a depth d r of 400 nm. In preferred embodiments the radiating elements 33 have a depth d r of less than 10 m, optionally not more than about 5 pm.
  • the radiating elements 33 have a spacing s therebetween of 1 pm.
  • the spacing s is not greater than about 5 pm, optionally not greater than about 3 pm, optionally not greater than about 2 pm, optionally not greater than 1.5 pm, and optionally not greater than about 1 pm.
  • the radiating elements 33 could extend out of a plane of the main body 31, such as vertically, upwardly and/or downwardly, in relation to the plane of the main body 31. In an alternative embodiment the radiating elements 33 could enclose an acute angle with the main body 31. In yet another embodiment the radiating elements 33 could extend both in the plane of and out of the plane of the main body 31.
  • the insulating layer 19 is deposited on the substrate body 17.
  • the substrate body 17 is a ⁇ 100> Si wafer and is cleaned using a conventional RCA clean prior to processing to remove any contaminants from the surface of the substrate body 17.
  • the insulating layer 19 is a 50 nm Si0 2 layer deposited using plasma-enhanced chemical vapour deposition (PE-CVD).
  • PE-CVD plasma-enhanced chemical vapour deposition
  • the insulating layer could be deposited using hot-wire chemical vapour deposition (HW-CVD), low-pressure chemical vapour deposition (LP-CVD), sputtering, including RF and electron beam sputtering, or thermal oxidation.
  • the insulating layer 19 is densified, in order to prevent outgassing of the material of the insulating layer 19 into the semiconductor material of the at least one semiconductor structure 11, here the outgassing of Si0 2 into the Ge of the at least one semiconductor structure 11 during subsequent processing.
  • the insulating layer 19 is patterned, here using standard UV photolithography and a dilute (20 : 1) HF wet etch, in order to form the least one aperture 21 in the insulating layer 19 and expose the underlying substrate body 17, which in this embodiment provides the at least one seed 7 for crystallization of the semiconductor material of the at least one semiconductor structure 11, here exposing the underlying Si to act as a seed for the Ge of the at least one semiconductor structure 11 during subsequent processing.
  • a layer of semiconductor material is deposited over the insulating layer 19 as patterned, here a 400 nm Ge layer deposited using a non-selective plasma-enhanced chemical vapour deposition (PE-CVD) process.
  • PE-CVD plasma-enhanced chemical vapour deposition
  • the layer of the host material could be deposited using hot-wire chemical vapour deposition (HW-CVD), reduced-pressure chemical vapour deposition (RP-CVD), or sputtering, including RF or e-beam sputtering .
  • HW-CVD hot-wire chemical vapour deposition
  • RP-CVD reduced-pressure chemical vapour deposition
  • sputtering including RF or e-beam sputtering .
  • the semiconductor material is deposited in an amorphous state.
  • the layer of the semiconductor material is patterned to form at least one structural form 11' which corresponds to the at least one structure 11 and overlaps the at least one seed 7 as provided by the at least one aperture 21, here using standard UV photolithography and an inductively-coupled plasma (ICR) etch to leave the at least one Ge structure overlapping the at least one Si seed.
  • ICR inductively-coupled plasma
  • the capping insulating layer 15 is then deposited to encapsulate the at least one structural form 11', here a 1 pm Si0 2 layer deposited by PE-CVD.
  • the insulating layer 15 could be deposited using hot-wire chemical vapour deposition (HW- CVD), low-pressure chemical vapour deposition (LP-CVD), sputtering, including RF and electron beam sputtering, or thermal oxidation .
  • the resulting pre-form is heated in order to melt the material of the at least one structural form 11', and initiate crystallization of the semiconductor material from the at least one seed 7.
  • the heating is done using a rapid thermal annealer (RTA).
  • the heating could be done by laser.
  • the assembly is first stabilized at a temperature below the melting point of the semiconductor material of the at least one structural form 11', here to a temperature of 500 °C, and subsequently ramped up to a maximum temperature (in this embodiment in the range of 955 °C to 1133 °C) at a rate of approximately 100 °C/s.
  • a maximum temperature in this embodiment in the range of 955 °C to 1133 °C
  • the temperature is increased at a rate of at least about 50 °C/s, optionally at least 80 °C/s.
  • the assembly is then maintained at the maximum temperature for a predetermined period of time, here for 1 second, in order to soak the assembly.
  • the assembly is soaked for not longer than about 10 s, optionally not longer than about 5 s, optionally not longer than about 2 s, and optionally not longer than about 1 s.
  • the assembly could not be subjected to any soaking time, and instead cooled immediately on reaching the maximum temperature.
  • the assembly is cooled by ramping down the temperature to a temperature below the melting point of the semiconductor material, in this embodiment to room temperature, at a rate, at least initially, of approximately 100 °C/s, in order to provide the finished, fabricated assembly.
  • the temperature is decreased at a rate of at least about 50 °C/s, optionally at least 80 °C/s.
  • the rate of cooling ensures that the growth front propagates at a speed sufficient to avoid random nucleation within the at least one structural form 11' as such would result in multiple growth fronts and a polycrystalline material .
  • the capping insulating layer 15 is removed, here removing the Si0 2 layer using a dilute (20 : 1) HF wet etch.
  • the melt-growth process of the present invention utilizes the fact that the host semiconductor material, in this embodiment Ge, has a lower melting point than the substituting or alloying material, in this embodiment Si, here temperatures of 938.2 °C and 1414 °C respectively, which means that the host material can be melted whilst the at least one seed 7 maintains its crystal structure.
  • the assembly is configured such that nucleation initially occurs at the at least one seed 7, thereby ensuring single-crystal, in this embodiment epitaxial, growth which initiates at the at least one seed 7 and propagates along the main body 31 of the at least one structural form 11'.
  • This controlled nucleation is in part caused by the at least one seed 7 and the associated substrate 3 acting as a heat sink, which provides that the semiconductor material is cooler at interface between the at least one seed 7 and the at least one structural form 11' than within the bulk of the at least one structural form 11' which is encapsulated by the insulating layers 15, 19, which are not only electrically insulating but also refractory in nature and provide thermal insulation.
  • this controlled nucleation is also in part caused by diffusion of the alloying material, in this embodiment Si, from the liquid into the host material, in this embodiment Ge, at the growth front, and diffusion of the host material, in this embodiment Ge, from the growth front into the liquid, which, as a consequence of the increased concentration of the alloying material at the solid-liquid interface, causes the material at the solid-liquid interface to have a higher solidification temperature as compared to the material within the bulk.
  • Figure 6 illustrates the phase diagram for the alloy GeSi (taken from Olesinski et al, "The Ge-Si (Germanium-Silicon) system", Bulletin of Alloy Phase Diagrams, Vol 5, pages 180-183, 1984), where it will be seen that the solidus temperature increases with increasing concentration of Si, thus promoting solidification at the region of highest concentration of Si and initially at the surface of the at least one seed 7.
  • the host material of the at least one structural form 11' melts and becomes liquid
  • diffusion of the alloying material, here Si into the host material dramatically increases, forming a liquid alloy, here a GeSi alloy.
  • the diffusivity of the alloying material, here Si, in the host material, here Ge is low in the solid state and high in the liquid state, being many orders of magnitude higher in liquid state, there is substantially no diffusion in the solid phase and it is expected that the alloy composition within the bulk of the liquid material of the at least one structural form 11' is substantially uniform.
  • the crystallization is nucleated at the at least one seed 7, in this embodiment as provided by the exposed substrate body 17, and mimics the crystal structure of the underlying substrate body 17, in this embodiment ⁇ 001 > Si.
  • the semiconducting material has solidified at the seed interface, because of the very low diffusivity of the alloying material, here Si, in the solidified alloy, here the GeSi alloy, there is then only a finite amount of the alloying material in the semiconducting material which remains in the liquid phase.
  • the phase diagram in Figure 6 With continued cooling, there is a preferential solidification at the solid-liquid interface, insofar as the solid-liquid interface is rich in the alloying material and thus has a higher solidification temperature.
  • the alloying material in the remaining liquid phase is depleted before the end of the wire or strip is reached, and is a function of the distance from the solid-liquid interface.
  • Figure 7 illustrates a plot of the concentration of the host material, in this embodiment Ge, as a function of the distance from the seed 7 for (Sample #1) an assembly comprising only the main body 31 and no radiating elements 33, and the main body 31 having a width w m of 3 ⁇ and a depth dm of 400 nm, annealed at a temperature of 955 °C, and (Sample #2) an assembly of Figures 1 and 2 in which the main body 31 has a width w m of 3 pm and a depth d m of 400 nm and the radiating elements 33 have a width w r of 5 pm, a depth d m of 400 nm and a spacing s of 1 pm, annealed at a temperature of 955 °C.
  • the concentration of the alloying material, here Si, in the semiconductor material of the at least one semiconductor structure 11, here Ge is characterized using 532 nm Raman spectroscopy with a spot size of approximately 0.5 m by taking a ratio of the SiGe mode integrated intensity to the GeGe mode integrated intensity, following ooney et al 35 .
  • the concentration of the alloying material decreases markedly as a function of distance along a length of the main body 31.
  • the present invention by virtue of providing the radiating elements 33 to the main body 31, the amount of the alloying material is substantially greater, which ensures that the depletion of the alloying material at the g rowth front is substantially reduced. Furthermore, by providing a plurality of radiating elements 33, and also arranging the radiating elements 33 in spaced relation along a propagation direction of the growth front, the present invention ensures that a reserve or pool of the liquid alloying material is maintained at the growth front, and though successive ones of the reserves or pools of the liquid alloying material become isolated from the growth front, further reserves or pools of the liquid alloying material remain available as the growth front advances.
  • Figure 8 illustrates a plot of the concentration of the host material, in this embodiment Ge, as a function of the distance from the seed 7 for the main body 31 and the branch or radiating elements 33 (Branches #1-8, with Branch #1 being closest to the seed 7) of Sample #2.
  • the composition of the main body 31 is substantially uniform over a length thereof, whereas, in the branch or radiating elements 33, the concentration of the alloying material decreases markedly as a function of distance from the main body 31.
  • the cooling and solidification of the at least one semiconductor structure 11 was characterized using a poly-Si seed on a thick S1O2 layer rather than a bulk Si wafer. This arrangement is such as to slow the cooling of the at least one semiconductor structure 11 by removing the heat sinking provided by the Si wafer substrate body 17. From scanning electron microscope (SEM) images, it is apparent that the main body 31 cools and solidifies prior to the branch or radiating elements 33 because random nucleation is observed in the branch or radiating elements 33 but not in the main body 31.
  • SEM scanning electron microscope
  • the growth front propagates along the main body 31, and in so doing consumes the alloying material as provided by the branch or radiating elements 33 until solidification occurs thereat, and only then the growth propagates along the individual branch or radiating elements 33 with the solidified main body 31 at the inner ends of the respect branch or radiating elements 33 acting as a seed.
  • the alloy composition can be controlled by the peak temperature employed in the growth process and the annealing time.
  • the peak temperature employed in the growth process and the annealing time not only is there increased thermal energy at higher temperatures, but, since the solidus curve provides for an increasing concentration of the alloying material, here Si, in the host material, here Ge, with increasing temperature, the alloy composition has an increasing concentration of the alloying material with increasing temperature.
  • Figure 9 illustrates a plot of the concentration of the host material, in this embodiment Ge, as a function of the distance from the seed 7 for three assemblies of Figures 1 and 2 in which the main body 31 has a width w m of 3 ⁇ and a depth d m of 400 nm and the radiating elements 33 have a width w r of 5 pm, a depth d m of 400 nm and a spacing s of 1 pm, annealed at temperatures of 955 °C, 1027 °C and 1101 °C, respectively. The temperatures were recorded using a pyrometer measuring the infra-red radiation from the back of the substrate 3 during annealing.
  • the semiconductor material shows a relatively- uniform composition over the entire main body 31 of the semiconductor structure 11, with the variance in concentration of the alloying material, here Si, being about 9 % at 955 °C, about 8 % at 1027 °C and 3 % at 1101 °C.
  • This substantially-uniform composition over the entire main body 31 of the semiconductor structure 11 compares to the wire or strip having the same dimension as the main body 31 but without the radiating elements 33, which exhibits a very significant variation in the concentration of the host material, in this embodiment Ge, as a function of distance from the seed interface, as illustrated in Figure 7.
  • the present invention enables the resulting at least one structure 11 to be tailored to the application, such as to enable tuning of the band edge and lattice parameters of the semiconductor.
  • Electon back-scatter diffraction (EBSD) measurements were also performed on structures 11 fabricated in accordance with the present invention.
  • Figure 10 illustrates an electon back-scatter diffraction (EBSD) scan on a structure 11 fabricated in accordance with the present invention, which confirms that the main body 31 and the branch or radiating elements 33 of the semiconductor structure 11 have the same orientation as the substrate body 17, with no influence on growth direction .
  • EBSD electon back-scatter diffraction
  • Figure 11 illustrates transmission electron microscope (TEM) images of the interface between the at least one seed 7 at the surface of the substrate body 17 and the at least one semiconductor structure 11.
  • TEM transmission electron microscope
  • Threading dislocations caused by the lattice constant mismatch between alloying material, here Si, and the host material, here Ge, are clearly observed in the transmission electron microscope (TEM), but are confined to the seed area and do not propagate along the main body 31 of the at least one semiconductor structure 11.
  • the high-resolution cross-section confirms a single-crystal, defect- free structure, here an SGOI. Diffusion of the host material, here Ge, into the substrate body 17, here a Si wafer, can also be observed.
  • Figure 12 illustrates a semiconductor assembly in accordance with a fourth embodiment of the present invention.
  • the semiconductor assembly of this embodiment has some similarity to the semiconductor assembly of the first-described embodiment, and thus in order to avoid unnecessary duplication of description, only the differences will be described in detail, with like parts being identified by like reference signs.
  • the semiconductor assembly differs from the first-described embodiment in comprising a plurality of semiconductor structures l la-d, each being formed from a respective structural form 11'.
  • the main bodies 31 of the semiconductor structures lla-d each have a portion which is shared with one or more of the other semiconductor structures lla-d
  • the main bodies 31 of each of the semiconductor structures l la-d have a first section 31a'-d' which is proximal the one seed 7 and a second section 31a"-d" which is distal the one seed 7, with the second section 31a"-d” having the branch or radiating elements 33 connected thereto and being a portion of the respective main body 31 which is not shared with the main bodies 31 of the other semiconductor structures lla-d, with a distance d a - d from the one seed 7 to a location proximal the second section 31a"-d" being different for each of the semiconductor structures lla-d.
  • first sections 31a'-d' of the main bodies 31 of the semiconductor structures lla-d together define an interconnecting, manifold element 41, here an elongate or linear strip, and the second sections 31a'-d' of the main bodies 31 branch or radiate from the manifold element 41, here in orthogonal relation, but could have any angular relation.
  • the second sections 31a'-d' of the main bodies 31 branch or radiate from one side of the manifold element 41, but in an alternative embodiment one or more of the second sections 31a'-d' of the main bodies 31 could branch or radiate to opposite sides of the manifold element 41.
  • the resulting semiconductor structures l la-d can be formed with different, but uniform composition from the structural forms 11' of common composition and when subjected to the same thermal treatment.
  • This configuration allows the composition of a plurality of semiconductor structures l la-d to be determined by selectively setting the distances d a -d of the proximal ends of the second sections 31a"-d" of the main bodies 31 from the one seed 7.
  • Figure 13 illustrates plots of the concentrations of the host material, in this embodiment Ge, as a function of the distance from the seed 7 for (Sample #3) the manifold element 41 and the second sections 31a"-d" of the main bodies 31 of the semiconductor structures l la-d, with the manifold element 41 having a width of 5 pm, a depth of 400 nm and a length of 230 ⁇ , the second sections 31a"-d" of the main bodies 31 having a width w m of 5 ⁇ , a depth d m of 400 nm, a length of 65 pm and having proximal locations at 30 ⁇ , 90 pm, 150 pm and 210 pm from the seed 7, and the radiating elements 33 have a width w r of 5 ⁇ , a depth d m of 400 nm, a length of 20 pm and a spacing s of 3 pm, annealed at a temperature of 1017 °C.
  • the concentration of the alloying material, here Si, in the semiconductor material of the manifold element 41 and the second sections 31a"-d" of the main bodies 31 of the semiconductor structures l la-d, here Ge, is characterized using 532 nm Raman spectroscopy with a spot size of approximately 0.5 pm by taking a ratio of the SiGe mode integrated intensity to the GeGe mode integrated intensity, following Mooney et al 3S .
  • the concentration of the alloying material decreases markedly as a function of distance along a length of the manifold element 41.
  • the concentration of the alloying material in the second sections 31a"- d" of the main bodies 31 of the semiconductor structures lla-d is substantially uniform over the major extent thereof, here over a length of 56 ⁇ , with the concentration being dependent upon the distance d a -d of the proximal location of each semiconductor structure l la-d from the seed 7.
  • the semiconductor structures l la-d would, following fabrication, be etched to isolate the regions of the second sections 31a"-d" of the main bodies 31 which have substantially uniform composition.
  • the second sections 31a"-d" of the main bodies 31 of the semiconductor structures l la-d have average concentrations from eight measured points respectively of 0.81, 0.92, 0.95 and 0.97 of the host material, with the standard deviations of the measured points in the second sections 31a"- d" of the main bodies 31 being respectively 0.006, 0.008, 0.004 and 0.002, which represents a variation in composition of less than 1% from the mean composition (and is within the measurement error).
  • the present invention ensures that a reserve or pool of the liquid alloying material is maintained at the growth front, and though successive ones of the reserves or pools of the liquid alloying material become isolated from the growth front, further reserves or pools of the liquid alloying material remain available as the growth front advances.
  • Figure 14 illustrates a semiconductor assembly in accordance with a fifth embodiment of the present invention.
  • the semiconductor assembly of this embodiment is quite similar to the semiconductor assembly of the fourth-described embodiment, and thus in order to avoid unnecessary duplication of description, only the differences will be described in detail, with like parts being identified by like reference signs.
  • the semiconductor assembly differs from the fourth- described embodiment in comprising a plurality seeds 7a-d, and in that the respective structural forms 11' and the resulting semiconductor structures 11a- d are separate, with the main bodies 31 thereof sharing no common portion, and each extend from respective ones of the seeds 7a-d.
  • the resulting semiconductor structures l la-d can be formed with different, but uniform composition from the structural forms 11' of common composition and when subjected to the same thermal treatment.
  • This configuration allows the composition of a plurality of semiconductor structures l la-d to be determined by selectively setting the distances d a -d of the proximal ends of the second sections 31a"-d" of the main bodies 31 from the respective seeds 7.
  • Figure 15 illustrates a semiconductor assembly in accordance with a sixth embodiment of the present invention.
  • the semiconductor assembly of this embodiment is quite similar to the semiconductor assembly of the fourth-described embodiment, and thus in order to avoid unnecessary duplication of description, only the differences will be described in detail, with like parts being identified by like reference signs.
  • the semiconductor assembly differs from the fourth - described embodiment in that the respective structural forms 11' and the resulting semiconductor structures l la-d are separate, with the main bodies 31 thereof sharing no common portion, each extending from the one seed 7.
  • the resulting semiconductor structures l la-d can be formed with different, but uniform composition from the structural forms 11' of common composition and when subjected to the same thermal treatment.
  • This configuration allows the composition of a plurality of semiconductor structures l la-d to be determined by selectively setting the distances d a -d of the proximal ends of the second sections 31a"-d" of the main bodies 31 from the one seed 7.
  • Figure 16 illustrates a semiconductor assembly in accordance with a seventh embodiment of the present invention.
  • the semiconductor assembly of this embodiment is similar to the semiconductor assembly of the fourth-described embodiment, and thus in order to avoid unnecessary duplication of description, only the differences will be described in detail, with like parts being identified by like reference signs.
  • the semiconductor assembly of this embodiment differs from the fourth- described embodiment in that the respective structural forms 11' and the resulting semiconductor structures l la-d are arranged in series, with the main bodies 31 thereof being provided by segments of a common, elongate element 51, here in the form of a strip, which extends from the one seed 7 at one proximal end.
  • the resulting semiconductor structures l la-d can be formed with different, but uniform composition from the structural forms 11 ' of common composition and when subjected to the same thermal treatment.
  • This configuration allows the composition of a plurality of semiconductor structures l la-d to be determined by selectively setting the distances d a -d of the proximal ends of the second sections 31a"-d" of the main bodies 31 from the one seed 7.
  • the host material of the at least one structural form 11' is deposited as an elemental substance in amorphous form, here Ge, but could be deposited as an amorphous alloy, such as GeSi.
  • the main body 31 could take forms other than an elongate linear strip.
  • the main body element 31 could have any elongate form, or have other shape, such as rectangular, circular or annular form.
  • the present invention can also be applied to the fabrication of semiconductor structures 11 comprising substantially Ge or a GeSi alloy having a low concentration of Si, typically less than 1 at%, optionally less than 0.1 at%.
  • the at least one structure 11, fabricated in the manner as described hereinabove can be subjected to a condensation process subsequent to melt growth, in which the alloying material of the at least one structure 11, in this embodiment Si, is preferentially oxidized, with the alloying material migrating to the surface of the at least one structure 11 and forming an oxide film, in this embodiment a S1O2 film, with the remaining bulk being substantially formed of the host material, in this embodiment Ge, and having a concentration of less than 1 at% of the alloying material, optionally less than 0.1 at%.
  • the oxidation is performed at a temperature below the melting point of the material of the at least one structure 11, in one embodiment less than 938 °C.
  • the oxidation process is performed over an extended period, typically several hours depending upon the partial pressure of 0 2 .
  • this condensation step subsequent to melt growth it is possible to achieve a substantially defect-free single-crystal structure of an elemental substance, in this embodiment Ge, which has high purity.
  • This structure has particular application in photonics and electronics devices, and cannot be achieved using existing condensation methodologies, which yield structures with significant layer defects.
  • the semiconductor assembly is fabricated with the capping layer 15 for purposes of melt processing, and the capping layer 15 is removed, typically by wet etching or a combination of dry and wet etching, to allow for oxidation, which can be wet or dry oxidation, and a further capping layer, in this embodiment an insulating layer, is subsequently formed following oxidation, at least partially and over the at least one structure 11.
  • the capping layer 15 can remain during the condensation step.
  • the at least one seed 7 could be formed of the host material, in this embodiment Ge, or substantially the host material, optionally in the form of a wafer, optionally a single crystal or polycrystalline.
  • the at least one seed 7 could comprise an alloy of the host material and the alloying material, with the host material in major or substantial fraction, optionally having less than about 10 at% of the alloying material, in this embodiment Si, optionally less than about 5 at% of the alloying material, optionally in the form of a wafer, optionally as a single crystal or polycrystalline.

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Abstract

L'invention concerne un procédé de fabrication d'au moins une structure semi-conductrice d'alliage monocristallin, consistant : à former au moins un germe sur un substrat pour la croissance d'au moins une structure semi-conductrice d'alliage monocristallin, et au moins un germe contenant un matériau d'alliage ; à réaliser au moins une forme structurelle sur le substrat qui est cristallisée pour former la ou les structures semi-conductrices d'alliage monocristallin, la ou les formes structurelles étant constituées d'un matériau hôte et comprenant un corps principal qui s'étend depuis le(s) germe(s) et d'une pluralité d'éléments qui sont reliés en relation spatiale au corps principal ; à chauffer la ou les formes structurelles de sorte que le matériau de la ou des formes structurelles se trouve à l'état liquide ; et à refroidir la ou les formes structurelles, de sorte que le matériau de la ou des formes structurelles entraîne la nucléation du ou des germes et se cristallise sous forme d'un monocristal pour réaliser au moins une structure semi-conductrice d'alliage monocristallin, un front de croissance du monocristal se propageant dans le corps principal de la forme structurelle respective en s'éloignant du germe respectif ; la pluralité d'éléments de chaque forme structurelle constituant des réservoirs du matériau d'alliage à l'état liquide, de sorte que des éléments successifs de la pluralité d'éléments agissent pour maintenir, à l'état liquide, une réserve disponible du matériau d'alliage au front de croissance du monocristal dans le corps principal de la forme structurelle respective.
PCT/EP2015/062623 2014-06-06 2015-06-05 Croissance par fusion de structures semi-conductrices d'alliage monocristallin et ensembles semi-conducteurs incorporant de telles structures WO2015185750A1 (fr)

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EP15727645.2A EP3152780B1 (fr) 2014-06-06 2015-06-05 Croissance par fusion de structures semi-conductrices d'alliage monocristallines
US15/316,555 US11198951B2 (en) 2014-06-06 2015-06-05 Melt-growth of single-crystal alloy semiconductor structures and semiconductor assemblies incorporating such structures

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GB1410106.7A GB2526880A (en) 2014-06-06 2014-06-06 Melt-growth of single-crystal alloy semiconductor structures and semiconductor assemblies incorporating such structures
GB1410106.7 2014-06-06
GB1507821.5A GB2530128A (en) 2014-06-06 2015-05-07 Melt-growth of single-crystal alloy semiconductor structures and semiconductor assemblies incorporating such structures
GB1507821.5 2015-05-07

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US10969547B2 (en) 2017-06-09 2021-04-06 University Of Southampton Optoelectronic device and method of manufacturing thereof

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US10969547B2 (en) 2017-06-09 2021-04-06 University Of Southampton Optoelectronic device and method of manufacturing thereof

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