WO2015180545A1 - Appareil d'embrouillage et procédé de configuration d'embrouillage - Google Patents

Appareil d'embrouillage et procédé de configuration d'embrouillage Download PDF

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Publication number
WO2015180545A1
WO2015180545A1 PCT/CN2015/077210 CN2015077210W WO2015180545A1 WO 2015180545 A1 WO2015180545 A1 WO 2015180545A1 CN 2015077210 W CN2015077210 W CN 2015077210W WO 2015180545 A1 WO2015180545 A1 WO 2015180545A1
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Prior art keywords
scrambling
scrambled
circuit
calculation unit
input
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PCT/CN2015/077210
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English (en)
Chinese (zh)
Inventor
李长松
叶珍华
李志军
陈志强
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华为技术有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • the present invention relates to the field of communications, and in particular, to a scrambling device and a scrambling configuration method.
  • Ethernet interface bandwidth also ranges from 10G to 100G and evolves to 400G/1TG.
  • OTN optical transport network
  • Flexible Grid OTN technology refers to the optical layer dynamically adjusting the transmission bandwidth based on information such as transmission distance and channel quality.
  • flexible Ethernet English: flexible ethernet
  • a scrambling algorithm is used to ensure the randomness of the data to reduce the possibility of continuous occurrence of 0 or 1.
  • the existing scrambling algorithm can be divided into frame synchronous scrambling (English: frame synchronous scrambling, FSS for short), discrete sample scrambling (DSS), self-synchronous scrambling (English: selfsynchronous scrambling, Abbreviation: SSS) and so on.
  • scrambling According to the scope of the scrambling, it can be roughly divided into two types: one is to scramble all physical links (English: all lane, abbreviation: AL) together, such as Ethernet 802.3 protocol; the other is to physical links ( English: physical lane, referred to as: PL) independent scrambling, such as the interlaken protocol.
  • AL physical links
  • PL physical links
  • AL scrambling versus PL scrambling can reduce the probability that a mis-spreading will result in a cross-packet.
  • the AL-based scrambling scheme conforms to the existing Ethernet 40G/100G standard.
  • current AL-based scrambling algorithms are designed for fixed bandwidth interfaces, and when scrambling is introduced into variable bandwidth Ethernet, it is not possible to dynamically adapt the scrambling requirements of different bandwidths.
  • Embodiments of the present invention provide a scrambling device and a scrambling configuration method for implementing flexible and configurable variable bandwidth Ethernet scrambling.
  • a scrambling device comprising: M scrambling circuits and M multiplexers, the M scrambling circuits being cascaded into M by the M multiplexers a level scrambling circuit, the M-stage scrambling circuit includes a 0th stage to an M-1th level scrambling circuit in a cascading order, and each stage scrambling circuit is used to scramble the S bits, M>1, S> 1, where:
  • Each stage scrambling circuit is connected to a multiplexer, each input of the multiplexer is a scrambled status word, and one of the inputs of the multiplexer is configured to be valid and configured
  • the scrambled status word corresponding to the active input is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation, wherein the input of the multiplexer connected to the i-th scramble circuit is derived from the i-th
  • the feedback from the stage to the M-1 level scrambling circuit and the feedforward of the i-1th stage scrambling circuit 1 ⁇ i ⁇ N.
  • the inputs of the multiplexers connected to the level 0 scrambling circuit are derived from the feedback of the level 0 to the M-1 level scrambling circuits, respectively.
  • the S is the number of bits of the smallest data unit.
  • a scrambling configuration method implemented based on the foregoing scrambling device comprising:
  • the feedback of the Kth scramble circuit of all the path inputs is set to be valid, and the other path inputs are set to be invalid, for each of the second to Kth stage scramble circuits
  • the multiplexer connected by the scrambling circuit sets the feedforward of the previous stage scrambling circuit of all the channel inputs to be valid, and sets the other channel inputs to be invalid.
  • the method further includes:
  • a scrambling circuit is selected, and the selected ones of all the path inputs are selected for the multiplexer connected to the selected scrambling circuit.
  • the scrambling circuit is cascaded by the multiplexer, and the input of the multiplexer connected to each level scrambling circuit is derived from the scrambled status word fed back by the scramble circuit of the present stage.
  • the number of one or more cascaded scrambling circuits for performing scrambling calculation is selected by strobing the effective state of the input of the multiplexer connected to the scrambling circuit selected to perform the scrambling calculation to strobe the corresponding
  • the scrambled status word is passed to the scrambling circuit to participate in the scrambling calculation.
  • the embodiment of the present invention provides a flexible and configurable scrambling structure, which can select a corresponding number of scrambling circuits to perform scrambling calculation according to the number of bits to be scrambled input in one clock cycle, and is selected through configuration.
  • the multiplexer connected to the scrambling circuit causes the selected scrambling circuit to perform scrambling calculation using the correct scrambled status word, thereby implementing flexible and configurable variable bandwidth Ethernet scrambling.
  • a scrambling device comprising: a scrambling module and a feedback module;
  • the scrambling module includes a first input selector, a first output selector, and an R-level scrambling calculation unit that is cascaded by R scrambling calculation units, R>1, where:
  • the first input selector is configured to distribute the to-be-scrambled bits input by the first clock cycle to a scrambling calculation unit or K cascaded scrambling calculation units for scrambling the to-be-scrambled bits , 1 ⁇ K ⁇ R;
  • Each level scrambling calculation unit is configured to perform, according to the scrambled status word fed forward by the previous stage scrambling calculation unit or the scrambled status word output by the feedback module, the to-be-scrambled bits distributed to the scrambling calculation unit of the current stage. Scrambling
  • the first output selector is configured to merge the scrambling result of the scrambling calculation unit that performs the scrambling calculation into the scrambled result of the to-be-scrambled bit and output the result;
  • the feedback module includes a second input selector, a second output selector, and X feedback calculation units, X ⁇ 1, wherein:
  • the second input selector is configured to distribute the to-be-scrambled bits to a feedback calculation unit for calculating a scrambled status word for the number of bits according to the number of bits to be scrambled input by the first clock cycle ;
  • Each feedback calculation unit is configured to calculate a scrambled status word according to the to-be-scrambled bits distributed by the second input selector;
  • the second output selector is configured to output the scrambled status word calculated by the feedback calculation unit to the scramble calculation unit.
  • each scrambling calculation unit is configured to perform scrambling calculation on M ⁇ S bits in parallel, where S is the number of bits of the minimum data unit, M>1;
  • the first input selector is specifically configured to: distribute the n ⁇ S to-be-scrambled bits input by the first clock cycle to the H cascaded scrambling calculation units,
  • the lowest level scrambling calculation unit is specifically configured to add the to-be-scrambled bits distributed to the current scrambling calculation unit according to the scrambled status word output by the feedback calculation unit.
  • the scrambling calculation unit of the other stage is specifically configured to perform the scrambling bit to be distributed to the scrambling calculation unit of the present stage according to the scrambled status word fed forward by the scrambling calculation unit of the previous stage of the scrambling calculation unit.
  • the second input selector is specifically configured to: distribute n ⁇ S to-be-scrambled bits input by the first clock cycle to a feedback calculation unit for calculating a scrambled status word for n ⁇ S bits;
  • the second output selector is specifically configured to: output the scrambled status word calculated by the feedback calculation unit for calculating the scrambled status word for the n ⁇ S bits into the H cascaded scrambling calculation unit The lowest level of scrambling calculation unit.
  • the first register or the first register group is further connected between the adjacent two-stage scrambling computing units.
  • the first register or the first register set is configured to delay the scrambled status word calculated by the previous-stage scrambling calculation unit in the adjacent two-stage scrambling calculation unit by Y clock cycles, and output the result to the next stage. Disturbance calculation unit, Y ⁇ 1.
  • a connection between the scrambled result output of each scrambling calculation unit and the input end of the first output selector is a second register or a second register set, the second register or the second register set being configured to delay the scrambling result and output to the first output selector;
  • the scrambling result of the scrambling calculation unit of the previous stage is delayed by more than the number of clock cycles compared to the latter stage scrambling calculation unit.
  • the scrambling calculation unit includes: M scrambling circuits and M multiplexers, the M scrambling circuits are cascaded into M-stage scrambling circuits by the M multiplexers, and the M-stage scrambling circuits include 0th to Mth in a cascading order - Level 1 scrambling circuit, each level scrambling circuit is used to scramble the S bits, M>1, S>1, where:
  • Each level of scrambling circuit is connected to a multiplexer, and each input of the multiplexer is scrambled Word, all the inputs of the multiplexer have one input configured to be active, and the scrambled status word corresponding to one input that is configured as valid is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation
  • the input of the multiplexer connected to the i-th scramble circuit is derived from the feedback of the ith stage to the M-1th level scrambling circuit, the feedforward of the i-1th stage scramble circuit, and the feedback
  • the output of the module 1 ⁇ i ⁇ N.
  • the scrambled status word calculated by the M-1th level scrambling circuit in a scrambling calculation unit is output to the current level.
  • the scrambled status word calculated by each scrambling circuit is delayed by one clock cycle after one register Feedback to the multiplexer connected to the scrambling circuit;
  • the scrambled status word calculated by each scrambling circuit in a scrambling calculation unit is delayed by one clock cycle and fed back to the multiplexer connected to all the pre-stage scrambling circuits.
  • a third register or a third register set is connected between the outputs, and the third register or the third register set is configured to delay the bit to be scrambled and output to the scrambling circuit;
  • the number of clock cycles to be scrambled by the scrambling circuit of the previous stage is less than Y, and the Y is two adjacent levels of scrambling. Between the calculation units, the number of clock cycles that the previous stage scrambling calculation unit feeds forward to the scrambled state word of the subsequent stage scrambling calculation unit is delayed.
  • the X feedback calculation units include at least one first feedback a computing unit, the first feedback computing unit includes W scrambling circuits and W multiplexers, and the W scrambling circuits are cascaded into W-level scrambling circuits by the W multiplexers.
  • the W-stage scrambling circuit includes a 0th stage to a W-1th level scrambling circuit in a cascading order, each stage scrambling circuit is used to scramble 2 i ⁇ S bits, and each stage scramble circuit is scrambled
  • the number of bits is the same or different, W>1, i is an integer greater than or equal to 0, where:
  • Each stage scrambling circuit is connected to a multiplexer, each input of the multiplexer is a scrambled status word, and one of the inputs of the multiplexer is configured to be valid and configured
  • the scrambled status word corresponding to the active input is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation, wherein the input of the multiplexer connected to the i-th scramble circuit is derived from the i-th
  • the feedback from the stage to the W-1 level scrambling circuit and the feedforward of the i-1th stage scrambling circuit is derived from the i-th.
  • the X feedback calculation units include at least one second feedback a calculation unit, the second feedback calculation unit includes an L-stage scrambling circuit, wherein at least one of the L-stage scrambling circuits is formed by L1 scrambling circuits connected in parallel by L1 multiplexers, wherein the L The remaining scrambling circuit in the level scrambling circuit is used to scramble 2 i ⁇ S bits, W>1, i is an integer equal to 0 or greater than 0, n is an integer greater than or equal to 0, L>1, 1 ⁇ L1 ⁇ L, where;
  • Each scrambling circuit in the parallel scrambling circuit is connected to a multiplexer, and all multiplexers connected by the parallel scrambling circuit: each input of each multiplexer is a scrambled status word, One of the inputs of each multiplexer is configured to be active, and the scrambled status word corresponding to one of the active inputs is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation.
  • the input of each of the multiplexers is respectively derived from the feedback of the scramble circuit connected to itself, the feedback of all the post-stage scrambling circuits of the current scrambling circuit, and the front of the previous-stage scrambling circuit of the current scrambling circuit. Feed
  • Each stage of the scramble circuit except the parallel scramble circuit is connected to a multiplexer, and the multiplexer is connected to all stages of the scramble circuit except the parallel scramble circuit: each multiplexer
  • Each input of the device is a scrambled status word, one of the inputs of the multiplexer is configured to be active, and the scrambled status word corresponding to one of the valid inputs is output to the multiplex selection
  • the scramble circuit is connected to participate in the scrambling operation, wherein the input of each multiplexer is respectively derived from the feedback of all the post-stage scrambling circuits of the scramble circuit of the present stage, the feedback of the scramble circuit of the present stage, and the level Feedforward of the previous stage scrambling circuit of the scrambling circuit.
  • a fourth aspect provides a scrambling configuration method implemented based on the foregoing scrambling device, the method comprising:
  • a cascaded number of stages of a scrambling calculation unit for scrambling the n ⁇ S to-be-scrambled bits Determining, according to the n ⁇ S, a cascaded number of stages of a scrambling calculation unit for scrambling the n ⁇ S to-be-scrambled bits, and determining, according to the number of cascaded stages, for the one clock H cascaded scrambling calculation units that are scrambled by the periodically input to be scrambled bits, the H cascaded scrambling calculation units including a first scrambling calculation unit to an Hth scrambling calculation unit, the to The scrambling bits are scrambled by the first scrambling calculation unit to the Hth scrambling calculation unit in the order from the low bit to the high bit, and H represents the number of cascaded stages, Each scrambling calculation unit is configured to perform scrambling calculation on M ⁇ S bits in parallel;
  • the input channel of the scrambled status word output by the strobe feedback calculation unit is strobed for each scrambling calculation unit in the second to H-th scrambling calculation unit The input channel of the scrambled status word fed forward by the previous stage scrambling calculation unit;
  • a feedback calculation unit for calculating a scrambled status word for the n ⁇ S bits is determined according to the n ⁇ S.
  • the input channel of the scrambled status word output by the strobe feedback calculation unit for the first scrambling calculation unit includes:
  • the scrambled status word fed forward by the previous stage scrambling circuit The corresponding one input setting is valid, and the other input is set to be invalid;
  • the input channel of the scrambled status word fed forward by the previous stage scrambling calculation unit includes:
  • the previous stage scrambling calculation unit of the multiplexer connected to the scrambling circuit feeds forward
  • the one input corresponding to the scrambled status word is set to be valid, and the other input is set to be invalid;
  • a multiplexer connected to the scrambling circuit for each of the first to M-1 level scrambling circuits cascaded in each of the scramble calculation units in the second to the Hth level scrambling calculation unit
  • the one input corresponding to the scrambled status word fed forward by the middle-first stage scrambling circuit is set to be valid, and the other input is set to be invalid.
  • the method further includes:
  • a scrambling circuit level for calculating a scrambled status word for the n ⁇ S number of to-be-scrambled bits in a feedback calculation unit for calculating a scrambled status word for n ⁇ S bits Union number
  • B cascaded scrambling circuits for calculating the to-scrambled status word for the n ⁇ S to-be-scrambled bits, the B cascaded scrambling circuits including the first a scrambling circuit to the B-th scramble circuit, wherein the n ⁇ S to-be-scrambled bits are scrambled by the first scrambling circuit to the B-th scramble circuit in an order from a low bit to a high bit;
  • one input corresponding to the scrambled status word fed back by the Bth scrambling circuit is set to be valid, and the other input is set to be invalid;
  • one input corresponding to the scrambled status word fed forward by the previous stage scrambling circuit is set to be valid, and the other input is set to be invalid.
  • the method further includes:
  • n cascaded scrambling circuits for scrambling the n ⁇ S number of bits to be scrambled, the n cascaded scrambling calculation units including first to nth scrambling circuits, Said n ⁇ S to-be-scrambled bits are scrambled by the first to n-th scrambling calculation units in order from low-order bits to high-order bits;
  • one input corresponding to the scrambled status word fed back by the nth scramble circuit is set to be valid, and the other input is set to be invalid;
  • one input corresponding to the scrambled status word fed forward by the previous stage scrambling circuit is set to be valid, and the other input is set to be invalid.
  • each scrambling calculation unit includes a plurality of cascaded scrambling circuits, so that the number of bits to be scrambled can be selected according to the number of bits to be scrambled.
  • the corresponding number of scrambling calculation units perform scrambling calculation, that is, the scrambling calculation unit participating in the scrambling calculation can be selected according to the bandwidth requirement, thereby implementing flexible and configurable variable bandwidth Ethernet scrambling;
  • the feedback calculation unit calculates the scrambled status word and outputs it to the corresponding scrambling calculation unit, which can reduce the logical combination level of the scramble circuit internally cascaded by the scrambling calculation unit. Number, saving resources overhead.
  • FIG. 1 is a schematic diagram of a location of a scrambling operation in an Ethernet network in the prior art
  • FIG. 2 is a schematic structural diagram of a scrambling device 100 according to an embodiment of the present invention.
  • FIG. 3 is a structural diagram of a scrambling device with 64 bits as a minimum data unit according to an embodiment of the present invention
  • FIG. 4 is a schematic flow chart of a scrambling configuration implemented based on the scrambling device 100 shown in FIG. 2;
  • FIG. 5 is a schematic diagram of a scrambling process implemented based on the scrambling device 100 shown in FIG. 2;
  • FIG. 6 is a schematic diagram of the overall structure of a scrambling device 200 according to an embodiment of the present invention.
  • FIG. 7A and 7B are schematic diagrams showing the internal structure of the scrambling device 200 shown in FIG. 6, respectively;
  • FIG. 8 is a schematic diagram showing the internal structure of the scrambling calculation unit in FIG. 7A or FIG. 7B;
  • FIG. 10 and FIG. 11 are schematic diagrams showing internal structures of the feedback calculation unit in FIG. 7A or FIG. 7B, respectively;
  • FIG. 12 is a schematic diagram of an alternative manner of a scrambling device 200 according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a scrambling configuration flow implemented by the scrambling device 200.
  • the scrambling calculation is performed in the physical coding sublayer (English: physical coding sublayer, PCS).
  • the physical layer may include a coordination sublayer (English: reconciliation sublayer, abbreviated as: RS), a PCS, a physical medium attachment (PMA) sublayer, Physical media correlation (English: physical media, abbreviated as: PMD) sublayer.
  • RS reconciliation sublayer
  • PMA physical medium attachment
  • PMD Physical media correlation
  • PCS after multi-channel distribution, multiple PCS lanes are obtained and 64b/66b encoding is performed for each PCS lane. Then, the encoded multi-channel PCS lanes are separately scrambled, and finally the scrambled multi-channel data streams are virtualized.
  • Channel (English: virtual lane, referred to as: VL) distribution.
  • the scrambling calculation is done by the scrambling device.
  • the "scrambling device” can be implemented by a Field-Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).
  • FPGA Field-Programmable Gate Array
  • ASIC Application Specific Integrated Circuit
  • the scrambling device provided by the embodiment of the present invention may be a PHY (Chinese: physical layer), a PHY chip (English: PHY chip), a system chip (English: system chip), or a multi-port Ethernet device (English: multi-port Ethernet device) ).
  • the PHY can be implemented by an FPGA or an ASIC.
  • the PHY may be a component in a network interface card (English: network interface card, NIC for short), and the NIC may be a line card or a physical interface card (English: physical interface card, referred to as PCI) ).
  • the PHY may include a media-independent interface (MII) for connecting to a media access control (MAC) sublayer.
  • MII media-independent interface
  • MAC media access control
  • the PHY chip can include multiple PHYs.
  • the PHY chip can be implemented by an FPGA or an ASIC.
  • the system chip may include a plurality of MACs and a plurality of PHYs; the system chip may be implemented by an FPGA or an ASIC.
  • the multi-port Ethernet device can be an Ethernet hub, an Ethernet router, or an Ethernet switch. Place The multi-port Ethernet device includes a plurality of ports, each of which may include a system chip, and the system chip included in the port may include a MAC and a PHY. In the multi-port Ethernet device, it is also possible to integrate multiple MACs into one MAC chip (English: MAC chip), and integrate multiple PHYs into one PHY chip. The multi-port Ethernet device can also integrate multiple MACs and multiple PHYs into one system chip.
  • FIG. 2 is a schematic structural diagram of a scrambling device 100 according to an embodiment of the present invention.
  • the scrambling device 100 can include M scrambling circuits 11 and M multiplexers 12, which are cascaded into M-levels by the M multiplexers 12.
  • the scrambling circuit includes the 0th stage to the M-1th level scrambling circuit in a cascading order, and each stage scrambling circuit is used to scramble the S bits, M>1, S>1.
  • S represents the number of bits of the smallest data unit, and S takes the value of 64 when using the IEEE802.3ba Ethernet standard.
  • the M-stage scrambling circuit is configured as a pipeline structure, and includes a 0th stage to an M-1th level scrambling circuit in a pipeline execution order.
  • Each stage scrambling circuit is connected to a multiplexer, each input of the multiplexer is a scrambled status word, and one of the inputs of the multiplexer is configured to be valid and configured
  • the scrambled status word corresponding to the active one-way input is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation.
  • Each level scrambling circuit scrambles the to-be-scrambled bit input to the current-level scrambling circuit by using the scrambled status word selected by the multiplexer, outputs the scrambled result of the scrambling circuit of the present stage, and scrambles according to the current level
  • the scrambling result of the circuit results in a scrambled status word.
  • the scrambled status words calculated by each level of scrambling circuit are respectively fed back to the current level scramble circuit and the multiplexers connected by all the stage scrambling circuits before the stage, as one input of these multiplexers;
  • the scrambled state word calculated by the first-stage scrambling circuit is also fed forward to the multiplexer connected to the subsequent-stage scrambling circuit as one input of the multiplexer connected by the subsequent-stage scrambling circuit.
  • the inputs of the multiplexer connected to the i-th scramble circuit are respectively derived from the feedback of the i-th to M-1th scrambling circuits and the i-1th-level scramble circuit. Feed forward, 1 ⁇ i ⁇ N.
  • the inputs of the multiplexer connected to the level 0 scrambling circuit are derived from the feedback of the 0th stage and the 1st to M-1th level scrambling circuits, respectively.
  • the scrambled status word calculated by each level of the scrambling circuit is stored in a register of the current level scramble circuit and the multiplexer input connected to the previous level scrambling circuit, and the registers may be in the next clock cycle.
  • the stored scrambled status word is output to the current level scrambling circuit and the multiplexer connected to all the stage scrambling circuits before the stage.
  • the scrambled state word calculated by the scrambling circuit of each stage in the current clock cycle is fed forward to the multiplexer connected to the next-stage scrambling circuit without being registered, in the next clock cycle of the current clock cycle, according to The configuration of the path selector, the corresponding scrambled status word at its input is output to the scrambling circuit for scrambling calculation. That is, at the current clock Period, the scrambling status word used by each stage scrambling circuit for scrambling is calculated in the current clock cycle if it is the feedforward output of the pre-stage module; if it is the feedback output of the module of the current or subsequent stage, it is the current Calculated from the last clock cycle of the clock cycle.
  • a scrambled state word fed back to the previous stage by a scrambling circuit and a scrambled status word fed forward to the subsequent stage may be selected from the scrambled result of the scramble circuit, that is, Part of the bits in the scrambling result are used as scrambling status words.
  • the selection of the scrambled status word is related to the self-synchronizing scrambling algorithm employed. For example, if the scrambling algorithm described by the following code is used, the scrambling circuit selects the last 58 bits of the scrambling result as the scrambled status word fed back to the previous stage and fed forward to the subsequent stage:
  • the input source of the multiplexer includes the scrambled status word fed back by the 0th stage scrambling circuit and the scrambled feedback by the 1st to M-1th level scrambling circuit.
  • the status word has a total of M inputs, so you need to use the M:1 multiplexer.
  • the input source of the multiplexer includes the scrambled status word fed back by the first-stage scrambling circuit, the scrambled status word fed forward by the 0th-level scrambling circuit, and the 2nd to the M-
  • the scrambled status word fed back by the level 1 scrambling circuit has a total of M inputs, so it is also necessary to use the M:1 multiplexer.
  • the input source of the multiplexer includes the scrambled status word fed back by the second-stage scrambling circuit, the scrambled status word fed by the first-stage scrambling circuit, and the third to M-1 stages.
  • each scrambling circuit in the scrambling device 100 is paralleled in one clock cycle.
  • the number of bits processed is the same as the number of bits of the smallest data unit.
  • the number of bits of the smallest data unit in the 100G Ethernet standard is 64, so the bandwidth of each scrambling circuit 11 in the scrambling device 100 is 64 bits, that is, one scrambling circuit 11 is Configured to scramble 64-bit data in parallel.
  • the scrambling circuit located at the intermediate position calculates that the scrambled status word is directly fed back to the current stage and each pre-stage scrambling circuit is connected without going through the register.
  • a path selector that is fed forward to the multiplexer connected to the next stage scrambling circuit so that these feedback and feedforward scrambled status words Both take effect on the next clock cycle, improving the accuracy of the scrambling calculation.
  • the number of scrambling circuits cascaded in the scrambling device 100 is optional. Can be controlled within a certain range. For example, for flexible Ethernets of 100G and less, the number of cascaded scrambling circuits can be chosen to be four. For flexible Ethernet of 400G or more, the FPGA can be structurally optimized when the FPGA is scrambled, or ASIC can be used for scrambling.
  • Figure 3 shows a scrambling device with a 64 bits scrambling circuit as a basic scrambling unit.
  • Mux represents a multiplexer.
  • Curr_poly and Next_poly represent the scrambled status word before data scrambling and the new scrambled status word generated after data scrambling, respectively, and both are 58 bits.
  • Unscrambler_data indicates the data to be scrambled
  • scrambled_data indicates the scrambled data
  • the data to be scrambled and the scrambled data are both 64 bits.
  • the process of flexibly configuring the scrambling according to the bandwidth of the data to be scrambled may be as shown in FIG. 4, including:
  • S401 Acquire the number of bits to be scrambled input by one clock cycle.
  • the bandwidth of the electrical layer logical interface can be flexibly configured.
  • One electrical layer logical interface corresponds to multiple PCS lanes, and the bandwidth of one PCS lane is fixed.
  • One or more PCS lanes can be defined as one substream.
  • An electrical layer logical interface can be divided into one or more substreams.
  • the data stream of the MAC sublayer can distribute the data to the substream of the corresponding electrical layer logical interface according to the flow label (id).
  • the PCS lanes of the data streams belonging to the same MAC sublayer need to be scrambled together. Therefore, the data stream for one MAC sublayer is scrambled using a scrambling device 100.
  • the "bits to be scrambled input by one clock cycle" described herein belongs to a data stream of one MAC sublayer.
  • a module that implements the data distribution function to distribute the to-be-scrambled bits of the data stream belonging to the same MAC sub-layer to the scrambling device for scrambling processing.
  • the embodiment of the present invention does not limit the specific implementation process of distributing the to-be-scrambled bits to the scrambling device.
  • S represents the number of bits of the smallest data unit
  • S takes the value of 64 when using the IEEE802.3ba Ethernet standard.
  • each scrambling circuit scrambles the S bits, it is input according to one clock cycle.
  • the K scrambling circuits are referred to as first to Kth scrambling circuits in a cascading sequence, and all the to-be-scrambled bits input in one clock cycle are distributed to the first to the order from the low bit to the high bit.
  • the Kth scrambling circuit, each scrambling circuit is distributed to S bits. For example, among the K scrambling circuits, the first scrambling circuit scrambles the PCS lane 0, the second scrambling circuit scrambles the PCS lane 1, and so on, and the Kth scramble circuit adds the PCS lane K-1 Disturb.
  • K cascaded scrambling circuits may be selected starting from any one of the M scrambling circuits cascaded in the scrambling device 100.
  • the 0 to K-1 level scrambling circuit may be selected to perform scrambling calculation
  • the 1st to Kth level scrambling circuits may be selected to perform scrambling calculation.
  • S403 For the multiplexer connected to the first scrambling circuit, set the feedback of the Kth scrambling circuit of all the channel inputs to be valid, and set the other channel inputs to be invalid, for the second to Kth stage scrambling circuits.
  • the multiplexer connected to each scrambling circuit sets the feedforward of the previous stage scrambling circuit of all the circuit inputs to be valid, and sets the other path inputs to be invalid.
  • the scrambled state word calculated by the Kth scrambling circuit can be fed back to the first scrambling circuit, and the scramble circuit other than the Kth scramble circuit in the selected K-stage cascade scrambling circuit is The calculated scrambled status word is fed forward to the next stage scrambling circuit.
  • K ⁇ M that is, only a part of the cascaded scrambling circuit is selected from the M-level scrambling circuit to perform the scrambling operation, for the scrambling circuit that is not selected to perform the scrambling operation, due to its feedback
  • the scrambled status word of the pre-stage scrambling circuit and the scrambled status word fed forward to the next-stage scrambling circuit are all set to be invalid, and thus have no effect on the scrambling operation of the scrambling circuit selected to perform the scrambling operation. .
  • the number of bits to be scrambled input by one clock cycle is S, only one scrambling circuit needs to be selected for the scrambling operation.
  • the scrambling circuit is configured, for the multiplexer connected to the scrambling circuit, the feedback of the scrambling circuit in all the path inputs is set to be valid, and the other path inputs are set to be invalid.
  • the above process can be performed by a control circuit.
  • the control circuit sets the state of the registers that control the input of the multiplexer by transmitting control signals to the respective multiplexers.
  • the scrambling process can be as shown in FIG. 5, including:
  • S501 K cascaded scrambling circuits selected to perform scrambling calculation receive the first clock cycle input to be added Disturbing bits. Each scrambling circuit receives a PCS lane.
  • the to-be-scrambled bits input in one clock cycle belong to the data stream of the same MAC sub-layer.
  • the bits to be scrambled may be first divided into minimum data units, and the number of bits S of the minimum data unit is equal to 64, and the bits to be scrambled are divided into 64 bits, and each level of scrambling circuit obtains a 64. Bit block.
  • S502 Each of the K scrambling circuits scrambles the input to-be-scrambled bits in parallel, respectively.
  • the scrambled result output by the K scrambling circuits constitutes the scrambled result of the bit to be scrambled input in S501.
  • each of the K scrambling circuits adds a to-be-scrambled bit received by the scrambling circuit by using a first scrambled status word output by the multiplexer connected to the scrambling circuit. Disturbing, obtaining a second scrambled status word according to the scrambled result, and feeding back the second scrambled status word to the multiplexer connected to the first scramble circuit by the scramble circuit, and feeding forward to the present A multiplexer connected to the next-stage scrambling circuit of the scrambling circuit.
  • the first scrambled status word is divided into two categories: one is a scrambled status word calculated from a first clock period of the previous stage; and the other is a scrambled state calculated by the second clock period of the current stage and subsequent stages word.
  • the second clock cycle is the last clock cycle of the first clock cycle.
  • the scrambled status word used in scrambling of each level of scrambling circuit is calculated in the current clock cycle if it is the feedforward output of the pre-stage module; if it is the current or post-level module
  • the feedback output is calculated from the previous clock cycle of the current clock cycle.
  • the scrambled state word calculated by the scrambling circuit of each stage in the current clock cycle is fed forward to the next-stage scrambling circuit without being registered, and is simultaneously stored in the register of the corresponding multi-channel selector input of the current stage and the previous stage, Update the scrambled status word stored in this register.
  • the corresponding scrambled status word at its input is output to the scrambling circuit for scrambling calculation.
  • each stage scrambling circuit performs an exclusive OR operation on some bits of the input to-be-scrambled bits according to a scrambling algorithm and some bits of the scrambled status word to obtain a scrambled result.
  • a scrambling algorithm described in the following code can be used:
  • the input of the multiplexer connected to each level of the scrambling circuit further includes an initially set scrambling status word.
  • the scrambling circuit performs scrambling calculation using the initially set scrambling status word. For example, if the 0 ⁇ K-1 level scrambling circuit is selected to perform the scrambling calculation, in the initial case, the 0th to K-1th level scrambling circuit uses the initial set scrambling pattern.
  • the state word is scrambled.
  • the value of the initially set scrambling status word can be all ones or other non-zero values, depending on the algorithm.
  • the scrambling circuit can return to the initial state according to the set period.
  • the scrambling circuit is cascaded by the multiplexer, and the input of the multiplexer connected to each level of the scrambling circuit comes from The scrambled status word fed back by the scrambling circuit of the current stage, the scrambled status word fed back by each level scramble circuit after the scramble circuit of the current stage, and the scrambled status word fed forward by the scramble circuit of the previous stage, so that Selecting one or more cascaded scrambling circuits for performing scrambling calculation according to the number of bits of the data to be scrambled input by one clock cycle, by configuring the scramble circuit selected to perform the scrambling calculation
  • the active state of the input of the path selector is transmitted to the scrambling circuit to participate in the scrambling calculation by strobing the corresponding scrambled status word.
  • the embodiment of the present invention provides a flexible and configurable scrambling structure, which can select a corresponding number of scrambling circuits to perform scrambling calculation according to the number of bits to be scrambled input in one clock cycle, and is selected through configuration.
  • the multiplexer connected to the scrambling circuit causes the selected scrambling circuit to perform scrambling calculation using the correct scrambled status word, thereby implementing flexible and configurable variable bandwidth Ethernet scrambling.
  • the second embodiment proposes an optimization scheme of multi-granular structure parallel connection based on the cascade of scrambling circuits.
  • FIG. 6 is a schematic structural diagram of a scrambling device 200 according to Embodiment 2 of the present invention.
  • the scrambling device 200 includes a scrambling module 21 and a feedback module 22.
  • the scrambling module 21 is configured to perform scrambling calculation
  • the feedback module 22 is configured to perform calculation of the scrambled status word and output the calculated scrambled status word to the scrambling module 21, so that the scrambling module performs the scrambling status word according to the scrambling status word.
  • Scrambling calculation The scrambling calculation and scrambling status word calculation are separately processed by setting the scrambling module 21 and the feedback module 22.
  • the scrambling module 21 may employ a pipelined structure to reduce the number of combined logic stages.
  • the scrambling module 21 may implement scrambling calculation through a plurality of cascaded scrambling calculation units.
  • Each level scrambling calculation unit is configured to scramble the to-be-scrambled bits input to the present scrambling calculation unit according to the scrambled status word output by the feedback module 22 or the scrambled status word fed forward by the previous-stage scrambling calculation unit .
  • the scrambled status word outputted by the feedback module 22 to the scrambling module 21 is calculated in the previous clock cycle of the current clock cycle.
  • the calculation of the scrambled status word required to complete in one clock cycle is implemented by the feedback calculation unit in feedback module 22.
  • the feedback module 22 includes one or more feedback calculation units according to different bandwidth requirements.
  • a feedback calculation unit can be implemented by only the primary scrambling circuit to calculate the scrambled status word for a bandwidth requirement.
  • One The feedback calculation unit can also be implemented by a multi-stage scrambling circuit to calculate a scrambled status word for a plurality of bandwidth requirements.
  • 7A and 7B are diagrams showing the internal structure of the scrambling device 200.
  • the scrambling module 21 includes a first input selector 211, a first output selector 213, and an R-level scrambling calculation unit that is cascaded by R scrambling calculation units 212, R>1, among them:
  • the first input selector 211 is a multiplexer located on the side of the scrambling bit input side of the scrambling calculation unit for distributing the to-be-scrambled bits input in the first clock cycle to the to-be-scrambled a scrambling calculation unit for bit scrambling calculation or K cascaded scrambling calculation units, 1 ⁇ K ⁇ R;
  • Each level scrambling calculation unit 212 is configured to: according to the scrambled status word fed forward by the previous stage scrambling calculation unit or the scrambled status word output by the feedback module, the to-be-scrambled bits distributed to the scrambling calculation unit of the present stage Perform scrambling;
  • the first output selector 213 is a multiplexer located on the side of the scrambled result output end of the scrambling calculation unit for combining the scrambled result of the scramble calculation unit performing the scrambling calculation into the to-be-scrambled bit The scrambled result is output.
  • the feedback module 22 includes a second input selector 221, a second output selector 223, and X feedback calculation units 222, X ⁇ 1, where:
  • the second input selector 221 is a multiplexer located on the side of the input of the feedback calculation unit to be scrambled, and is configured to perform the scrambling according to the number of bits to be scrambled input according to the first clock cycle. Bits are distributed to a feedback calculation unit for computing a scrambled status word for the number of bits;
  • Each feedback calculation unit 222 is configured to calculate a scrambled status word according to the to-be-scrambled bits distributed by the second input selector 221;
  • the second output selector 223 is a multiplexer located on the side of the scrambled state word output end of the feedback calculation unit for outputting the scrambled status word calculated by the feedback calculation unit 222 to the scramble calculation unit 212.
  • each scrambling calculation unit is configured to perform scrambling calculation on the M ⁇ S bits in parallel, where S is the number of bits of the smallest data unit, for example, the value of S may be 64, M>1.
  • factors such as resource consumption and difficulty of implementation may be comprehensively determined to determine the value of M. The larger the value of M, the more resource consumption and the difficulty of implementation.
  • each scrambling calculation unit performs scrambling calculation on M ⁇ S bits in parallel:
  • the first input selector 211 may distribute the n ⁇ S to-be-scrambled bits input by the first clock cycle to the H cascaded scrambling calculation units, among them, Indicates rounding up;
  • the lowest level scrambling calculation unit is specifically configured to add the to-be-scrambled bits distributed to the current scrambling calculation unit according to the scrambled status word output by the feedback calculation unit.
  • the scrambling calculation unit is specifically configured to perform scrambling calculation on the to-be-scrambled bits distributed to the scrambling calculation unit of the current level according to the scrambled status word fed forward by the scrambling calculation unit of the previous-stage scrambling calculation unit;
  • the second input selector 221 is specifically configured to: distribute the n ⁇ S to-be-scrambled bits input by the first clock cycle to a feedback calculation unit for calculating a scrambled status word for the n ⁇ S bits;
  • the second output selector 223 is specifically configured to: output the scrambled status word calculated by the feedback calculation unit for calculating the scrambled status word for the n ⁇ S bits into the H cascaded scrambling calculation unit The lowest level of scrambling calculation unit.
  • a register or register set 214 (“reg 241" as shown in FIG. 7B) is also connected between adjacent two-stage scrambling calculation units, which is called for convenience of description. Is the first register or the first register set.
  • the first register or the first register set is configured to delay the scrambled status word calculated by the adjacent two-stage scrambling calculation unit by Y (Y ⁇ 1) clock cycles, and then input to the next-stage scrambling calculation unit.
  • the first register set may be formed by serially connecting Y registers, wherein each register may delay data by one clock cycle and output.
  • the scrambling results of all the scrambling calculation units are passed through a register or a register set (referred to as a second register or referred to as a
  • the two register sets are output to the first output selector after being delayed by the corresponding clock cycle, and the second register set may be formed by a plurality of register serial connections.
  • the number of registers in the second register set connected to the output of the scrambled result of each level of scrambling calculation unit is related to the number of registers in the first register set between stages.
  • the R cascaded scrambling calculation units are the 0th stage scrambling calculation unit to the R-1th level scrambling calculation unit, and the scrambling result output end of the 0th stage scrambling calculation unit is connected by R ⁇ Y
  • the second register group is connected in series with the register, and the scrambling result output end of the first-stage scrambling calculation unit is connected to the second register group which is serially connected by (R-1) ⁇ Y registers, and the second level is scrambled.
  • the scrambling result output terminal of the calculation unit is connected to the second register group which is serially connected by (R-2) ⁇ Y registers, and so on, and the second of the scrambling calculation unit of each level of the scrambling calculation unit is connected to the output end.
  • the number of registers in the register set is more than Y in the subsequent level of scrambling calculation unit.
  • FIG. 8 shows an internal structure of a scrambling calculation unit 212, in which Curr_poly and Next_poly respectively represent a scrambled status word before scrambling of current clock cycle data and a scrambled state generated after data scrambling, respectively.
  • Words such as the scrambled status word can be 58 bits.
  • the scrambling calculation unit 212 may include: M scrambling circuits and M multiplexers, wherein the M scrambling circuits are cascaded into M-level scrambles by the M multiplexers.
  • the M-stage scrambling circuit includes a 0th stage to an M-1th level scrambling circuit in a cascading order, each stage scramble circuit Used to scramble S bits, M>1, S>1, where:
  • Each stage scrambling circuit is connected to a multiplexer, each input of the multiplexer is a scrambled status word, and one of the inputs of the multiplexer is configured to be valid and configured
  • the scrambled status word corresponding to the active input is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation, wherein the input of the multiplexer connected to the i-th scramble circuit is derived from the i-th
  • the input of the multiplexer connected to the level 0 scrambling circuit is derived from the feedback of the M-1 stage scrambling circuit.
  • the scrambled status word calculated by the M-1th level scrambling circuit in a scrambling calculation unit is output to the 0th stage scramble circuit in the next-stage scrambling calculation unit of the scrambling calculation unit of the current stage.
  • the input of the connected multiplexer Specifically, for the 0th stage scrambling calculation unit, one input of the multiplexer connected to the 0th stage scrambling circuit in the 0th stage scrambling calculation unit is from the R-1 level scrambling calculation unit The scrambled status word output by the M-1 level scrambling circuit.
  • the scrambled status word calculated by each scrambling circuit is delayed by one clock period and returned to the multiplexer connected to the scrambling circuit via a register (the reg represents the register).
  • the scrambled status word calculated by each scrambling circuit in a scrambling calculation unit is delayed by one clock period and then fed back to the multiplexers connected by all the pre-stage scrambling circuits.
  • the to-be-scrambled bit input of each scrambling circuit is selected with the first input
  • a third register or a third register set is connected between the outputs of the devices, and the third register set may be composed of a plurality of registers.
  • the number of clock cycles to be scrambled by the scrambling circuit of the previous stage is less than Y, and the Y is two adjacent levels of scrambling. Between the calculation units, the number of clock cycles that the previous stage scrambling calculation unit feeds forward to the scrambled state word of the subsequent stage scrambling calculation unit is delayed.
  • the feedback module in the scrambling device 200 will be described in detail below.
  • a scrambling calculation unit can be set according to bandwidth requirements.
  • a scrambling calculation unit can be a multi-stage scrambling structure that can be flexibly configured for different bandwidth requirements.
  • the X feedback calculation units in the feedback module 22 of the scrambling device 200 include at least one first feedback calculation unit.
  • the first feedback calculation unit includes W (W>1) scrambling circuits and W multiplexers, and the W scrambling circuits are cascaded by the W multiplexers to classify W levels.
  • the circuit, the W-stage scrambling circuit includes a 0th stage to a W-1th stage scrambling circuit in a cascading order.
  • Each level of scrambling circuit is used to scramble 2 i ⁇ S (i is an integer greater than or equal to 0) bits, S represents the number of bits of the smallest data unit, and S takes 64 as the IEEE 802.3ba Ethernet standard. That is, each stage of the scrambling circuit is a power 2 granularity scrambling circuit.
  • the first feedback calculation unit is referred to as a power 2 granularity feedback calculation unit.
  • each stage scrambling circuit is connected to a multiplexer, each input of the multiplexer is a scrambled status word, and all the inputs of the multiplexer One of the inputs is configured to be active, and the scrambled status word corresponding to one of the active inputs is output to the scramble circuit connected to the multiplexer to participate in the scrambling operation, wherein the i-th scramble circuit is connected
  • the inputs of the multiplexer are derived from the feedback of the i-th stage to the W-1th level scrambling circuit and the feedforward of the i-1th stage scramble circuit.
  • the number of bits scrambled by each power 2 granularity scrambling circuit may be the same or different, and may be calculated for different numbers of to-be-disturbed bits by different combinations. Scramble status word.
  • a power 2 granularity feedback calculation unit includes three cascaded scrambling circuits, and each scrambling circuit is configured to scramble 2 2 ⁇ 64 bits in parallel, so that 4 ⁇ 64 bits, 8 ⁇ can be satisfied. 64bits, 12 ⁇ 64bits three bandwidth requirements.
  • a power 2 granularity feedback calculation unit includes three cascaded scrambling circuits, including a 2 1 ⁇ 64 bits granular scrambling circuit, a 2 2 ⁇ 64 bits granular scrambling circuit, and 2 3 ⁇ in a cascading order.
  • the 64-bit granularity scrambling circuit can satisfy seven bandwidth requirements of 2 ⁇ 64 bits, 4 ⁇ 64 bits, 6 ⁇ 64 bits, 8 ⁇ 64 bits, 10 ⁇ 64 bits, 12 ⁇ 64 bits, and 14 ⁇ 64 bits.
  • the different power 2 granularity feedback calculation units may have differences in one or more aspects, and thus may be satisfied by different power 2 granularity feedback calculation units.
  • the different bandwidth requirements, the one or more aspects may include: the number of cascaded scrambled feedback circuits is different, and the bandwidth of the scrambled feedback circuit is different (ie, the number of scrambled bits of the scrambling circuit is different).
  • the partial power 2 granularity feedback calculation unit may calculate the scrambled status word for the small bandwidth requirement, and the partial power 2 granularity feedback calculation unit may be for large The bandwidth requirement calculates the scrambling status word.
  • the power 2 granularity feedback calculation unit may employ a scrambling circuit cascade of the same granularity. For example, if the number of bits to be scrambled input in one clock cycle is less than 128 bits, the feedback calculation unit of the power 2 granularity may be cascaded by two 64-bit scrambling circuits through two multiplexers, so that the power 2 The granularity feedback calculation unit may calculate the scrambled status word for the bits to be scrambled from 64 bits to 128 bits.
  • the power 2 granularity feedback calculation unit may be cascaded with a larger granularity scrambling circuit, for example, 128 bits or a 256-bit scrambling circuit cascade, wherein a 128-bit scrambling circuit indicates that the scrambling circuit is configured to be in parallel
  • the scrambling calculation is performed on 128 bits
  • the 256-bit scrambling circuit indicates that the scrambling circuit is configured to perform scrambling calculation on 256 bits in parallel.
  • a power 2 granularity scrambling circuit cascade is used in the power 2 granularity feedback computing unit, which can better satisfy the timing realizability.
  • cascading scrambling circuits with different powers of 2 granularity can also meet different bandwidth requirements and meet the most resource-saving requirements.
  • Fig. 9 exemplarily shows the internal structure of a power 2 granularity feedback calculation unit.
  • Curr_poly and Next_poly represent the scrambled status word before scrambling of the current clock cycle data and the scrambled status word generated after data scrambling, respectively.
  • Reg represents a register that is used to delay the data output after one clock cycle. Since the scrambled status word is actually obtained by delaying a part of the bits of the scrambled data by one clock cycle, the power 2 granularity feedback calculation unit is similar to the internal structure of the scramble calculation unit.
  • the path selector (mux in the figure represents a multiplexer) is cascaded to calculate the scrambled status word for a plurality of bit width requirements with fewer cascade stages.
  • the Curr_poly of each power 2 granularity scrambling circuit comes from the multiplexer.
  • the input of the multiplexer comes from the feedback poly of the scrambling circuit itself, the feedforward poly of the pre-stage scrambling circuit, and the feedback of the post-stage scrambling circuit. Poly.
  • the Next_poly of each power 2 granularity scrambling circuit is delayed by one clock cycle after the register is delayed to generate the feedback poly of the current scrambling circuit.
  • the scrambling circuits at each level only contain the computational logic of the feedback poly.
  • the need to calculate the scrambled status word for the odd-numbered 64-bit bandwidth is optional.
  • at least one of the X feedback calculation units in the feedback module 22 of the scrambling device 200 may be included.
  • the second feedback calculation unit includes an L (L>1) level scrambling circuit, wherein at least one level of the scrambling circuit in the L-stage scrambling circuit is performed by L1 (1 ⁇ L1 ⁇ L)
  • the scrambling circuit is constructed by paralleling L1 multiplexers, and the remaining scrambling circuits in the L-stage scrambling circuit are used to scramble 2 i ⁇ S (i is an integer equal to 0 or greater than 0) bits.
  • each of the parallel scrambling circuits is connected to a multiplexer, and all of the multiplexers connected by the parallel scrambling circuit: each of the multiplexers One input is a scrambled status word, one of all the inputs of each multiplexer is configured to be active, and the scrambled status word corresponding to one input is configured to be output to the multiplexer.
  • the scrambling circuit participates in the scrambling operation, wherein the input of each multiplexer is respectively derived from the feedback of the scramble circuit connected thereto, the feedback of all the post-stage scrambling circuits of the current scrambling circuit, and the scrambling of the current stage Feedforward of the previous stage scrambling circuit of the circuit.
  • each stage of the scramble circuit except the parallel scramble circuit is connected to a multiplexer, and all the stages of the scramble circuit except the parallel scramble circuit are connected in multiple ways.
  • each more Each input of the way selector is a scrambled status word, one of the inputs of the multiplexer is configured to be active, and the scrambled status word corresponding to one input is configured to be outputted
  • the scramble circuit connected to the path selector is configured to participate in the scrambling operation, wherein the input of each multiplexer is respectively derived from the feedback of all the post-stage scrambling circuits of the current scrambling circuit, the feedback of the current scrambling circuit, and Feedforward of the previous stage scrambling circuit of the scrambling circuit of this stage.
  • the plurality of parallel scrambling circuits are located at the same level in the pipeline structure, and at least one of the parallel scrambling circuits is configured to parallel to an odd multiple of S
  • the bits are scrambled (S is the number of bits of the smallest data unit) so that the scrambled status word for odd multiples of S bits is available.
  • the second feedback calculation unit is configurable to calculate the scrambled status word for an odd multiple of the S bits
  • a feedback calculation unit that computes the power 2 granularity of the scrambled status word for only an even multiple of the S bits provides a complementary scheme, thus
  • the second feedback calculation unit is hereinafter referred to as a supplementary granularity feedback calculation unit.
  • FIG. 10 exemplarily shows an internal structure diagram of a supplementary granularity feedback calculation unit.
  • the supplementary granularity feedback calculation unit includes a plurality of power 2 granularity scrambling circuits and a plurality of complementary granularity scrambling circuits.
  • the J ⁇ 64bits scrambling circuit and the K ⁇ 64bits scrambling circuit are connected in parallel and are located at the same level.
  • the reg in the figure represents a register for delaying data by one clock cycle.
  • the scrambling calculation bit width of the supplementary granularity scrambling circuit may be a power of 2 granularity or a powerless 2 granularity.
  • the value of J and/or K in the figure may be 2 n (n is an integer equal to 0 or greater than 0), or may be an odd number.
  • the Curr_poly of the scrambling unit of each level comes from the multiplexer.
  • the input of the multiplexer comes from the scrambled status word fed back by the scrambling circuit itself, the scrambled status word fed forward by the pre-stage scrambling circuit and the post-stage scrambling circuit.
  • the scrambled status word of the feedback comes from the Next_poly of each level scrambling circuit.
  • the Next_poly of each level scrambling circuit is delayed by one clock cycle to generate a scrambled status word fed back by the current scrambling circuit.
  • the scrambling circuits of the same stage are in a parallel relationship, and do not pass the feedforward scrambled status word or the feedback scrambled status word.
  • Each scrambling circuit only contains the computational logic of the scrambled status word.
  • the supplemental granularity feedback calculation unit is generally used as a supplement to the power 2 granularity feedback calculation unit.
  • the supplemental granularity feedback calculation unit can achieve equivalent functions with fewer cascaded stages, but at the cost of requiring more resource consumption.
  • the aforementioned 3-level feedback calculation unit formed by cascading a 2 1 ⁇ 64 bits granular scrambling circuit, a 2 2 ⁇ 64 bits granular scrambling circuit, and a 2 3 ⁇ 64 bits granular scrambling circuit cannot cover an odd multiple 64 bits.
  • the wide scrambled state word calculates the demand, which can be solved by adding a level 1 2 0 ⁇ 64 bits scrambling unit + 1 multiplexer.
  • an increase in the number of cascaded stages increases the difficulty of implementation. If the scramble calculation unit of the supplementary granularity shown in Fig. 11 is used, the same purpose can be achieved without increasing the number of cascade stages.
  • the feedback calculation unit in FIG. 11 is a three-stage cascade structure, that is, a 2 3 ⁇ 64 bits scrambling circuit + 2 2 ⁇ 64 bits scrambling circuit + a 3 ⁇ 64 bits 2 / 64 bits / 1 ⁇ 64 bits scramble circuit connected in parallel,
  • the equivalent function of the feedback calculation unit of the cascade of 4 levels is realized by the cascade of 3 levels.
  • FIG. 12 shows an alternative configuration of a scrambling device 200.
  • the feedback module includes p power 2 granularity feedback computing units and q supplementary granularity feedback computing units.
  • the process of flexibly configuring the scrambling according to the bandwidth of the data to be scrambled may be as shown in FIG. 13, and includes:
  • S1301 Acquire the number of n ⁇ S to-be-scrambled bits input in one clock cycle.
  • S represents the number of bits of the smallest data unit, and S takes the value of 64 when using the IEEE802.3ba Ethernet standard.
  • the bandwidth of the electrical layer logical interface can be flexibly configured.
  • One electrical layer logical interface corresponds to multiple PCS lanes, and the bandwidth of one PCS lane is fixed.
  • One or more PCS lanes can be defined as one substream.
  • An electrical layer logical interface can be divided into one or more substreams.
  • the data stream of the MAC sublayer can distribute the data to the substream of the corresponding electrical layer logical interface according to the flow label (id).
  • the PCS lanes of the data streams belonging to the same MAC sublayer need to be scrambled together. Therefore, the data stream for one MAC sublayer is scrambled using a scrambling device 100.
  • the "bits to be scrambled input by one clock cycle" described herein belongs to a data stream of one MAC sublayer.
  • a module that implements the data distribution function to distribute the to-be-scrambled bits of the data stream belonging to the same MAC sub-layer to the scrambling device for scrambling processing.
  • the embodiment of the present invention does not limit the specific implementation process of distributing the to-be-scrambled bits to the scrambling device.
  • S1302 Determine, according to the n ⁇ S, a number of cascaded stages of scrambling calculation units used to scramble the n ⁇ S to-be-scrambled bits, and determine, according to the number of cascaded stages, H cascaded scrambling calculation units for scrambling the input to be scrambled bits of one clock cycle, the H cascaded scrambling calculation units including the first scrambling calculation unit to the Hth scrambling calculation unit
  • the scrambling bits are scrambled from the first scrambling calculation unit to the Hth scrambling calculation unit in order from the low bit to the high bit, where H represents the number of cascaded stages, Representing rounding up, each scrambling calculation unit is configured to scramble the M x S bits in parallel.
  • each scrambling circuit scrambles the M ⁇ S bits
  • the number of to-be-scrambled bits input n ⁇ S according to one clock cycle can determine the scrambling calculation unit for performing the scrambling operation.
  • the number of cascaded levels is H, of which Then, H cascaded scrambling calculation units are selected according to the cascaded number H, and the H scrambling calculation units scramble all the bits to be scrambled.
  • the H scrambling calculation units are referred to as first to H-th scrambling calculation units in a cascading order, and all to-be-scrambled bits input in one clock cycle are distributed to the order from low-order bits to high-order bits.
  • each scramble calculation unit is distributed to the M ⁇ S bits, and if the number of bits distributed by the last stage scrambling calculation unit is less than M ⁇ S, the redundant calculation unit is configured Not enabled.
  • H cascaded scrambling calculations may be selected from any one of the R scrambling circuits cascaded in the scrambling device 200. unit.
  • the 0th to the H-1th scrambling calculation unit may be selected to perform the scrambling calculation, or the 1st to the Hth level scrambling calculation unit may be selected to perform the scrambling calculation.
  • S1304 Determine, according to the n ⁇ S, a feedback calculation unit for calculating a scrambled status word for the n ⁇ S bits.
  • S1304 may also occur before S1303 or simultaneously with S1303.
  • the process of configuring the first scrambling calculation unit in S1303 may include: a multiplexer connected to the 0th stage scrambling circuit among the M scrambling circuits cascaded in the first scrambling calculation unit And setting one input corresponding to the scrambled status word outputted by the feedback module to be valid, and setting other input to be invalid; for the first to M- of the M scrambling circuits cascaded in the first scrambling calculation unit; The multiplexer connected to the level 1 scrambling circuit sets one input corresponding to the scrambled status word fed forward by the previous stage scrambling circuit to be valid, and sets the other input to be invalid; for the second to the Hth level The cascading level 0 scrambling circuit in each scrambling calculation unit in the scrambling calculation unit, the one input corresponding to the scrambled status word fed forward by the previous stage scrambling calculation unit in the multiplexer connected to the scrambling circuit Set to be valid, set other path inputs to be invalid; each scrambled in
  • determining, by the n ⁇ S, a feedback calculation unit for calculating a scrambled status word for the n ⁇ S bits further includes a process of configuring the feedback calculation unit.
  • the process of configuring the feedback calculation unit may include:
  • a scrambling circuit level for calculating a scrambled status word for the n ⁇ S number of to-be-scrambled bits in a feedback calculation unit for calculating a scrambled status word for n ⁇ S bits Union number
  • the B cascaded scrambling circuit includes a first scrambling circuit to a Bth scrambling circuit, and the n ⁇ S to-be-scrambled bits are in order from a low bit to a high bit Scrambling from the first scrambling circuit to the Bth scrambling circuit;
  • the register for storing the scrambled status word fed back by the Bth scramble circuit is set to be valid, and the other registers for storing the scrambled status word are set to be invalid;
  • one input corresponding to the scrambled status word fed forward by the previous stage scrambling circuit is set to be valid, and the other input is set to be invalid.
  • n ⁇ M that is, the input to-be-scrambled bits are subjected to scrambling calculation by a scrambling calculation unit
  • a scrambling calculation unit is selected to determine that the n ⁇ S are to be scrambled n concatenated scrambling circuits scrambled by bits, the n concatenated scrambling calculation units including first to nth scrambling circuits, the n ⁇ S to-be-scrambled bits according to low-order bits The order to the high bits is scrambled by the first to nth scrambling calculation units.
  • one input corresponding to the scrambled status word fed back by the nth scramble circuit is set to be valid, and the other input is set to be invalid.
  • one input corresponding to the scrambled status word fed forward by the previous stage scrambling circuit is set to be valid, and the other input is set to be invalid.
  • the data stream to be scrambled input by one clock cycle is split into n 64-bit bit data streams, and respectively fed into multiple M ⁇ 64 bits in parallel.
  • the scrambling calculation unit and the feedback calculation unit The M ⁇ 64bits scrambling calculation unit generates n channels of 64-bit scrambled data according to the input n-channel scrambling data and the scrambled status word provided by the feedback calculation unit, and outputs the data.
  • the second input selector outputs the data to be scrambled to the feedback calculation unit according to the difference in the bandwidth configuration mode.
  • the scrambled status word generated by the feedback calculation unit is output to the scramble calculation unit through the second output selector.
  • the first input selector distributes 4*64 bits to the scrambling calculation unit of the 0th order M*64bits, and assigns the subsequent 4*64 bits to the scramble calculation unit of the first level M*64bits, and the subsequent 2* 64bits is assigned to the second level M*64bits scrambling calculation unit.
  • the second input selector distributes the 10*64 bits of data to be scrambled to a feedback calculation unit for computing a 10*64 bits scrambled status word, which may be cascaded by (2 2 *64 bits + 2 3 *64 bits) to make.
  • the scrambling calculation unit of the 0th stage M*64bits uses the scrambled status word outputted by the feedback calculation unit (calculated for the last input to be scrambled bit) to scramble, and outputs the scrambled result to the first output.
  • the scrambling calculation unit of the first level M*64bits uses the scrambling calculation unit of the 0th order M*64bits to feed forward the scrambling
  • the status word is scrambled, and the scrambled result is output to the first output selector;
  • the second-level M*64bits scrambling calculation unit performs scrambling using the scrambled state word of the first-stage M*64bits scrambling calculation unit feedforward, and outputs the scrambled result to the first output selector;
  • the first output selector splices and combines the scrambled results of the scrambling calculation units of the 0th to 2nd order M*64bits and outputs them.
  • the feedback calculation unit performs a scrambling calculation, obtains a scrambled status word according to the scrambled result, and outputs the scrambled status word to the second output selector.
  • the second output selector outputs the scrambled status word to the scramble calculation unit of the 0th stage M*64bits for scrambling the next input data to be scrambled by 10*64 bits.
  • the scrambled status word output by the feedback calculation unit is output to the 0th 64-bit scramble circuit of the 0th stage M*64bits scrambling calculation unit.
  • the scrambling apparatus 200 provided by the embodiment of the present invention includes, on the one hand, a plurality of cascaded scrambling calculation units, each of which includes a plurality of cascaded scrambling units.
  • the corresponding number of scrambling calculation units can be selected for scrambling calculation according to the number of bits to be scrambled, that is, the scrambling calculation unit participating in the scrambling calculation can be selected according to the bandwidth requirement, thereby realizing flexible and configurable Variable bandwidth Ethernet scrambling; on the other hand, for the case where the number of bits to be scrambled is large, the feedback calculation unit calculates the scrambled status word and outputs it to the corresponding scrambling calculation unit, which can reduce the scrambling calculation.
  • the logical combination level of the scrambling circuit internally cascaded in the unit saves resource overhead.
  • the above-mentioned embodiment of the present invention provides a scrambling scheme that solves the problem of flexible configurability of variable bandwidth Ethernet for AL scrambling.
  • the power 2 granularity scrambling structure is used to ensure the balance between resource occupancy and timing convergence.
  • the scrambling method provided by the embodiment of the present invention is applicable not only to self-synchronization scrambling but also to other scrambling algorithms, such as frame synchronization scrambling or discrete sampling scrambling.
  • the scrambling scheme provided by the embodiment of the present invention is not limited in specific applications, such as the interface rate, the number of PCS lanes, and the number of bits to be scrambled input in one clock cycle.
  • the number of cascaded stages and the number and type of scrambling calculation units of the power 2 granularity may be selected according to the solution provided by the embodiment of the present invention to achieve a balance between resources and timing.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operations S are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide S for implementing the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un appareil d'embrouillage et un procédé de configuration d'embrouillage. Des circuits d'embrouillage sont mis en cascade par utilisation de multiplexeurs, et une entrée de multiplexeurs connectés à des circuits d'embrouillage sur chaque niveau provient de mots d'état d'embrouillage renvoyés par les circuits d'embrouillage sur ce niveau, de mots d'état d'embrouillage renvoyés par des circuits d'embrouillage sur chaque niveau suivant ce niveau, et de mots d'état d'embrouillage renvoyés par des circuits d'embrouillage sur un niveau précédent, de telle sorte qu'un circuit d'embrouillage ou des circuits d'embrouillage mis en cascade sur de multiples niveaux peuvent être sélectionnés de manière souple selon le nombre de bits des données à embrouiller entrées dans une période d'horloge. Par configuration d'états effectifs de bornes d'entrée des multiplexeurs connectés aux circuits d'embrouillage, des mots d'état d'embrouillage correspondants sont commandés et transmis aux circuits d'embrouillage pour participer à un calcul d'embrouillage, de telle sorte qu'un embrouillage Ethernet souple, pouvant être configuré et à bande passante variable est mis en œuvre. En outre, une unité de calcul de rétroaction peut calculer les mots d'état d'embrouillage et délivrer les mots d'état d'embrouillage calculés à une unité de calcul d'embrouillage correspondante à utiliser, de façon à réduire le nombre de niveaux de combinaisons logiques des circuits d'embrouillage en cascade dans l'unité de calcul d'embrouillage et à réduire le surdébit de ressources.
PCT/CN2015/077210 2014-05-30 2015-04-22 Appareil d'embrouillage et procédé de configuration d'embrouillage WO2015180545A1 (fr)

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