WO2015174138A1 - Variable attenuator, attenuation adjustment circuit, and attenuation adjustment method - Google Patents
Variable attenuator, attenuation adjustment circuit, and attenuation adjustment method Download PDFInfo
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- WO2015174138A1 WO2015174138A1 PCT/JP2015/058159 JP2015058159W WO2015174138A1 WO 2015174138 A1 WO2015174138 A1 WO 2015174138A1 JP 2015058159 W JP2015058159 W JP 2015058159W WO 2015174138 A1 WO2015174138 A1 WO 2015174138A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/22—Attenuating devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/24—Frequency-independent attenuators
Definitions
- the present invention relates to a variable attenuator, an attenuation adjustment circuit, and an attenuation adjustment method.
- Method 1 Gain control method by drain current control of field effect transistor (FET) constituting amplifier.
- FET field effect transistor
- the FET is inserted between the high-frequency transmission line and the ground terminal, the drain terminal and the source terminal of the FET are connected to the high-frequency transmission line and the ground terminal, respectively, and the gate voltage input separately is used.
- Gain control is performed by changing the impedance of the FET (see, for example, Patent Document 1).
- an FET with a small gate width is used so that the area where the parasitic capacitance Cds is formed is reduced.
- an FET with a small gate width has a poor high-frequency distortion characteristic and may distort the signal.
- the variable attenuator using the FET as the variable attenuating element has a trade-off relationship between the passage loss of the high frequency signal and the distortion characteristic.
- the present invention has been made in view of the above problems, and an object thereof is to provide a variable attenuator, an attenuation adjustment circuit, and an attenuation adjustment method in which loss and distortion characteristics of a high-frequency signal to be transmitted are improved. It is in.
- a coupler that distributes a high-frequency signal input from an input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port;
- An attenuation adjustment unit having at least two FETs connected in series via a source terminal and a drain terminal between the output port and the ground terminal and between the third output port and the ground terminal, respectively.
- a variable attenuator is provided.
- the second output of the coupler that distributes a high-frequency signal input from an input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port.
- Attenuation amount having at least two FETs connected in series via a source terminal and a drain terminal between a port and a ground terminal and between the third output port of the coupler and the ground terminal, respectively. It is an adjustment circuit.
- a high-frequency signal is input to the input port of a coupler having an input port, a first output port, a second output port, and a third output port, and the second output port and a ground terminal
- an attenuation adjustment method for applying a voltage to the gate terminals of at least two FETs connected in series via a source terminal and a drain terminal, respectively, between the third output port and the ground terminal It is.
- variable attenuator attenuation adjustment circuit, and attenuation adjustment method, it is possible to improve the loss and distortion characteristics of the transmitted high-frequency signal.
- FIG. 1 is a diagram illustrating an overall configuration of a variable attenuator according to the first embodiment.
- the variable attenuator 1 according to this embodiment includes a Lange coupler 10 (coupler), an attenuation adjustment unit 11 (an attenuation adjustment circuit), and a variable voltage source 13.
- the Lange coupler 10 distributes a high frequency signal (RFin) input from the input port Pin, and outputs the distributed high frequency signal from each of the first output port Pout1, the second output port Pout2, and the third output port Pout3.
- RFin high frequency signal
- the Lange coupler 10 includes a first coupled line 100 that connects the input port Pin and the second output port Pout2, and a second coupled line 101 that connects the first output port Pout1 and the third output port Pout3. .
- the first coupled line 100 and the second coupled line 101 are arranged in parallel with a coupled line length L.
- the coupling line length L is set to a length (specifically, 1/4 of the wavelength ⁇ of the high frequency signal) according to the frequency (wavelength) of the high frequency signal input from the input port Pin.
- the high-frequency signal input from the input port Pin is connected to each of the first output port Pout1, the second output port Pout2, and the third output port Pout3 by electromagnetic coupling between the first coupling line 100 and the second coupling line 101.
- variable attenuator 1 is a variable attenuator applied to a high-frequency signal in the 75 to 110 GHz frequency band that is a millimeter wave band.
- the coupled line length L in the Lange coupler 10 is, for example, 300 ⁇ m, which is a quarter wavelength of 90 GHz, which is substantially the center frequency of the frequency band (75 to 110 GHz).
- the variable attenuator according to another embodiment is not limited to the above-described aspect, and for example, the coupled line length L may be set to a length optimized for a frequency band other than the millimeter wave band.
- the attenuation adjustment unit 11 includes a terminal connected to the second output port Pout2 and the third output port Pout3 of the Lange coupler 10, a ground terminal GND connected to a potential line that applies a ground potential (0V), and a variable voltage source 13. And a control terminal C connected to the. Further, the attenuation adjustment unit 11 includes a first FET 120, a second FET 121, and a second FET 121 that are connected in series via the source terminal S and the drain terminal D between the second output port Pout2 of the Lange coupler 10 and the ground terminal GND. ,have.
- the attenuation adjustment unit 11 includes a third FET 122, a fourth FET 123, and a third FET 122 connected in series via the source terminal S and the drain terminal D between the third output port Pout3 of the Lange coupler 10 and the ground terminal GND. ,have. More specifically, the second output port Pout2 and the drain terminal D of the first FET 120 are connected, the source terminal S of the first FET 120 and the drain terminal D of the second FET 121 are connected, and the source terminal S of the second FET 121 and the ground. Terminal GND is connected.
- each of the first FET 120 to the fourth FET 123 is an FET made of GaAs (gallium arsenide) generally used for millimeter wave band MMICs.
- the gate width W of each of the first FET 120 to the fourth FET 123 is formed to be about 25 ⁇ m, for example.
- the present invention is not limited to this mode, and the first FET 120 to the fourth FET 123 may be formed of FETs made of Si (silicon), for example.
- the attenuation adjustment unit 11 further includes resistance elements R1 to R4.
- One end of the resistance element R1 is connected to the gate terminal G of the first FET 120, and the other end is connected to the control terminal C.
- one end of the resistor element R2 is connected to the gate terminal G of the second FET 121
- one end of the resistor element R3 is connected to the gate terminal G of the third FET 122
- one end of the resistor element R4 is connected to the gate terminal G of the fourth FET 123.
- the other ends of the resistance elements R2 to R4 are all connected to the control terminal C. That is, the control terminal C is connected to all the gate terminals G of the first FET 120 to the fourth FET 123 via the resistance elements R1 to R4.
- Each of the resistance elements R1 to R4 is provided so that the variable voltage source 13 stably controls the DC (direct current) voltage applied to the gate terminals G of the first FET 120 to the fourth FET 123.
- Each of the resistance elements R1 to R4 has a resistance value of, for example, about 1 k ⁇ .
- the variable voltage source 13 is connected to the control terminal C and applies a predetermined DC voltage to the control terminal C.
- the variable voltage source 13 can change the DC voltage applied to the control terminal C as desired within a certain range (for example, ⁇ 1 V).
- the variable attenuator 1 having the above configuration operates, for example, as follows.
- the variable voltage source 13 applies an off voltage (for example, ⁇ 1V) to the gate terminals G of the first FET 120 to the fourth FET 123
- the first FET 120 to the fourth FET 123 are in an off state (a state where the impedance is high).
- the second output port Pout2 and the third output port Pout3 are opened.
- the high frequency signal RFin input from the input terminal Pin is substantially totally reflected at the second output port Pout2 and the third output port Pout3, and is output from the first output terminal Pout1 as a high frequency signal RFout without being attenuated.
- variable voltage source 13 applies an on voltage (for example, +1 V) to the gate terminals G of the first FET 120 to the fourth FET 123
- the first FET 120 to the fourth FET 123 are in an on state (low impedance state).
- a current flows between the source and drain. Therefore, the strength of the high frequency signal transmitted from the second output port Pout2 and the third output port Pout3 to the ground terminal GND increases, and as a result, the high frequency signal RFout output from the first output port Pout1 is attenuated.
- variable attenuator 1 using the Lange coupler 10 in order to appropriately attenuate the high-frequency signal RFin input to the first output port Pout1 based on the impedance at the second output port Pout2 or the third output port Pout3.
- the impedances of the FETs connected to the second output port Pout2 and the third output port Pout3 need to be changed while being uniform.
- variable attenuator 1 adjusts the DC voltage applied to the control terminal C (that is, each gate terminal G) by the variable voltage source 13 to change the impedance of the first FET 120 to the fourth FET 123, thereby changing the high frequency.
- the amount of signal attenuation can be changed.
- FIG. 2 is a diagram for explaining the overall configuration of a variable attenuator related to the comparison.
- the proportional variable attenuator 9 includes a Lange coupler 10, a variable voltage source 13, and an attenuation adjustment unit 91.
- the Lange coupler 10 and the variable voltage source 13 are the same as those provided in the variable attenuator 1 according to the first embodiment.
- the attenuation adjustment unit 91 according to proportionality includes a first FET 120, a third FET 122, a resistance element R1, and a resistance element R3.
- the aspects (material, size, etc.) of these FETs and resistance elements are the same as those in the first embodiment.
- the first FET 120 is inserted between the second output port Pout2 of the Lange coupler 10 and the ground terminal GND, and the drain terminal D and the source of the first FET 120 are connected to the second output port Pout2 and the ground terminal GND. Terminals S are connected to each other.
- the third FET 122 is inserted between the third output port Pout3 and the ground terminal GND of the Lange coupler 10, and the drain terminal D and the source terminal S of the third FET 122 are connected to the third output port Pout3 and the ground terminal GND, respectively.
- the variable attenuator 9 having such a configuration also operates in the same manner as the variable attenuator 1 (FIG. 1) according to the first embodiment.
- variable attenuator 1 As shown in FIGS. 1 and 2, the variable attenuator 1 according to the first embodiment has each of the second output port Pout2 and the third output port Pout3 compared to the variable attenuator 9 according to the proportionality. 2 differs in that two FETs are connected in series. Next, the effect of two FETs connected in series in the variable attenuator 1 according to this embodiment will be described in detail.
- FIG. 3A and FIG. 3B are first diagrams illustrating the operational effects of the variable attenuator according to the first embodiment.
- FIG. 3A shows an equivalent circuit of the first FET 120 that constitutes the attenuation adjustment unit 91 of the variable attenuator 9 (FIG. 2) that is in proportion.
- FIG. 3B shows an equivalent circuit of the first FET 120 and the second FET 121 that are included in the variable attenuator 1 (FIG. 1) according to the present embodiment and that are connected in series.
- the circuit diagram shown in FIG. 3A is a general equivalent circuit of an FET.
- a parasitic capacitance Cds is provided between the drain terminal D and the source terminal S of the first FET 120.
- This drain-source capacitance Cds is mainly caused by a pn junction formed inside the FET.
- drain terminal D and the source terminal S of the first FET 120 are connected between the second output port Pout2 and the ground terminal GND of the Lange coupler 10, between the second output port Pout2 and the ground terminal GND, A drain-source capacitance Cds is always connected. Then, even if the first FET 120 is in an OFF state, a high frequency signal flows to the ground terminal GND via the drain-source capacitance Cds. That is, even when it is desired to transmit without causing a passage loss, a high-frequency signal passage loss is caused by the drain-source capacitance Cds that is always present.
- passage loss is a value (unit: dB) indicating a ratio of the level of the high-frequency signal RFout output from the first output port Pout1 to the level (intensity) of the high-frequency signal RFin input to the input port Pin. is there.
- the passing loss is 0 dB.
- the passage loss is indicated by a negative value.
- the gate width W of the FET when the gate width W of the FET is reduced, the area in which the parasitic capacitance (drain-source capacitance Cds) based on the pn junction is formed is reduced accordingly, so that the drain-source capacitance Cds is reduced. Therefore, in order to suppress the passage loss, it is necessary to reduce the gate width W of the first FET 120. However, if the gate width W of the FET is made too small, the high-frequency characteristic distortion characteristics of the FET may deteriorate and the high-frequency signal may be distorted. Therefore, there is a limit to reducing the gate width W for the purpose of reducing the drain-source capacitance Cds. Therefore, the variable attenuator 9 according to the proportionality cannot sufficiently reduce the drain-source capacitance Cds, and has a large passage loss of the high-frequency signal.
- the configuration of the attenuation adjustment unit 11 of the variable attenuator 1 according to the present embodiment (FIG. 1) will be described below.
- the drain terminal D of the first FET 120 is connected to the second output port Pout2 of the Lange coupler 10 (see FIG. 1).
- the gate terminals G of the first FET 120 and the second FET 121 are connected to the variable voltage source 13 through the resistance element R1 and the resistance element R2, respectively (see FIG. 1).
- the two drain-source capacitances Cds are connected in series between the second output port Pout2 and the ground terminal GND.
- the attenuation amount adjustment unit 11 having such a configuration, the relative attenuation is obtained. Compared with the quantity adjustment unit 91, it is possible to suppress the passage loss of the high-frequency signal.
- FIG. 4A and FIG. 4B are second diagrams for explaining the effects of the variable attenuator according to the embodiment.
- the graph shown in FIG. 4A shows the characteristics of the passage loss of the variable attenuator 9 according to the comparison.
- the graph shown to FIG. 4B has shown the characteristic of the passage loss of the variable attenuator 1 which concerns on 1st Embodiment. 4A and 4B, the characteristics of the passage loss when the off voltage ( ⁇ 1V) is applied to the gate terminals G of the first FET 120 to the fourth FET 123 are indicated by solid lines, and the gate terminals G of the first FET 120 to the fourth FET 123 are turned on.
- the characteristics of the passage loss when a voltage (+1 V) is applied are indicated by broken lines.
- variable attenuator 9 As shown in FIG. 4A, the variable attenuator 9 according to the proportionality is about ⁇ 3.5 dB in a high-frequency signal having a frequency of 90 GHz even though the off-voltage is applied to the gate terminals G of the first FET 120 and the third FET 122. (See the solid line in FIG. 4A). As described above, this passage loss is caused by the drain-source capacitance Cds of the first FET 120 (third FET 122). On the other hand, as shown in FIG.
- the passage loss in the high-frequency signal of 90 GHz is ⁇ It is suppressed to about 1.5 dB.
- the drain-source capacitance Cds parasitic to the first FET 120 and the second FET 121 (the third FET 122 and the fourth FET 123) is connected in series, so that the second output port Pout2 (the third output port Pout3) and the ground terminal GND are connected. This is because the parasitic capacitance generated between them is reduced to 1 ⁇ 2.
- variable attenuator 1 can control the amount of attenuation by the applied gate voltage in the same manner as the variable attenuator 9 according to the comparative example.
- FIG. 5 is a third diagram for explaining the operational effects of the variable attenuator according to the first embodiment.
- the graph shown in FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the variable attenuator 9 (broken line) according to the proportionality and the variable attenuator 1 (solid line) according to the present embodiment. Yes.
- FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the variable attenuator 9 (broken line) according to the proportionality and the variable attenuator 1 (solid line) according to the present embodiment. Yes.
- FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the variable attenuator 9 (broken line) according to the proportionality and the variable attenuator 1 (solid line) according to the present embodiment. Yes.
- FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the
- variable attenuator 9 when the gate voltage Vgs applied to the gate terminals G of the first FET 120 and the third FET 122 of the variable attenuator 9 which is proportional to each other is changed from ⁇ 1.5 V to +1.5 V, the variable attenuator The passing loss of the high-frequency signal transmitted from the nine input ports Pin to the first output port Pout1 varies from ⁇ 3.5 dB to ⁇ 11.0 dB.
- variable attenuator 1 when the gate voltage Vgs applied to each gate terminal G of the first FET 120 to the fourth FET 123 of the variable attenuator 1 according to this embodiment is changed from ⁇ 1.5 V to +1.5 V, the variable attenuator 1
- the passing loss of the high-frequency signal transmitted from the input port Pin to the first output port Pout1 varies from ⁇ 1.0 dB to ⁇ 11.0 dB.
- the variable attenuator 1 according to the present embodiment reduces the parasitic capacitance generated between the second output port Pout2 (third output port Pout3) and the ground terminal GND, so that the variable attenuation according to the proportionality is achieved.
- the range of attenuation that can be controlled is larger than that of the device 9.
- FIG. 6 is a fourth diagram illustrating the operational effect of the variable attenuator according to the first embodiment.
- the graph shown in FIG. 6 shows the characteristic of the third-order intermodulation distortion (IM3) with respect to the gate voltage Vgs of the variable attenuator 9 (broken line) and the variable attenuator 1 (solid line) according to the present embodiment.
- IM3 third-order intermodulation distortion
- the variable attenuator 1 according to the present embodiment has a distortion characteristic improved by about 8 dB compared to the variable attenuator 9 according to the proportionality when the gate voltage Vgs is ⁇ 1V.
- the distortion characteristics of the variable attenuator 1 are improved by about 15 dB compared to the variable attenuator 9 according to the proportionality. In this way, by connecting FETs used for attenuation control in multiple stages in series, the voltage applied between the source and drain of each FET is reduced, so that the distortion characteristics can be improved.
- the loss and distortion of the high-frequency signal to be transmitted are obtained by connecting the FET for controlling the attenuation amount in series through the source terminal and the drain terminal. The characteristics can be improved.
- variable attenuator 1 two FETs (first FET 120 to fourth FET 123) are connected in series in each of the second output port Pout2 and the third output port Pout3 of the Lange coupler 10.
- the number of FETs connected in series to each of the second output port Pout2 and the third output port Pout3 of the Lange coupler 10 may be three or more. By doing so, the loss and distortion characteristics of the high-frequency signal to be transmitted can be further improved.
- the same number (two) of the attenuation adjustment units 11 according to the present embodiment is provided between the second output port Pout2 and the ground terminal GND of the Lange coupler 10 and between the third output port Pout3 and the ground terminal GND.
- FETs are connected in series. Thereby, it becomes easy to uniformly change the impedance of the FET connected to the second output port Pout2 and the impedance of the FET connected to the third output port Pout3.
- the variable attenuator 1 according to another embodiment is not limited to this aspect.
- the attenuation adjustment unit 11 has been described as having a single control terminal C connected to all the gate terminals G of the first FET 120 to the fourth FET 123.
- the variable voltage source 13 can apply the same gate voltage Vgs to the gate terminals G of all FETs only by applying a desired DC voltage only to the single control terminal C. Therefore, it is possible to easily change the impedance of the FET connected to the second output port Pout2 and the impedance of the FET connected to the third output port Pout3 uniformly.
- the variable attenuator 1 according to another embodiment is not limited to this aspect.
- the gate voltage Vgs is individually applied to the gate terminals G of two or more FETs connected in series to the second output port Pout2 and two or more FETs connected in series to the third output port Pout3. May be applied. In such an embodiment, even if different gate voltages Vgs are applied, if the overall impedance of each FET connected to the second output port Pout2 or the third output port Pout3 is uniform, the same applies. The effect of this can be obtained.
- variable attenuator 1 includes the Lange coupler 10 and the components of the attenuation adjustment unit 11 (first FET 120 to fourth FET 123, resistance element R1 to resistance element R4, etc.) on the same semiconductor substrate. It is good also as an aspect formed integrally. By doing so, the variable attenuator 1 can be reduced in size, which contributes to a reduction in manufacturing cost.
- the present invention is not limited to this mode.
- the constituent elements of the Lange coupler 10 and the attenuation amount adjustment unit 11 may be individually mounted.
- the configuration of the Lange coupler 10 according to the present embodiment is not limited to the above-described aspect.
- the Lange coupler 10 may be a distributed constant branch line coupler. If the frequency of the high frequency signal is relatively low, a lumped constant branch line coupler using a spiral inductor may be used.
- FIG. 7 is a diagram illustrating a functional configuration of an attenuation adjustment circuit according to another embodiment.
- the attenuation adjustment circuit 11A distributes a high-frequency signal input from the input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port.
- at least two FETs 12 connected in series via a source terminal S and a drain terminal D between the first output terminal and the ground terminal GND and between the third output port of the coupler and the ground terminal GND. .
- the high frequency signal RFin is input to the input port Pin of the coupler 10 having the input port Pin, the first output port Pout1, the second output port Pout2, and the third output port Pout3. , At least 2 connected in series via the source terminal S and the drain terminal D between the second output port Pout2 and the ground terminal GND and between the third output port Pout3 and the ground terminal GND, respectively.
- a voltage is applied to the gate terminals of one or more FETs 12 to adjust the attenuation amount of the high-frequency signal RFout output to the first output port Pout1.
- the present invention can be applied to, for example, gain control of a high frequency signal. According to the present invention, loss and distortion characteristics of a high-frequency signal to be transmitted can be improved.
- Variable attenuator 10 Lange coupler (coupler) 100 first coupled line 101 second coupled line 11 attenuation adjustment unit 11A attenuation adjustment circuit 12 FET 120 1st FET 121 2nd FET 122 3rd FET 123 4th FET 13 Variable voltage source
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Abstract
Provided is a variable attenuator whereby loss of high frequency signals can be reduced. This variable attenuator is provided with: a coupler, which distributes high frequency signals inputted from an input port, and which outputs the thus distributed high frequency signals from a first output port, a second output port, and a third output port; and an attenuation adjustment unit having at least two FETs between the second output port and a grounding terminal, and between the third output port and the grounding terminal, said at least two FETs being connected in series by having a source terminal and a drain terminal therebetween.
Description
本発明は、可変減衰器、減衰量調整回路及び減衰量調整方法に関する。
The present invention relates to a variable attenuator, an attenuation adjustment circuit, and an attenuation adjustment method.
近年の通信トラフィック量の増加に伴い、利用可能な周波数が広帯域なミリ波帯、テラヘルツ帯の注目が高まっている。このような高周波信号の可変減衰機能を持つマイクロ波モノリシック集積回路(MMIC:Monolithic Microwave Integrated Circuit)では、利得制御機能に周波数の広帯域性が求められている。そのため、MMICは、一般的に次の2つの方法で高周波信号のレベル制御を行っている。
方法1.増幅器を構成する電界効果トランジスタ(FET:Field Effect Transistor)のドレイン電流制御による利得コントロール
方法2.FETのインピーダンス制御を用いた減衰回路による利得コントロール
方法1に挙げた制御方法は、増幅器と減衰器の両機能を合わせ持たせることが可能であるため広く用いられているが、利得を下げる際にドレイン電流を下げる必要があるため、増幅器の動作点がAB級動作に近づき、歪み特性が劣化する可能性がある。
一方、方法2に挙げた制御方法は、高周波伝送線路と接地端子の間にFETが挿入され、高周波伝送線路と接地端子にそれぞれFETのドレイン端子とソース端子を接続させ、別途入力するゲート電圧によりFETのインピーダンスを変化させることで利得制御を行う(例えば、特許文献1参照)。 With the recent increase in the amount of communication traffic, attention has been focused on the millimeter wave band and the terahertz band, which have a wide range of usable frequencies. In such a microwave monolithic integrated circuit (MMIC: Monolithic Microwave Integrated Circuit) having a variable attenuation function of a high-frequency signal, the gain control function is required to have a wide frequency band. Therefore, the MMIC generally performs high-frequency signal level control by the following two methods.
Method 1. 1. Gain control method by drain current control of field effect transistor (FET) constituting amplifier. Gain control by attenuation circuit using FET impedance control The control method listed in Method 1 is widely used because it can have both functions of an amplifier and an attenuator. Since it is necessary to lower the drain current, the operating point of the amplifier approaches a class AB operation, and the distortion characteristics may deteriorate.
On the other hand, in the control method listed inMethod 2, the FET is inserted between the high-frequency transmission line and the ground terminal, the drain terminal and the source terminal of the FET are connected to the high-frequency transmission line and the ground terminal, respectively, and the gate voltage input separately is used. Gain control is performed by changing the impedance of the FET (see, for example, Patent Document 1).
方法1.増幅器を構成する電界効果トランジスタ(FET:Field Effect Transistor)のドレイン電流制御による利得コントロール
方法2.FETのインピーダンス制御を用いた減衰回路による利得コントロール
方法1に挙げた制御方法は、増幅器と減衰器の両機能を合わせ持たせることが可能であるため広く用いられているが、利得を下げる際にドレイン電流を下げる必要があるため、増幅器の動作点がAB級動作に近づき、歪み特性が劣化する可能性がある。
一方、方法2に挙げた制御方法は、高周波伝送線路と接地端子の間にFETが挿入され、高周波伝送線路と接地端子にそれぞれFETのドレイン端子とソース端子を接続させ、別途入力するゲート電圧によりFETのインピーダンスを変化させることで利得制御を行う(例えば、特許文献1参照)。 With the recent increase in the amount of communication traffic, attention has been focused on the millimeter wave band and the terahertz band, which have a wide range of usable frequencies. In such a microwave monolithic integrated circuit (MMIC: Monolithic Microwave Integrated Circuit) having a variable attenuation function of a high-frequency signal, the gain control function is required to have a wide frequency band. Therefore, the MMIC generally performs high-frequency signal level control by the following two methods.
On the other hand, in the control method listed in
方法2の場合、高周波信号の通過損失を低く抑えるため、FETのドレイン端子とソース端子の間に生じる寄生容量Cdsを十分に小さくする必要がある。そのため、寄生容量Cdsが形成される面積が減縮されるように、ゲート幅の小さいFETが用いられている。しかしながら、しかし、ゲート幅の小さいFETは、高周波特性の歪み特性が悪く、信号を歪ませてしまう可能性がある。
このように、可変減衰素子としてFETを用いた可変減衰器には、高周波信号の通過損失と、歪み特性との間にトレードオフの関係があった。 In the case ofMethod 2, it is necessary to sufficiently reduce the parasitic capacitance Cds generated between the drain terminal and the source terminal of the FET in order to suppress the high-frequency signal passing loss. Therefore, an FET with a small gate width is used so that the area where the parasitic capacitance Cds is formed is reduced. However, an FET with a small gate width has a poor high-frequency distortion characteristic and may distort the signal.
As described above, the variable attenuator using the FET as the variable attenuating element has a trade-off relationship between the passage loss of the high frequency signal and the distortion characteristic.
このように、可変減衰素子としてFETを用いた可変減衰器には、高周波信号の通過損失と、歪み特性との間にトレードオフの関係があった。 In the case of
As described above, the variable attenuator using the FET as the variable attenuating element has a trade-off relationship between the passage loss of the high frequency signal and the distortion characteristic.
この発明は、上記課題に鑑みてなされたものであって、その目的は、伝送する高周波信号の損失及び歪み特性が改善された可変減衰器、減衰量調整回路及び減衰量調整方法を提供することにある。
The present invention has been made in view of the above problems, and an object thereof is to provide a variable attenuator, an attenuation adjustment circuit, and an attenuation adjustment method in which loss and distortion characteristics of a high-frequency signal to be transmitted are improved. It is in.
本発明の一態様は、入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラと、前記第2出力ポートと接地端子の間、及び、前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETを有する減衰量調整部と、を備える可変減衰器である。
According to one aspect of the present invention, a coupler that distributes a high-frequency signal input from an input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port; An attenuation adjustment unit having at least two FETs connected in series via a source terminal and a drain terminal between the output port and the ground terminal and between the third output port and the ground terminal, respectively. And a variable attenuator.
本発明の一態様は、入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラの前記第2出力ポートと接地端子の間、及び、前記カプラの前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETを有する減衰量調整回路である。
According to an aspect of the present invention, the second output of the coupler that distributes a high-frequency signal input from an input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port. Attenuation amount having at least two FETs connected in series via a source terminal and a drain terminal between a port and a ground terminal and between the third output port of the coupler and the ground terminal, respectively. It is an adjustment circuit.
また、本発明の一態様は、入力ポート、第1出力ポート、第2出力ポート及び第3出力ポートを有するカプラの前記入力ポートに高周波信号を入力し、前記第2出力ポートと接地端子との間、及び、前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETのゲート端子に電圧を印加する減衰量調整方法である。
In one embodiment of the present invention, a high-frequency signal is input to the input port of a coupler having an input port, a first output port, a second output port, and a third output port, and the second output port and a ground terminal And an attenuation adjustment method for applying a voltage to the gate terminals of at least two FETs connected in series via a source terminal and a drain terminal, respectively, between the third output port and the ground terminal It is.
上述の可変減衰器、減衰量調整回路及び減衰量調整方法によれば、伝送する高周波信号の損失及び歪み特性を改善することができる。
According to the above-described variable attenuator, attenuation adjustment circuit, and attenuation adjustment method, it is possible to improve the loss and distortion characteristics of the transmitted high-frequency signal.
<第1の実施形態>
以下、第1の実施形態に係る可変減衰器を、図面を参照ながら説明する。
図1は、第1の実施形態に係る可変減衰器の全体構成を示す図である。
図1に示すように、本実施形態に係る可変減衰器1は、ランゲカプラ10(カプラ)と、減衰量調整部11(減衰量調整回路)と、可変電圧源13と、を備えている。
ランゲカプラ10は、入力ポートPinから入力される高周波信号(RFin)を分配して、分配された高周波信号を第1出力ポートPout1、第2出力ポートPout2及び第3出力ポートPout3のそれぞれから出力する。ランゲカプラ10は、入力ポートPinと第2出力ポートPout2とを接続する第1結合線路100と、第1出力ポートPout1と第3出力ポートPout3とを接続する第2結合線路101と、を備えている。
第1結合線路100と、第2結合線路101とは、結合線路長Lをもって平行に配されている。結合線路長Lは、入力ポートPinから入力される高周波信号の周波数(波長)に応じた長さ(具体的には、高周波信号の波長λの1/4)とされる。これにより、入力ポートPinから入力された高周波信号は、第1結合線路100と第2結合線路101との電磁結合により、第1出力ポートPout1、第2出力ポートPout2、第3出力ポートPout3のそれぞれに分配される。第1出力ポートPout1、第2出力ポートPout2及び第3出力ポートPout3それぞれへの分配比率は、各出力ポートの先に接続される素子のインピーダンスに応じて定まる。
なお、本実施形態に係る可変減衰器1は、ミリ波帯である75~110GHzの周波数帯域の高周波信号に適用される可変減衰器とする。この場合、ランゲカプラ10における結合線路長Lは、例えば、上記周波数帯域(75~110GHz)のほぼ中心周波数にあたる90GHzの1/4波長の300μmとする。ただし、他の実施形態に係る可変減衰器は、上記態様に限定されず、例えば、結合線路長Lがミリ波帯以外の周波数帯に最適化された長さに設定されていてもよい。 <First Embodiment>
The variable attenuator according to the first embodiment will be described below with reference to the drawings.
FIG. 1 is a diagram illustrating an overall configuration of a variable attenuator according to the first embodiment.
As shown in FIG. 1, thevariable attenuator 1 according to this embodiment includes a Lange coupler 10 (coupler), an attenuation adjustment unit 11 (an attenuation adjustment circuit), and a variable voltage source 13.
The Langecoupler 10 distributes a high frequency signal (RFin) input from the input port Pin, and outputs the distributed high frequency signal from each of the first output port Pout1, the second output port Pout2, and the third output port Pout3. The Lange coupler 10 includes a first coupled line 100 that connects the input port Pin and the second output port Pout2, and a second coupled line 101 that connects the first output port Pout1 and the third output port Pout3. .
The first coupledline 100 and the second coupled line 101 are arranged in parallel with a coupled line length L. The coupling line length L is set to a length (specifically, 1/4 of the wavelength λ of the high frequency signal) according to the frequency (wavelength) of the high frequency signal input from the input port Pin. As a result, the high-frequency signal input from the input port Pin is connected to each of the first output port Pout1, the second output port Pout2, and the third output port Pout3 by electromagnetic coupling between the first coupling line 100 and the second coupling line 101. Distributed to. The distribution ratio to each of the first output port Pout1, the second output port Pout2, and the third output port Pout3 is determined according to the impedance of the element connected to the tip of each output port.
Note that thevariable attenuator 1 according to the present embodiment is a variable attenuator applied to a high-frequency signal in the 75 to 110 GHz frequency band that is a millimeter wave band. In this case, the coupled line length L in the Lange coupler 10 is, for example, 300 μm, which is a quarter wavelength of 90 GHz, which is substantially the center frequency of the frequency band (75 to 110 GHz). However, the variable attenuator according to another embodiment is not limited to the above-described aspect, and for example, the coupled line length L may be set to a length optimized for a frequency band other than the millimeter wave band.
以下、第1の実施形態に係る可変減衰器を、図面を参照ながら説明する。
図1は、第1の実施形態に係る可変減衰器の全体構成を示す図である。
図1に示すように、本実施形態に係る可変減衰器1は、ランゲカプラ10(カプラ)と、減衰量調整部11(減衰量調整回路)と、可変電圧源13と、を備えている。
ランゲカプラ10は、入力ポートPinから入力される高周波信号(RFin)を分配して、分配された高周波信号を第1出力ポートPout1、第2出力ポートPout2及び第3出力ポートPout3のそれぞれから出力する。ランゲカプラ10は、入力ポートPinと第2出力ポートPout2とを接続する第1結合線路100と、第1出力ポートPout1と第3出力ポートPout3とを接続する第2結合線路101と、を備えている。
第1結合線路100と、第2結合線路101とは、結合線路長Lをもって平行に配されている。結合線路長Lは、入力ポートPinから入力される高周波信号の周波数(波長)に応じた長さ(具体的には、高周波信号の波長λの1/4)とされる。これにより、入力ポートPinから入力された高周波信号は、第1結合線路100と第2結合線路101との電磁結合により、第1出力ポートPout1、第2出力ポートPout2、第3出力ポートPout3のそれぞれに分配される。第1出力ポートPout1、第2出力ポートPout2及び第3出力ポートPout3それぞれへの分配比率は、各出力ポートの先に接続される素子のインピーダンスに応じて定まる。
なお、本実施形態に係る可変減衰器1は、ミリ波帯である75~110GHzの周波数帯域の高周波信号に適用される可変減衰器とする。この場合、ランゲカプラ10における結合線路長Lは、例えば、上記周波数帯域(75~110GHz)のほぼ中心周波数にあたる90GHzの1/4波長の300μmとする。ただし、他の実施形態に係る可変減衰器は、上記態様に限定されず、例えば、結合線路長Lがミリ波帯以外の周波数帯に最適化された長さに設定されていてもよい。 <First Embodiment>
The variable attenuator according to the first embodiment will be described below with reference to the drawings.
FIG. 1 is a diagram illustrating an overall configuration of a variable attenuator according to the first embodiment.
As shown in FIG. 1, the
The Lange
The first coupled
Note that the
減衰量調整部11は、ランゲカプラ10の第2出力ポートPout2及び第3出力ポートPout3に接続される端子と、接地電位(0V)を与える電位線に接続される接地端子GNDと、可変電圧源13に接続されるコントロール端子Cと、を有する。
また、減衰量調整部11は、ランゲカプラ10の第2出力ポートPout2と接地端子GNDの間において、各々のソース端子Sとドレイン端子Dとを介して直列に接続された第1FET120と、第2FET121と、を有している。また、減衰量調整部11は、ランゲカプラ10の第3出力ポートPout3と接地端子GNDの間において、各々のソース端子Sとドレイン端子Dとを介して直列に接続された第3FET122と、第4FET123と、を有している。
より具体的に説明すると、第2出力ポートPout2と第1FET120のドレイン端子Dとが接続され、第1FET120のソース端子Sと第2FET121のドレイン端子Dとが接続され、第2FET121のソース端子Sと接地端子GNDとが接続される。
同様に、第3出力ポートPout3と第3FET122のドレイン端子Dとが接続され、第3FET122のソース端子Sと第4FET123のドレイン端子Dとが接続され、第4FET123のソース端子Sと接地端子GNDとが接続される。
本実施形態において、各第1FET120~第4FET123は、ミリ波帯のMMICに一般的に用いられるGaAs(ガリウムヒ素)を素材とするFETである。また、各第1FET120~第4FET123のゲート幅W(ソースドレイン間に電流が流れる方向に直交する方向のゲート端子の幅)は、例えば25μm程度に形成される。しかし、他の実施形態においては、この態様に限定されず、第1FET120~第4FET123は、例えば、Si(シリコン)を素材とするFETで形成されていてもよい。 Theattenuation adjustment unit 11 includes a terminal connected to the second output port Pout2 and the third output port Pout3 of the Lange coupler 10, a ground terminal GND connected to a potential line that applies a ground potential (0V), and a variable voltage source 13. And a control terminal C connected to the.
Further, theattenuation adjustment unit 11 includes a first FET 120, a second FET 121, and a second FET 121 that are connected in series via the source terminal S and the drain terminal D between the second output port Pout2 of the Lange coupler 10 and the ground terminal GND. ,have. The attenuation adjustment unit 11 includes a third FET 122, a fourth FET 123, and a third FET 122 connected in series via the source terminal S and the drain terminal D between the third output port Pout3 of the Lange coupler 10 and the ground terminal GND. ,have.
More specifically, the second output port Pout2 and the drain terminal D of thefirst FET 120 are connected, the source terminal S of the first FET 120 and the drain terminal D of the second FET 121 are connected, and the source terminal S of the second FET 121 and the ground. Terminal GND is connected.
Similarly, the third output port Pout3 and the drain terminal D of thethird FET 122 are connected, the source terminal S of the third FET 122 and the drain terminal D of the fourth FET 123 are connected, and the source terminal S of the fourth FET 123 and the ground terminal GND are connected. Connected.
In the present embodiment, each of thefirst FET 120 to the fourth FET 123 is an FET made of GaAs (gallium arsenide) generally used for millimeter wave band MMICs. Further, the gate width W of each of the first FET 120 to the fourth FET 123 (the width of the gate terminal in the direction orthogonal to the direction in which current flows between the source and drain) is formed to be about 25 μm, for example. However, in other embodiments, the present invention is not limited to this mode, and the first FET 120 to the fourth FET 123 may be formed of FETs made of Si (silicon), for example.
また、減衰量調整部11は、ランゲカプラ10の第2出力ポートPout2と接地端子GNDの間において、各々のソース端子Sとドレイン端子Dとを介して直列に接続された第1FET120と、第2FET121と、を有している。また、減衰量調整部11は、ランゲカプラ10の第3出力ポートPout3と接地端子GNDの間において、各々のソース端子Sとドレイン端子Dとを介して直列に接続された第3FET122と、第4FET123と、を有している。
より具体的に説明すると、第2出力ポートPout2と第1FET120のドレイン端子Dとが接続され、第1FET120のソース端子Sと第2FET121のドレイン端子Dとが接続され、第2FET121のソース端子Sと接地端子GNDとが接続される。
同様に、第3出力ポートPout3と第3FET122のドレイン端子Dとが接続され、第3FET122のソース端子Sと第4FET123のドレイン端子Dとが接続され、第4FET123のソース端子Sと接地端子GNDとが接続される。
本実施形態において、各第1FET120~第4FET123は、ミリ波帯のMMICに一般的に用いられるGaAs(ガリウムヒ素)を素材とするFETである。また、各第1FET120~第4FET123のゲート幅W(ソースドレイン間に電流が流れる方向に直交する方向のゲート端子の幅)は、例えば25μm程度に形成される。しかし、他の実施形態においては、この態様に限定されず、第1FET120~第4FET123は、例えば、Si(シリコン)を素材とするFETで形成されていてもよい。 The
Further, the
More specifically, the second output port Pout2 and the drain terminal D of the
Similarly, the third output port Pout3 and the drain terminal D of the
In the present embodiment, each of the
図1に示すように、減衰量調整部11は、更に、抵抗素子R1~抵抗素子R4を備えている。
抵抗素子R1の一端は、第1FET120のゲート端子Gに接続され、他端がコントロール端子Cに接続される。同様に、抵抗素子R2の一端は第2FET121のゲート端子Gに接続され、抵抗素子R3の一端は第3FET122のゲート端子Gに接続され、抵抗素子R4の一端は第4FET123のゲート端子Gに接続され接続され、各抵抗素子R2~R4の他端は、全てコントロール端子Cに接続される。即ち、コントロール端子Cは、各抵抗素子R1~抵抗素子R4を介して、第1FET120~第4FET123の各ゲート端子Gの全てに接続されている。各抵抗素子R1~抵抗素子R4は、可変電圧源13が、第1FET120~第4FET123のゲート端子Gに印加するDC(直流)電圧を安定して制御するために設けられる。この各抵抗素子R1~抵抗素子R4の抵抗値は、例えば、1kΩ程度とされる。 As shown in FIG. 1, theattenuation adjustment unit 11 further includes resistance elements R1 to R4.
One end of the resistance element R1 is connected to the gate terminal G of thefirst FET 120, and the other end is connected to the control terminal C. Similarly, one end of the resistor element R2 is connected to the gate terminal G of the second FET 121, one end of the resistor element R3 is connected to the gate terminal G of the third FET 122, and one end of the resistor element R4 is connected to the gate terminal G of the fourth FET 123. The other ends of the resistance elements R2 to R4 are all connected to the control terminal C. That is, the control terminal C is connected to all the gate terminals G of the first FET 120 to the fourth FET 123 via the resistance elements R1 to R4. Each of the resistance elements R1 to R4 is provided so that the variable voltage source 13 stably controls the DC (direct current) voltage applied to the gate terminals G of the first FET 120 to the fourth FET 123. Each of the resistance elements R1 to R4 has a resistance value of, for example, about 1 kΩ.
抵抗素子R1の一端は、第1FET120のゲート端子Gに接続され、他端がコントロール端子Cに接続される。同様に、抵抗素子R2の一端は第2FET121のゲート端子Gに接続され、抵抗素子R3の一端は第3FET122のゲート端子Gに接続され、抵抗素子R4の一端は第4FET123のゲート端子Gに接続され接続され、各抵抗素子R2~R4の他端は、全てコントロール端子Cに接続される。即ち、コントロール端子Cは、各抵抗素子R1~抵抗素子R4を介して、第1FET120~第4FET123の各ゲート端子Gの全てに接続されている。各抵抗素子R1~抵抗素子R4は、可変電圧源13が、第1FET120~第4FET123のゲート端子Gに印加するDC(直流)電圧を安定して制御するために設けられる。この各抵抗素子R1~抵抗素子R4の抵抗値は、例えば、1kΩ程度とされる。 As shown in FIG. 1, the
One end of the resistance element R1 is connected to the gate terminal G of the
また、可変電圧源13は、コントロール端子Cに接続され、当該コントロール端子Cに所定のDC電圧を印加する。可変電圧源13は、コントロール端子Cに印加するDC電圧を一定の範囲(例えば、±1V)で所望に変化させることができる。
The variable voltage source 13 is connected to the control terminal C and applies a predetermined DC voltage to the control terminal C. The variable voltage source 13 can change the DC voltage applied to the control terminal C as desired within a certain range (for example, ± 1 V).
以上のような構成の可変減衰器1は、例えば、以下のように動作する。
可変電圧源13が第1FET120~第4FET123の各ゲート端子Gにオフ電圧(例えば、-1V)を印加しているときは、第1FET120~第4FET123は、オフ状態(インピーダンスが高い状態)となって、ソースドレイン間に電流が流れない。したがって、第2出力ポートPout2及び第3出力ポートPout3は、開放状態となる。
そうすると、入力端子Pinから入力された高周波信号RFinは、第2出力ポートPout2及び第3出力ポートPout3でほぼ全反射され、減衰せずに第1出力端子Pout1から高周波信号RFoutとして出力される。 Thevariable attenuator 1 having the above configuration operates, for example, as follows.
When thevariable voltage source 13 applies an off voltage (for example, −1V) to the gate terminals G of the first FET 120 to the fourth FET 123, the first FET 120 to the fourth FET 123 are in an off state (a state where the impedance is high). No current flows between the source and drain. Accordingly, the second output port Pout2 and the third output port Pout3 are opened.
Then, the high frequency signal RFin input from the input terminal Pin is substantially totally reflected at the second output port Pout2 and the third output port Pout3, and is output from the first output terminal Pout1 as a high frequency signal RFout without being attenuated.
可変電圧源13が第1FET120~第4FET123の各ゲート端子Gにオフ電圧(例えば、-1V)を印加しているときは、第1FET120~第4FET123は、オフ状態(インピーダンスが高い状態)となって、ソースドレイン間に電流が流れない。したがって、第2出力ポートPout2及び第3出力ポートPout3は、開放状態となる。
そうすると、入力端子Pinから入力された高周波信号RFinは、第2出力ポートPout2及び第3出力ポートPout3でほぼ全反射され、減衰せずに第1出力端子Pout1から高周波信号RFoutとして出力される。 The
When the
Then, the high frequency signal RFin input from the input terminal Pin is substantially totally reflected at the second output port Pout2 and the third output port Pout3, and is output from the first output terminal Pout1 as a high frequency signal RFout without being attenuated.
一方、可変電圧源13が第1FET120~第4FET123の各ゲート端子Gにオン電圧(例えば、+1V)を印加しているときは、第1FET120~第4FET123はオン状態(低インピーダンスの状態)となって、ソースドレイン間に電流が流れる。したがって、第2出力ポートPout2及び第3出力ポートPout3から接地端子GNDに伝送する高周波信号の強度が増し、結果として、第1出力ポートPout1から出力される高周波信号RFoutが減衰する。
なお、ランゲカプラ10を用いた可変減衰器1においては、第2出力ポートPout2又は第3出力ポートPout3におけるインピーダンスに基づいて第1出力ポートPout1に入力される高周波信号RFinを適切に減衰させるためには、第2出力ポートPout2、第3出力ポートPout3のそれぞれに接続されるFETのインピーダンスを均一にしながら変化させる必要がある。 On the other hand, when thevariable voltage source 13 applies an on voltage (for example, +1 V) to the gate terminals G of the first FET 120 to the fourth FET 123, the first FET 120 to the fourth FET 123 are in an on state (low impedance state). A current flows between the source and drain. Therefore, the strength of the high frequency signal transmitted from the second output port Pout2 and the third output port Pout3 to the ground terminal GND increases, and as a result, the high frequency signal RFout output from the first output port Pout1 is attenuated.
In thevariable attenuator 1 using the Lange coupler 10, in order to appropriately attenuate the high-frequency signal RFin input to the first output port Pout1 based on the impedance at the second output port Pout2 or the third output port Pout3. The impedances of the FETs connected to the second output port Pout2 and the third output port Pout3 need to be changed while being uniform.
なお、ランゲカプラ10を用いた可変減衰器1においては、第2出力ポートPout2又は第3出力ポートPout3におけるインピーダンスに基づいて第1出力ポートPout1に入力される高周波信号RFinを適切に減衰させるためには、第2出力ポートPout2、第3出力ポートPout3のそれぞれに接続されるFETのインピーダンスを均一にしながら変化させる必要がある。 On the other hand, when the
In the
以上のように、可変減衰器1は、可変電圧源13がコントロール端子C(即ち、各ゲート端子G)に印加するDC電圧を調節して第1FET120~第4FET123のインピーダンスを変化させることにより、高周波信号の減衰量を変化させることができる。
As described above, the variable attenuator 1 adjusts the DC voltage applied to the control terminal C (that is, each gate terminal G) by the variable voltage source 13 to change the impedance of the first FET 120 to the fourth FET 123, thereby changing the high frequency. The amount of signal attenuation can be changed.
図2は、対比例に係る可変減衰器の全体構成を説明する図である。
図2に示すように、対比例に係る可変減衰器9は、ランゲカプラ10と、可変電圧源13と、減衰量調整部91と、を備えている。ここで、ランゲカプラ10及び可変電圧源13は、それぞれ第1の実施形態に係る可変減衰器1が備えるものと同一である。
図2に示すように、対比例に係る減衰量調整部91は、第1FET120と、第3FET122と、抵抗素子R1と、抵抗素子R3とを備えている。これらの各FET、抵抗素子の態様(素材、サイズ等)は、第1の実施形態と同等である。 FIG. 2 is a diagram for explaining the overall configuration of a variable attenuator related to the comparison.
As shown in FIG. 2, the proportionalvariable attenuator 9 includes a Lange coupler 10, a variable voltage source 13, and an attenuation adjustment unit 91. Here, the Lange coupler 10 and the variable voltage source 13 are the same as those provided in the variable attenuator 1 according to the first embodiment.
As shown in FIG. 2, theattenuation adjustment unit 91 according to proportionality includes a first FET 120, a third FET 122, a resistance element R1, and a resistance element R3. The aspects (material, size, etc.) of these FETs and resistance elements are the same as those in the first embodiment.
図2に示すように、対比例に係る可変減衰器9は、ランゲカプラ10と、可変電圧源13と、減衰量調整部91と、を備えている。ここで、ランゲカプラ10及び可変電圧源13は、それぞれ第1の実施形態に係る可変減衰器1が備えるものと同一である。
図2に示すように、対比例に係る減衰量調整部91は、第1FET120と、第3FET122と、抵抗素子R1と、抵抗素子R3とを備えている。これらの各FET、抵抗素子の態様(素材、サイズ等)は、第1の実施形態と同等である。 FIG. 2 is a diagram for explaining the overall configuration of a variable attenuator related to the comparison.
As shown in FIG. 2, the proportional
As shown in FIG. 2, the
対比例に係る減衰量調整部91では、ランゲカプラ10の第2出力ポートPout2と接地端子GNDの間に第1FET120が挿入され、第2出力ポートPout2と接地端子GNDに第1FET120のドレイン端子Dとソース端子Sがそれぞれ接続されている。また、ランゲカプラ10の第3出力ポートPout3と接地端子GNDの間に第3FET122が挿入され、第3出力ポートPout3と接地端子GNDに第3FET122のドレイン端子Dとソース端子Sがそれぞれ接続されている。
このような構成の可変減衰器9も、第1の実施形態に係る可変減衰器1(図1)と同等に動作する。 In theattenuation adjustment unit 91 related to the proportionality, the first FET 120 is inserted between the second output port Pout2 of the Lange coupler 10 and the ground terminal GND, and the drain terminal D and the source of the first FET 120 are connected to the second output port Pout2 and the ground terminal GND. Terminals S are connected to each other. The third FET 122 is inserted between the third output port Pout3 and the ground terminal GND of the Lange coupler 10, and the drain terminal D and the source terminal S of the third FET 122 are connected to the third output port Pout3 and the ground terminal GND, respectively.
Thevariable attenuator 9 having such a configuration also operates in the same manner as the variable attenuator 1 (FIG. 1) according to the first embodiment.
このような構成の可変減衰器9も、第1の実施形態に係る可変減衰器1(図1)と同等に動作する。 In the
The
図1、図2に示したように、第1の実施形態に係る可変減衰器1は、対比例に係る可変減衰器9と比較して、第2出力ポートPout2及び第3出力ポートPout3のそれぞれにおいて2つのFETが直列に接続されている点で異なっている。次に、本実施形態に係る可変減衰器1において、2つのFETが直列に接続されていることの効果について詳細に説明する。
As shown in FIGS. 1 and 2, the variable attenuator 1 according to the first embodiment has each of the second output port Pout2 and the third output port Pout3 compared to the variable attenuator 9 according to the proportionality. 2 differs in that two FETs are connected in series. Next, the effect of two FETs connected in series in the variable attenuator 1 according to this embodiment will be described in detail.
図3A及び図3Bは、第1の実施形態に係る可変減衰器の作用効果を説明する第1の図である。
図3Aには、対比例に係る可変減衰器9(図2)の減衰量調整部91を構成する第1FET120の等価回路を示している。また、図3Bには、本実施形態に係る可変減衰器1(図1)の減衰量調整部11を構成し、直列に接続される第1FET120及び第2FET121の等価回路を示している。 FIG. 3A and FIG. 3B are first diagrams illustrating the operational effects of the variable attenuator according to the first embodiment.
FIG. 3A shows an equivalent circuit of thefirst FET 120 that constitutes the attenuation adjustment unit 91 of the variable attenuator 9 (FIG. 2) that is in proportion. FIG. 3B shows an equivalent circuit of the first FET 120 and the second FET 121 that are included in the variable attenuator 1 (FIG. 1) according to the present embodiment and that are connected in series.
図3Aには、対比例に係る可変減衰器9(図2)の減衰量調整部91を構成する第1FET120の等価回路を示している。また、図3Bには、本実施形態に係る可変減衰器1(図1)の減衰量調整部11を構成し、直列に接続される第1FET120及び第2FET121の等価回路を示している。 FIG. 3A and FIG. 3B are first diagrams illustrating the operational effects of the variable attenuator according to the first embodiment.
FIG. 3A shows an equivalent circuit of the
図3Aに示す回路図は、FETの一般的な等価回路である。
対比例に係る可変減衰器9の減衰量調整部91の構成(図2)によれば、図3Aに示すように、第1FET120のドレイン端子Dとソース端子Sとの間には、寄生容量Cds(以下、「ドレインソース間容量Cds」とも記載する)が存在する。このドレインソース間容量Cdsは、主に、FETの内部に形成されるpn接合に起因して生じるものである。
このような第1FET120のドレイン端子D及びソース端子Sが、ランゲカプラ10の第2出力ポートPout2及び接地端子GNDとの間に接続されると、第2出力ポートPout2と接地端子GNDとの間に、常にドレインソース間容量Cdsが接続される。そうすると、第1FET120がオフ状態であったとしても、高周波信号がこのドレインソース間容量Cdsを経由して接地端子GNDに流れてしまう。つまり、通過損失が生じないように伝送したい場合であっても、常に存在するドレインソース間容量Cdsによって高周波信号の通過損失が生じてしまう。
ここで「通過損失」とは、入力ポートPinに入力した高周波信号RFinのレベル(強度)に対する、第1出力ポートPout1から出力された高周波信号RFoutのレベルの比を示す値(単位:dB)である。高周波信号RFinの入力レベルと高周波信号RFoutの出力レベルとが同等の場合(即ち、損失が生じていない場合)、通過損失は0dBとなる。高周波信号RFinの入力レベルに対し、高周波信号RFoutの出力レベルが低下していた場合(即ち、所定量の損失が生じた場合)、通過損失は負の値で示される。 The circuit diagram shown in FIG. 3A is a general equivalent circuit of an FET.
According to the configuration (FIG. 2) of theattenuation adjustment unit 91 of the variable attenuator 9 according to the comparison, as shown in FIG. 3A, a parasitic capacitance Cds is provided between the drain terminal D and the source terminal S of the first FET 120. (Hereinafter also referred to as “drain-source capacitance Cds”). This drain-source capacitance Cds is mainly caused by a pn junction formed inside the FET.
When the drain terminal D and the source terminal S of thefirst FET 120 are connected between the second output port Pout2 and the ground terminal GND of the Lange coupler 10, between the second output port Pout2 and the ground terminal GND, A drain-source capacitance Cds is always connected. Then, even if the first FET 120 is in an OFF state, a high frequency signal flows to the ground terminal GND via the drain-source capacitance Cds. That is, even when it is desired to transmit without causing a passage loss, a high-frequency signal passage loss is caused by the drain-source capacitance Cds that is always present.
Here, “passage loss” is a value (unit: dB) indicating a ratio of the level of the high-frequency signal RFout output from the first output port Pout1 to the level (intensity) of the high-frequency signal RFin input to the input port Pin. is there. When the input level of the high-frequency signal RFin is equal to the output level of the high-frequency signal RFout (that is, when no loss occurs), the passing loss is 0 dB. When the output level of the high-frequency signal RFout is lower than the input level of the high-frequency signal RFin (that is, when a predetermined amount of loss occurs), the passage loss is indicated by a negative value.
対比例に係る可変減衰器9の減衰量調整部91の構成(図2)によれば、図3Aに示すように、第1FET120のドレイン端子Dとソース端子Sとの間には、寄生容量Cds(以下、「ドレインソース間容量Cds」とも記載する)が存在する。このドレインソース間容量Cdsは、主に、FETの内部に形成されるpn接合に起因して生じるものである。
このような第1FET120のドレイン端子D及びソース端子Sが、ランゲカプラ10の第2出力ポートPout2及び接地端子GNDとの間に接続されると、第2出力ポートPout2と接地端子GNDとの間に、常にドレインソース間容量Cdsが接続される。そうすると、第1FET120がオフ状態であったとしても、高周波信号がこのドレインソース間容量Cdsを経由して接地端子GNDに流れてしまう。つまり、通過損失が生じないように伝送したい場合であっても、常に存在するドレインソース間容量Cdsによって高周波信号の通過損失が生じてしまう。
ここで「通過損失」とは、入力ポートPinに入力した高周波信号RFinのレベル(強度)に対する、第1出力ポートPout1から出力された高周波信号RFoutのレベルの比を示す値(単位:dB)である。高周波信号RFinの入力レベルと高周波信号RFoutの出力レベルとが同等の場合(即ち、損失が生じていない場合)、通過損失は0dBとなる。高周波信号RFinの入力レベルに対し、高周波信号RFoutの出力レベルが低下していた場合(即ち、所定量の損失が生じた場合)、通過損失は負の値で示される。 The circuit diagram shown in FIG. 3A is a general equivalent circuit of an FET.
According to the configuration (FIG. 2) of the
When the drain terminal D and the source terminal S of the
Here, “passage loss” is a value (unit: dB) indicating a ratio of the level of the high-frequency signal RFout output from the first output port Pout1 to the level (intensity) of the high-frequency signal RFin input to the input port Pin. is there. When the input level of the high-frequency signal RFin is equal to the output level of the high-frequency signal RFout (that is, when no loss occurs), the passing loss is 0 dB. When the output level of the high-frequency signal RFout is lower than the input level of the high-frequency signal RFin (that is, when a predetermined amount of loss occurs), the passage loss is indicated by a negative value.
一般に、FETのゲート幅Wを小さくすると、これに伴ってpn接合に基づく寄生容量(ドレインソース間容量Cds)が形成される面積も減少するため、ドレインソース間容量Cdsが減少する。したがって、通過損失を抑えるためには、第1FET120のゲート幅Wを小さくする必要がある。しかしながら、FETのゲート幅Wを小さくし過ぎると、当該FETにおける高周波特性の歪み特性が悪化し、高周波信号を歪ませてしまう場合がある。そのため、ドレインソース間容量Cdsを低減する目的でゲート幅Wを小さくすることには限界がある。したがって、対比例に係る可変減衰器9は、ドレインソース間容量Cdsが十分に低減できておらず、高周波信号の通過損失が大きいものとなっている。
Generally, when the gate width W of the FET is reduced, the area in which the parasitic capacitance (drain-source capacitance Cds) based on the pn junction is formed is reduced accordingly, so that the drain-source capacitance Cds is reduced. Therefore, in order to suppress the passage loss, it is necessary to reduce the gate width W of the first FET 120. However, if the gate width W of the FET is made too small, the high-frequency characteristic distortion characteristics of the FET may deteriorate and the high-frequency signal may be distorted. Therefore, there is a limit to reducing the gate width W for the purpose of reducing the drain-source capacitance Cds. Therefore, the variable attenuator 9 according to the proportionality cannot sufficiently reduce the drain-source capacitance Cds, and has a large passage loss of the high-frequency signal.
これに対し、本実施形態に係る可変減衰器1の減衰量調整部11の構成(図1)の場合について以下に説明する。この場合、図3Bの等価回路においては、第1FET120のドレイン端子Dがランゲカプラ10の第2出力ポートPout2に接続される(図1参照)。また、第1FET120及び第2FET121のゲート端子Gは、それぞれ抵抗素子R1及び抵抗素子R2を介して可変電圧源13に接続されている(図1参照)。このように、本実施形態に係る減衰量調整部11では、第2出力ポートPout2と接地端子GNDとの間に、2つのドレインソース間容量Cdsが直列に接続される。そうすると、第2出力ポートPout2と接地端子GNDとの間に生じる正味の寄生容量は、1/2×Cdsとなるため、このような構成の減衰量調整部11によれば、対比例に係る減衰量調整部91と比較して、高周波信号の通過損失を低く抑えることが出来る。
In contrast, the configuration of the attenuation adjustment unit 11 of the variable attenuator 1 according to the present embodiment (FIG. 1) will be described below. In this case, in the equivalent circuit of FIG. 3B, the drain terminal D of the first FET 120 is connected to the second output port Pout2 of the Lange coupler 10 (see FIG. 1). Further, the gate terminals G of the first FET 120 and the second FET 121 are connected to the variable voltage source 13 through the resistance element R1 and the resistance element R2, respectively (see FIG. 1). As described above, in the attenuation amount adjusting unit 11 according to the present embodiment, the two drain-source capacitances Cds are connected in series between the second output port Pout2 and the ground terminal GND. Then, since the net parasitic capacitance generated between the second output port Pout2 and the ground terminal GND is ½ × Cds, according to the attenuation amount adjustment unit 11 having such a configuration, the relative attenuation is obtained. Compared with the quantity adjustment unit 91, it is possible to suppress the passage loss of the high-frequency signal.
図4Aおよび図4Bは、実施形態に係る可変減衰器の作用効果を説明する第2の図である。
図4Aに示すグラフ図は、対比例に係る可変減衰器9の通過損失の特性を示している。また、図4Bに示すグラフ図は、第1の実施形態に係る可変減衰器1の通過損失の特性を示している。また、図4Aおよび図4Bにおいて、第1FET120~第4FET123のゲート端子Gにオフ電圧(-1V)を印加した場合における通過損失の特性を実線で示し、第1FET120~第4FET123のゲート端子Gにオン電圧(+1V)を印加した場合における通過損失の特性を破線で示している。 FIG. 4A and FIG. 4B are second diagrams for explaining the effects of the variable attenuator according to the embodiment.
The graph shown in FIG. 4A shows the characteristics of the passage loss of thevariable attenuator 9 according to the comparison. Moreover, the graph shown to FIG. 4B has shown the characteristic of the passage loss of the variable attenuator 1 which concerns on 1st Embodiment. 4A and 4B, the characteristics of the passage loss when the off voltage (−1V) is applied to the gate terminals G of the first FET 120 to the fourth FET 123 are indicated by solid lines, and the gate terminals G of the first FET 120 to the fourth FET 123 are turned on. The characteristics of the passage loss when a voltage (+1 V) is applied are indicated by broken lines.
図4Aに示すグラフ図は、対比例に係る可変減衰器9の通過損失の特性を示している。また、図4Bに示すグラフ図は、第1の実施形態に係る可変減衰器1の通過損失の特性を示している。また、図4Aおよび図4Bにおいて、第1FET120~第4FET123のゲート端子Gにオフ電圧(-1V)を印加した場合における通過損失の特性を実線で示し、第1FET120~第4FET123のゲート端子Gにオン電圧(+1V)を印加した場合における通過損失の特性を破線で示している。 FIG. 4A and FIG. 4B are second diagrams for explaining the effects of the variable attenuator according to the embodiment.
The graph shown in FIG. 4A shows the characteristics of the passage loss of the
図4Aに示すように、対比例に係る可変減衰器9は、第1FET120及び第3FET122のゲート端子Gにオフ電圧を印加しているにもかかわらず、周波数90GHzの高周波信号において-3.5dB程度の通過損失が生じている(図4A実線参照)。この通過損失は、上述したように、第1FET120(第3FET122)のドレインソース間容量Cdsに起因して生じている。
一方、図4Bに示すように、本実施形態に係る可変減衰器1は、第1FET120~第4FET123の各ゲート端子Gにオフ電圧を印加している場合、周波数90GHzの高周波信号における通過損失が-1.5dB程度に抑制されている。これは、第1FET120及び第2FET121(第3FET122及び第4FET123)に寄生するドレインソース間容量Cdsが直列に接続されることで、第2出力ポートPout2(第3出力ポートPout3)と接地端子GNDとの間に生じる寄生容量が1/2に低減されていることに起因する。 As shown in FIG. 4A, thevariable attenuator 9 according to the proportionality is about −3.5 dB in a high-frequency signal having a frequency of 90 GHz even though the off-voltage is applied to the gate terminals G of the first FET 120 and the third FET 122. (See the solid line in FIG. 4A). As described above, this passage loss is caused by the drain-source capacitance Cds of the first FET 120 (third FET 122).
On the other hand, as shown in FIG. 4B, in thevariable attenuator 1 according to the present embodiment, when the off voltage is applied to the gate terminals G of the first FET 120 to the fourth FET 123, the passage loss in the high-frequency signal of 90 GHz is − It is suppressed to about 1.5 dB. This is because the drain-source capacitance Cds parasitic to the first FET 120 and the second FET 121 (the third FET 122 and the fourth FET 123) is connected in series, so that the second output port Pout2 (the third output port Pout3) and the ground terminal GND are connected. This is because the parasitic capacitance generated between them is reduced to ½.
一方、図4Bに示すように、本実施形態に係る可変減衰器1は、第1FET120~第4FET123の各ゲート端子Gにオフ電圧を印加している場合、周波数90GHzの高周波信号における通過損失が-1.5dB程度に抑制されている。これは、第1FET120及び第2FET121(第3FET122及び第4FET123)に寄生するドレインソース間容量Cdsが直列に接続されることで、第2出力ポートPout2(第3出力ポートPout3)と接地端子GNDとの間に生じる寄生容量が1/2に低減されていることに起因する。 As shown in FIG. 4A, the
On the other hand, as shown in FIG. 4B, in the
一方、第1FET120~第4FET123のゲート端子Gにオン電圧(+1V)を印加した場合における通過損失は、周波数90GHzの高周波信号において-11.0dB程度と、対比例に係る可変減衰器9と同等の特性となっている。即ち、本実施形態に係る可変減衰器1は、印加するゲート電圧により、対比例に係る可変減衰器9と同等に、減衰量を制御出来ていることがわかる。
On the other hand, the passing loss when the on-voltage (+ 1V) is applied to the gate terminals G of the first FET 120 to the fourth FET 123 is about -11.0 dB in the high-frequency signal with the frequency of 90 GHz, which is equivalent to the variable attenuator 9 related to the comparison. It is a characteristic. That is, it can be seen that the variable attenuator 1 according to the present embodiment can control the amount of attenuation by the applied gate voltage in the same manner as the variable attenuator 9 according to the comparative example.
図5は、第1の実施形態に係る可変減衰器の作用効果を説明する第3の図である。
図5に示すグラフは、対比例に係る可変減衰器9(破線)と、本実施形態に係る可変減衰器1(実線)と、の周波数90GHzにおけるゲート電圧Vgsと通過損失との関係を示している。
図5に示すように、対比例に係る可変減衰器9の第1FET120、第3FET122の各ゲート端子Gに印加するゲート電圧Vgsを-1.5Vから+1.5Vまで変化させた場合、可変減衰器9の入力ポートPinから第1出力ポートPout1に伝送される高周波信号の通過損失は、-3.5dBから-11.0dBまで変化する。
これに対し、本実施形態に係る可変減衰器1の第1FET120~第4FET123の各ゲート端子Gに印加するゲート電圧Vgsを-1.5Vから+1.5Vまで変化させた場合、可変減衰器1の入力ポートPinから第1出力ポートPout1に伝送される高周波信号の通過損失は、-1.0dBから-11.0dBまで変化する。
このように、本実施形態に係る可変減衰器1は、第2出力ポートPout2(第3出力ポートPout3)と接地端子GNDとの間に生じる寄生容量を低減したことにより、対比例に係る可変減衰器9よりも制御可能な減衰量の幅が拡大されている。 FIG. 5 is a third diagram for explaining the operational effects of the variable attenuator according to the first embodiment.
The graph shown in FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the variable attenuator 9 (broken line) according to the proportionality and the variable attenuator 1 (solid line) according to the present embodiment. Yes.
As shown in FIG. 5, when the gate voltage Vgs applied to the gate terminals G of thefirst FET 120 and the third FET 122 of the variable attenuator 9 which is proportional to each other is changed from −1.5 V to +1.5 V, the variable attenuator The passing loss of the high-frequency signal transmitted from the nine input ports Pin to the first output port Pout1 varies from −3.5 dB to −11.0 dB.
On the other hand, when the gate voltage Vgs applied to each gate terminal G of thefirst FET 120 to the fourth FET 123 of the variable attenuator 1 according to this embodiment is changed from −1.5 V to +1.5 V, the variable attenuator 1 The passing loss of the high-frequency signal transmitted from the input port Pin to the first output port Pout1 varies from −1.0 dB to −11.0 dB.
As described above, thevariable attenuator 1 according to the present embodiment reduces the parasitic capacitance generated between the second output port Pout2 (third output port Pout3) and the ground terminal GND, so that the variable attenuation according to the proportionality is achieved. The range of attenuation that can be controlled is larger than that of the device 9.
図5に示すグラフは、対比例に係る可変減衰器9(破線)と、本実施形態に係る可変減衰器1(実線)と、の周波数90GHzにおけるゲート電圧Vgsと通過損失との関係を示している。
図5に示すように、対比例に係る可変減衰器9の第1FET120、第3FET122の各ゲート端子Gに印加するゲート電圧Vgsを-1.5Vから+1.5Vまで変化させた場合、可変減衰器9の入力ポートPinから第1出力ポートPout1に伝送される高周波信号の通過損失は、-3.5dBから-11.0dBまで変化する。
これに対し、本実施形態に係る可変減衰器1の第1FET120~第4FET123の各ゲート端子Gに印加するゲート電圧Vgsを-1.5Vから+1.5Vまで変化させた場合、可変減衰器1の入力ポートPinから第1出力ポートPout1に伝送される高周波信号の通過損失は、-1.0dBから-11.0dBまで変化する。
このように、本実施形態に係る可変減衰器1は、第2出力ポートPout2(第3出力ポートPout3)と接地端子GNDとの間に生じる寄生容量を低減したことにより、対比例に係る可変減衰器9よりも制御可能な減衰量の幅が拡大されている。 FIG. 5 is a third diagram for explaining the operational effects of the variable attenuator according to the first embodiment.
The graph shown in FIG. 5 shows the relationship between the gate voltage Vgs and the passage loss at a frequency of 90 GHz of the variable attenuator 9 (broken line) according to the proportionality and the variable attenuator 1 (solid line) according to the present embodiment. Yes.
As shown in FIG. 5, when the gate voltage Vgs applied to the gate terminals G of the
On the other hand, when the gate voltage Vgs applied to each gate terminal G of the
As described above, the
図6は、第1の実施形態に係る可変減衰器の作用効果を説明する第4の図である。
図6に示すグラフは、対比例に係る可変減衰器9(破線)と本実施形態に係る可変減衰器1(実線)とのゲート電圧Vgsに対する3次相互変調歪み(IM3)の特性を示している。図6に示す通り、本実施形態に係る可変減衰器1は、ゲート電圧Vgsが-1Vのときには、対比例に係る可変減衰器9に比べて8dB程度歪み特性が改善されている。また、ゲート電圧Vgsが+1Vのときには、可変減衰器1は、対比例に係る可変減衰器9に比べて15dB程度歪み特性が改善されている。
このように、減衰量の制御に用いるFETを直列に多段接続することで、一つ当たりのFETのソースドレイン間に印加される電圧が軽減されるため、歪み特性を改善することができる。 FIG. 6 is a fourth diagram illustrating the operational effect of the variable attenuator according to the first embodiment.
The graph shown in FIG. 6 shows the characteristic of the third-order intermodulation distortion (IM3) with respect to the gate voltage Vgs of the variable attenuator 9 (broken line) and the variable attenuator 1 (solid line) according to the present embodiment. Yes. As shown in FIG. 6, thevariable attenuator 1 according to the present embodiment has a distortion characteristic improved by about 8 dB compared to the variable attenuator 9 according to the proportionality when the gate voltage Vgs is −1V. When the gate voltage Vgs is +1 V, the distortion characteristics of the variable attenuator 1 are improved by about 15 dB compared to the variable attenuator 9 according to the proportionality.
In this way, by connecting FETs used for attenuation control in multiple stages in series, the voltage applied between the source and drain of each FET is reduced, so that the distortion characteristics can be improved.
図6に示すグラフは、対比例に係る可変減衰器9(破線)と本実施形態に係る可変減衰器1(実線)とのゲート電圧Vgsに対する3次相互変調歪み(IM3)の特性を示している。図6に示す通り、本実施形態に係る可変減衰器1は、ゲート電圧Vgsが-1Vのときには、対比例に係る可変減衰器9に比べて8dB程度歪み特性が改善されている。また、ゲート電圧Vgsが+1Vのときには、可変減衰器1は、対比例に係る可変減衰器9に比べて15dB程度歪み特性が改善されている。
このように、減衰量の制御に用いるFETを直列に多段接続することで、一つ当たりのFETのソースドレイン間に印加される電圧が軽減されるため、歪み特性を改善することができる。 FIG. 6 is a fourth diagram illustrating the operational effect of the variable attenuator according to the first embodiment.
The graph shown in FIG. 6 shows the characteristic of the third-order intermodulation distortion (IM3) with respect to the gate voltage Vgs of the variable attenuator 9 (broken line) and the variable attenuator 1 (solid line) according to the present embodiment. Yes. As shown in FIG. 6, the
In this way, by connecting FETs used for attenuation control in multiple stages in series, the voltage applied between the source and drain of each FET is reduced, so that the distortion characteristics can be improved.
以上、第1の実施形態に係る可変減衰器1によれば、減衰量を制御するFETがソース端子とドレイン端子とを介して直列に多段接続されることで、伝送する高周波信号の損失及び歪み特性を改善することができる。
As described above, according to the variable attenuator 1 according to the first embodiment, the loss and distortion of the high-frequency signal to be transmitted are obtained by connecting the FET for controlling the attenuation amount in series through the source terminal and the drain terminal. The characteristics can be improved.
なお、本実施形態に係る可変減衰器1は、ランゲカプラ10の第2出力ポートPout2及び第3出力ポートPout3のそれぞれにおいてFET(第1FET120~第4FET123)が、それぞれ2つずつ直列に接続される態様としているが、他の実施形態においてはこの態様に限定されない。例えば、ランゲカプラ10の第2出力ポートPout2及び第3出力ポートPout3のそれぞれに直列に接続されるFETの数を3つ以上としてもよい。このようにすることで、伝送する高周波信号の損失及び歪み特性を一層改善することができる。
In the variable attenuator 1 according to the present embodiment, two FETs (first FET 120 to fourth FET 123) are connected in series in each of the second output port Pout2 and the third output port Pout3 of the Lange coupler 10. However, other embodiments are not limited to this aspect. For example, the number of FETs connected in series to each of the second output port Pout2 and the third output port Pout3 of the Lange coupler 10 may be three or more. By doing so, the loss and distortion characteristics of the high-frequency signal to be transmitted can be further improved.
また、本実施形態に係る減衰量調整部11は、ランゲカプラ10の第2出力ポートPout2と接地端子GNDとの間、及び、第3出力ポートPout3と接地端子GNDとの間において同数(2つ)のFETを直列に接続している。これにより、第2出力ポートPout2に接続されるFETのインピーダンスと、第3出力ポートPout3に接続されるFETのインピーダンスと、を均一に変化させることが容易となる。
ただし、他の実施形態に係る可変減衰器1は、この態様に限定されない。すなわち、第2出力ポートPout2へ直列に接続されるFETの数と、第3出力ポートPout3へ直列に接続されるFETの数とが異なっていても、第2出力ポートPout2又は第3出力ポートPout3に接続される各FETの総合的なインピーダンスが均一となっていれば、同様の作用効果を得ることができる。 Further, the same number (two) of theattenuation adjustment units 11 according to the present embodiment is provided between the second output port Pout2 and the ground terminal GND of the Lange coupler 10 and between the third output port Pout3 and the ground terminal GND. FETs are connected in series. Thereby, it becomes easy to uniformly change the impedance of the FET connected to the second output port Pout2 and the impedance of the FET connected to the third output port Pout3.
However, thevariable attenuator 1 according to another embodiment is not limited to this aspect. That is, even if the number of FETs connected in series to the second output port Pout2 is different from the number of FETs connected in series to the third output port Pout3, the second output port Pout2 or the third output port Pout3 Similar effects can be obtained if the overall impedance of the FETs connected to is uniform.
ただし、他の実施形態に係る可変減衰器1は、この態様に限定されない。すなわち、第2出力ポートPout2へ直列に接続されるFETの数と、第3出力ポートPout3へ直列に接続されるFETの数とが異なっていても、第2出力ポートPout2又は第3出力ポートPout3に接続される各FETの総合的なインピーダンスが均一となっていれば、同様の作用効果を得ることができる。 Further, the same number (two) of the
However, the
また、本実施形態に係る減衰量調整部11は、第1FET120~第4FET123の各ゲート端子Gの全てに接続される単一のコントロール端子Cを有するものとして説明した。これにより、可変電圧源13は、当該単一のコントロール端子Cのみに所望のDC電圧を印加するだけで、全てのFETのゲート端子Gに同一のゲート電圧Vgsを印加することができる。したがって、第2出力ポートPout2に接続されるFETのインピーダンスと、第3出力ポートPout3に接続されるFETのインピーダンスと、を均一に変化させることを容易にすることができる。
ただし、他の実施形態に係る可変減衰器1は、この態様に限定されない。すなわち、第2出力ポートPout2へ直列に接続される2つ以上のFET、及び、第3出力ポートPout3へ直列に接続される2つ以上のFETのそれぞれのゲート端子Gに、個別にゲート電圧Vgsを印加してもよい。このような態様において、それぞれ異なるゲート電圧Vgsが印加されていたとしても、第2出力ポートPout2又は第3出力ポートPout3に接続される各FETの総合的なインピーダンスが均一となっていれば、同様の作用効果を得ることができる。 Further, theattenuation adjustment unit 11 according to the present embodiment has been described as having a single control terminal C connected to all the gate terminals G of the first FET 120 to the fourth FET 123. Thereby, the variable voltage source 13 can apply the same gate voltage Vgs to the gate terminals G of all FETs only by applying a desired DC voltage only to the single control terminal C. Therefore, it is possible to easily change the impedance of the FET connected to the second output port Pout2 and the impedance of the FET connected to the third output port Pout3 uniformly.
However, thevariable attenuator 1 according to another embodiment is not limited to this aspect. That is, the gate voltage Vgs is individually applied to the gate terminals G of two or more FETs connected in series to the second output port Pout2 and two or more FETs connected in series to the third output port Pout3. May be applied. In such an embodiment, even if different gate voltages Vgs are applied, if the overall impedance of each FET connected to the second output port Pout2 or the third output port Pout3 is uniform, the same applies. The effect of this can be obtained.
ただし、他の実施形態に係る可変減衰器1は、この態様に限定されない。すなわち、第2出力ポートPout2へ直列に接続される2つ以上のFET、及び、第3出力ポートPout3へ直列に接続される2つ以上のFETのそれぞれのゲート端子Gに、個別にゲート電圧Vgsを印加してもよい。このような態様において、それぞれ異なるゲート電圧Vgsが印加されていたとしても、第2出力ポートPout2又は第3出力ポートPout3に接続される各FETの総合的なインピーダンスが均一となっていれば、同様の作用効果を得ることができる。 Further, the
However, the
また、本実施形態に係る可変減衰器1は、ランゲカプラ10と、減衰量調整部11の各構成要素(第1FET120~第4FET123、抵抗素子R1~抵抗素子R4等)と、が同一の半導体基板上に一体に形成される態様としてもよい。このようにすることで、可変減衰器1の小型化を図ることができ、製造コストの低減に資する。
ただし、他の実施形態においてはこの態様に限定されず、例えば、ランゲカプラ10、減衰量調整部11の各構成要素が個別に実装される態様であってもよい。 Further, thevariable attenuator 1 according to the present embodiment includes the Lange coupler 10 and the components of the attenuation adjustment unit 11 (first FET 120 to fourth FET 123, resistance element R1 to resistance element R4, etc.) on the same semiconductor substrate. It is good also as an aspect formed integrally. By doing so, the variable attenuator 1 can be reduced in size, which contributes to a reduction in manufacturing cost.
However, in other embodiments, the present invention is not limited to this mode. For example, the constituent elements of theLange coupler 10 and the attenuation amount adjustment unit 11 may be individually mounted.
ただし、他の実施形態においてはこの態様に限定されず、例えば、ランゲカプラ10、減衰量調整部11の各構成要素が個別に実装される態様であってもよい。 Further, the
However, in other embodiments, the present invention is not limited to this mode. For example, the constituent elements of the
また、本実施形態に係るランゲカプラ10の構成は、上述した態様に限定されない。例えば、ランゲカプラ10を、分布定数ブランチラインカプラとしてもよい。また、高周波信号の周波数が比較的低い場合は、スパイラルインダクタを用いた集中定数型ブランチラインカプラを用いてもよい。
Further, the configuration of the Lange coupler 10 according to the present embodiment is not limited to the above-described aspect. For example, the Lange coupler 10 may be a distributed constant branch line coupler. If the frequency of the high frequency signal is relatively low, a lumped constant branch line coupler using a spiral inductor may be used.
図7は、他の実施形態に係る減衰量調整回路の機能構成を示す図である。
減衰量調整回路11Aは、入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラの第2出力ポートと接地端子GNDの間、及び、カプラの第3出力ポートと接地端子GNDとの間のそれぞれにおいて、ソース端子Sとドレイン端子Dとを介して直列に接続された少なくとも2つ以上のFET12を有する。 FIG. 7 is a diagram illustrating a functional configuration of an attenuation adjustment circuit according to another embodiment.
Theattenuation adjustment circuit 11A distributes a high-frequency signal input from the input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port. And at least two FETs 12 connected in series via a source terminal S and a drain terminal D between the first output terminal and the ground terminal GND and between the third output port of the coupler and the ground terminal GND. .
減衰量調整回路11Aは、入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラの第2出力ポートと接地端子GNDの間、及び、カプラの第3出力ポートと接地端子GNDとの間のそれぞれにおいて、ソース端子Sとドレイン端子Dとを介して直列に接続された少なくとも2つ以上のFET12を有する。 FIG. 7 is a diagram illustrating a functional configuration of an attenuation adjustment circuit according to another embodiment.
The
また、他の実施形態に係る減衰量調整方法は、入力ポートPin、第1出力ポートPout1、第2出力ポートPout2及び第3出力ポートPout3を有するカプラ10の入力ポートPinに高周波信号RFinを入力し、第2出力ポートPout2と接地端子GNDとの間、及び、第3出力ポートPout3と接地端子GNDとの間のそれぞれにおいて、ソース端子Sとドレイン端子Dとを介して直列に接続された少なくとも2つ以上のFET12のゲート端子に電圧を印加して、第1出力ポートPout1に出力される高周波信号RFoutの減衰量を調整する。
Further, in the attenuation adjustment method according to another embodiment, the high frequency signal RFin is input to the input port Pin of the coupler 10 having the input port Pin, the first output port Pout1, the second output port Pout2, and the third output port Pout3. , At least 2 connected in series via the source terminal S and the drain terminal D between the second output port Pout2 and the ground terminal GND and between the third output port Pout3 and the ground terminal GND, respectively. A voltage is applied to the gate terminals of one or more FETs 12 to adjust the attenuation amount of the high-frequency signal RFout output to the first output port Pout1.
以上、本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものとする。
Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof, as long as they are included in the scope and gist of the invention.
本願は、2014年5月15日に、日本に出願された特願2014-101112号に基づき優先権を主張し、その内容をここに援用する。
This application claims priority based on Japanese Patent Application No. 2014-101112 filed in Japan on May 15, 2014, the contents of which are incorporated herein by reference.
本発明は、例えば、高周波信号の利得制御に適用することができる。本発明によれば、伝送する高周波信号の損失及び歪み特性を改善することができる。
The present invention can be applied to, for example, gain control of a high frequency signal. According to the present invention, loss and distortion characteristics of a high-frequency signal to be transmitted can be improved.
1 可変減衰器
10 ランゲカプラ(カプラ)
100 第1結合線路
101 第2結合線路
11 減衰量調整部
11A 減衰量調整回路
12 FET
120 第1FET
121 第2FET
122 第3FET
123 第4FET
13 可変電圧源 1Variable attenuator 10 Lange coupler (coupler)
100 first coupledline 101 second coupled line 11 attenuation adjustment unit 11A attenuation adjustment circuit 12 FET
120 1st FET
121 2nd FET
122 3rd FET
123 4th FET
13 Variable voltage source
10 ランゲカプラ(カプラ)
100 第1結合線路
101 第2結合線路
11 減衰量調整部
11A 減衰量調整回路
12 FET
120 第1FET
121 第2FET
122 第3FET
123 第4FET
13 可変電圧源 1
100 first coupled
120 1st FET
121 2nd FET
122 3rd FET
123 4th FET
13 Variable voltage source
Claims (6)
- 入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラと、
前記第2出力ポートと接地端子の間、及び、前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETを有する減衰量調整部と、
を備える可変減衰器。 A coupler that distributes a high-frequency signal input from the input port and outputs a high-frequency signal distributed from each of the first output port, the second output port, and the third output port;
An attenuation having at least two FETs connected in series via a source terminal and a drain terminal between the second output port and the ground terminal and between the third output port and the ground terminal, respectively. An amount adjustment unit;
A variable attenuator comprising: - 前記減衰量調整部は、
前記第2出力ポートと前記接地端子との間、及び、前記第3出力ポートと前記接地端子との間において直列に接続された前記FETの数が同数である
請求項1に記載の可変減衰器。 The attenuation adjustment unit
The variable attenuator according to claim 1, wherein the number of the FETs connected in series between the second output port and the ground terminal and in series between the third output port and the ground terminal is the same. . - 前記減衰量調整部は、
前記FETのゲート端子の全てに接続されるコントロール端子を有する
請求項2に記載の可変減衰器。 The attenuation adjustment unit
The variable attenuator according to claim 2, further comprising a control terminal connected to all of the gate terminals of the FET. - 前記カプラと、前記減衰量調整部とは、
同一の基板上に一体に形成されている
請求項1から請求項3の何れか一項に記載の可変減衰器。 The coupler and the attenuation adjustment unit are:
The variable attenuator according to any one of claims 1 to 3, wherein the variable attenuator is integrally formed on the same substrate. - 入力ポートから入力される高周波信号を分配して第1出力ポート、第2出力ポート及び第3出力ポートのそれぞれから分配された高周波信号を出力するカプラの前記第2出力ポートと接地端子の間、及び、前記カプラの前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETを有する減衰量調整回路。 Between the second output port and the ground terminal of the coupler that distributes the high frequency signal input from the input port and outputs the high frequency signal distributed from each of the first output port, the second output port, and the third output port; And an attenuation adjustment circuit having at least two FETs connected in series via a source terminal and a drain terminal, respectively, between the third output port of the coupler and the ground terminal.
- 入力ポート、第1出力ポート、第2出力ポート及び第3出力ポートを有するカプラの前記入力ポートに高周波信号を入力し、
前記第2出力ポートと接地端子との間、及び、前記第3出力ポートと前記接地端子との間のそれぞれにおいて、ソース端子とドレイン端子とを介して直列に接続された少なくとも2つのFETのゲート端子に電圧を印加する
減衰量調整方法。 A high frequency signal is input to the input port of the coupler having an input port, a first output port, a second output port, and a third output port;
Gates of at least two FETs connected in series via a source terminal and a drain terminal between the second output port and the ground terminal and between the third output port and the ground terminal, respectively. Attenuation adjustment method to apply voltage to terminals.
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438105U (en) * | 1990-07-30 | 1992-03-31 | ||
JPH06232607A (en) * | 1993-02-04 | 1994-08-19 | Mitsubishi Electric Corp | Attenuator |
JPH1051209A (en) * | 1996-08-02 | 1998-02-20 | Nippon Telegr & Teleph Corp <Ntt> | Microwave circuit |
JP2000124709A (en) * | 1998-10-19 | 2000-04-28 | Toshiba Corp | Microwave variable attenuation circuit |
JP2004201055A (en) * | 2002-12-19 | 2004-07-15 | Mitsubishi Electric Corp | Attenuator |
US20120075017A1 (en) * | 2009-11-20 | 2012-03-29 | Huawei Technologies Co., Ltd. | Attenuator |
-
2015
- 2015-03-19 WO PCT/JP2015/058159 patent/WO2015174138A1/en active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0438105U (en) * | 1990-07-30 | 1992-03-31 | ||
JPH06232607A (en) * | 1993-02-04 | 1994-08-19 | Mitsubishi Electric Corp | Attenuator |
JPH1051209A (en) * | 1996-08-02 | 1998-02-20 | Nippon Telegr & Teleph Corp <Ntt> | Microwave circuit |
JP2000124709A (en) * | 1998-10-19 | 2000-04-28 | Toshiba Corp | Microwave variable attenuation circuit |
JP2004201055A (en) * | 2002-12-19 | 2004-07-15 | Mitsubishi Electric Corp | Attenuator |
US20120075017A1 (en) * | 2009-11-20 | 2012-03-29 | Huawei Technologies Co., Ltd. | Attenuator |
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