WO2015168862A1

WO2015168862A1 - Data processing device and method

Info

Publication number: WO2015168862A1
Application number: PCT/CN2014/076889
Authority: WO
Inventors: 金丽丽; 李沫; 喻凡
Original assignee: 华为技术有限公司
Priority date: 2014-05-06
Filing date: 2014-05-06
Publication date: 2015-11-12
Also published as: CN106464701A; CN106464701B

Abstract

The present invention provides a data processing device and method, relating to the field of communications, and can reduce the bit error rate of irregular Low Density Parity Check Code (LDPC) decoding and error platform risk. The method includes: obtaining the value of each check node and the value of each posterior probability in the _-th iteration according to the value of each variable node in the _-th iteration of the irregular LDPC decoding; determining whether _ is less than a preset number of the iterations; if it is determined that _ is less than the preset number of the iterations, determining the number of rows not satisfied a parity check equation in a check matrix; obtaining the value of each variable node in the (_)-th iteration according to the number of rows not satisfied the parity check equation in the check matrix, the value of each check node and the value of each posterior probability in the _-th iteration; if _ is greater than or equal to the preset number of the iterations, outputting the value of each posterior probability in the _-th iteration. The data processing method and device provided by the present invention are used for irregular LDPC decoding.

Description

Data processing device and method

The present invention relates to the field of communications, and in particular, to a data processing device and method.

Background technique

The LDPC (Low Density Parity Check Code) code is a type of block code defined by a sparse check matrix. The LDPC code not only has good performance close to the Shannon limit, but also has low decoding complexity and structure. Flexible, LDPC codes can be classified into regular LDPC codes and irregular LDPC codes. Among them, the irregular LDPC code has better gain performance than the regular LDPC code because of its different row weight and column weight, and can flexibly construct different code rates, but its error platform risk is higher than the regular LDPC code.

In the prior art, taking the process of implementing irregular LDPC decoding by an LDPC decoder as an example, the LDPC decoder includes a posteriori probability APP value memory, a variable node Vn value memory, a check node Cn value memory, and an exchange/inverse A switching module and a minimum sum decoding module, wherein the minimum sum decoding module is used for LDPC decoding. In the LDPC decoding process, the Vn value of the i+1th iteration is calculated according to the Cn value and the APP value of the i-th iteration, and the Cn value of the i+1th iteration is calculated according to the Vn value of the i+1th iteration. APP value. Based on the Cn value and the APP value of the i+1 iteration, the V value of the i+2th iteration is calculated, and the above iterative process is repeated until the number of iterations reaches a predetermined number of times, and the APP value result is output. In the process of irregular LDPC decoding, the APP value, Vn value and Cn value need to be quantized. The smaller the quantization bit width, the less logic resources the LDPC decoder occupies and the lower the system complexity. At the same time, when the quantization bit width is small, the situation may occur during the iterative process. When the number of iterations does not reach the preset number of iterations, the system reaches a false balance, and the Cn value, Vn value, and APP value no longer change, resulting in APP. The final output of the value is wrong, resulting in an increase in the bit error rate and an increased risk of the wrong platform.

Summary of the invention

Embodiments of the present invention provide a data processing apparatus and method capable of reducing a bit error rate and an error platform risk of irregular LDPC decoding. To achieve the above objective, the embodiment of the present invention adopts the following technical solutions: In a first aspect, a data processing device is provided, including:

a first acquiring unit, configured to acquire, according to a value of each variable node of the i-th iteration of the irregular LDPC decoding, a value of each check node of the i-th iteration and each of the i-th iteration a value of the posterior probability, the i being a positive integer;

a first determining unit, configured to determine whether the i is less than a preset number of iterations, and a second determining unit, configured to determine a check matrix when the first determining unit determines that the i is less than the preset number of iterations The number of rows of the parity check equation is not satisfied; the second obtaining unit is configured to obtain, according to the second determining unit, the number of rows of the parity check matrix that does not satisfy the parity check equation, and obtain by the first acquiring unit The value of each check node of the ith iteration and the value of each posterior probability of the ith iteration acquire the value of each variable node of the i+1th iteration;

The second determining unit is further configured to output, when the first determining unit determines that the i is greater than or equal to the preset number of iterations, output a value of each posterior probability of the i th iteration.

In combination with the first aspect, in a first implementation manner, the second obtaining unit is specifically configured to:

Determining whether the number of rows in the check matrix determined by the second determining unit that does not satisfy the parity check equation is less than a preset threshold;

If the number of rows in the check matrix that does not satisfy the parity check equation is less than the preset threshold, subtracting the value of each posterior probability of the ith iteration from the correspondence of the ith iteration The result of checking the value of the node as the value of the corresponding variable node of the i+1th iteration;

Adding X to the value of the variable node of the ith + 1th iteration corresponding to the last non-zero item of each row in the check matrix, where X is an integer greater than -2 ^M and less than SM^ - I M is the bit width of the variable node.

In combination with the first aspect or the first achievable manner, in the second implementable manner, the X is 1.

Combining the first aspect, the first to the second achievable manner, and the third achievable In the mode, the second acquiring unit is further configured to:

If the number of rows in the check matrix that does not satisfy the parity check equation is greater than or equal to the preset threshold, subtracting the value of each posterior probability of the ith iteration from the ith iteration The result of the corresponding check node value is the value of the corresponding variable node of the i+1th iteration.

In conjunction with the third implementation manner, in the fourth implementation manner, the first acquiring unit is specifically configured to:

Obtaining a value of each check node of the i-th iteration according to a value of each variable node of the i-th iteration, and a value of each check node of the i-th iteration satisfies a check formula:

C _n = ( l signa )) χ max((min ψ _η |)-^), 0),

Where ^ is a constant, i is the number of iterations, « ' is the variable node of the ith iteration, and ^C " is the check node of the ith iteration;

The sum of the value of each variable node of the i-th iteration and the value of the corresponding check node of the i-th iteration is taken as the value of the corresponding posterior probability of the i-th iteration.

With reference to the first aspect, the first to the fourth implementation manner, in the fifth implementation manner, the first obtaining unit is further configured to:

Determining whether a value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N - ^! -l, where N is a bit width of a posteriori probability;

If the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N -1, replace the value of the first posterior probability of the ith iteration with 2 ^N -1;

Determining whether the value of the posterior probability of the i-1th iteration is less than or equal to ^^ + l; if the value of the first posterior probability of the i-1th iteration is less than or equal to -2 ^Ν + 1 , Then the value of the first posterior probability of the ith iteration is replaced by -2 ^N + 1.

With reference to the first aspect, the first achievable manner, and the fifth achievable manner, in the sixth achievable manner, the second determining unit includes:

a dividing subunit, configured to divide the check matrix into a predetermined number of matrices by rows; and acquiring a subunit, configured to obtain a number of rows in each of the submatrices that do not satisfy the parity check equation; And a processing sub-unit, configured to use, as a sum of the number of rows in each of the sub-matrices that does not satisfy the parity check equation, a number of rows in the check matrix that do not satisfy the parity check equation.

In conjunction with the sixth implementation, in the seventh implementation, the obtaining subunit is specifically configured to:

Calculating a symbol product of values of the variable nodes of the i-th iteration corresponding to each non-zero entry of the first sub-matrix;

Determining whether a symbol product of values of the variable nodes of the i-th iteration corresponding to each non-zero entry of the first sub-matrix is equal to -1;

If the symbol product of the value of the variable node of the i-th iteration corresponding to the w-row non-zero entry in the first sub-matrix is equal to -1, the w is an unsatisfied parity in the first sub-matrix The number of rows of the equation is determined, and the w is smaller than the number of rows of the first sub-matrix.

In a second aspect, a data processing device is provided, including:

a processor, configured to obtain, according to a value of each variable node of the i-th iteration of the irregular LDPC decoding, a value of each check node of the i-th iteration and each posterior of the i-th iteration a value of probability, the i being a positive integer;

The processor is further configured to determine whether the i is less than a preset number of iterations; the processor is further configured to: if it is determined that the i is less than the preset number of iterations, determine that the check matrix does not satisfy the parity Check the number of rows of the equation;

The processor is further configured to: according to the number of rows in the check matrix that do not satisfy the parity check equation, the value of each check node of the ith iteration, and each of the ith iterations The value of the probability is obtained to obtain the value of each variable node of the i+1th iteration;

The processor is further configured to output a value of each posterior probability of the i-th iteration if it is determined that the i is greater than or equal to the preset number of iterations.

With reference to the second aspect, in a first implementation manner, the processor is specifically configured to: determine whether a number of rows in the check matrix that do not satisfy the parity check equation is less than a preset threshold;

If the number of rows in the check matrix that does not satisfy the parity check equation is less than the preset threshold, subtracting the value of each posterior probability of the ith iteration from the correspondence of the ith iteration The result of checking the value of the node as the corresponding variable section of the i+1th iteration Point value

Adding X to the value of the variable node of the ith + 1 iteration corresponding to the last non-zero entry of each row in the check matrix, the X being greater than -2 ^M and less than

The integer, the M is the bit width of the variable node.

In combination with the second aspect or the first implementation manner, in the second implementation manner, the X is 1.

In combination with the second aspect, the first to the second implementation manners, in a third implementation manner, the processor is further configured to:

In combination with the third implementation manner, in a fourth implementation manner, the processor is specifically configured to:

C _n = ( l signa )) χ max((min ψ _η |)-^), 0),

Where ^ is a constant, i is the number of iterations, « ' is the variable node of the i-th iteration, and is the check node of the i-th iteration;

With reference to the second aspect, the first to fourth implementable manners, in a fifth implementable manner, the processor is further configured to:

Obtaining the value of the first posterior probability of the i-1th iteration;

If the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N -1, replace the value of the first posterior probability of the ith iteration with 2 ^N -1; Determining whether the value of the posterior probability of the i-th iteration is less than or equal to ^^ + l; if the value of the first posterior probability of the i-th iteration is less than or equal to -2 ^Ν + 1 , Then the value of the first posterior probability of the ith iteration is replaced by -2 ^N + 1.

In combination with the second aspect, the first achievable manner, and the fifth achievable manner, in a sixth implementation manner, the processor is specifically configured to:

Dividing the check matrix into a predetermined number of matrices by rows;

Obtaining a number of rows in each of the sub-matrices that do not satisfy the parity check equation;

The sum of the number of rows in each of the sub-matrices that does not satisfy the parity check equation is taken as the number of rows in the check matrix that do not satisfy the parity check equation.

In combination with the sixth implementation manner, in a seventh implementation manner, the processor is specifically configured to:

In a third aspect, a data processing method is provided, including:

Obtaining a value of each check node of the ith iteration and a value of each posterior probability of the ith iteration according to a value of each variable node of the i-th iteration of the irregular LDPC decoding, Said i is a positive integer;

Determining whether the i is less than a preset number of iterations;

If it is determined that the i is less than the preset number of iterations, determining a number of rows in the check matrix that do not satisfy the parity check equation;

Obtaining the i+1 according to the number of rows in the check matrix that do not satisfy the parity check equation, the value of each check node of the i-th iteration, and the value of each posterior probability of the i-th iteration The value of each variable node of the iteration;

If it is determined that the i is greater than or equal to the preset number of iterations, outputting the ith The value of each posterior probability of the iteration.

With reference to the third aspect, in a first implementation manner, the determining, according to the check matrix, the number of rows that do not satisfy the parity check equation, the value of each check node of the i-th iteration, and the The value of each posterior probability of the i-th iteration acquires the value of each variable node of the i+1th iteration, including:

Determining whether the number of rows in the check matrix that does not satisfy the parity check equation is less than a preset threshold;

In combination with the third aspect or the first achievable manner, in the second implementable manner, the X is 1.

With reference to the third aspect, the first to the second implementation manner, the value of each check node that does not satisfy the parity check equation in the check matrix, and the value of each check node of the ith iteration The value of each posterior probability of the i-th iteration acquires the value of each variable node of the i+1th iteration, and further includes:

With reference to the third implementation manner, in a fourth implementation manner, the value of each variable node according to the ith iteration of the irregular LDPC decoding acquires the value of each check node of the ith iteration And the value of each posterior probability of the ith iteration, including:

Acquiring, according to the value of each variable node of the i-th iteration, a value of each check node of the i-th iteration, and the value of each check node of the i-th iteration satisfies a check Formula:

C _n = ( l signa )) x max((min ψ _η |)-^), 0),

With reference to the third aspect, the first to fourth implementable manners, in the fifth implementable manner, for the first a posteriori probability of the i-th iteration, the ith iteration according to the irregular LDPC decoding The value of the first variable node obtains the value of the first check node of the ith iteration and the value of the first posterior probability of the ith iteration, and further includes:

Obtaining a value of the first posterior probability of the i-1th iteration;

Determining whether the value of the first posterior probability of the i-1th iteration is greater than or equal to 2^-1;

If the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N -1 , replacing the value of the first posterior probability of the i th iteration with 2N-1-1;

With reference to the third aspect, the first achievable manner, and the fifth achievable manner, in the sixth implementation manner, determining the number of rows in the check matrix that does not satisfy the parity check equation includes:

Dividing the check matrix into a predetermined number of matrices by rows;

With reference to the sixth implementation manner, in the seventh implementation manner, for the first sub-matrix, the obtaining the number of rows in the first sub-matrix that does not satisfy the parity check equation includes:

Calculating the ith iteration of the non-zero entry corresponding to each row of the first sub-matrix The symbol product of the value of the variable node;

The present invention provides a data processing device and a data processing method, including: acquiring, according to the value of each variable node of the i-th iteration of the irregular LDPC decoding, the value and location of each check node of the i-th iteration a value of each a posteriori probability of the i-th iteration, wherein the i is a positive integer; determining whether the i is less than a preset number of iterations; and determining that the i is less than the preset number of iterations, determining a check matrix The number of rows of the parity check equation is not satisfied; according to the number of rows in the check matrix that do not satisfy the parity check equation, the value of the check node of the ith iteration, and each of the ith iterations The value of the posterior probability obtains the value of the variable node of the i+1th iteration; if the i is greater than or equal to the preset number of iterations, the value of each posterior probability of the i th iteration is output. In this way, when the system reaches a false balance, the value of the posterior probability, the value of the check node, and the value of the variable node no longer change, the data processing device changes according to the number of rows in the check matrix that do not satisfy the parity check equation. The value of the variable node of i+ 1 iteration, therefore, the value of the changed variable node can change the value of the posterior probability of the i+1th iteration and the value of the check node of the i+1th iteration, thereby breaking the system's false Balance, making the iterative results more accurate, the risk of the wrong platform is reduced, and the error rate generated by the irregular LDPC decoding due to the wrong platform is also reduced accordingly.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

1 is a schematic structural diagram of a data processing device according to an embodiment of the present invention; 2 is a schematic structural diagram of another data processing device according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of still another data processing device according to an embodiment of the present disclosure;

4 is a flowchart of a data processing method according to an embodiment of the present invention; FIG. 5 is a flowchart of another data processing method according to an embodiment of the present invention; FIG. 6 is a first sub-matrix according to an embodiment of the present invention; Schematic diagram

Figure 7 is a comparison of bit error rate and signal to noise ratio of the prior art and the optimization method of the present invention. detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

Embodiment 1

The embodiment of the present invention provides a data processing device 10, as shown in FIG. 1, including: a first obtaining unit 101, configured to acquire an i-th time according to the value of each variable node of the i-th iteration of the irregular LDPC decoding The value of each check node of the iteration and the value of each posterior probability of the i-th iteration, the i being a positive integer.

The first determining unit 102 is configured to determine whether the i is less than a preset number of iterations. The second determining unit 103 is configured to determine, when the first determining unit 102 determines that the i is less than the preset number of iterations, determine the number of rows in the check matrix that do not satisfy the parity check equation.

a second obtaining unit 104, configured to determine, according to the second determining unit 102, the number of rows of the parity check matrix that does not satisfy the parity check equation, and the ith iteration of the first acquiring unit 101 The value of each check node and the value of each posterior probability of the ith iteration acquire the value of each variable node of the i+1th iteration.

The second determining unit 103 is further configured to output, when the first determining unit 102 determines that the i is greater than or equal to the preset number of iterations, output each of the ith iterations The value of a posterior probability.

In this way, when the system reaches a false balance, the value of the posterior probability of the i-th iteration, the value of the check node, and the value of the variable node no longer change, the data processing device does not satisfy the parity check equation according to the check matrix. The number of rows changes the value of the variable node of the i+1th iteration. Therefore, the value of the changed variable node can change the value of the posterior probability of the i+1th iteration and the value of the check node of the i+1th iteration. Thereby breaking the false balance of the system, the iterative result is more accurate, the risk of the wrong platform is reduced, and the error rate generated by the irregular platform by the irregular LDPC decoding is correspondingly reduced.

Further, the second obtaining unit may be specifically configured to:

Determining whether the number of rows in the check matrix determined by the second determining unit 103 that does not satisfy the parity check equation is less than a preset threshold;

Preferably, X is 1.

Further, the second obtaining unit 104 is further configured to:

Further, the first acquiring unit 101 may be specifically configured to:

Obtaining a value of each check node of the i th iteration according to a value of each variable node of the i th iteration, and a value of each check node of the i th iteration satisfies a proof formula:

C _n = ( l signa )) χ max((min ψ _η |) -^), 0) , Where is a constant, i is the number of iterations, « ' is the variable node of the ith iteration, ^c " is the check node of the ith iteration;

Further, for the first posterior probability of the i-th iteration, the first acquiring unit 101 can also be used to:

Obtaining the value of the first posterior probability of the i-ith iteration;

Determining whether the value of the first posterior probability of the i-th iteration is greater than or equal to

2 ^N - ^! -l, where N is the bit width of the posterior probability;

If the value of the first posterior probability of the ilth iteration is greater than or equal to 2 ^N -1, replace the value of the first posterior probability of the ith iteration with 2 ^N -1;

Determining whether the value of the posterior probability of the il iteration is less than or equal to ^^ + l; if the value of the first posterior probability of the il iteration is less than or equal to -2 ^Ν + 1 , then -2 ^N + 1 replaces the value of the first posterior probability of the ith iteration.

Further, the second determining unit 103, as shown in FIG. 2, may include: a dividing subunit 1031, configured to divide the check matrix into a predetermined number of matrices in rows.

The obtaining sub-unit 1032 is configured to obtain the number of rows in each of the sub-matrices that do not satisfy the parity check equation.

The processing sub-unit 1033 is configured to use, as the number of rows in each of the sub-matrices, the number of rows that do not satisfy the parity check equation as the number of rows in the check matrix that does not satisfy the parity check equation.

Further, for the first sub-matrix, the obtaining sub-unit 1032 may be specifically used for:

If the symbol product of the value of the variable node of the i-th iteration corresponding to the w-row non-zero entry in the first sub-matrix is equal to -1, the w is not satisfied in the first sub-matrix The number of rows of the parity check equation, the W being smaller than the number of rows of the first sub-matrix. Embodiment 2

FIG. 3 is a schematic diagram of still another data processing device according to an embodiment of the present invention. The data processing device 20 may include a processor 201, and a memory 202, configured to perform at least one connection between devices in the data processing device 20. The communication bus 203 is used to implement connection and mutual communication between these devices.

The communication bus 203 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Wait. The bus 205 can be divided into an address bus, a data bus, a control bus, and the like.

Memory 202 can include read only memory and random access memory and provides instructions and data to processor 203.

The processor 201 may be a central processing unit (CPU), or a specific integrated circuit (APP), or one or other embodiments configured to implement the embodiments of the present invention. Multiple integrated circuits.

The processor 201 is configured to obtain, according to the value of each variable node of the i-th iteration of the irregular LDPC decoding, the value of each check node of the i-th iteration and each posterior probability of the i-th iteration a value, the i is a positive integer; determining whether the i is less than a preset number of iterations; if it is determined that the i is less than the preset number of iterations, determining a number of rows in the check matrix that do not satisfy the parity check equation; The number of rows in the check matrix that do not satisfy the parity check equation, the value of each check node of the i-th iteration, and the value of each posterior probability of the i-th iteration acquires the i+1th time The value of each variable node of the iteration; if it is determined that the i is greater than or equal to the preset number of iterations, the value of each posterior probability of the i-th iteration is output.

Further, the processor 201 may be specifically configured to determine whether the number of rows in the check matrix that does not satisfy the parity check equation is less than a preset threshold; if the check matrix does not satisfy the row of the parity check equation The number is less than the preset threshold, then the ith iteration The result of subtracting the value of the corresponding check node of the ith iteration from the value of each posterior probability as the value of the corresponding variable node of the (i+1)th iteration; The value of the variable node of the i+1th iteration corresponding to the last non-zero item of each row is increased by X, and the X is greater than -2 ^M and less than

An integer, the M is a bit width of the variable node; if the number of rows in the parity check matrix that does not satisfy the parity check equation is greater than or equal to the preset threshold, each of the ith iterations is The result of the probability of subtraction is subtracted from the value of the corresponding check node of the i-th iteration as the value of the corresponding variable node of the (i+1)th iteration.

Preferably, X is 1.

Further, the processor 201 is further configured to:

The processor 201 may obtain, according to the value of each variable node of the i-th iteration, a value of each check node of the i-th iteration, and the value of each check node of the i-th iteration satisfies a school Test formula:

C _n = ( l signa )) χ max((min _η |)-^),0),

Where is a constant, i is the number of iterations, « ' is the variable node of the ith iteration, and is the check node of the ith iteration;

The processor 201 may use the sum of the value of each variable node of the ith iteration and the value of the corresponding check node of the ith iteration as the value of the corresponding posterior probability of the ith iteration.

Further, the processor 201 may acquire the value of the posterior probability of the i-1th iteration; determine whether the value of the posterior probability of the i-1th iteration is greater than or equal to 2 ^N -1, and the N is after Detecting the bit width of the probability; if the value of the posterior probability of the i-1th iteration is greater than or equal to S^1, replacing the value of each posterior probability of the i-th iteration with 2 ^N -1; Determining whether the value of the posterior probability of the i-1th iteration is less than or equal to -2 ^N + 1; if the value of the posterior probability of the i-1th iteration is less than or equal to

+ l replaces the value of each posterior probability of the ith iteration.

Further, the processor 201 may calculate a symbol product of values of the variable nodes of the ith iteration corresponding to each non-zero entry of the first sub-matrix; and determine each row of the first sub-matrix The value of the variable node of the ith iteration corresponding to the zero term Whether the symbol product is equal to -1; if the symbol product of the value of the variable node of the i-th iteration corresponding to the w-row non-zero entry in the first sub-matrix is equal to -1, then the w is the The number of rows of the parity check equation is not satisfied in a sub-matrix, and the w is smaller than the number of rows of the first sub-matrix.

Embodiment 3

The embodiment of the invention provides a data processing method, which is applied to a data processing device. The specific steps are as shown in FIG. 4, and include:

Step 301: Acquire, according to a value of each variable node of the i-th iteration of the irregular LDPC decoding, a value of each check node of the i-th iteration and a value of each posterior probability of the i-th iteration, i is a positive integer.

Specifically, the data processing device may obtain the value of the check node of the i-th iteration according to the value of each variable node of the i-th iteration, and the value of the check node of the i-th iteration satisfies the checksum Formula:

C _n = ( l signa )) χ max((min _η |) -^),0) ,

The data processing device may use the sum of the value of the variable node of the i-th iteration and the value of the check node of the i-th iteration as the value of each posterior probability of the i-th iteration.

Step 302: Determine whether i is less than a preset number of iterations.

If it is determined that i is less than the preset number of iterations, step 303 is performed; if it is determined that i is not less than the preset number of iterations, step 305 is performed.

Step 303: Determine a number of rows in the check matrix that do not satisfy the parity check equation. The check matrix is a lower triangular matrix composed of 0 and 1, where 0 represents the coefficient of the corresponding unknown quantity of the check equation corresponding to the row of 0 is 0, and 1 represents the check equation corresponding to the row of 1 The coefficient corresponding to the unknown is a non-zero number.

The data processing device may divide the check matrix into a predetermined number of matrices in rows; obtain a number of rows in each of the sub-matrices that do not satisfy the parity check equation; and not satisfy parity in each of the sub-matrices The sum of the number of rows of the equation is taken as the number of rows in the check matrix that do not satisfy the parity check equation.

Specifically, the obtaining, by the data processing device, the non-zero term of each row of the first sub-matrix Corresponding to the symbol product of the value of the variable node of the ith iteration; determining whether the symbol product of the value of the variable node of the ith iteration corresponding to each non-zero item of the first sub-matrix is equal to -1 And if the symbol product of the value of the variable node of the i-th iteration corresponding to the w-row non-zero entry in the first sub-matrix is equal to -1, the w is a parity that is not satisfied in the first sub-matrix The number of rows of the equation is checked, and the w is smaller than the number of rows of the first sub-matrix.

Step 304: Obtain an i+1 according to a value of a row in the check matrix that does not satisfy the parity check equation, a value of each check section of the i-th iteration, and a value of each posterior probability of the i-th iteration. The value of each variable node for the next iteration.

The data processing device can determine whether the number of rows in the check matrix that do not satisfy the parity check equation is less than a preset threshold.

If the number of rows in the parity check matrix that does not satisfy the parity check equation is less than the preset threshold, the data processing device may first subtract the value of each posterior probability of the ith iteration from the corresponding value of the ith iteration. The result of checking the value of the node is taken as the value of the corresponding variable node of the i+1th iteration; and the value of the variable node of the i+1th iteration corresponding to the last non-zero item of each row in the check matrix is added X The X is an integer greater than and less than S^^ - l, and the M is a bit width of the variable node. Preferably, X is 1.

If the number of rows in the parity check matrix that does not satisfy the parity check equation is greater than or equal to a preset threshold, the data processing device may subtract the value of each posterior probability of the ith iteration from the value of the ith iteration. The result of checking the value of the node as the variable node of the i + 1th iteration Value.

Step 305: Output a value of each posterior probability of the i-th iteration.

In this way, when the system reaches a false balance, the value of the posterior probability of the i-th iteration, the value of the check node, and the value of the variable node no longer change, the data processing device does not satisfy the parity check equation according to the check matrix. The number of rows changes the value of the variable node of the i+1th iteration. Therefore, the value of the changed variable node can change the value of the posterior probability of the i+1th iteration and the check node of the i+1th iteration. The value of the system thus breaks the false balance of the system, making the iterative result more accurate, the risk of the wrong platform is reduced, and the error rate generated by the irregular platform of the irregular LDPC decoding is correspondingly reduced.

Further, for the first a posteriori probability of the i-th iteration, the step 301 may further include: the data processing device may acquire the value of the first posterior probability of the i-1th iteration; and determine the i-1th iteration Whether the value of the first posterior probability is greater than or equal to 2 ^N -1, where N is the bit width of the posterior probability; if the value of the first posterior probability of the i-1th iteration is greater than or equal to S^ l, Then replacing the value of the first posterior probability of the ith iteration with 2 ^N -1; determining whether the value of the posterior probability of the i-1th iteration is less than or equal to -2 ^N + 1; The value of the first posterior probability of the second iteration is less than or equal to -2 ^Ν + 1 , and the value of the first posterior probability of the ith iteration is replaced by -2 ^N + 1. In this way, the result of each iteration does not exceed the bit width requirement, which reduces the bit error rate caused by this saturation inversion.

Embodiment 4

The embodiment of the present invention provides a data processing method, which is applied to a data processing device. It is assumed that the non-regular LDPC decoding in the embodiment of the present invention adopts a basic minimum sum algorithm, and the information to be decoded is data information sent by an audio broadcast, specifically The steps are as shown in Figure 5, including:

Step 401: Quantify data to be decoded into an input matrix, and perform step 402. The data information quantized by the data information transmitted by the audio broadcast is stored in a binary code having a bit width M, and the quantized data information is composed into an input matrix [ ^Μ , ^Λ2 , ..., ⁸ ], and the specific quantization process has been performed in the prior art. Very mature, not detailed here.

Step 402, initializing the posterior probability ΑΡΡ and the check value node Cn, performing steps

403. The initialized APP is the input matrix, and the initialized Cn value is 0.

Among them, APP includes APP 1 to APP8, and correspondingly, Cn includes Cnl to Cn8, and variable node Vn includes Vnl to Vn8. The APP value after initialization is the APP value of the 0th iteration, and the Cn value after initialization is the Cn value of the 0th iteration.

Step 403: Determine whether the number of times in the Cn that does not satisfy the parity check equation is less than the second threshold. If yes, go to step 404; if no, go to step 405.

Step 404: Obtain a Vn value of the j+1th iteration according to the APP value of the jth iteration, the Cn value of the jth iteration, and 1 .

The data processing device may subtract each Cn value of the corresponding jth iteration from each APP value of the jth iteration to obtain each Vn of the corresponding jth iteration, and then the last non of each row of the check matrix The Vn value of the j+1th iteration corresponding to the zero term is incremented by one. Where j is an integer greater than and equal to 0.

Step 405: The result of subtracting the Cn of the jth iteration from the APP of the jth iteration as the value of the variable node Vn of the j+1th iteration.

The data processing device may subtract the result of each Cn value of the corresponding jth iteration for each APP value of the jth iteration as each Vn value as the j + 1th iteration.

Step 406: Limit each Vn of the j+1th iteration.

Specifically, the data processing device can determine whether each Vn exceeds the bit width. Assuming that the bit width of Vn is 4, the data processing device can determine whether each Vn value exceeds [-7, 7], if there is more than [7] in Vn. The Vn l value of 7] makes the absolute value of Vnl 7. Further, if Vn l is a number less than -7, Vn l is equal to -7; if Vnl is a number greater than 7, Vnl is equal to 7.

Step 407: Acquire Cn of the j+1th iteration and APP of the j+1th iteration according to Vn of the j+1th iteration.

The data processing device can obtain the corresponding Cn value of the j+1th iteration according to each Vn value of the j+1th iteration, and each Cn value of the j+1th iteration, Cn satisfies the check formula:

C _n ^+l = (Yl sign(V _n ^j+l )) x max((min|r ⁺¹ 1) - β), 0) ,

Where is a constant, i is the number of iterations, ⁺¹ is the variable node of the j + 1 iteration, and C is the check node of the j + 1 iteration. It is worth noting that the value of ^ is based on Set by the decoded data and environment.

The data processing device may use the sum of each Vn value of the j + 1th iteration and the corresponding Cn value of the j + 1th iteration as the corresponding APP value of the j + 1th iteration. For APP

APP1, the data processing device can also optimize the APP1 value of the j+1th iteration. Specifically, the data processing device may obtain the APP1 value of the jth iteration, and determine whether the APP1 value of the jth iteration is greater than or equal to S^l, and if the APPl value of the jth iteration is greater than or equal to S^l, then 2 ^N -1 replaces the APPl value of the j + 1 iteration; and judges whether the APP1 value of the jth iteration is less than or equal to

+ I, If the APPl value of the jth iteration is less than or equal to ^Ν^ + Ι, replace the APPl value of the j + 1 iteration with -2 ^N + 1 . Thus, when the data of the APP value exceeds the bit width range, the method can prevent the occurrence of the saturation inversion of the data and suppress the decoding error.

For example, suppose the APP bit width is 5, correspondingly, the APP default range [-15, 15], and APP1, APP2, APP3, and APP4 in the APP of the jth iteration are 1.2, 3.3, -9, respectively. , -17, where the APP4 value -17 is greater than -15, then the APP4 of the j + 1 iteration is -15.

Step 408: Determine the number of times that the parity check matrix does not satisfy the parity check matrix in the j+1th iteration.

The data processing device can determine that there are many methods in the check matrix that do not satisfy the number of rows of the parity check equation, for example, the overall method, the step method, and the like. Optionally, the overall method specifically includes: the data processing device can directly calculate The symbol product of the Vn value of the j + 1th iteration corresponding to the non-zero entry of each row of the check matrix, determining whether the symbol product is equal to -1, if the check matrix has a symbol product of n rows equal to -1, then n is not The number of rows satisfying the parity check equation; optionally, the step-by-step method specifically includes: the data processing device may divide the check matrix into m sub-matrices by rows, and calculate a symbol product of each row of the first sub-matrices of the m sub-matrices; Whether the symbol product of the Vn value of the j+1th iteration corresponding to each row of the first sub-matrix is equal to -1; if the symbol product of the w-row of the first sub-matrix is equal to -1, the w is the first sub-matrix The number of rows in the parity check equation is not satisfied; the same method can be used to obtain the number of rows in other sub-matrices that do not satisfy the parity check equation, and the data processing device can obtain the unsatisfied parity check equation of each sub-matrix of m sub-matrices. Number of rows , will not be in each submatrix The number of rows satisfying the parity check equation is added, and the number of rows in the check matrix that do not satisfy the parity check equation is obtained.

For example, ^^ sets the first sub-matrix as shown in FIG. 6. Correspondingly, the value of the variable node of the j+1th iteration corresponding to the first row of the first sub-matrix is -1.58 and -1.2, and the symbol is negative. Negative; the value of the variable node of the j + 1 iteration corresponding to the second row is 3.51 and 4.35, the sign is positive and positive; the value of the variable node of the j + 1 iteration corresponding to the third row is -5, -8.31 and 5.19, the symbols are negative, negative, positive; the values of the variable nodes of the j+1th iteration corresponding to the fourth row are -1, 2.22, and 6.8, and the symbols are negative, positive, positive; The values of the variable nodes of j + 1 iterations are 9.1, -3.41, and 4.45, and the symbols are positive, negative, and positive. The symbol product of the value of the variable node of the j+1th iteration corresponding to the first row non-zero entry is 1, and the sign product of the value of the variable node of the j+1th iteration corresponding to the non-zero entry of the second row is 1, The symbol product of the value of the variable node of the j + 1th iteration corresponding to the non-zero item of the third row is 1, and the sign product of the value of the variable node of the j + 1th iteration corresponding to the non-zero item of the fourth row is -1 The symbol product of the value of the variable node of the j + 1th iteration corresponding to the non-zero item of the fifth row is -1, wherein the symbol product of the value of the variable node of the j + 1th iteration corresponding to 2 rows of non-zero entries If it is -1, the number of rows in the first submatrix that do not satisfy the parity check equation is 2.

It is worth noting that the data processing device can determine that the number of rows that do not satisfy the parity check equation can be determined not only by determining the number of rows of the symbol product of each row of the check matrix, but also by determining that each row of the check matrix corresponds to a non-zero entry. Whether the number of negative variable nodes is an odd number, if the Vn value has n rows of data and the negative number is odd, then n is the number of rows that do not satisfy the parity check equation.

Step 409: Determine whether j + 1 is less than a preset number of iterations. If no, step 410 is performed; if yes, step 403 is performed.

Step 410: Output the APP of the j+1th iteration.

It is assumed that the non-regular LDPC decoding adopts a basic minimum sum algorithm. As shown in FIG. 7, the dotted line indicates the relationship between the decoding error rate and the signal-to-noise ratio of the data information transmitted by the prior art audio broadcast, wherein, the quantization The bit width is 5 bits, the bit width of Cn is 6 bits, and the bit width of APP is 8 bits, which is abbreviated as prior art; the solid line indicates the translation of data information transmitted by the audio broadcast using the method of the embodiment of the present invention. Code error rate And a signal-to-noise ratio curve, wherein the bit width of the data information transmitted by the audio broadcast is 4 bits, the bit width of Cn is 4 bits with a sign, and the bit width of the APP is 5 bits, which is abbreviated as the optimization method of the present invention. 2; a chain line indicates a relationship between a decoding error rate and a signal-to-noise ratio of a data signal transmitted by an audio broadcast using only a method of reducing a bit error rate generated by saturation inversion in the embodiment of the present invention, wherein The bit width of the data information transmitted by the audio broadcast is 4 bits, the bit width of Cn is 4 bits with a sign, and the bit width of the APP is 5 bits, which is abbreviated as the optimization method 2 of the present invention. Before the signal-to-noise ratio is 14 decibels, the error rate of the prior art is lower than the error rate of the optimization method 1 + 2 of the present invention, between 14 decibels and 14.5 decibels, and the signal-to-noise ratio is between 14 decibels and 14.5 decibels. The error rate of the optimization method 1 + 2 of the present invention is similar to the error rate of the prior art; before the signal to noise ratio of 13.5 dB, the error rate of the optimization method 1 + 2 of the present invention and the optimization method 2 of the present invention are similar, The signal-to-noise ratio is 13.5 dB to 15.5 dB, and the error rate of the optimization method 1 + 2 of the present invention is far lower than the error rate of the optimization method 2 of the present invention, and the value of the posterior probability and the variable node of the optimization method 1 + 2 of the present invention The bit width of the value is 5 bits, which saves 37.5% of resources compared with the prior art; the value of the check node of the prior art method has a bit width of 6 bits, and the check node of the optimization method 1 + 2 of the present invention The bit width of the value is 4 bits, which saves 33.3% of resources compared with the prior art. The sum of the minimum value, the second smallest value, the minimum position and the bit width of the check node of the prior art method is 18, The minimum value, the second smallest value, the minimum position, and the check node of the method of the embodiment The sum of the bit widths of the symbols is 14, which saves 22.2% of resources compared with the prior art. In summary, the method provided in this embodiment reduces the bit width, and the signal-to-noise ratio loses 0.2 decibels while saving 30% of resources. At the same time, the risk of the wrong platform remains unchanged.

An embodiment of the present invention provides a data processing method, including: obtaining, according to a value of each variable node of the jth iteration of the irregular LDPC decoding, a value of each check node of the jth iteration and a jth iteration a value of each a posteriori probability, the j is a positive integer; determining whether the j is less than a preset number of iterations; if it is determined that the j is less than the preset number of iterations, determining that the check matrix does not satisfy the parity check The number of rows of the equation; obtaining according to the number of rows in the check matrix that do not satisfy the parity check equation, the value of the check node of the jth iteration, and the value of each posterior probability of the jth iteration a value of a variable node of the j+1th iteration; if the j is greater than or equal to the preset number of iterations, outputting the jth iteration The value of each posterior probability. In this way, when the system reaches a false balance, the value of the posterior probability of the jth iteration, the value of the check node, and the value of the variable node no longer change, the data processing device does not satisfy the parity check equation according to the check matrix. The number of rows changes the value of the variable node of the j + 1th iteration, so the value of the changed variable node can change the value of the posterior probability of the j + 1 iteration and the check node of the j + 1 iteration The value of the system thus breaks the false balance of the system, making the iterative result more accurate, the risk of the wrong platform is reduced, and the error rate generated by the irregular platform for the irregular LDPC decoding is correspondingly reduced.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

It should be noted that the sequence of the steps of the data processing method provided by the embodiment of the present invention may be appropriately adjusted, and the steps may also be correspondingly increased or decreased according to the situation, and any person skilled in the art may be within the technical scope disclosed by the present invention. Methods that can be easily conceived of variations are encompassed within the scope of the present invention and therefore will not be described again.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the appended claims.

Claims

claims

1. A data processing equipment, characterized in that it includes:

A first acquisition unit, configured to acquire the value of each check node of the i-th iteration and the value of each variable node of the i-th iteration of the irregular low-density parity check code LDPC decoding. The value of each posterior probability of i iterations, where i is a positive integer;

The first determination unit is used to determine whether the i is less than the preset number of iterations; the second determination unit is used to determine the check matrix when the first determination unit determines that the i is less than the preset number of iterations. The number of rows in that do not satisfy the parity check equation;

The second acquisition unit is configured to determine the number of rows in the check matrix that do not satisfy the parity check equation according to the number of rows in the check matrix determined by the second determination unit, and each check value of the i-th iteration obtained by the first acquisition unit. The value of each variable node of the i+1th iteration is obtained from the value of the posterior probability of the i-th iteration and the value of the posterior probability of the i-th iteration;

The second determination unit is also configured to output the value of each posterior probability of the i-th iteration when the first determination unit determines that i is greater than or equal to the preset number of iterations.

2. The data processing device according to claim 1, characterized in that the second acquisition unit is specifically used for:

Determine whether the number of rows in the check matrix determined by the second determination unit that do not satisfy the parity check equation is less than a preset threshold;

If the number of rows in the check matrix that do not satisfy the parity check equation is less than the preset threshold, then subtract the corresponding value of the i-th iteration from the value of each posterior probability of the i-th iteration. The result of the value of the check node is used as the value of the corresponding variable node of the i+1th iteration;

Add X to the value of the variable node of the i+1th iteration corresponding to the last non-zero item in each row of the check matrix, where X is an integer greater than -2 ^M and less than SM^-I, M is the bit width of the variable node.

3. The data processing device according to claim 2, wherein X is 1.

4. Data processing equipment according to any one of claims 1 to 3, It is characterized in that the second acquisition unit is also used to:

If the number of rows in the check matrix that do not satisfy the parity check equation is greater than or equal to the preset threshold, then subtract the value of each posterior probability of the i-th iteration from the value of the i-th iteration. The result of the value of the corresponding check node is used as the value of the corresponding variable node of the i+1th iteration.

5. The data processing device according to claim 4, characterized in that the first acquisition unit is specifically used for:

The value of each check node of the i-th iteration is obtained according to the value of each variable node of the i-th iteration, and the value of each check node of the i-th iteration satisfies the check formula:

C[ = ( l sign(V _n ' )) x max((min | |) - β), 0) ,

Among them, is a constant, i is the number of iterations, is the variable node of the i-th iteration, and C is the check node of the i-th iteration;

The sum of the value of each variable node of the i-th iteration and the value of the corresponding check node of the i-th iteration is used as the value of the corresponding posterior probability of the i-th iteration.

6. The data processing device according to any one of claims 1 to 5, characterized in that, for the first posterior probability of the i-th iteration, the first acquisition unit is also used to:

Get the value of the first posterior probability of the i-1th iteration;

Determine whether the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N - ^! -1, where N is the bit width of the posterior probability;

If the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N -1, then use 2 ^N -1 to replace the value of the first posterior probability of the i-th iteration;

Determine whether the value of the posterior probability of the i-1th iteration is less than or equal to ^N^ + I; if the value of the first posterior probability of the i-1th iteration is less than or equal to -2 ^N + 1 , then use - 2 ^N · ¹ + 1 to replace the value of the first posterior probability of the i-th iteration.

7. The data processing device according to any one of claims 1 to 6, characterized in that the second determination unit includes:

Split sub-units, used to divide the check matrix into a preset number of matrices by row; Obtain sub-units for obtaining the number of rows in each of the sub-matrix that do not satisfy the parity check equation;

A processing subunit, configured to use the sum of the number of rows in each sub-matrix that does not satisfy the parity check equation as the number of rows in the check matrix that does not satisfy the parity check equation.

8. The data processing device according to claim 7, characterized in that, for the first sub-matrix, the acquisition sub-unit is specifically used for:

Calculate the signed product of the values of the variable nodes of the i-th iteration corresponding to the non-zero entries in each row of the first sub-matrix;

Determine whether the signed product of the values of the variable nodes of the i-th iteration corresponding to the non-zero entries in each row of the first sub-matrix is equal to - 1;

If the sign product of the values of the variable nodes of the i-th iteration corresponding to w rows of non-zero entries in the first sub-matrix is equal to - 1, then w is the value of the variable node in the first sub-matrix that does not satisfy the parity check. The number of rows of the empirical equation, and the w is smaller than the number of rows of the first sub-matrix.

9. A data processing equipment, characterized by including:

A processor, configured to obtain the value of each check node of the i-th iteration and each posterior of the i-th iteration according to the value of each variable node of the i-th iteration of irregular LDPC decoding. The value of probability, the i is a positive integer;

The processor is also used to determine whether the i is less than the preset number of iterations; the processor is also used to determine that the parity in the check matrix does not satisfy if it is determined that the i is less than the preset number of iterations. The number of rows of the check equation;

The processor is further configured to calculate the number of rows in the check matrix that do not satisfy the parity check equation, the value of each check node of the i-th iteration, and the value of each check node of the i-th iteration. The value of the empirical probability is used to obtain the value of each variable node of the i+1th iteration;

The processor is further configured to output the value of each posterior probability of the i-th iteration if it is determined that i is greater than or equal to the preset number of iterations.

10. The data processing equipment according to claim 9, characterized in that the processor is specifically used for:

Determine whether the number of rows in the check matrix that do not satisfy the parity check equation is less than a preset threshold; If the number of rows in the check matrix that do not satisfy the parity check equation is less than the preset threshold, then subtract the corresponding value of the i-th iteration from the value of each posterior probability of the i-th iteration. The result of the value of the check node is used as the value of the corresponding variable node of the i+1th iteration;

11. The data processing equipment according to claim 10, characterized in that, the X is 1.

12. The data processing device according to any one of claims 9 to 11, characterized in that the processor is also used for:

13. The data processing device according to claim 12, characterized in that the processor is specifically used for:

14. The data processing equipment according to any one of claims 9 to 13, characterized in that,

The processor is also used to:

Get the value of the first posterior probability of the i-1th iteration; Determine whether the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N - ^! -l, where N is the bit width of the posterior probability;

15. The data processing device according to any one of claims 9 to 14, characterized in that the processor is specifically used for:

Divide the check matrix into a preset number of matrices by row;

Get the number of rows in each of said sub-matrices that do not satisfy the parity check equation;

The sum of the number of rows in each sub-matrix that does not satisfy the parity check equation is taken as the number of rows in the check matrix that does not satisfy the parity check equation.

16. The data processing device according to claim 15, characterized in that the processor is specifically used for:

Determine whether the sign product of the value of the variable node of the i-th iteration corresponding to the non-zero entry in each row of the first sub-matrix is equal to -1;

If there are w rows of non-zero entries in the first sub-matrix and the sign product of the values of the variable nodes of the i-th iteration corresponding to it is equal to -1, then w is the value of the variable node in the first sub-matrix that does not satisfy the parity check. The number of rows of the empirical equation, and the w is smaller than the number of rows of the first sub-matrix.

17. A data processing method, characterized by including:

Obtain the value of each check node of the i-th iteration and the value of each posterior probability of the i-th iteration according to the value of each variable node of the i-th iteration of irregular LDPC decoding, so Said i is a positive integer;

Determine whether the i is less than the preset number of iterations;

If it is determined that the i is less than the preset number of iterations, determine the number of rows in the check matrix that do not satisfy the parity check equation; The i+1th is obtained based on the number of rows in the check matrix that do not satisfy the parity check equation, the value of each check node of the i-th iteration, and the value of each posterior probability of the i-th iteration. The value of each variable node for iterations;

If it is determined that i is greater than or equal to the preset number of iterations, then output the value of each posterior probability of the i-th iteration.

18. The data processing method according to claim 17, characterized in that, the value of each check node of the i-th iteration is based on the number of rows in the check matrix that do not satisfy the parity check equation. and the value of each posterior probability of the i-th iteration to obtain the value of each variable node of the i+1-th iteration, including:

Determine whether the number of rows in the check matrix that do not satisfy the parity check equation is less than a preset threshold;

19. The data processing method according to claim 18, wherein X is 1.

20. The data processing method according to any one of claims 17 to 19, characterized in that, according to the number of rows in the check matrix that do not satisfy the parity check equation, the number of rows in the i-th iteration The value of each check node and the value of each posterior probability of the i-th iteration are used to obtain the value of each variable node of the i+1-th iteration, which also includes:

21. The data processing method according to claim 20, characterized in that: Obtaining the value of each check node of the i-th iteration and the value of each posterior probability of the i-th iteration according to the value of each variable node of the i-th iteration of irregular LDPC decoding, including: according to the above The value of each variable node of the i-th iteration obtains the value of each check node of the i-th iteration, and the value of each check node of the i-th iteration satisfies the check formula:

Among them, is a constant, i is the number of iterations, is the variable node of the i-th iteration, C _n ' is the check node of the i-th iteration;

22. The data processing method according to any one of claims 17 to 21, characterized in that, for the first posterior probability of the i-th iteration, the i-th iteration of the decoding according to irregular LDPC is The value of the first variable node obtains the value of the first check node of the i-th iteration and the value of the first posterior probability of the i-th iteration, and also includes:

Get the value of the first posterior probability of the i-1th iteration;

Determine whether the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N - ' - 1 , where N is the bit width of the posterior probability;

If the value of the first posterior probability of the i-1th iteration is greater than or equal to 2 ^N - 1, then use 2 ^N - 1 to replace the value of the first posterior probability of the i-th iteration;

23. The data processing method according to any one of claims 17 to 22, wherein determining the number of rows in the check matrix that do not satisfy the parity check equation includes: converting the check matrix into The rows are divided into a preset number of matrices;

24. The data processing method according to claim 23, characterized in that: The first sub-matrix, said obtaining the number of rows in the first sub-matrix that does not satisfy the parity check equation, includes: