WO2015144930A1

WO2015144930A1 - High-resolution patterning of multiple layers side by side

Info

Publication number: WO2015144930A1
Application number: PCT/EP2015/056823
Authority: WO
Inventors: Atsushi Nakamura; Tung Huei KE; Pawel Malinowski
Original assignee: Imec Vzw; Fujifilm Corporation
Priority date: 2014-03-28
Filing date: 2015-03-28
Publication date: 2015-10-01
Also published as: KR20160138966A; TW201537639A; CN106133935B; JP2017510951A; JP6585614B2; CN106133935A; KR102290616B1; TWI640041B

Abstract

A method is provided for fabricating a device comprising a first patterned device layer (31) at a first location and a second patterned device layer (32) at a second location on a single substrate. The method comprises: depositing a first interlayer (21) on the substrate; patterning the first interlayer (21), thereby removing the first interlayer at the first location; depositing a first device layer (31); depositing a second interlayer (22); patterning the second interlayer and the underlying layers, thereby removing the second interlayer and the underlying layers at the second location; depositing a second device layer (32); and afterwards patterning the first device layer and the second device layer to form the first patterned device layer at the first location and the second patterned device layer at the second location.

Description

High-resolution patterning of multiple layers side by side

Field of the invention

The invention relates to the field of high-resolution patterning. More specifically it relates to methods for high-resolution patterning of multiple layers side by side, and for high resolution patterning of multiple layer stacks side by side. For example, the present invention may relate to high-resolution methods for forming non-overlapping patterns of different organic semiconductor layers and for forming non-overlapping patterns of layer stacks comprising at least one organic semiconductor layer.

Background of the invention

For the fabrication of displays and imagers based on organic semiconductors, a reliable and high resolution patterning method is needed. Preferably, a patterning method would also allow the patterning of different organic semiconductor layers or different layer stacks side by side on a substrate, e.g. for achieving multicolor emission in an OLED (Organic Light Emitting Diode) display or multicolor sensitivity in an imager.

Several patterning methods are known in the art. For example, a patterning technique commonly used in fabrication processes for organic electronic devices is based on shadow masking technology. The organic semiconductors can be patterned directly during evaporation by using a fine metal mask as a shadow mask in a vacuum system. Such technique allows the defining of features with a size in the order of 30 micrometer or higher. However, it is a disadvantage of such approach that it does not allow very accurate alignment. It is a further disadvantage of shadow masking technology that it requires rather cumbersome hardware maintenance, and that it is difficult to scale up to large substrate sizes.

The use of additive techniques such as inkjet printing is also known in the art. This may offer a similar resolution as shadow masking. However, additive techniques are not well suited for complex layer stacks, e.g. multilayer stacks. For example, accurate alignment may be difficult.

Several other patterning processes are also known in the art, such as for example techniques based on self-assembly, e.g. comprising a spin-casting process on a pre-patterned substrate. However, such process requires a careful selection of repelling/attracting patterning materials for a specific organic active layer. Another example of an emerging patterning approach is laser-induced forward transfer (LIFT). However, in such process, the resolution is limited to 5 to 10 micrometer and the thermal transfer process may degrade the electrical characteristics of the organic device.

A promising technique to achieve a pattern resolution below 10 micrometer in a reproducible way and on large wafer sizes is photolithography. However, using a photolithographic process in combination with organic semiconductors is not straightforward, because most of the solvents used within standard photoresists, as well as the solvents used for resist development and/or resist stripping may dissolve or damage the organic layers.

Lithographic patterning of organic layers may be achieved using orthogonal processing, wherein fluorinated photoresists are used. This approach offers micrometer resolutions with standard photolithography equipment. For example, in US 2013/0236999 a method for fabricating a multicolor OLED device using orthogonal processing is described, wherein multiple light-emitting layers or layer stacks, each emitting a different color of light, are deposited and patterned side by side on a single substrate to form multiple light emitting elements. However, it is a disadvantage of this approach that it is costly to manufacture the fluorinated products, and also the disposal of such products can be expensive and troublesome.

In US 2012/0252150, a method of manufacturing an organic electroluminescence display is described wherein the different organic electroluminescent elements corresponding to different colors are formed by photolithography, using a standard, conventional photoresist. This method may for example use a first mask layer comprising a stack of a water-soluble material, a material which is insoluble in the resist liquids as a second mask layer and a photoresist layer. In this way, an underlying organic compound layer may be patterned with a reduced risk of being dissolved or damaged by a liquid used during photolithographic patterning. The first mask layer and the second mask layer may be left and used to protect the patterned organic compound layer in further steps, such as steps for forming other patterned organic compound layers.

Summary of the invention

It is an object of embodiments of the present invention to provide methods for forming non-overlapping patterns of multiple layers, such as organic semiconductor layers, and/or for forming non-overlapping patterns of different layer stacks side by side on a substrate by means of photolithography.

The above objective is accomplished by a method and device according to the present invention.

It is an advantage of embodiments of the present invention that conventional photoresist materials can be used.

It is an advantage of embodiments of the present invention and that the risk of damage to or degradation of the layers or layer stacks as a result of a photolithographic process is low, e.g. as compared to known methods in the art.

Embodiments of the present invention may advantageously be used in fabrication processes for organic electronic devices requiring high resolution, such as for example high definition full color displays without color filters, high definition full color photodetectors and photodetector arrays without color filters, or smart pixels or pixel arrays with multiple integrated organic photodetector and organic light emitting diode sub-pixel elements.

The present invention relates to a method for fabricating a device comprising a first patterned device layer at a first location, e.g. at first locations, and a second patterned device layer at a second location, e.g. at second locations, on a substrate, e.g. on a single substrate, e.g. on a contiguous substrate. The method comprises: depositing a first interlayer on the substrate; patterning the first interlayer, thereby removing the first interlayer at the first location, e.g. at the first locations; depositing a first device layer; depositing a second interlayer; patterning the second interlayer and the underlying layers, thereby removing the second interlayer and the underlying layers at the second location, e.g. at the second locations; depositing a second device layer; and afterwards patterning the first device layer and the second device layer to form the first patterned device layer at the first location, e.g. at the first locations, and the second patterned device layer at the second location, e.g. at the second locations.

A method of the present invention may further comprise, before patterning the first device layer and the second device layer: depositing a third interlayer; patterning the third interlayer and the underlying layers, thereby removing the third interlayer and the underlying layers at a third location, e.g. at third locations; and depositing a third device layer. These steps may be repeated for forming additional patterned device layers at additional corresponding locations. All device layers are patterned afterwards, i.e. patterning of the device layers is done in a single patterning process after all device layers have been deposited.

In embodiments of the present invention the first device layer may be a stack of at least two layers and/or the second device layer may be a stack of at least two layers and/or the third device layer may be a stack of at least two layers and/or any additional device layers may be a stack of at least two layers.

The first device layer, the second device layer, the third device layer, and any additional device layer may for example comprise an electroluminescent layer, a photosensitive layer or a semiconductor layer. For example, the first device layer may comprise a first organic semiconductor layer, the second device layer may comprise a second organic semiconductor layer and the third device layer may comprise a third organic semiconductor layer. The first organic semiconductor layer, the second organic semiconductor layer and the third organic semiconductor layer may have substantially distinct material compositions, e.g. to achieve light sensitivity or light emission in different light spectra.

In embodiments of the present invention, the first interlayer, the second interlayer, the third interlayer and any additional interlayer or further interlayer may be a water-soluble layer or an alcohol- soluble layer. The interlayers may contain a polymer such as for example polyvinyl alcohol, polyvinyl pyrrolidone, water-soluble cellulose, polyethylene glycol, polyglycerin or pullullan, the present disclosure not being limited thereto. The interlayers may further contain a solvent, the solvent comprising water and/or an alcohol. The alcohol may for example be an alcohol without alkoxy groups, such as for example isopropyl alcohol, the present disclosure not being limited thereto. The alcohol may for example be a water-soluble alcohol. The solvent may contain only water, only an alcohol, or a mixture of water and a water-soluble alcohol.

In embodiments of the present invention, the step of patterning the first device layer, the second device layer and the third device layer may comprise: providing a patterned photoresist layer covering the first location, e.g. the first locations, the second location, e.g. the second locations, and the third location, e.g. the third locations; performing an etching step using the patterned photoresist layer as a mask, the etching being continued till exposure of the substrate; and dissolving the first interlayer, the second interlayer and the third interlayer in water or in alcohol. The patterned photoresist layer may be removed before dissolving the first interlayer, the second interlayer and the third interlayer. As an alternative to continuing the etching till exposure of the substrate, the etching may be continued till exposure of the first interlayer or till removal of at least part of the first device layer at locations different from the first locations.

In embodiments of the present invention, the step of patterning the first device layer, the second device layer and the third device layer may comprise: depositing a further interlayer; performing an etching step till the first interlayer is exposed; and dissolving the first interlayer in water or in an alcohol. As an alternative to continuing the etching till exposure of the first interlayer, the etching may be continued till removal of at least part of the first device layer at locations different from the first locations.

In embodiments of the present invention, the step of patterning the first device layer, the second device layer and the third device layer may comprise: depositing a further interlayer; providing a patterned photoresist layer covering the first location, the second location and the third location, e.g. covering the first locations, the second locations and the third locations; performing an etching step using the patterned photoresist layer as a mask, the etching being continued till exposure of the substrate; and dissolving the first interlayer, the second interlayer, the third interlayer and the further interlayer in water or in an alcohol. The patterned photoresist layer may be removed before dissolving the first interlayer, the second interlayer, the third interlayer and the further interlayer. As an alternative to continuing the etching till exposure of the substrate, the etching may be continued till exposure of the first interlayer or till removal of at least part of the first device layer at locations different from the first locations.

In embodiments of the present invention, the step of patterning the first device layer, the second device layer and the third device layer may comprise: depositing a further interlayer; providing a patterned photoresist layer covering the first location, the second location and the third location, e.g. covering the first locations, the second locations and the third locations; performing a first etching step using the patterned photoresist layer as a mask, the first etching step being continued till exposure of the substrate; removing the patterned photoresist layer; performing a second etching step till the second interlayer is exposed; and dissolving the first interlayer and the second interlayer in water or in an alcohol. As an alternative to continuing the second etching till exposure of the second interlayer, the second etching may be continued till exposure of the first interlayer or till removal of at least part of the first device layer at locations different from the first locations.

A method of the present invention may advantageously be used in a process for fabricating organic semiconductor based devices and circuits having patterns of different organic materials or different material stacks side by side on a substrate, such as for example multi-color organic photodetectors (OPD), or multi-color organic light-emitting diodes (OLED) or organic smart pixels comprising at least one OLED sub-pixel element and at least one OPD sub-pixel element, including arrays of such devices.

A method of the present invention may for example be used in a fabrication process for high definition multi-color OLED displays or high definition multi-color photodetector arrays without color filters, allowing obtaining higher resolutions than with the currently used shadow masking technology. For example, a method of the present disclosure may also be used for patterning of micron sized or sub- micron sized pixel arrays of organic CMOS imagers.

In known processes for photolithographic patterning of organic semiconductors, each set of sub-pixel elements (such as sub-pixel elements representing a single color in a multicolor display or imager) is patterned one after another. The photolithographic patterning of a sub-pixel element is performed directly after deposition of the corresponding electroluminescent layer stack. It is a disadvantage of such known approach that the sensitive organic semiconductor layer or layer stack is exposed multiple times to the products used during photolithography (such as photoresist, developer, resist stripper). Even though these products can be made benign to the materials underneath, deposition and stripping of these products numerous times can pose a risk of degradation or damage of the underlying layers. Furthermore, during local removal of the electroluminescent layer stack the side walls of the already patterned sub-pixel elements are exposed to an environment that may cause degradation or damage.

It is an advantage of embodiments of the present disclosure that during photolithographic patterning each device layer may be protected at all times at locations where that device layer is part of the final device. Therefore, methods according to embodiments of the present disclosure can advantageously be used for patterning device layers that may be degraded or negatively affected by the products used during photolithography, such as for example organic device layers. In methods of the present disclosure, direct contact between such products and the device layers may be avoided.

It is an advantage of embodiments of the present disclosure that conventional photolithographic products (photoresists, developers), i.e. photolithographic products already used in the microelectronics industry, may be used. It is an advantage of embodiments of the present disclosure that there is no need for using expensive products such as fluorinated photoresists.

It is an advantage of a method according to embodiments of the present disclosure that it is up- scalable and that it is compatible with existing semiconductor process lines.

It is an advantage of a method according to embodiments of the present disclosure that the highest processing temperature used for patterning of the device layers may be below 150°C. Therefore the method may be used on flexible foil substrates such as for example on a polyethylene naphthalate (PEN) foil or a polyethylene terephthalate (PET) foil, thus enabling the fabrication of flexible organic devices and circuits with high resolution.

It is an advantage of a method according to embodiments of the present disclosure that it may be cost effective and well controllable.

Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Brief description of the drawings

FIG. 1 illustrates a first step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 2 illustrates a second step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 3 illustrates a third step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 4 illustrates a fourth step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 5 illustrates a fifth step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 6 illustrates a sixth step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 7 illustrates a seventh step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 8 illustrates a eight step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 9 illustrates a ninth step of a sequence of process steps of a method according embodiments of the present invention.

FIG. 10 illustrates a first process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on photolithography with a benign photoresist system. FIG. 11 illustrates a second process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on photolithography with a benign photoresist system. FIG. 12 illustrates a third process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on photolithography with a benign photoresist system. FIG. 13 illustrates a fourth process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on photolithography with a benign photoresist system. FIG. 14 illustrates, in cross section, a patterned photoresist layer extending beyond the edges of an opening made in an interlayer, in accordance with embodiments of the present invention.

FIG. 15 illustrates, in top view, a patterned photoresist layer extending beyond the edges of an opening made in an interlayer, in accordance with embodiments of the present invention.

FIG. 16 illustrates a first process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer.

FIG. 17 illustrates a second process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer.

FIG. 18 illustrates a third process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer.

FIG. 19 illustrates a first process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and a single etching step.

FIG. 20 illustrates a second process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and a single etching step.

FIG. 21 illustrates a third process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and a single etching step.

FIG. 22 illustrates a first process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and two etching steps.

FIG. 23 illustrates a second process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and two etching steps.

FIG. 24 illustrates a third process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and two etching steps.

FIG. 25 illustrates a fourth process step of a method for removing superfluous material in accordance with embodiments of the present invention, based on the use of a further interlayer combined with photoresist patterning and two etching steps.

Any reference signs in the claims shall not be construed as limiting the scope of the present invention.

In the different drawings, the same reference signs refer to the same or analogous elements. The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.

Detailed description of illustrative embodiments The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.

Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.

In the description provided herein, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Methods of the present disclosure may advantageously be used for high-resolution patterning of layers or layer stacks comprising materials that degrade under the influence of products used during conventional photolithography, such as photoresists, developers and strippers. Such materials include for example organic semiconductors, organic dielectrics, quantum dots, ionic conductors, organic tissue, reactive metals or salts.

In the further description, methods of the present disclosure are described for examples wherein the device layer or device layer stack comprises an organic semiconductor material. In the further description and in the claims, 'device layer' may refer to a single layer as well as to a stack of at least two layers.

The present invention relates to a method for fabricating a device comprising a first patterned device layer at a first location, e.g. at first locations, and a second patterned device layer at a second location, e.g. at second locations, on a substrate. The first location and the second location may be different locations on the substrate such that the first patterned device layer and the second patterned device layer in the fabricated device do not overlap, e.g. are arranged side by side. The method comprises depositing a first interlayer on a substrate, and patterning the first interlayer such as to remove the first interlayer at the first location and depositing a first device layer. The method further comprises depositing a second interlayer, and patterning the second interlayer and the underlying layers such as to remove the second interlayer and the underlying layers at the second location. The method also comprises depositing a second device layer and afterwards patterning the first device layer and the second device layer to form the first patterned device layer at the first location and the second patterned device layer at the second location.

Process steps of an exemplary method in accordance with the present invention are schematically illustrated in FIG. 1 to FIG. 9. As an example, process steps for the fabrication of a device, e.g. an OLED device, comprising a first patterned device layer at a first location on a substrate, e.g. for providing a first color, and a second patterned device layer at a second location on the substrate, e.g. for providing a second color, are shown. This exemplary process further comprises a third patterned device layer, e.g. at a third location on the substrate, e.g. for providing a third color. Thus the exemplary process particularly may form part of a manufacture process for fabricating a three-color OLED. The figures show cross sections corresponding to a single OLED comprising three sub-pixels.

However, it shall be understood that an OLED device may comprise a large number of such pixels, each comprising three such sub-pixels, the pixels being for example arranged in a pixel grid or array. A process according to embodiments of the present invention can thus be used for fabricating a plurality of three-color OLEDs, corresponding to a plurality of pixels, on a single substrate, such as for example an array of three-color OLEDs, e.g. arranged in a plurality of rows and a plurality of columns. More in general, a process according to embodiments can be used for the formation of patterned layer stacks with different properties side by side, e.g. for providing different colors in an OLED or in an OPD or for providing various functionalities in a circuit, and for the fabrication of arrays of such patterned multilayer stacks.

In the present description, a pixel refers to a single image point in an imager or a display. In an imager or a display a plurality of pixels is typically arranged in rows and columns. Each pixel may be composed of sub-pixels, each sub-pixel for example corresponding to a different color. Each sub-pixel comprises a pixel element, for example a light emitting element such as an OLED or a photo-detecting element such as an organic photodetector.

FIG. 1 schematically shows a substrate 10 which may have, e.g. provided on a surface thereof, a first bottom electrode 11, a second bottom electrode 12 and a third bottom electrode 13. For example, at least a first layer may be performed on the substrate to provide electrical connections to the device layers to be provided thereon in accordance with embodiments of the present invention. For example, in the final device, e.g. in the finished OLED device, the first bottom electrode 11 may be a bottom electrode of a first sub-pixel, e.g. corresponding to a first color functionality, the second bottom electrode 12 may be a bottom electrode of a second sub-pixel, e.g. corresponding to a second color, and the third bottom electrode 13 may be a bottom electrode of a third sub-pixel, e.g. corresponding to a third color. At the edges of the bottom electrodes an edge cover layer (not illustrated) may be present to provide protection against shorts and leakage. Such edge cover layer can be made of an organic or inorganic material with good electrical insulating properties. The substrate 10 may be a glass substrate or a flexible foil substrate or any other suitable substrate known by the person skilled in the art. The bottom electrodes may for example comprise ITO (Indium Tin Oxide), Mo, Ag, Au, Cu, a conductive polymer such as for example PEDOT:PSS (poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate), or a conductive CNT (carbon nanotube) or graphene layer, the present disclosure not being limited thereto.

The exemplary method according to embodiments of the present invention comprises depositing a first interlayer 21 on the substrate 10. Thus, on the substrate 10 a first interlayer 21 is provided, as shown in FIG. 1. The first interlayer 21 may be a layer that does not cause degradation of a device layer or device layer stack to be provided further in the process. The first interlayer can for example be a water-based material or an alcohol-based material. The first interlayer may contain a polymer such as for example polyvinyl alcohol, polyvinyl pyrrolidone, water-soluble cellulose, polyethylene glycol, polyglycerin or pullullan. The first interlayer may further contain a solvent comprising water and/or an alcohol. The alcohol may for example be an alcohol without alkoxy groups, such as for example isopropyl alcohol. The alcohol may for example be a water-soluble alcohol. The solvent may contain only water, only an alcohol, or a mixture of water and a water-soluble alcohol. The thickness of the first interlayer 21 may for example be in the range between 100 nm and 6000 nm, e.g. between 500 nm and 2000 nm, the present disclosure not being limited thereto.

The exemplary method according to embodiments of the present invention comprises patterning the first interlayer 21, thereby removing the first interlayer 21 at the first location. For example, this step of patterning the first interlayer 21 may be following the step of depositing a first interlayer 21 on the substrate 10. As illustrated in FIG. 2, the first interlayer 21 is patterned, e.g. such as to make a first opening 1 through the first interlayer 21 and exposing the first bottom electrode 11. The first interlayer 21 may be patterned by conventional photolithography, followed by dry etching (e.g. using an O2, SF6 or CF6 plasma) and/or wet etching. Preferably a solvent-developable photoresist is used for patterning the first interlayer 21. However, the present disclosure is not limited thereto and other photoresists may be used. The first opening 1 may have any suitable shape, such as for example a rectangular shape or a circular shape, the present disclosure not being limited thereto. The first bottom electrode 11 may be fully exposed or partially exposed, e.g. it may be almost fully exposed, meaning that only the edges of the first bottom electrode 1 1 remain covered by the first interlayer 21. After this step, the second bottom electrode 12 and the third bottom electrode 13 may remain covered by the first interlayer 21.

In a next step, illustrated in FIG. 3, a first device layer 31 is deposited, e.g. over substantially the entire substrate, e.g. at least where the first interlayer 21 was removed at the first location. In this way, the first device layer 31 may be brought into contact with the first bottom electrode 11. In the example described here, the first device layer 31 may correspond to a first color (first sub-pixel), e.g. the first device layer may comprise an organic semiconductor material suitable for emitting light of a first color, e.g. emitting light having a first color spectrum.

In embodiments according to the present invention, e.g. in the example described here relating to a three-color OLED, the first device layer 31 may for example be a layer stack, e.g. comprising a hole injection layer, an electron blocking layer, a hole transport layer, an electroluminescent organic layer, an electron transport layer, a hole blocking layer and/or an electron injection layer, the present disclosure not being limited thereto. The first device layer 31 may comprise at least a first electroluminescent organic layer. The first device layer 31 may be deposited by solution processing (e.g. spin-coating, printing, spray-coating, slot die coating and/or blade coating), gas phase deposition (e.g. CVD or OVPD) or vacuum deposition (e.g. evaporation).

After deposition of the first device layer 31, a second interlayer 22 is deposited, e.g. on the first device layer 31, as shown in FIG. 4, for example by spin-coating, slot-die coating, dip-coating, printing or blade coating, the present disclosure not being limited thereto. The second interlayer 22 may be a layer that does not cause degradation of the first device layer 31 and of a device layer or device layer stack to be provided further in the process. It may protect the first device layer or device layer stack against the influences of products used in photolithographic steps further in the process. It may have the same composition as the first interlayer 21 or it may have a different composition.

Next, as illustrated in FIG. 5, the second interlayer 22 and the underlying layers, e.g. the first device layer 31 and the first interlayer 21, are patterned, thereby removing the second interlayer and the underlying layers at the second location, e.g. forming a second opening 2 through these layers only at the location of the second bottom electrode 12 such as to expose the second bottom electrode 12. Patterning of the second interlayer 22 and the underlying layers may be done by photolithography, e.g. using a conventional photoresist. Preferably a solvent-developable photoresist is used. However, the present disclosure is not limited thereto and other photoresists may be used. After photolithography, an etching step may be performed to locally remove the second interlayer 22, the first device layer 31 and the first interlayer 21. The etching step can be a wet etching step or a dry etching step (e.g. using an 0₂, SFS or CFS plasma), and a single etching agent can be used for removing the different layers.

In a next step, illustrated in FIG. 6, a second device layer 32 is deposited, e.g. over substantially the entire substrate, e.g. at least where the second interlayer 21 and the underlying layers were removed at the second location. In this way, the second device layer 32 may be brought into contact with the second bottom electrode 12. In the example described here, the second device layer or device layer stack 32 may correspond to a second color and may comprise an organic semiconductor material suitable for emitting light of the second color, e.g. for emitting light having a second color spectrum, in which the second color spectrum may be at least different from the first color spectrum over a substantial spectral range. The second device layer 32 may for example comprise a hole injection layer, an electron blocking layer, a hole transport layer, an electroluminescent organic layer, an electron transport layer, a hole blocking layer and/or an electron injection layer, the present disclosure not being limited thereto. The second device layer 32 may comprise at least a second electroluminescent organic layer. The second device layer may be deposited by solution processing (e.g. spin-coating, printing, spray-coating, slot die coating and/or blade coating), gas phase deposition (e.g. CVD or OVPD) or vacuum deposition (e.g. evaporation).

The method also comprises afterwards patterning the first device layer 31 and the second device layer 32 to form the first patterned device layer 311 at the first location and the second patterned device layer 321 at the second locations, as described further hereinbelow.

The steps illustrated in FIG. 4 to FIG. 6 may be repeated, e.g. for forming a third sub-pixel.

After deposition of the second device layer 32, a third interlayer 23 may be deposited on the second device layer 32, e.g. as shown in FIG. 7. The third interlayer 23 may be a layer that does not cause degradation of the underlying device layer and of a device layer or device layer stack to be provided further in the process. It may protect the second device layer or device layer stack 32 against the influences of products used in photolithographic steps further in the process.

The third interlayer 23 may contain a polymer such as for example polyvinyl alcohol, polyvinyl pyrrolidone, water-soluble cellulose, polyethylene glycol, polyglycerin or pullullan. The third interlayer may further contain a solvent selected comprising water and/or an alcohol. The alcohol may for example be an alcohol without alkoxy groups, such as for example isopropyl alcohol. The alcohol may for example be a water-soluble alcohol. The solvent may contain only water, only an alcohol, or a mixture of water and a water-soluble alcohol.

Next, as illustrated in FIG. 8, the third interlayer 23 and the underlying layers, e.g. the second device layer 32, second interlayer 22, first device layer 31 and first interlayer 21, may be patterned, e.g. thereby forming a third opening 3 through these layers only at the location of the third bottom electrode 13 and exposing the third bottom electrode 13. Patterning of the third interlayer 23 and the underlying layers may be done by photolithography, using a conventional photoresist. Preferably a solvent- developable photoresist may be used. However, the present disclosure is not limited thereto and other photoresists may be used. After photolithography, an etching step is performed to locally remove the third interlayer 23, second device layer 32, the second interlayer 22, the first device layer 31 and the first interlayer 21. The etching step can be a wet etching step or a dry etching step (e.g. using an (¾, SFS or CFS plasma), and a single etching agent can be used for removing the different layers.

In a next step, illustrated in FIG. 9, a third device layer 33 is deposited. In this way, the third device layer 33 may be brought into contact with the third bottom electrode 13. In the example described here, the third device layer 33 may correspond to a third color and may comprise an organic semiconductor material suitable for emitting light of the third color, e.g. for emitting light having a third color spectrum being different from both the first color spectrum and the second color spectrum over a respective substantial wavelength range. The third layer stack 33 may for example comprise a hole injection layer, an electron blocking layer, a hole transport layer, an electroluminescent organic layer, an electron transport layer, a hole blocking layer and/or an electron injection layer, the present disclosure not being limited thereto. The third device layer 33 may comprise at least a third electroluminescent organic layer. The third device layer may be deposited by solution processing (e.g. spin-coating, printing, spray-coating, slot die coating and/or blade coating), gas phase deposition (e.g. CVD or OVPD) or vacuum deposition (e.g. evaporation).

After deposition of a desired number of device layers or colors, e.g. three in the example illustrated in FIG. 1 to FIG. 9, the different layers may be removed at respective locations where they are not needed in the final device, i.e. the different layers may be patterned. This removal can be done in different ways, as further illustrated: (i) photolithography with a benign photoresist system; (ii) use of a further interlayer; (iii) use of a further interlayer combined with photoresist patterning and a single etching step; and (iv) use of a further interlayer combined with a photoresist patterning and two etching step.

A first method for removing superfluous material is based on photolithography with a benign photoresist system, e.g. a photoresist system that does not cause degradation of exposed layers, e.g. layers that come in direct contact with the photolithography products. A conventional photoresist system may be used in case the exposed layers are layers that are not degraded or damaged by the products used during photolithography. In case the exposed layers are degraded or damaged by conventional photoresist products, a fluorinated photoresist system may be used. Process steps of this method are schematically illustrated in FIG. 10 to FIG. 13.

In this method, a photoresist layer that does not cause degradation of the exposed layer, e.g. in this example the third device layer 33, of the multilayer stack is deposited on the structure of FIG. 9. As illustrated in FIG. 10, the photoresist layer 40 is patterned in such a way that it remains at locations corresponding to the first location, e.g. the opening 1 in the first interlayer 21, the second location, e.g. the opening 2 in the second interlayer 22, and the third location, e.g. the opening 3 in the third interlayer 23. This patterning step may thus be done for all sub-pixels, e.g. all colors and/or all device layers, at the same time. The patterned photoresist layer 40 may either match the openings 1, 2, 3 previously made in the interlayers 21, 22, 23, or it may extend beyond the edges of these openings. In the example shown in FIG. 10 the photoresist layer 40 extends beyond, i.e. overlaps with, the edges of the openings. This overlap d_ov between the photoresist layer 40 and an opening in an interlayer is schematically illustrated in FIG. 14 (cross section) and FIG. 15 (top view), for an example wherein the opening is square shaped. Device layers and electrode layers are not shown in detail in these figures, for clarity reasons.

After patterning of the photoresist layer 40, e.g. by illumination through a shadow mask and development, the underlying layers in the exposed areas, e.g. the areas not covered by patterned photoresist layer 40, may be removed by etching. For example, RIE etching, e.g. oxygen, N0₂, SF₆, CF₄ RIE etching, may be used for removing the unwanted or superfluous material. In embodiments of the present disclosure the etching may for example continue, e.g. using the same etchant, until the substrate 10 is exposed. This etching step may be a time controlled etching. A cross section of the resulting structure is shown in FIG. 11.

In an alternative embodiment (not illustrated) the etching may continue until the first interlayer 21 is exposed. In such embodiments, preferably the first interlayer 21 may be thicker than the first device layer 31 and the second device layer 32. Under these conditions, after the etching step at least part of the second interlayer 22 may still cover the first device layer 31 at the first location and at least part of the third interlayer 23 may still cover the second device layer 32 at the second location. The third device layer 33 may be covered by the photoresist layer 40 during etching. It is an advantage that all device layers are protected during the etching step, at least at the first, second and any further location, e.g. where sub-pixels are to be formed.

In another alternative embodiment (not illustrated) the etching may continue until a first electroluminescent layer, part of the first device layer stack 31, is removed at locations different from the first location. In this way, electroluminescent layers of different sub-pixels, e.g. corresponding to different colors, may be separated from each other.

After the etching step, the photoresist layer 40 may be removed, e.g. as shown in FIG. 12. Next all superfluous layers may be removed by applying a solution that dissolves the interlayers 21, 22 and 23. This dissolving solution can for example be water or an alcohol, depending on the particular material used for the interlayers (e.g. water-soluble or alcohol-soluble). In an alternative process (not illustrated), the step of removing the photoresist layer 40 may be combined with the step of removing the superfluous layers, by applying a solution that dissolves the interlayers 21, 22 and 23, without prior removal of the photoresist layer 40.

After treatment of the sample with the dissolving solution, a structure as shown in FIG. 13 is obtained, for example a structure comprising side by side a first patterned device layer 311 at a first location, e.g. at first locations, a second patterned device layer 321 at a second location, e.g. at second locations, and a third patterned device layer 331 at a third location, e.g. at third locations.

It is an advantage of a method for removing superfluous material in accordance with embodiments of the present invention, e.g. as illustrated in FIG. 10 to FIG. 13, that the first device layer 31 and the second device layer 32 can be protected during the entire process, e.g. at least at the location where the first sub-pixel 311 and the second sub-pixel 321 are formed. These device layers are at these locations only exposed to the dissolving solution used for removing the interlayers. In the example shown, the third device layer 33 may be exposed to the photoresist 40 and the products used during photolithography. Therefore this method is suitable for applications wherein the third device layer 33 is a robust layer that is not damaged or degraded by these lithographic products. In case the third device layer 33 is not sufficiently resistant against the influences of conventional lithographic products, a fluorinated photoresist system may be used.

A second exemplary method for removing superfluous material may be based on the use of a further interlayer. Process steps of this method are schematically illustrated in FIG. 16 to FIG. 18. It is an advantage of this second method that all device layers 31, 32, 33 can be protected during the entire process, e.g. at least at the respective location where the first sub-pixel 311, the second sub-pixel 321 and the third sub-pixel 331 are formed. The device layers are at these locations only exposed to the dissolving solution used for removing the interlayers.

In this second method, a further interlayer 24 is deposited on the structure of FIG. 9. This further interlayer 24 may be either a planarizing layer as illustrated in FIG. 16 or it may be a non- planarizing layer, e.g. conformal or semi-conformal. The further interlayer 24 may contain a polymer such as for example polyvinyl alcohol, polyvinyl pyrrolidone, water-soluble cellulose, polyethylene glycol, polyglycerin or pullullan. The further interlayer may further contain a solvent selected comprising water and/or an alcohol. The alcohol may for example be an alcohol without alkoxy groups, such as for example isopropyl alcohol. The alcohol may for example be a water-soluble alcohol. The solvent may contain only water, only an alcohol, or a mixture of water and a water-soluble alcohol.

After deposition of the further interlayer 24, a time controlled dry or wet etching step may be applied. In embodiments of the present disclosure the etching may continue until the first interlayer 21 is exposed, e.g. as illustrated in FIG. 17. Preferably the first interlayer 21 may be thicker than the first device layer 31, the second device layer 32 and the third device layer 33. Under these conditions, after the etching step, at least part of the second interlayer 22 may still cover the first device layer 31 , at least part of the third interlayer 23 may still cover the second device layer 32 and at least part of the further interlayer 24 may still cover the third device layer 33 at the respective location where sub-pixels are to be formed. It is an advantage that all device layers are protected during the etching step, e.g. at least at the respective locations where sub-pixels are to be formed.

In alternative embodiments (not illustrated) the etching may continue until at least the first electroluminescent layer, e.g. part of the first device layer 31, is removed at locations different from the first location. In this way, the electroluminescent layers of the different sub-pixels, e.g. corresponding to different colors, may be separated from each other.

Next, a solvent or solution, e.g. water or an alcohol, dissolving the first interlayer 21, the second interlayer 22, the third interlayer 23 and the further interlayer 24 may be used to remove the unnecessary layers, resulting in the structure shown in FIG. 18, e.g. the structure comprising side by side a first patterned device layer 311 at a first location or first locations, a second patterned device layer 321 at a second location or second locations and a third patterned device layer 331 at a third location or third locations. It is an advantage of this approach that the first device layer 31, the second device layer 32 and the third device layer 33 at the location where the sub-pixels are formed can be protected by the overlying interlayers during the etching step. Therefore, this etching step does not damage the device layers.

A third method for removing superfluous material is based on the use of a further interlayer combined with photoresist patterning and a single etching step. It is an advantage of this method that all device layers 31, 32, 33 may be protected during the entire process at least at the respective location where the first sub-pixel 311, the second sub-pixel 321 and the third sub-pixel 331 are formed. The device layers may be at these locations only exposed to the dissolving solution used for removing the interlayers, and not to products used during photolithography. Process steps of this method are schematically illustrated in FIG. 19 to FIG. 21.

In this method, a further interlayer 24 is deposited on the structure of FIG. 9. This interlayer 24 can be either a planarizing layer as illustrated in FIG. 19 or it can be a non-planarizing layer, e.g. conformal or semi-conformal. The further interlayer 24 may contain a polymer such as for example polyvinyl alcohol, polyvinyl pyrrolidone, water-soluble cellulose, polyethylene glycol, polyglycerin or pullullan. The further interlayer may further contain a solvent comprising water and/or an alcohol. The alcohol may for example be an alcohol without alkoxy groups, such as for example isopropyl alcohol. The alcohol may for example be a water-soluble alcohol. The solvent may contain only water, only an alcohol, or a mixture of water and a water-soluble alcohol.

After deposition of the further interlayer 24, a photoresist layer 40 is deposited and patterned, as illustrated in FIG. 19. Preferably a solvent-developable photoresist is used. However, the present disclosure is not limited thereto and other photoresists may be used. The photoresist layer 40 may be patterned in such a way that it remains at locations corresponding to the first location, e.g. the first opening 1 in the first interlayer 21, the second location, e.g. the second opening 2 in the second interlayer 22, and the third location, e.g. the third opening 3 in the third interlayer 23. This patterning step is thus done for all sub-pixels, e.g. corresponding to all colors, e.g. for all device layers, at the same time. The patterned photoresist layer 40 may either match the openings 1, 2, 3 previously made in the interlayers 21, 22, 23, or it may extend beyond the edges of these openings. In the example shown in FIG. 19 the photoresist layer 40 extends beyond the edges of the openings. This overlap d_ov between the photoresist layer 40 and an opening in an interlayer is schematically illustrated in FIG. 14 (cross section) and FIG. 15 (top view), for an example wherein the opening is square shaped. Device layers and electrode layers are not shown in detail in these figures, for clarity reasons.

After patterning of the photoresist layer 40, e.g. by illumination through a shadow mask and development, the layers may be removed in the exposed areas, e.g. in the areas not covered by patterned photoresist layer 40, by wet or dry etching, till the substrate 10 is exposed. This is schematically shown in FIG. 20. For example, RIE etching, e.g. oxygen, N0₂, SF₆ or CF₄ RIE etching, may be used for removing the unwanted material.

In an alternative embodiment the etching may continue until the first interlayer 21 is exposed. In another alternative embodiment (not illustrated) the etching may continue until at least the first electroluminescent layer (being part of the first device layer 31) is removed at locations different from the first location. In this way, the electroluminescent layers of the different sub-pixels, e.g. corresponding to different colors, are separated from each other.

Next the photoresist layer 40 may be removed and all superfluous layers may be removed by applying a solvent or solution that dissolves the interlayers 21, 22, 23 and 24. This solvent or solution can for example be water or alcohol, depending on the particular material used for the interlayers. After treating the sample with the dissolving solution, a structure as shown in FIG. 21 is obtained, comprising side by side a first patterned device layer 311 at at least a first location, a second patterned device layer 321 at at least a second location and a third patterned device layer 331 at at least a third location on the substrate.

A fourth method for removing superfluous material is based on the use of a further interlayer combined with photoresist patterning, a first etching step and a second etching step. Process steps of this method are schematically illustrated in FIG. 22 to FIG. 25.

In this method according to embodiments of the invention, a further interlayer 24 is deposited on the structure of FIG. 9. This further interlayer 24 can be either a planarizing layer as illustrated in FIG. 22 or it can be a non-planarizing layer, e.g. conformal or semi-conformal.

After deposition of the further interlayer 24, a photoresist layer 40 may be deposited and patterned, as illustrated in FIG. 22. Preferably a solvent-developable photoresist may be used. However, the present disclosure is not limited thereto and other photoresists may be used. The photoresist layer 40 may be patterned in such a way that it remains at locations corresponding to the first location, e.g. the first opening 1 in the first interlayer 21, the second location, e.g. the second opening 2 in the second interlayer 22, and the third location, e.g. the third opening 3 in the third interlayer 23. This patterning step is thus done for all sub-pixels, e.g. for all colors; e.g. for all device layers, at the same time. The patterned photoresist layer 40 may either match the openings 1, 2, 3 previously made in the interlayers 21, 22, 23, or it may extend beyond the edges of these openings. In the example shown in FIG. 22 the photoresist layer 40 extends beyond the edges of the openings. This overlap d_ov between the photoresist layer 40 and an opening in an interlayer is schematically illustrated in FIG. 14 (cross section) and FIG. 15 (top view), for an example wherein the opening is square shaped. Device layers and electrode layers are not shown in detail in this figure, for clarity reasons.

After patterning of the photoresist layer 40, e.g. by illumination through a shadow mask and development, the underlying layers in the exposed areas, e.g. the areas not covered by patterned photoresist layer 40, may be removed by performing a first etching step, till the substrate is exposed, see FIG. 23. For example, RIE etching, e.g. oxygen, N(¾, SF₆ or CF₄ RIE etching, may be used for the first etching step. Next a second etching step may be done until the second interlayer 22 is exposed. In some embodiments, the second etching step may be a continuation of the first etching step. A cross section of the resulting structure is schematically shown in FIG. 24.

In alternative embodiments (not illustrated) the second etching step may continue till the first interlayer 21 is exposed. In other alternative embodiments (not illustrated) the second etching step may continue until at least the first electroluminescent layer, e.g. part of the first device layer 31, is removed at locations different from the first location or locations. In this way, the electroluminescent layers of the different sub-pixels, e.g. corresponding to different colors, are separated from each other.

After the second etching step all remaining superfluous layers are removed by applying a solvent or solution that dissolves the interlayers 21 and 22 and further interlayer 24. This solvent or solution can for example be water or alcohol, depending on the particular material used for the interlayers. After treating the sample with the dissolving solution, a structure as shown in FIG. 25 is obtained, comprising side by side a first patterned device layer 311 at a first location, a second patterned device layer 321 at a second location and a third patterned device layer 331 at a third location.

In embodiments of the present disclosure the device layer stacks may comprise a complete OLED stack or they may comprise an incomplete OLED stack. As an example of an incomplete stack, a stack may be deposited for each element/color up to the electroluminescent layer. The remaining layers and a top electrode may then be deposited as a common stack after the patterning process described above.

Methods of the present disclosure may be used for fabricating devices comprising multiple pixels, such as for example a two-dimensional array of pixels. For example, methods of the present disclosure may be used for fabricating OLED arrays or OLED displays, such as multicolor displays (e.g. RGB, RGBW) or displays combining hyperspectral displaying with one or more colors. For example, methods of the present disclosure may be used for fabricating OPD arrays or OPD imagers, such as multicolor imagers (e.g. RGB, RGBW) or imagers combining hyperspectral imaging with one or more colors. Methods of the present disclosure may also be used for fabricating OTFTs or OTFT circuits with different semiconductors side by side or for fabricating biosensors. Methods of the present disclosure may be used for fabricating "smart" pixels wherein for example OPD, OLED en OTFT are combined, e.g. RGB OLED + white OPD, OPD + readout OTFT, OLED + readout OTFT.

[0090] The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

Whereas the above detailed description as well as the summary of the invention has been focused on a method for fabricating a device, the present invention also relates to a device comprising patterned layers obtained using a method according to any of the embodiments as described above.

While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the invention.

Claims

1.- A method for fabricating a device comprising a first patterned device layer (311) at a first location and a second patterned device layer (321) at a second location on a substrate (10), the method comprising:

depositing a first interlayer (21) on the substrate (10);

patterning the first interlayer (21), thereby removing the first interlayer at the first location;

depositing a first device layer (31);

depositing a second interlayer (22);

patterning the second interlayer (22) and the underlying layers, thereby removing the second interlayer and the underlying layers at the second location;

depositing a second device layer (32); and

afterwards patterning the first device layer (31) and the second device layer (32) to form the first patterned device layer (311) at the first location and the second patterned device layer (321) at the second location.

2.- The method according to claim 1, further comprising, before patterning the first device layer (31) and the second device layer (32): depositing a third interlayer (23); patterning the third interlayer (23) and the underlying layers, thereby removing the third interlayer and the underlying layers at a third location; and depositing a third device layer (33), wherein this sequence of steps is repeated until a predetermined number of device layers is obtained.

3.- The method according to claim 2 wherein patterning of all device layers is done in a single patterning process after all device layers have been deposited.

4. - The method according to any of the previous claims wherein the first interlayer (21), the second interlayer (22) and the third interlayer (23) are soluble in water or in alcohol.

5. - The method according to any of the previous claims wherein the first device layer (31) is a stack of at least two layers.

6. - The method according to any of the previous claims wherein the second device layer (32) is a stack of at least two layers.

7. - The method according to any of the previous claims wherein each of the device layers is a stack of at least two layers.

8.- The method according to any of the previous claims wherein the device layers comprise an electroluminescent layer, a photosensitive layer and/or a semiconductor layer.

9. - The method according to any of the previous claims wherein each of the device layers comprises a different organic semiconductor layer.

10. - The method according to any of the previous claims wherein the step of patterning the first device layer (31) and the second device layer (32) comprises:

providing a patterned photoresist layer (40) covering the first location and the second location; performing an etching step using the patterned photoresist layer (40) as a mask, the etching being continued till exposure of the substrate (10); removing the patterned photoresist layer (40); and

dissolving the first interlayer (21) and the second interlayer (22) in water or in an alcohol.

The method according to any of claims 1 to 9 wherein the step of patterning the first device layer (31) and the second device layer (32) comprises:

depositing a further interlayer (24);

performing an etching step till the first interlayer (21)is exposed; and

depositing a further interlayer (24);

providing a patterned photoresist layer (40) covering the first location and the second location; performing an etching step using the patterned photoresist layer (40) as a mask, the etching being continued till exposure of the substrate (10);

removing the patterned photoresist layer (40); and

dissolving the first interlayer (21), the second interlayer (22) and the further interlayer (24) in water or in an alcohol.

depositing a further interlayer (24);

providing a patterned photoresist layer (40) covering the first location and the second location; performing a first etching step using the patterned photoresist layer (40) as a mask, the etching being continued till exposure of the substrate (10);

removing the patterned photoresist layer (40);

performing a second etching step till the second interlayer (22) is exposed; and

dissolving the first interlayer (21), the second interlayer (22), and the further interlayer (24) in water or in an alcohol.

A method for fabricating a multi-color organic light emitting diode array using a method according to any of the previous claims, wherein the first patterned device layer (311) comprises a first electroluminescent layer for emitting a first color spectrum, the second patterned device layer (321) comprises a second electroluminescent layer for emitting a second color spectrum, and the third device layer (331) comprises a third electroluminescent layer for emitting a third color spectrum.

A method for fabricating a multi-color organic photodetector array using a method according to any of the previous claims, wherein the first patterned device layer (311) comprises a first semiconductor layer having a first absorption spectrum, the second patterned device layer (321) comprises a second semiconductor layer having a second absorption spectrum, and the third patterned device layer (331) comprises a third semiconductor layer having a third absorption spectrum.