WO2015131521A1 - 以太网sfp电模块及实现同步以太网的方法 - Google Patents

以太网sfp电模块及实现同步以太网的方法 Download PDF

Info

Publication number
WO2015131521A1
WO2015131521A1 PCT/CN2014/088357 CN2014088357W WO2015131521A1 WO 2015131521 A1 WO2015131521 A1 WO 2015131521A1 CN 2014088357 W CN2014088357 W CN 2014088357W WO 2015131521 A1 WO2015131521 A1 WO 2015131521A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
ethernet
module
clock
sfp
Prior art date
Application number
PCT/CN2014/088357
Other languages
English (en)
French (fr)
Inventor
章灿辉
朱冬艳
计世荣
吴海波
Original Assignee
烽火通信科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 烽火通信科技股份有限公司 filed Critical 烽火通信科技股份有限公司
Publication of WO2015131521A1 publication Critical patent/WO2015131521A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node

Definitions

  • the present invention relates to synchronous Ethernet, and in particular to an Ethernet SFP electrical module and a method for implementing synchronous Ethernet.
  • the SFP (SMALL FORM PLUGGABLE) module is used to realize the mutual conversion of optical signals and electrical signals, and has been widely used in the fields of telecommunications and data communication.
  • the SFP module is standardized by a Multilateral Protocol (MSA) between competing vendors, and can only achieve simple mutual conversion of optical signals and electrical signals, and does not involve transcoding.
  • MSA Multilateral Protocol
  • PHY physical layer function defined by the Ethernet standard
  • the PHY Physical Layer
  • the PHY defines electrical and optical signals, line states, clock references, data codes, and circuits required for data transmission and reception according to the Ethernet standard (IEEE 802.3x), and provides data link layer devices. Standard interface.
  • the MAC Medium Access Control
  • the MAC and PHY communicate through the SGMII (Serial Gigabit Media Independent Interface) Ethernet serial differential bus signal.
  • Ethernet SFP electrical module The structure and application scenario of this Ethernet SFP electrical module is shown in Figure 1.
  • the printed circuit board is powered.
  • the road mainly realizes the code conversion between the SGMII bus and the cable signal, and the realization circuit is as shown in FIG. 2 .
  • the left interface signal is the well-known MSA standard (INF-8074i) SFP connector interface signal, wherein RD ⁇ and TD ⁇ are the SGMII differential serial bus interface between the module and the system device.
  • Signal; the RX and TX signals on the RJ45 socket in the right interface are Ethernet cable signals.
  • the function of the Ethernet SFP electrical module is to complete the code conversion of the SGMII bus signal to the Ethernet cable signal.
  • the PHY chip uses an internal clock oscillator source (OSC) as its reference operating clock (RefCLK) input.
  • OSC internal clock oscillator source
  • RefCLK reference operating clock
  • the PHY converts the signal TD ⁇ originally containing the system equipment clock information into only the transition process from the TD ⁇ signal decoding to the socket signal TX re-encoding.
  • the cable signal TX of the internal clock oscillation source (OSC) clock information the system device clock information is lost, which violates the principle of synchronous Ethernet; in the other direction, the PHY is re-encoded from the socket signal RX to the RD ⁇ signal.
  • the signal RX containing the line clock information is also converted into a signal RD ⁇ containing only the internal clock oscillation source (OSC) clock information, and the clock information of the cable signal is lost, which also violates the synchronous Ethernet.
  • OSC internal clock oscillation source
  • Ethernet that satisfies such conditions is called Synchronous Ethernet, which requires that the cable signal frequency sent by the system device must be synchronized with the clock of the system device, and the system device also has the capability of (optionally) frequency synchronization with the cable signal clock information, which can be implemented according to the application. One or all of them are implemented.
  • the existing Ethernet SFP electrical module uses the internal clock oscillation source to supply the PHY chip as its reference working clock, and the clock information contained in the cable signal cannot be uploaded to the system, so that the transmission of the clock information is cut off. .
  • the technical problem to be solved by the present invention is to solve the problem of the cable signal of the Ethernet SFP electrical module.
  • the clock information cannot be uploaded to the system.
  • the technical solution adopted by the present invention is to provide an Ethernet SFP electrical module, including an Ethernet MII interface, a PHY module, and an MCU, where the TxDisable signal and the local clock signal in the Ethernet MII interface pass through a 2-to-1 selector is connected to the RefCLK signal input pin on the PHY module, and the RcvCLK signal and the low-level signal output by the PHY module PHY module are connected to the Ethernet MII interface via a second 2-to-1 selector
  • the MCU controls the first 2-to-1 controller by the reference clock control signal CLKSEL0, selects the input signal of the TxDisable pin or selects the local clock signal as the reference clock input signal; and restores the clock control signal CLKSEL1 to control
  • the second 2-to-1 controller selects the output line recovery clock on the TxFault pin or outputs a low level.
  • connection loss signal of the PHY module is outputted to the LOS pin in the Ethernet MII interface via the MCU, and the MCU controls the PHY module according to the connection loss signal.
  • Hardware reset and reinitialization
  • the MOD-DEF1 and MOD-DEF2 pins in the Ethernet MII interface pass the serial communication I2C interface signal.
  • the type of the current SFP module is determined according to the bus address, the register address, and the connector type of the I2C interface signal.
  • the register address is 2
  • the connector type is 00.
  • the current SFP module is an Ethernet SFP electrical module.
  • the bus address of the I2C interface signal is A0h
  • the register address is 2
  • the connector type is 07
  • the current SFP module is a traditional SFP optical module.
  • the PHY module hardware reset is set by the bus address A2h and the register address 250 of the I2C interface signal, and the write 00 triggers the hardware reset, and automatically returns to 01 after the reset.
  • the initialization of the PHY module is set by the bus address A2h and the register address 250 of the I2C interface signal, and the write 00 trigger module is initialized, and automatically returns to 01 after the reset.
  • the present invention also provides a method for implementing synchronous Ethernet by using the above Ethernet SFP electrical module, comprising the following steps:
  • the second 2-to-1 controller is controlled by the MCU output recovery clock control signal CLKSEL1, and the output line recovery clock is selected on the TxFault pin, or the output is low.
  • the power-on of the Ethernet SFP electrical module is set to use a local clock signal to restore the clock output low.
  • the system clock is transmitted to the module as a PHY reference clock by using two pins associated with only the optical module, and the line clock extracted by the PHY is transmitted to the system as a system lock.
  • the phase-ring reference source realizes the synchronization processing of the Ethernet SFP electrical module, and solves the shortcomings of the previous use of such a module that does not support synchronous Ethernet, while maintaining the compatibility and stability of the module.
  • FIG. 1 is a schematic diagram of a structure and an application scenario of an existing Ethernet SFP electrical module
  • FIG. 2 is a circuit diagram of an implementation of an existing Ethernet SFP electrical module
  • FIG. 3 is a circuit diagram of an implementation of an Ethernet SFP electrical module provided by the present invention.
  • the Ethernet SFP electrical module needs to occupy two pins of the MSA standard SFP optical module to provide the system reference clock and extract the line recovery clock.
  • the LINKDOWN (connection lost) signal of the PHY module needs to be able to
  • the output of the hardware pin signal is compatible with the standard MSA SFP optical module; in addition, it is considered to be compatible with most of the old systems already running on the network, so that when using the synchronized Ethernet SFP electrical module, Need to change the circuit Board, just upgrade the software (including programmable logic) to achieve support for synchronous Ethernet.
  • the present invention provides an Ethernet SFP electrical module, which utilizes two pins TxDisable and Txfault defined by the MSA standard to implement the transmission of clock information in two directions required by synchronous Ethernet, so that the system device is using Ethernet.
  • the network SFP electrical module does not cause interruption of clock information transmission.
  • the Ethernet SFP electrical module provided by the present invention includes an Ethernet MII interface and a PHY module, and the aforementioned TxDisable and Txfault pins and the LOS pin of the output LINKDOWN signal are set on the Ethernet MII interface.
  • the PHY module is connected to the RJ45 interface through a transformer to implement connection with the Ethernet.
  • the data transceiving signals TD+, TD-, RD+, and RD- in the Ethernet MII interface are respectively connected to the PHY module, respectively.
  • the Ethernet SFP electrical module is provided with a micro control unit (MCU), and the TxDisable signal in the Ethernet MII interface and the local clock signal output from the local crystal oscillator clock source (OSC) are connected to the PHY module via the first 2-to-1 selector.
  • MCU micro control unit
  • OSC local crystal oscillator clock source
  • the RefCLK signal input pin, the RcvCLK signal and the low level signal output by the PHY module are connected to the Txfault signal pin in the Ethernet MII interface via the second 2-to-1 selector.
  • the PHY reference clock control signal CLKSEL0 output by the MCU controls the first 2-to-1 controller, selects the input signal of the TxDisable pin as the reference clock input signal, or selects the local clock signal as the reference clock input signal.
  • the recovery clock control signal CLKSEL1 output by the MCU controls the second 2-to-1 controller, selects the output line recovery clock on the TxFault pin, or outputs a low level.
  • MOD-DEF1 and MOD-DEF2 in the Ethernet MII interface are serial communication I2C interface signals defined by the MSA standard (INF-8074i), and the following functions are implemented through the I2C interface signals:
  • identification module type is an SFP optical module or an SFP electrical module, which is compatible with the SFF-8472 standard definition
  • the module power-on default is to use the local clock signal to restore the clock output low level to be compatible with older systems that do not require synchronous Ethernet and older systems that do not provide a system reference clock;
  • Table 1 is a description of the main functional difference pins of the Ethernet SFP electrical module and the conventional SFP optical module in the present invention.
  • Table 2 shows the definition of the I2C register of the SFP optical module that supports synchronous Ethernet, which is different from the SFP optical module of the MSA standard.
  • TxDisable and Txfault pins are utilized as follows:
  • the two pins themselves have application significance only in the MSA standard SFP optical module, and have no corresponding meaning for the Ethernet SFP electrical modules with the majority of applications, so that they can be used to transmit clock information.
  • the invention is guaranteed to have good module compatibility.
  • the present invention also provides a method for implementing synchronous Ethernet by using the foregoing Ethernet SFP electrical module, including the following steps:
  • the second 2-to-1 controller is controlled by the MCU output recovery clock control signal CLKSEL1, and the output line recovery clock is selected on the TxFault pin, or the output is low.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

公开了一种以太网SFP电模块及实现同步以太网的方法，该模块包括以太网ΜII接口、PHY模块和MCU，接口中的TxDisable信号和本地时钟信号经第一2选1选择器连接PHY模块上的RefCLK信号输入引脚，PHY模块输出的RcvCLK信号和低电平信号经第二2选1选择器连接到接口中的Txfault信号引脚；MCU通过参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；MCU通过恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。利用只与光模块相关的两个引脚，传递系统时钟给模块作为PHY参考时钟，传递PHY提取的线路时钟给系统作为系统锁相环参考源，实现了以太网SFP电模块的同步化处理。

Description

以太网SFP电模块及实现同步以太网的方法 技术领域
本发明涉及同步以太网，具体涉及以太网SFP电模块及实现同步以太网的方法。
背景技术
SFP(SMALL FORM PLUGGABLE)模块作为一种可热插拔小封装模块，其作用是实现光信号与电信号的相互转换，在电信和数据通讯领域得到了广泛应用。
SFP模块由一个竞争厂商之间的多边协议(MSA)进行规范，只能实现光信号和电信号的简单相互转换，不涉及编码转换。但是随着以太网标准在电信领域的逐渐普及，在遵循MSA标准的基础上，很多模块厂商开始推出一种所谓“以太网SFP电模块”，即将以太网标准定义的实现物理层功能的芯片(PHY)内置于SFP电模块印刷电路板电路中，以减少对设备主系统的电路板空间的占用，同时实现灵活更换、速率升级或更换传输介质的目的。PHY(Physical,物理层)根据以太网标准(IEEE 802.3x)定义了数据传送与接收所需要的电与光信号、线路状态、时钟基准、数据编码和电路等，并向数据链路层设备提供标准接口。系统设备上的MAC(Medium Access Control，介质访问控制层)根据以太网标准(IEEE 802.3x)定义，提供寻址机构、数据帧的构建、数据差错检查、传送控制、向网络层提供标准的数据接口等功能。MAC和PHY之间通过SGMII(Serial Gigabit Media Independent Interface，串行千兆媒介无关接口)以太网串行差分总线信号进行通信。
这种以太网SFP电模块的构造和应用场景如图1所示，印刷电路板电 路主要实现SGMII总线和线缆信号之间的编码转换，实现电路如图2所示。
图2所示以太网SFP电模块中，左侧接口信号为业界熟知的MSA标准(INF-8074i)SFP连接器接口信号，其中RD±和TD±为模块与系统设备接口的SGMII差分串行总线信号；右侧接口中插座RJ45上的RX和TX信号为以太网线缆信号，以太网SFP电模块的功能就是完成SGMII总线信号到以太网线缆信号的编码转换。PHY芯片采用内部时钟振荡源(OSC)作为其参考工作时钟(RefCLK)输入。虽然TD±信号内含有系统设备的时钟信息，但PHY在完成从TD±信号解码到插座信号TX重新编码的转变过程中，同时也将原本含有系统设备时钟信息的信号TD±转变成了只含内部时钟振荡源(OSC)时钟信息的线缆信号TX，丢失了系统设备时钟信息，这就违背了同步以太网的原则；另一方向上，PHY在完成从插座信号RX解码到RD±信号重新编码的转变过程中，同时也将含有线路时钟信息的信号RX转变成了只含内部时钟振荡源(OSC)时钟信息的信号RD±,丢失了线缆信号的时钟信息，这也违背了同步以太网的上下游设备频率同步的原则。
在电信领域中，很多应用场合都要求相互连接的上下游设备之间能达到频率同步，并且，使用太网标准进行电信传输时，通常也要求实现频率同步，满足这样条件的以太网被称为同步以太网，它要求系统设备发出的线缆信号频率必须同步于系统设备的时钟，同时系统设备也具备(可选择地)频率同步于线缆信号时钟信息的能力，根据应用场合可实现两者之一或者全部实现。
综上所述，现有的以太网SFP电模块由于采用内部时钟振荡源供给PHY芯片作为其参考工作时钟，而且线缆信号所含的时钟信息也无法上传给系统，导致时钟信息的传递被割断。
发明内容
本发明所要解决的技术问题是解决以太网SFP电模块线缆信号所含的 时钟信息也无法上传给系统的问题。
为了解决上述技术问题，本发明所采用的技术方案是提供一种以太网SFP电模块，包括以太网MII接口、PHY模块和MCU，所述以太网MII接口中的TxDisable信号和本地时钟信号经第一2选1选择器连接所述PHY模块上的RefCLK信号输入引脚，所述PHY模块PHY模块输出的RcvCLK信号和低电平信号经第二2选1选择器连接到所述以太网MII接口中的Txfault信号引脚；所述MCU通过参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
在上述以太网SFP电模块中，所述PHY模块的连接丢失信号经所述MCU输出到所述以太网MII接口中的LOS引脚，根据所述连接丢失信号，所述MCU控制所述PHY模块硬件复位和重新初始化。
在上述以太网SFP电模块中，所述以太网MII接口中的MOD-DEF1和MOD-DEF2引脚传递串行通信I2C接口信号。
在上述以太网SFP电模块中，根据I2C接口信号的总线地址、寄存器地址和接头类型确定当前SFP模块的类型，当I2C接口信号的总线地址为A0h、寄存器地址为2时、接头类型为00时，当前SFP模块为以太网SFP电模块；当I2C接口信号的总线地址为A0h、寄存器地址为2时、接头类型为07时，当前SFP模块为传统SFP光模块。
在上述以太网SFP电模块中，通过I2C接口信号的总线地址A2h和寄存器地址250设置所述PHY模块硬件复位，写00触发硬件复位，复位完后自动恢复为01。
在上述以太网SFP电模块中，通过I2C接口信号的总线地址A2h和寄存器地址250设置所述PHY模块的初始化，写00触发模块初始化，复位完后自动恢复为01。
本发明还提供了一种利用上述的以太网SFP电模块实现同步以太网的方法，包括以下步骤：
利用MCU输出参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；
利用MCU输出恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
在上述方法中，以太网SFP电模块模块上电缺省设置为使用本地时钟信号，恢复时钟输出低电平。
本发明，在已有的MSA标准的SFP连接器接口信号中，利用只与光模块相关的两个引脚，传递系统时钟给模块作为PHY参考时钟，传递PHY提取的线路时钟给系统作为系统锁相环参考源，实现了以太网SFP电模块的同步化处理，解决以前使用此类模块不支持同步以太网的缺点，同时保持模块的兼容性和稳定性。
附图说明
图1为现有以太网SFP电模块构造及应用场景示意图；
图2为现有以太网SFP电模块实现电路图；
图3为本发明提供的以太网SFP电模块实现电路图。
具体实施方式
要实现同步以太网，以太网SFP电模块需要占用MSA标准SFP光模块的两个引脚，用于提供系统参考时钟和提取线路恢复时钟；同时，PHY模块的LINKDOWN(连接丢失)信号需要能以硬件引脚信号的形式输出，从而兼容标准MSA的SFP光模块；另外，还要考虑兼容大多数已经在网运行的老系统，使其在使用同步化处理后的以太网SFP电模块时，不需要改变电路 板，只需升级软件(包括可编程逻辑)就可以实现对同步以太网的支持。
为此，本发明提供了一种以太网SFP电模块，利用MSA标准定义的两个引脚TxDisable和Txfault实现了同步以太网要求的两个方向上的时钟信息的传递，使得系统设备在使用以太网SFP电模块时不至于造成时钟信息传递的中断。
下面结合附图对本发明做出详细的说明。
如图3所示，本发明提供的以太网SFP电模块包括以太网MII接口和PHY模块，前面提到的TxDisable和Txfault引脚以及输出LINKDOWN信号的LOS引脚设置在以太网MII接口上。
与现有技术相同，PHY模块通过变压器连接RJ45接口，以实现与以太网的连接，以太网MII接口中的数据收发信号TD+、TD－、RD+和RD－分别相应地连接到PHY模块上，以实现数据传输功能。
以太网SFP电模块上设有微控制单元(MCU)，以太网MII接口中的TxDisable信号和本地晶振时钟振荡源(OSC)输出的本地时钟信号经第一2选1选择器连接到PHY模块上的RefCLK信号输入引脚，PHY模块输出的RcvCLK信号和低电平信号经第二2选1选择器连接到以太网MII接口中的Txfault信号引脚。
MCU输出的PHY参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号作为参考时钟输入信号，或者选择本地时钟信号作为参考时钟输入信号。MCU输出的恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
以太网MII接口中的MOD-DEF1和MOD-DEF2为MSA标准(INF-8074i)定义的串行通信I2C接口信号，通过I2C接口信号实现以下功能：
(1)识别模块类型是SFP光模块还是SFP电模块，兼容SFF-8472标准定义；
(2)透过单片机MCU选择使用本地信号或外部时钟信号作为PHY模块的参考时钟，也可以控制线路恢复时钟输出与否。模块上电缺省设置为使用本地时钟信号，恢复时钟输出低电平，以兼容不需要同步以太网的老系统和无法提供系统参考时钟的老系统；
(3)透过单片机MCU实现PHY模块的硬件复位和重新初始化。当参考时钟由模块外部供给时，时钟行为不可预知，异常的时钟行会使PHY模块功能紊乱，此时需要对PHY模块进行硬件复位和初始化干预，以提高模块的稳定性；
表1中为本发明中以太网SFP电模块与传统SFP光模块的主要功能差别引脚的描述。
表1：
Figure PCTCN2014088357-appb-000001
选择以上3个信号可以最大限度地满足系统兼容性，因为对于绝大多数系统而言，电路设计时，这3个引脚都按MSA标准的SFP光模块引入了可编程逻辑器件，这样就可以在可编程逻辑里针对SFP光模块和SFP电模块灵活处理。
表2给出了支持同步以太网的SFP电模块区别于MSA标准的SFP光模块的I2C寄存器的定义。
表2：
Figure PCTCN2014088357-appb-000002
Figure PCTCN2014088357-appb-000003
本发明中，利用的TxDisable和Txfault两个引脚具有以下特点：
(1)依照MSA标准SFP光模块参考电路设计的绝大部分旧系统设备电路，由于业界普遍将它们引进了可编程逻辑器件，可编程逻辑器件内部也通常具备设备系统时钟，旧系统就很容易升级以支持同步以太网，保证了本发明具有最好的新旧系统设备兼容性；
(2)这两个引脚本身只在MSA标准SFP光模块时有应用意义，对于应用数量占绝大多数的以太网SFP电模块而言没有相应的意义，恰好可以利用它们来传递时钟信息，保证了本发明具有良好的模块兼容性。
在此基础上，本发明还提供了一种利用上述以太网SFP电模块实现同步以太网的方法，包括以下步骤：
利用MCU输出参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；
利用MCU输出恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
本发明不局限于上述最佳实施方式，任何人应该得知在本发明的启示下作出的结构变化，凡是与本发明具有相同或相近的技术方案，均落入本发明的保护范围之内。

Claims (8)

  1. 以太网SFP电模块，包括以太网MII接口和PHY模块，其特征在于，还包括MCU，
    所述以太网MII接口中的TxDisable信号和本地时钟信号经第一2选1选择器连接所述PHY模块上的RefCLK信号输入引脚，所述PHY模块PHY模块输出的RcvCLK信号和低电平信号经第二2选1选择器连接到所述以太网MII接口中的Txfault信号引脚；
    所述MCU通过参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
  2. 如权利要求1所述的以太网SFP电模块，其特征在于，所述PHY模块的连接丢失信号经所述MCU输出到所述以太网MII接口中的LOS引脚，根据所述连接丢失信号，所述MCU控制所述PHY模块硬件复位和重新初始化。
  3. 如权利要求1所述的以太网SFP电模块，其特征在于，所述以太网MII接口中的MOD-DEF1和MOD-DEF2引脚传递串行通信I2C接口信号。
  4. 如权利要求3所述的以太网SFP电模块，其特征在于，根据I2C接口信号的总线地址、寄存器地址和接头类型确定当前SFP模块的类型，当I2C接口信号的总线地址为A0h、寄存器地址为2时、接头类型为00时，当前SFP模块为以太网SFP电模块；当I2C接口信号的总线地址为A0h、寄存器地址为2时、接头类型为07时，当前SFP模块为传统SFP光模块。
  5. 如权利要求3所述的以太网SFP电模块，其特征在于，通过I2C接口信号的总线地址A2h和寄存器地址250设置所述PHY模块硬件复位，写00触发硬件复位，复位完后自动恢复为01。
  6. 如权利要求3所述的以太网SFP电模块，其特征在于，通过I2C接 口信号的总线地址A2h和寄存器地址250设置所述PHY模块的初始化，写00触发模块初始化，复位完后自动恢复为01。
  7. 利用如权利要求1－6任一项所述的以太网SFP电模块实现同步以太网的方法，其特征在于，包括以下步骤：
    利用MCU输出参考时钟控制信号CLKSEL0控制第一2选1控制器，选择将TxDisable引脚的输入信号或者选择本地时钟信号作为参考时钟输入信号；
    利用MCU输出恢复时钟控制信号CLKSEL1控制第二2选1控制器，选择在TxFault引脚输出线路恢复时钟，或者输出低电平。
  8. 如权利要求8所述的方法，其特征在于，以太网SFP电模块模块上电缺省设置为使用本地时钟信号，恢复时钟输出低电平。
PCT/CN2014/088357 2014-03-03 2014-10-11 以太网sfp电模块及实现同步以太网的方法 WO2015131521A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410074891.5 2014-03-03
CN201410074891.5A CN103812566A (zh) 2014-03-03 2014-03-03 以太网sfp电模块及实现同步以太网的方法

Publications (1)

Publication Number Publication Date
WO2015131521A1 true WO2015131521A1 (zh) 2015-09-11

Family

ID=50708828

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/088357 WO2015131521A1 (zh) 2014-03-03 2014-10-11 以太网sfp电模块及实现同步以太网的方法

Country Status (2)

Country Link
CN (1) CN103812566A (zh)
WO (1) WO2015131521A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115314168A (zh) * 2022-09-22 2022-11-08 江苏云涌电子科技股份有限公司 一种以太网传输数据的冗余系统

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103812566A (zh) * 2014-03-03 2014-05-21 烽火通信科技股份有限公司 以太网sfp电模块及实现同步以太网的方法
US9866257B2 (en) * 2015-02-12 2018-01-09 Metanoia Communications Inc. XDSL and G.Fast SFP for any-PHY platform
CN107579832B (zh) * 2017-07-31 2023-11-28 博为科技有限公司 无网络变压器的以太网口通信电路
US11271712B2 (en) * 2020-01-07 2022-03-08 Microchip Technology Inc. Daisy-chained synchronous ethernet clock recovery

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013456A (zh) * 2007-01-29 2007-08-08 杭州华为三康技术有限公司 可插拔电子组件中数据存储器件及实现防伪的系统及方法
CN101039148A (zh) * 2007-02-07 2007-09-19 华为技术有限公司 一种光模块及其支持ge光口和fe光口的方法、网络设备
US20100280858A1 (en) * 2009-04-30 2010-11-04 Embarq Holdings Company, Llc System and method for a small form pluggable ethernet demarcation device
CN103067180A (zh) * 2011-10-19 2013-04-24 沈阳晨讯希姆通科技有限公司 光纤交换机
CN103812566A (zh) * 2014-03-03 2014-05-21 烽火通信科技股份有限公司 以太网sfp电模块及实现同步以太网的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100153550A1 (en) * 2008-12-15 2010-06-17 Broadcom Corporation Pluggable device that enables an addition of security functionality in a network
CN102347830B (zh) * 2011-11-09 2017-12-05 中兴通讯股份有限公司 以太网同步方法和系统
CN103236915B (zh) * 2013-04-24 2016-02-10 深圳市极致兴通科技有限公司 同步以太网电口模块

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101013456A (zh) * 2007-01-29 2007-08-08 杭州华为三康技术有限公司 可插拔电子组件中数据存储器件及实现防伪的系统及方法
CN101039148A (zh) * 2007-02-07 2007-09-19 华为技术有限公司 一种光模块及其支持ge光口和fe光口的方法、网络设备
US20100280858A1 (en) * 2009-04-30 2010-11-04 Embarq Holdings Company, Llc System and method for a small form pluggable ethernet demarcation device
CN103067180A (zh) * 2011-10-19 2013-04-24 沈阳晨讯希姆通科技有限公司 光纤交换机
CN103812566A (zh) * 2014-03-03 2014-05-21 烽火通信科技股份有限公司 以太网sfp电模块及实现同步以太网的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115314168A (zh) * 2022-09-22 2022-11-08 江苏云涌电子科技股份有限公司 一种以太网传输数据的冗余系统
CN115314168B (zh) * 2022-09-22 2023-01-13 江苏云涌电子科技股份有限公司 一种以太网传输数据的冗余系统

Also Published As

Publication number Publication date
CN103812566A (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
US8886840B2 (en) System and method for implementing a single chip having a multiple sub-layer PHY
EP1388975B1 (en) System and method for data transition control in a multirate communication system
US7093172B2 (en) System and method for determining on-chip bit error rate (BER) in a communication system
US9544069B2 (en) Methods and apparatus for link training, initialization and management via a high speed bus interface
WO2015131521A1 (zh) 以太网sfp电模块及实现同步以太网的方法
US7463706B2 (en) System and method for performing on-chip synchronization of system signals utilizing off-chip harmonic signal
US7733998B2 (en) System and method for programmably adjusting gain and frequency response in a 10-gigabit Ethernet/fibre channel system
US20050066045A1 (en) Integrated network interface supporting multiple data transfer protocols
US20060143355A1 (en) Protocol independent data transmission using a 10 Gigabit Attachment Unit Interface
US10609741B2 (en) Multi-gigabit wireless tunneling system
CN201336661Y (zh) 一种光模块接口转换装置
US8514731B2 (en) Variable-frequency network device and variable-frequency network connection establishing method
CN203840362U (zh) 一种同步以太网电接口模块结构
JP5545146B2 (ja) シリアル通信システム
ATA et al. Protocol Description
Aria et al. Document Revision History
Hard Transceiver Protocol Configurations in Cyclone V Devices
Devices Transceiver Protocol Configurations in
Slip et al. Low Latency Custom Configuration Channel Options

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14884722

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 139550140003003815

Country of ref document: IR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14884722

Country of ref document: EP

Kind code of ref document: A1