WO2015129717A1 - Fet parallel circuit cell and artificial high-voltage fet module - Google Patents

Fet parallel circuit cell and artificial high-voltage fet module Download PDF

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Publication number
WO2015129717A1
WO2015129717A1 PCT/JP2015/055324 JP2015055324W WO2015129717A1 WO 2015129717 A1 WO2015129717 A1 WO 2015129717A1 JP 2015055324 W JP2015055324 W JP 2015055324W WO 2015129717 A1 WO2015129717 A1 WO 2015129717A1
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Prior art keywords
circuit
sic
misfet
fet
converter
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PCT/JP2015/055324
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French (fr)
Japanese (ja)
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浩隆 大嶽
達也 柳
雄二 古久保
敦彦 平井
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ローム株式会社
株式会社京都ニュートロニクス
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Publication of WO2015129717A1 publication Critical patent/WO2015129717A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/12—Modifications for increasing the maximum permissible switched current
    • H03K17/122—Modifications for increasing the maximum permissible switched current in field-effect transistor switches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0009—AC switches, i.e. delivering AC power to a load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to an FET parallel circuit cell and a pseudo high voltage FET module, and more particularly to an FET parallel circuit cell and a pseudo high voltage FET module applicable to a high voltage pulse switching power supply.
  • SiC silicon carbide
  • SiC has a very large dielectric breakdown electric field compared to Si. Therefore, even if the drift layer film thickness for giving a withstand voltage is formed relatively thin and the carrier concentration is formed relatively high, it does not break.
  • Si-MISFET Metal-Insulator-Semiconductor-Field-Effect-Transistor
  • a semiconductor switch element is used for a high voltage pulse generation power source that performs high repetition operation, but in order to flow a large current while ensuring a withstand voltage, a circuit connected in series and in parallel is used (for example, refer nonpatent literature 1.).
  • a conventional pulse power supply using a Si-MISFET of 600V or higher as a switching element is suitable for high-speed response and high repetition frequency, but has high on-resistance and cannot flow a large current.
  • an insulated gate bipolar transistor IGBT: Insulated Gate Bipolar Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • Si-MISFET has a high on-resistance, so it does not perform any special timing adjustment beyond circuit pattern adjustment.
  • a conventional control method among the switch elements connected in series when the timing is shifted, When the partial pressure balance is lost, a high voltage is applied locally, and there is a risk that the switch element is destroyed.
  • An object of the present invention is to provide a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module in which a plurality of stages of the FET parallel circuit cells are connected in series and capable of switching a large current at a frequency in the MHz range.
  • a plurality of SiC-MISFETs connected in parallel, a plurality of gate drive circuits respectively connected to the gates of the plurality of SiC-MISFETs,
  • An FET parallel circuit cell including an OE converter that supplies a gate drive signal to a gate drive circuit, and a plurality of the gate drive circuits and an isolated DC / DC converter that supplies power to the OE converter is provided.
  • a pseudo high voltage FET module includes a pulse delay circuit that can be controlled on / off substantially simultaneously.
  • a plurality of SiC-MISFET AC load circuits connected in parallel, a plurality of gate drive circuits respectively connected to the gates of the plurality of SiC-MISFET AC load circuits
  • an MIS relay circuit cell comprising an OE converter that supplies a gate drive signal to a gate drive circuit, and a plurality of the gate drive circuits and an isolated DC / DC converter that supplies power to the OE converter.
  • a switching circuit in which a plurality of MIS type relay circuit cells are connected in series and a plurality of the MIS type relay circuit cells constituting the switching circuit are connected to each other, and a plurality of the MIS types are connected.
  • a pseudo high voltage FET module comprising a pulse delay circuit capable of controlling on / off of substantially simultaneous relay circuit cells.
  • the present invention it is possible to provide a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module in which a plurality of stages of the FET parallel circuit cells are serialized and capable of switching a large current at an MHz class frequency.
  • the typical circuit block diagram of the FET parallel circuit cell which concerns on basic technology.
  • the typical circuit block block diagram of the pseudo high voltage FET module which concerns on a basic technique.
  • the typical circuit block diagram of the FET parallel circuit cell which concerns on 1st Embodiment.
  • the typical circuit block block diagram of the pseudo high voltage FET module which concerns on 1st Embodiment.
  • the typical circuit block diagram of the FET parallel circuit cell which concerns on 2nd Embodiment.
  • the typical block block diagram of the FET parallel circuit cell which concerns on 3rd Embodiment to which the transformer insulation type DC / DC converter is applied.
  • the typical block block diagram of the FET parallel circuit cell which concerns on 3rd Embodiment to which a wireless electric power feeding type DC / DC converter is applied.
  • FIG. 4 is a schematic cross-sectional structure diagram of a SiC DIMISFET, which is an example of a semiconductor device applicable to the pseudo high voltage FET module according to the embodiment. It is an example of the semiconductor device applicable to the pseudo high voltage FET module which concerns on embodiment, Comprising: The typical cross-section figure of SiC TMISFET.
  • the FET parallel circuit cell 10A includes a plurality of Si-MISFETs Q M1 , Q M2 , Q M3 ,..., Q M6 and a plurality of Si-MISFETs Q M1 , Q M2 connected in parallel. , Q M3 ,..., Q M6 , a plurality of gate drive circuits 12 1 A, 12 2 A, 12 3 A,..., 12 6 A and a plurality of gate drive circuits 12 1 A, 12 2, respectively.
  • OE converter 14A supplies a gate drive signal to a, a plurality of gate drive circuits 12 1 a, 12 2 a, 12 3 a, ..., 12 6 a and OE converter And an isolated DC / DC converter 16A that supplies power to 14A.
  • An ON / OFF signal is supplied to the OE converter 14A via the optical fiber cable 18A, while a DC voltage of, for example, + 24V is supplied to the insulated DC / DC converter 16A via the gate drive voltage supply line 20A. Is supplied.
  • Si-MISFETQ M1, Q M2, Q M3, ..., the drain of Q M6 are commonly connected to the positive power terminal P (+), Si-MISFETQ M1, Q M2, Q M3, ..., the source of Q M6 is Are connected in common to the negative power terminal N ( ⁇ ).
  • the pseudo high voltage FET module 1A includes a switching circuit 4A in which a plurality of FET parallel circuit cells 10A are connected in series, and a plurality of FET parallel circuits constituting the switching circuit 4A.
  • cell 10 1 a, 10 2 a, 10 3 a, ..., 10 8 respectively a fiber optic cable 18 1 a, 18 2 a, 18 3 a, ..., 18 8 via the a connected EO converter 22 1 A, 22 2 A, 22 3 A,..., 22 8 A.
  • the optical fiber cables 18 1 A, 18 2 A, 18 3 A,..., 18 8 A can be bundled as an optical fiber cable bundle 180A.
  • the switching circuit 4A connected in series in a plurality of stages is connected to the global drain terminal D (+) on the drain side of the FET parallel circuit cell 10 1 A, and the global source terminal S ( ⁇ ) on the source side of the FET parallel circuit cell 10 8 A. Connected to.
  • the electrical input sides of the EO converters 22 1 A, 22 2 A, 22 3 A,..., 22 8 A are connected to the global gate terminal G through the buffer circuit 21A.
  • a multi-series circuit of Si-MISFETs Q M1 , Q M2 , Q M3 ,..., Q M6 is configured. That is, 6 parallel Si-MISFETQ M1, Q M2, Q M3, ..., 1 FET parallel circuit cell 10 includes a Q M6 A, 10 2 A, 10 3 A, ..., a 10 8 A connected to the 8 series, the pseudo A high voltage FET module 1A is realized.
  • the pseudo-high-voltage FET module 1A according to the basic technique, Si-MISFETQ M1, Q M2 , Q M3, ..., as Q M6, rated switching voltage 700 V, is applied to Si-MISFET rated switching current 100A, Switching performance of a rated switching voltage of 5.6 kV and a rated switching current of 600 A can be realized.
  • the FET parallel circuit cell 10 includes a plurality of SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 and a plurality of SiC-MISFET Qs connected in parallel.
  • the OE converter 14 supplies a gate drive signal to 6, a plurality of gate drive circuits 12 1, 12 2, 12 3, ..., 12 6 and insulated supplies power to OE converter 14 And a DC / DC converter 16.
  • the OE converter 14 is supplied with an ON / OFF signal via an optical fiber cable 18, while the insulated DC / DC converter 16 is supplied with a DC voltage of, for example, + 24V via a gate drive voltage supply line 20. Is supplied. SiC-MISFETQ S1, Q S2, Q S3, ..., the drain of Q S6 are commonly connected to the positive power terminal P (+), SiC-MISFETQ S1, Q S2, Q S3, ..., the source of Q S6 is Are connected in common to the negative power terminal N ( ⁇ ).
  • the OE converter 14 is a photoelectric conversion element, and for example, a photo coupler, a fiber coupler, or the like is applicable.
  • applicable SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 have, for example, a rated drain-source voltage of 1200 V and a rated drain pulse current of 80 A on a general specification.
  • SiC-MISFET has a large avalanche breakdown margin with respect to the rated drain-source voltage.
  • a 1200-V SiC-MISFET operates without avalanche breakdown up to about 1700 V with respect to a pulsed voltage.
  • a 3300V SiC-MISFET operates without avalanche breakdown up to about 4000V for a pulsed voltage.
  • the reason why the avalanche breakdown voltage is set high in the SiC-MISFET is as follows.
  • a gate insulating film (132: see FIG. 12 and FIG. 13) formed of SiO 2 obtained by oxidizing SiC, a part of carbon (C) atoms remains at the SiC / SiO 2 interface, and the interface state. Reduce density. For this reason, it is difficult to increase the thickness of the gate insulating film (SiO 2 ).
  • the pseudo high voltage FET module 1 includes a switching circuit 4 in which a plurality of FET parallel circuit cells 10 are connected in series, and a plurality of FETs constituting the switching circuit 4.
  • each optical fiber cable 18 1, 18 2, 18 3, ..., 18 a plurality of EO converter 22 connected 8 via a 1, 22 2, 22 3, ..., 22 8, a plurality of EO converter 22 1, 22 2, 22 3, ..., are connected to 22 8, more FET parallel circuit cells 10 1 constituting the switching circuit 4, 10 2, 10 3, ..., 10 8 substantially simultaneously oN / oFF controllable plurality of pulse delay circuit 24 1, 24 2, 24 3, ..., and a 24 8.
  • the optical fiber cables 18 1 , 18 2 , 18 3 ,..., 18 8 can be bundled as an optical fiber cable bundle 180.
  • the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 can be configured by, for example, FPGA (Field Programmable Gate Array) circuits.
  • the switching circuit 4 in which a plurality of FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 are connected in series is connected to the global drain terminal D (+) on the drain side of the FET parallel circuit cell 10 1.
  • the FET parallel circuit cell 10 8 is connected to the global source terminal S ( ⁇ ) on the source side.
  • the input sides of the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 are connected to the global gate terminal G through the buffer circuit 21.
  • the rise characteristics of m ⁇ n SiC-MISFETs arranged in m rows and n columns are measured to extract from the SiC-MISFET having the fastest rise time to the m-th fastest SiC-MISFET.
  • FIG. 3 as shown in- Figure 4, SiC-MISFETQ S1, Q S2, Q S3, ..., a plurality of FET parallel circuit cells 10 1 by Q S6, 10 2, 10 3, ... 10 8 are connected in series to realize the pseudo high voltage FET module 1.
  • SiC-MISFET is smaller the normalized on-resistance than 1/10 as compared with the Si-MISFET, each FET parallel circuit cells 10 1, 10 2, 10 3, ..., to substantially simultaneously turned on / off 10 8 Therefore, it is necessary to take special care and countermeasures. This is because if the FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 have different switching timings, the partial pressure balance is lost and an excessive voltage is generated in a specific FET parallel circuit cell. .
  • each FET parallel circuit cell 10 1 , 10 2 , 10 3 ,..., 10 8 is within plus or minus several ns, for example plus or minus 1 ns. Can be turned on / off within. Therefore, the FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 can be turned on / off substantially simultaneously.
  • the pseudo high voltage FET module 1 having a rated switching voltage of 9.6 kV and a rated switching current of 480 A can be realized.
  • SiC can maintain an off state even at 200 ° C. or higher as compared with Si, the frequency can be increased repeatedly with the same heat dissipation system as in the prior art.
  • the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially simultaneously, and the partial pressure balance of the FET parallel circuit cell can be controlled. It is possible to provide a pseudo high voltage FET module that can be well maintained and can switch a large current at a frequency in the MHz range.
  • an FET parallel circuit cell 10 As shown in FIG. 5, an FET parallel circuit cell 10 according to the second exemplary embodiment is connected in parallel with SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 and absorbs a surge voltage. 26.
  • the surge absorbing circuit 26 may include a constant voltage element, an avalanche diode (ABD: Avalanche Breakdown Diode), or the like.
  • ABS Avalanche Breakdown Diode
  • SiC-MISFETQ S1, Q S2, Q S3, ..., Q S6 and the surge absorption circuit more FET parallel circuit cells 10 1 with a 26, 10 2, 10 3 ,..., 10 8 can be connected in series to realize the pseudo high voltage FET module 1.
  • a SiC-MISFET having a rated drain-source voltage of 1200 V and a rated drain pulse current of 80 A is applied as the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6
  • the rated switching voltage is 9.6 kV and the rated switching current is 480 A
  • the pseudo high voltage FET module 1 can be realized.
  • SiC-MISFET has a large margin for the rated drain-source voltage.
  • a SiC-MISFET with a withstand voltage of 1200 V operates without avalanche breakdown up to about 1700 V with respect to a pulse voltage.
  • a 3300V SiC-MISFET operates without avalanche breakdown up to about 4000V for a pulsed voltage.
  • the 2 FET also each in the exemplary pseudo-high-voltage FET module according to the parallel circuit cells 10 1, 10 2, 10 3, ..., the pulse delay circuit 24 every 10 8 1, 24 2, 24 3, ..., 24 8 by installing, by adjusting the on-delay time and oFF-delay time, the FET parallel circuit cells 10 1, 10 2, 10 3, ..., and the circuit is substantially almost simultaneously turned on / off configuration 10 8 can do.
  • FET parallel circuit cells 10 1, 10 2, 10 3, ..., 10 8 for example, by installing a surge absorption circuit 26 due ABD (avalanche breakdown diode), Even if the parallel FET circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 are not suddenly completely turned on / off at the same time, they are turned on / off within ⁇ 10 ns, for example, within ⁇ 20 ns. Thus, the pseudo high voltage FET module 1 capable of normal operation can be realized.
  • ABD avalanche breakdown diode
  • the surge absorbing circuit 26 In the surge absorbing circuit 26, four ABDs having a breakdown voltage of about 350V are connected in series, and it is possible to avoid applying an excessive voltage exceeding 1400V to the SiC-MISFET.
  • an FET parallel circuit cell capable of absorbing a voltage surge higher than an avalanche breakdown voltage by ABD.
  • the voltage value per unit FET parallel circuit cell can be defined by the avalanche breakdown voltage of the ABD when ABDs are connected in parallel.
  • the avalanche breakdown voltage of the ABD is designed to be higher than the rated drain-source voltage of the SiC-MISFET and lower than the avalanche breakdown voltage of the SiC-MISFET.
  • the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module that can maintain a good pressure balance and can switch a large current at a frequency in the MHz range.
  • FIG. 1 A schematic block configuration of the FET parallel circuit cell 34A according to the third embodiment to which the transformer insulation type DC / DC converter 28A is applied is expressed as shown in FIG.
  • the FET parallel circuit cell 34A includes a transformer insulated DC / DC converter 28A, a SiC-MISFET drive circuit 30A connected to the transformer insulated DC / DC converter 28A, and a 6 connected to the SiC-MISFET drive circuit 30A. And a parallel SiC-MISFET circuit 32A.
  • the transformer-isolated DC / DC converter 28A supplies a DC voltage V DD to the SiC-MISFET drive circuit 30A, and the SiC-MISFET drive circuit 30A sends a gate drive signal FD to the 6-parallel SiC-MISFET circuit 32A. Supply.
  • the SiC-MISFET drive circuit 30A corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32A corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS.
  • the insulation breakdown voltage V BM is several tens of kV at the maximum.
  • FIG. 1 A schematic block configuration of the FET parallel circuit cell 34 according to the third embodiment to which the wireless power feeding type isolated DC / DC converter 28 is applied is expressed as shown in FIG.
  • the FET parallel circuit cell 34 includes a wireless power feeding type isolated DC / DC converter 28 and a SiC- connected to the insulated DC / DC converter 28.
  • a MISFET drive circuit 30 and a 6 parallel SiC-MISFET circuit 32 connected to the SiC-MISFET drive circuit 30 are provided.
  • the isolated DC / DC converter 28 supplies the DC voltage V DD to the SiC-MISFET drive circuit 30, and the SiC-MISFET drive circuit 30 supplies the gate drive signal FD to the 6-parallel SiC-MISFET circuit 32. Supply.
  • the SiC-MISFET drive circuit 30 corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32 corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS.
  • the wireless power feeding type isolated DC / DC converter 28 can wirelessly feed power from an oscillation circuit 38, a primary coil L1 connected to the oscillation circuit 38, and the primary coil L1.
  • a secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided.
  • the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S.
  • the creepage distance L S between the primary coil L1 and the secondary coil L2 is set according to the value of the dielectric breakdown electric field.
  • a housing 36 that includes the oscillation circuit 38 and the primary coil L1 and can control the withstand voltage V BS of the isolated DC / DC converter 28 may be provided.
  • the container 36 may be formed of resin or ceramics.
  • the withstand voltage value can be controlled by the thickness of the resin or ceramic. For example, when polyethylene resin is used, the dielectric breakdown electric field is about 50 kV / mm.
  • the value of the insulation withstand voltage V BS is several hundred kV or more at the maximum.
  • a dielectric breakdown electric field of 1 MV / 8 mm and about 120 kV / mm or more by using a resin box as the container 36.
  • the resin for example, Teflon (registered trademark), polyethylene, or the like is applicable.
  • a pseudo high voltage FET module can be realized by connecting a plurality of FET parallel circuit cells in series as in the first and second embodiments.
  • a pseudo high voltage FET module having a rated switching voltage of several hundred kV or more by mounting an ultra-high withstand voltage insulated DC / DC converter using a wireless power feeding circuit.
  • An FET module can be realized.
  • the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module for an ultra-high withstand voltage that can maintain a good current and can switch a large current at a frequency in the MHz range.
  • the ABD when the ABD is connected to the FET parallel circuit cell, it is possible to provide an ultra-high withstand voltage FET parallel circuit cell capable of absorbing a voltage surge higher than the avalanche breakdown voltage.
  • the FET parallel circuit cell 34 is connected to a wireless power feeding type insulated DC / DC converter 28 and an insulated DC / DC converter 28.
  • the SiC-MISFET drive circuit 30 and a 6 parallel SiC-MISFET circuit 32 connected to the SiC-MISFET drive circuit 30 are provided.
  • the SiC-MISFET drive circuit 30 corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32 corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS.
  • the isolated DC / DC converter 28 supplies the DC voltage V DD to the SiC-MISFET drive circuit 30, and the SiC-MISFET drive circuit 30 supplies the gate drive signal FD to the 6-parallel SiC-MISFET circuit 32. Supply.
  • the wireless power feeding type isolated DC / DC converter 28 can wirelessly feed power from the oscillation circuit 38, the primary coil L1 connected to the oscillation circuit 38, and the primary coil L1.
  • a secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided.
  • the FET parallel circuit cell 34 includes a storage circuit 42 connected between the output of the rectifier circuit 40 and the input of the SiC-MISFET drive circuit 30 as shown in FIG. Prepare.
  • a lithium ion battery, a super capacitor, an electric double tank capacitor (EDLC: Electric Double-Layer Capacitor), or the like can be applied to the power storage circuit 42.
  • the first anode is connected to the output of the rectifier circuit 40 and the input to the SiC-MISFET drive circuit 30 is the second as shown in FIG.
  • a first butt diode DT1 connected to one cathode, a second anode connected to the output of the rectifier circuit 40 via the storage circuit 42, and a second cathode connected to the input of the SiC-MISFET drive circuit 30.
  • a butt diode DT2 may be provided.
  • the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S.
  • Other configurations are the same as those of the FET parallel circuit cell 34 according to the third embodiment.
  • each FET parallel circuit cell 34 can be turned off simultaneously even when the DC + 24V power supply is lost. Even when the DC + 24V power supply is lost, the SiC-MISFET in the circuit can be prevented from being destroyed by the abnormal voltage, so that a highly reliable pseudo high voltage FET module can be realized.
  • the insulation withstand voltage is achieved by mounting an ultra-high withstand voltage isolated DC / DC converter using a wireless power feeding circuit. It is possible to realize a pseudo-high-voltage FET module having a maximum number 100kV or more of the rated switching voltage as V BS.
  • the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serialized can be controlled on / off substantially simultaneously. It is possible to provide a pseudo high voltage FET module for an ultra-high withstand voltage capable of maintaining a good cell partial pressure balance and switching a large current at a frequency in the MHz range.
  • the SiC-MISFET constituting the FET parallel circuit cell according to the first to third embodiments may be a bipolar type capable of switching an AC load.
  • the MIS relay circuit cell 44 includes a plurality of SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,.
  • a plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 respectively connected to the gates of the plurality of SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,.
  • the gate drive circuit 12 1, 12 2, 12 3, ..., 12 and the OE converter 14 supplies a gate drive signal to 6, a plurality of gate drive circuits 12 1, 12 2, 12 3, ..., 12 6 and OE conversion And an insulated DC / DC converter 16 for supplying power to the device 14.
  • the OE converter 14 is supplied with an ON / OFF signal via an optical fiber cable 18, while the insulated DC / DC converter 16 is supplied with a DC voltage of, for example, + 24V via a gate drive voltage supply line 20. Is supplied.
  • One drain of each of the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 is commonly connected to the positive side AC terminal TA, and the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 , ..., the other drain of Q A6 is commonly connected to the negative AC terminal TB.
  • FIG. 1 a circuit configuration example of the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 of the MIS type relay circuit cell 44 according to the fourth embodiment is as shown in FIG.
  • Another circuit configuration example is expressed as shown in FIG.
  • a bidirectional switch capable of switching an AC load can be realized by connecting two SiC-MOSFETs in series with a common source.
  • the SiC-MISFET AC load circuit Q A is connected in series with the first SiC-MISFET Q SA and the first SiC-MISFET Q SA , and the first SiC-MISFET Q SA is connected to the first SiC-MISFET Q SA .
  • a first SiC-MISFET Q SB in which a first source and a second source are connected in common, and a first gate and a second gate of the first SiC-MISFET Q SA are connected in common, and a first SiC-MISFET Q SA It comprises a first diode D1 which are connected in antiparallel between the main electrodes, and a second diode D2 which are reverse-connected in parallel between the main electrodes of the second SiC-MISFET Q SB.
  • the SiC-MISFET AC load circuit Q A can control the AC current between the first drain of the first SiC-MISFET Q SA and the second drain of the second SiC-MISFET Q SB .
  • the AC current is not parallel diodes D1 and D2, but mainly SiC having a low on-resistance. -Conduct the MOSFET Q SA and Q SB . That is, the SiC-MISFET AC load circuit Q A can perform switching control of the AC current between the AC terminals TA and TB.
  • the SiC-MISFET AC load circuit of the MIS type relay circuit cell 44 is connected in series to the first SiC-MISFET Q1 and the first SiC-MISFET Q1, as shown in FIG. 10 (b).
  • a first reverse blocking switch 50 1 comprising a first diode D1, and a second reverse blocking type comprising a second SiC-MISFET Q2 and a second diode D2 connected in series to the second SiC-MISFET Q2. it may be provided with a switch 50 2.
  • the SiC-MISFET AC load circuit Q A shown in FIG. 10B is capable of switching control of the AC current between the AC terminals TA and TB.
  • the performance of the SiC-MISFETs Q SA , Q SB , Q 1 , Q 2 applicable to the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 for example, rated drain-source voltage 1200V, rated drain pulse current 80A.
  • the insulation type DC / DC converter 16 As the insulation type DC / DC converter 16, a transformer insulation type DC / DC converter or a wireless power feeding type insulation type DC / DC converter can be applied.
  • the insulation breakdown voltage V BM is several tens of kV at the maximum.
  • the value of the breakdown voltage V BS is the maximum number of 100kV or higher.
  • the wireless power feeding type isolated DC / DC converter 28 has an oscillation circuit 38, a primary coil L ⁇ b> 1 connected to the oscillation circuit 38, and a wireless power feeding 2 from the primary coil L ⁇ b> 1.
  • a secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided.
  • the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S.
  • the wireless power supply type isolated DC / DC converter 28 includes an oscillation circuit 38 and a primary side coil L1 as in FIG. 7, and controls the insulation withstand voltage V BS of the isolated DC / DC converter 28.
  • a possible container 36 may be provided.
  • the container 36 may be formed of resin or ceramics.
  • the withstand voltage value can be controlled by the thickness of the resin or ceramic. For example, when polyethylene resin is used, the dielectric breakdown electric field is about 50 kV / mm.
  • a dielectric breakdown electric field of 1 MV / 8 mm and about 120 kV / mm or more by using a resin box as the container 36.
  • the resin for example, Teflon (registered trademark), polyethylene, or the like is applicable.
  • MIS-type relay circuit cell 44 similarly to FIG. 8, the gate drive circuit 12 1 outputs a plurality of rectifier circuits 40, 12 2, 12 3, ..., 12 6 input You may provide the electrical storage circuit 42 connected between.
  • a lithium ion battery, a super capacitor, an electric double tank capacitor (EDLC), or the like can be applied to the power storage circuit 42.
  • the first anode is connected to the output of the rectifier circuit 40 and the first cathode is connected to the input of the SiC-MISFET drive circuit 30 as in FIG.
  • the connected first butt diode DT1, and the second butt diode DT2 whose second anode is connected to the output of the rectifier circuit 40 via the storage circuit 42 and whose second cathode is connected to the input of the SiC-MISFET drive circuit 30. And may be provided.
  • the pseudo high voltage FET module 2 includes a switching circuit 8 in which a plurality of MIS type relay circuit cells 44 are connected in series, and a plurality of switching circuits 8.
  • MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 each optical fiber cable 18 1, 18 2, 18 3, ..., a plurality of EO converter 22 which is connected through a 18 8 1, 22 2, 22 3, ..., 22 8, a plurality of EO converter 22 1, 22 2, 22 3, ..., are connected to 22 8, more MIS type relay circuit cells 44 1 constituting the switching circuit 4, 44 2, 44 3, ..., at the same time oN / oFF controllable plurality of pulse delay circuit 44 8 24 1, 24 2, 24 3, ..., and a 24 8.
  • the optical fiber cables 18 1 , 18 2 , 18 3 ,..., 18 8 can be bundled as an optical fiber cable bundle 180.
  • the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 can be configured by, for example, FPGA circuits.
  • the input sides of the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 are connected to the global gate terminal G through the buffer circuit 21.
  • FIG. 9 as shown in-FIG. 11, SiC-MISFET AC load circuit Q A1, Q A2, Q A3 , ..., a plurality of MIS-type by Q A6 relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 are connected in series, thereby realizing the pseudo-high-voltage FET module 2.
  • the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 the pulse delay circuit 24 1 for each 8, 24 2, 24 3, ... , by installing 24 8, by adjusting the on-delay time and oFF-delay time, the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 within plus or minus the number ns, for example, plus It can be turned on / off within minus 1 ns. Therefore, the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., it is possible to substantially turn on / off simultaneously 44 8.
  • a pseudo high voltage FET module having a rated switching voltage of 9.6 kV and a rated switching current of 480 A 2 can be realized.
  • the MIS type relay circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module (pseudo high voltage MIS type relay module) having a high speed switching performance capable of satisfactorily maintaining the partial pressure balance of the relay circuit cell.
  • the ABD when the ABD is connected to the FET parallel circuit cell, it is possible to provide a MIS type relay circuit cell that can absorb a voltage surge higher than the avalanche breakdown voltage.
  • FIG. 12 shows an example of a semiconductor device 100 applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments, and a schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET. It is expressed as follows.
  • the SiC DIMISFET applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments is epitaxially grown on an n + SiC substrate 124 and an n + SiC substrate 124 as shown in FIG. N ⁇ drift layer 126, p body region 128 formed on the surface side of n ⁇ drift layer 126, n + source region 130 formed on the surface of p body region 128, and n between p body region 128 - a gate insulating layer 132 disposed on the surface of the drift layer 126, a gate electrode 138 disposed on the gate insulating layer 132, electrically connected to the source electrode to the n + source region 130 and the p-body region 128 134 and a drain electrode 136 electrically connected to the surface of the n + SiC substrate 124 opposite to the n ⁇ drift layer 126.
  • a p body region 128 and an n + source region 130 formed on the surface of the p body region 128 are formed by double ion implantation (DI), and the source pad electrode SP is n +.
  • DI double ion implantation
  • the gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating layer 132.
  • the source pad electrode SP / source electrode 134 and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144 that covers the surface of the semiconductor device 100 as shown in FIG.
  • ⁇ SiC TMISFET ⁇ 13 is an example of the semiconductor device 100 applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments, and a schematic cross-sectional structure of the SiC TMISFET is expressed as shown in FIG. .
  • the SiC TMISFET applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments is epitaxially grown on an n + SiC substrate 124 and an n + SiC substrate 124 as shown in FIG. N ⁇ drift layer 126N, p body region 128 formed on the surface side of n ⁇ drift layer 126N, n + source region 130 formed on the surface of p body region 128, and p body region 128.
  • a trench gate electrode 138TG formed through the gate insulating layer 132 and the interlayer insulating films 144U and 144B is formed in the trench formed through the p body region 128 to the semiconductor substrate 126N.
  • the source pad electrode SP is connected to the source electrode 134 connected to the source region 130 and the p body region 128.
  • the gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate layer 132.
  • the source pad electrode SP / source electrode 134 and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144U that covers the surface of the semiconductor device 100 as shown in FIG.
  • the SiC-TMISFET does not have a junction resistance extending from the p body region 128 in the drain current path, it is possible to provide a FET having a lower on-resistance than SIC DMISFET, and more than 100 A per element can be provided. It is also possible to allow a drain pulse current.
  • a GaN-based FET or the like can be applied to the semiconductor device 100 applicable to the pseudo high-voltage FET modules 1 and 2 according to the first to fourth embodiments instead of the SiC-based MISFET.
  • the SiC device has a high breakdown electric field (for example, about 3 MV / cm, about 3 times that of Si), the drift layer is made thinner and the carrier concentration is set higher than that of Si. Can withstand pressure. Due to the difference in the breakdown electric field, the peak electric field strength of the SiC-MISFET can be set higher than the peak electric field strength of the Si-MISFET.
  • n - thin thickness of the drift layer 126 ⁇ 126N required n - thin thickness of the drift layer 126 ⁇ 126N, by both the benefits of carrier concentration and thickness, n - reducing the resistance of the drift layer 126 ⁇ 126N, resistance R on The chip area can be reduced (smaller chip). Further, since the MISFET structure which is a unipolar device can be used, a breakdown voltage comparable to that of a Si IGBT can be realized, so that a high breakdown voltage and high-speed switching can be realized, and a reduction in switching loss can be expected.
  • a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module capable of switching a large current at a frequency in the MHz class, in which a plurality of FET parallel circuit cells are serialized, are provided. be able to.
  • the gate-source voltage at the gate-off time may be pulled to the negative voltage side for the purpose of speeding up the FET operation or avoiding malfunction.
  • the FET parallel circuit cell and pseudo high voltage FET module of the present invention can be applied to a wide range of application fields such as a pulse power generator having a high voltage high speed switch using a power SiC-MISFET and a high repetition voltage high voltage pulse power generator. .

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Abstract

　FET parallel circuit cells (101-108) are provided with a plurality of SiC-MISFETs coupled in parallel, a plurality of gate drive circuits coupled to each of the gates of the plurality of SiC-MISFETs, an OE converter for feeding gate drive signals to the gate drive circuits, and an insulated DC/DC converter for feeding electrical power to the gate drive circuits and the OE converter, and an artificial high-voltage FET module (1) is provided with switching circuits (4) that couple in series the plurality of FET parallel circuit cells (101-108), EO converters (221-228) coupled to the plurality of FET parallel circuit cells via optic fiber cables (181-188), and pulse delay circuits (241-248) that are coupled to the EO converters and are able to carry out on-off control of the plurality of FET parallel circuit cells at substantially the same time. The present invention provides SiC-MISFET parallel circuit cells and an artificial high-voltage FET module that is able to switch high currents at MHz-level frequencies.

Description

ＦＥＴ並列回路セルおよび疑似高電圧ＦＥＴモジュールFET parallel circuit cell and pseudo high voltage FET module
　本発明は、ＦＥＴ並列回路セルおよび疑似高電圧ＦＥＴモジュールに関し、特に、高電圧パルススイッチング電源に適用可能なＦＥＴ並列回路セルおよび疑似高電圧ＦＥＴモジュールに関する。 The present invention relates to an FET parallel circuit cell and a pseudo high voltage FET module, and more particularly to an FET parallel circuit cell and a pseudo high voltage FET module applicable to a high voltage pulse switching power supply.
　現在多くの研究機関において、シリコンカーバイド（ＳｉＣ：Silicon Carbide）デバイスの研究開発が行われている。ＳｉＣパワーデバイスの特徴として、従来のＳｉパワーデバイスよりも優れた低オン抵抗、高速スイッチングおよび高温動作などを挙げることができる（例えば、特許文献１および特許文献２、３参照。）。 Currently, many research institutes are conducting research and development of silicon carbide (SiC) devices. The characteristics of the SiC power device include a low on-resistance, high-speed switching, and high-temperature operation that are superior to conventional Si power devices (see, for example, Patent Document 1 and Patent Documents 2 and 3).
　ＳｉＣは、絶縁破壊電界がＳｉと比較して非常に大きい。したがって、耐圧を持たせるためのドリフト層膜厚を相対的に薄く形成し、また、キャリア濃度を相対的に濃く形成しても破壊しない。 SiC has a very large dielectric breakdown electric field compared to Si. Therefore, even if the drift layer film thickness for giving a withstand voltage is formed relatively thin and the carrier concentration is formed relatively high, it does not break.
　そのため、従来のシリコン金属絶縁物半導体電界効果トランジスタ（Ｓｉ－ＭＩＳＦＥＴ：Metal Insulator Semiconductor Field Effect Transistor）と比較して、ＳｉＣ－ＭＩＳＦＥＴでは、非常に小さいオン抵抗を実現できる。 Therefore, compared to the conventional silicon metal insulator semiconductor field effect transistor (Si-MISFET: Metal-Insulator-Semiconductor-Field-Effect-Transistor), the SiC-MISFET can realize a very small on-resistance.
　一方、高繰り返し運転を行う高電圧パルス発生電源には半導体スイッチ素子が使われるが、耐圧を確保しつつ、大電流を流すためには、直列、並列接続させた回路を構成して使用する（例えば、非特許文献１参照。）。 On the other hand, a semiconductor switch element is used for a high voltage pulse generation power source that performs high repetition operation, but in order to flow a large current while ensuring a withstand voltage, a circuit connected in series and in parallel is used ( For example, refer nonpatent literature 1.).
特開２００５－１８３４６３号公報JP 2005-183463 A 特開２００７－３０５９６２号公報JP 2007-305962 A 特開平１０－３０８５１０号公報Japanese Patent Laid-Open No. 10-308510
　従来の６００Ｖ以上のＳｉ－ＭＩＳＦＥＴをスイッチ素子として使用するパルス電源は高速応答、繰り返し周波数の高周波化に適しているが、オン抵抗が高く大電流が流せない。一方、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ：Insulated Gate Bipolar Transistor）は立ち上がり時間は速いためパルス電源に用いることができるが、立ち下がり時間が遅いため繰り返し周波数は高くできない。 A conventional pulse power supply using a Si-MISFET of 600V or higher as a switching element is suitable for high-speed response and high repetition frequency, but has high on-resistance and cannot flow a large current. On the other hand, an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) can be used for a pulse power supply because its rise time is fast, but the repetition frequency cannot be increased because the fall time is slow.
　したがって、オン抵抗が小さく耐圧の高いＭＩＳＦＥＴの導入ができれば高周波・大電流スイッチができるようになり、加速器、半導体リソグラフィ用ＥＵＶ（Extreme Ultraviolet）光源などの高出力化が可能になったり、直列・並列接続させる素子数を低減できると考えられる。 Therefore, if a MISFET with a small on-resistance and high withstand voltage can be introduced, a high-frequency and large-current switch can be realized, and it becomes possible to increase the output of an accelerator, an EUV (Extreme 半導体 Ultraviolet) light source for semiconductor lithography, or in series / parallel. It is considered that the number of elements to be connected can be reduced.
　しかし、オン抵抗の低いＳｉＣ－ＭＩＳＦＥＴを導入しようとした場合、１素子当たり数１０Ａから数１００Ａ以上の大電流が瞬間的に流れるようになるため、特に直列接続されたスイッチ素子群間のタイミングを合わせることが課題となる。 However, when trying to introduce a SiC-MISFET having a low on-resistance, a large current of several tens of to several hundreds of A per element flows instantaneously, so the timing between switch elements connected in series is particularly high. Matching is a challenge.
　Ｓｉ－ＭＩＳＦＥＴではオン抵抗が高いため回路パターンの調整以上の特段のタイミング合わせは行っていないが、このような従来の制御方法では、タイミングがずれた場合に直列接続されたスイッチ素子群の中で分圧のバランスが崩れることで局所的に高電圧が印加され、スイッチ素子が破壊する危険があった。 Si-MISFET has a high on-resistance, so it does not perform any special timing adjustment beyond circuit pattern adjustment. However, in such a conventional control method, among the switch elements connected in series when the timing is shifted, When the partial pressure balance is lost, a high voltage is applied locally, and there is a risk that the switch element is destroyed.
　本発明の目的は、ＳｉＣ－ＭＩＳＦＥＴ並列回路セルおよびこのＦＥＴ並列回路セルを複数段直列化した、大電流をＭＨｚ級の周波数でスイッチング可能な疑似高電圧ＦＥＴモジュールを提供することにある。 An object of the present invention is to provide a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module in which a plurality of stages of the FET parallel circuit cells are connected in series and capable of switching a large current at a frequency in the MHz range.
　上記目的を達成するための本発明の一態様によれば、並列接続された複数のＳｉＣ－ＭＩＳＦＥＴと、複数の前記ＳｉＣ－ＭＩＳＦＥＴのゲートにそれぞれ接続された複数のゲートドライブ回路と、複数の前記ゲートドライブ回路にゲート駆動信号を供給するＯＥ変換器と、複数の前記ゲートドライブ回路と前記ＯＥ変換器に電源を供給する絶縁型ＤＣ／ＤＣ変換器とを備えるＦＥＴ並列回路セルが提供される。 According to one aspect of the present invention for achieving the above object, a plurality of SiC-MISFETs connected in parallel, a plurality of gate drive circuits respectively connected to the gates of the plurality of SiC-MISFETs, An FET parallel circuit cell including an OE converter that supplies a gate drive signal to a gate drive circuit, and a plurality of the gate drive circuits and an isolated DC / DC converter that supplies power to the OE converter is provided.
　本発明の他の態様によれば、上記のＦＥＴ並列回路セルを複数段直列接続したスイッチング回路と、前記スイッチング回路を構成する複数のＦＥＴ並列回路セルにそれぞれ接続され、複数のＦＥＴ並列回路セルを実質的に同時にオン／オフ制御可能なパルスディレー回路とを備える疑似高電圧ＦＥＴモジュールが提供される。 According to another aspect of the present invention, a switching circuit in which a plurality of FET parallel circuit cells are connected in series, and a plurality of FET parallel circuit cells constituting the switching circuit, respectively, A pseudo high voltage FET module is provided that includes a pulse delay circuit that can be controlled on / off substantially simultaneously.
　本発明の他の態様によれば、並列接続された複数のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路と、複数の前記ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路のゲートにそれぞれ接続された複数のゲートドライブ回路と、複数の前記ゲートドライブ回路にゲート駆動信号を供給するＯＥ変換器と、複数の前記ゲートドライブ回路と前記ＯＥ変換器に電源を供給する絶縁型ＤＣ／ＤＣ変換器とを備えるＭＩＳ型リレー回路セルが提供される。 According to another aspect of the present invention, a plurality of SiC-MISFET AC load circuits connected in parallel, a plurality of gate drive circuits respectively connected to the gates of the plurality of SiC-MISFET AC load circuits, Provided is an MIS relay circuit cell comprising an OE converter that supplies a gate drive signal to a gate drive circuit, and a plurality of the gate drive circuits and an isolated DC / DC converter that supplies power to the OE converter. .
　本発明の他の態様によれば、上記のＭＩＳ型リレー回路セルを複数段直列接続したスイッチング回路と、前記スイッチング回路を構成する複数の前記ＭＩＳ型リレー回路セルにそれぞれ接続され、複数の前記ＭＩＳ型リレー回路セルを実質的に同時にオン／オフ制御可能なパルスディレー回路とを備える疑似高電圧ＦＥＴモジュールが提供される。 According to another aspect of the present invention, a switching circuit in which a plurality of MIS type relay circuit cells are connected in series and a plurality of the MIS type relay circuit cells constituting the switching circuit are connected to each other, and a plurality of the MIS types are connected. There is provided a pseudo high voltage FET module comprising a pulse delay circuit capable of controlling on / off of substantially simultaneous relay circuit cells.
　本発明によれば、ＳｉＣ―ＭＩＳＦＥＴ並列回路セルおよびこのＦＥＴ並列回路セルを複数段直列化した、大電流をＭＨｚ級の周波数でスイッチング可能な疑似高電圧ＦＥＴモジュールを提供することができる。 According to the present invention, it is possible to provide a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module in which a plurality of stages of the FET parallel circuit cells are serialized and capable of switching a large current at an MHz class frequency.
基本技術に係るＦＥＴ並列回路セルの模式的回路構成図。The typical circuit block diagram of the FET parallel circuit cell which concerns on basic technology. 基本技術に係る疑似高電圧ＦＥＴモジュールの模式的回路ブロック構成図。The typical circuit block block diagram of the pseudo high voltage FET module which concerns on a basic technique. 第１の実施の形態に係るＦＥＴ並列回路セルの模式的回路構成図。The typical circuit block diagram of the FET parallel circuit cell which concerns on 1st Embodiment. 第１の実施の形態に係る疑似高電圧ＦＥＴモジュールの模式的回路ブロック構成図。The typical circuit block block diagram of the pseudo high voltage FET module which concerns on 1st Embodiment. 第２の実施の形態に係るＦＥＴ並列回路セルの模式的回路構成図。The typical circuit block diagram of the FET parallel circuit cell which concerns on 2nd Embodiment. トランス絶縁型ＤＣ／ＤＣ変換器を適用した第３の実施の形態に係るＦＥＴ並列回路セルの模式的ブロック構成図。The typical block block diagram of the FET parallel circuit cell which concerns on 3rd Embodiment to which the transformer insulation type DC / DC converter is applied. ワイヤレス給電型ＤＣ／ＤＣ変換器を適用した第３の実施の形態に係るＦＥＴ並列回路セルの模式的ブロック構成図。The typical block block diagram of the FET parallel circuit cell which concerns on 3rd Embodiment to which a wireless electric power feeding type DC / DC converter is applied. ワイヤレス給電型ＤＣ／ＤＣ変換器を適用した第３の実施の形態の変形例に係るＦＥＴ並列回路セルの模式的ブロック構成図。The typical block block diagram of the FET parallel circuit cell which concerns on the modification of 3rd Embodiment to which a wireless electric power feeding type DC / DC converter is applied. 第４の実施の形態に係るＭＩＳ型リレー回路セルの模式的回路構成図。The typical circuit block diagram of the MIS type | mold relay circuit cell which concerns on 4th Embodiment. （ａ）第４の実施の形態に係るＭＩＳ型リレー回路セルのＦＥＴＡＣ負荷回路の回路構成例、（ｂ）別の回路構成例。(A) The circuit structural example of the FETAC load circuit of the MIS type relay circuit cell concerning 4th Embodiment, (b) Another circuit structural example. 第４の実施の形態に係る疑似高電圧ＦＥＴモジュールの模式的回路ブロック構成図。The typical circuit block block diagram of the pseudo high voltage FET module which concerns on 4th Embodiment. 実施の形態に係る疑似高電圧ＦＥＴモジュールに適用可能な半導体デバイスの例であって、ＳｉＣ　ＤＩＭＩＳＦＥＴの模式的断面構造図。FIG. 4 is a schematic cross-sectional structure diagram of a SiC DIMISFET, which is an example of a semiconductor device applicable to the pseudo high voltage FET module according to the embodiment. 実施の形態に係る疑似高電圧ＦＥＴモジュールに適用可能な半導体デバイスの例であって、ＳｉＣ　ＴＭＩＳＦＥＴの模式的断面構造図。It is an example of the semiconductor device applicable to the pseudo high voltage FET module which concerns on embodiment, Comprising: The typical cross-section figure of SiC TMISFET.
　次に、図面を参照して、実施の形態を説明する。以下の図面の記載において、同一または類似の部分には同一または類似の符号を付している。但し、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることはもちろんである。 Next, embodiments will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.
　また、以下に示す実施の形態は、この発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の実施の形態は、構成部品の材質、形状、構造、配置等を下記のものに特定するものでない。この発明の実施の形態は、特許請求の範囲において、種々の変更を加えることができる。 Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, The layout is not specified as follows. Various modifications can be made to the embodiment of the present invention within the scope of the claims.
　[基本技術]
　基本技術に係るＦＥＴ並列回路セル１０Ａは、図１に示すように、並列接続された複数のＳｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6と、複数のＳｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6のゲートにそれぞれ接続された複数のゲートドライブ回路１２1Ａ、１２2Ａ、１２3Ａ、…、１２6Ａと、複数のゲートドライブ回路１２1Ａ、１２2Ａ、１２3Ａ、…、１２6Ａにゲート駆動信号を供給するＯＥ変換器１４Ａと、複数のゲートドライブ回路１２1Ａ、１２2Ａ、１２3Ａ、…、１２6ＡとＯＥ変換器１４Ａに電源を供給する絶縁型ＤＣ／ＤＣ変換器１６Ａとを備える。ＯＥ変換器１４Ａには、光ファイバーケーブル１８Ａを介してＯＮ／ＯＦＦ信号が供給され、一方、絶縁型ＤＣ／ＤＣ変換器１６Ａには、ゲートドライブ電圧供給線２０Ａを介して、例えば、＋２４ＶのＤＣ電圧が供給される。Ｓｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6のドレインは、正側電力端子Ｐ（＋）に共通接続され、Ｓｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6のソースは、負側電力端子Ｎ（－）に共通接続されている。 [Basic technology]
As shown in FIG. 1, the FET parallel circuit cell 10A according to the basic technology includes a plurality of Si-MISFETs Q M1 , Q M2 , Q M3 ,..., Q M6 and a plurality of Si-MISFETs Q M1 , Q M2 connected in parallel. , Q M3 ,..., Q M6 , a plurality of gate drive circuits 12 1 A, 12 2 A, 12 3 A,..., 12 6 A and a plurality of gate drive circuits 12 1 A, 12 2, respectively. a, 12 3 a, ..., 12 6 and OE converter 14A supplies a gate drive signal to a, a plurality of gate drive circuits 12 1 a, 12 2 a, 12 3 a, ..., 12 6 a and OE converter And an isolated DC / DC converter 16A that supplies power to 14A. An ON / OFF signal is supplied to the OE converter 14A via the optical fiber cable 18A, while a DC voltage of, for example, + 24V is supplied to the insulated DC / DC converter 16A via the gate drive voltage supply line 20A. Is supplied. Si-MISFETQ M1, Q M2, Q M3, ..., the drain of Q M6 are commonly connected to the positive power terminal P (+), Si-MISFETQ M1, Q M2, Q M3, ..., the source of Q M6 is Are connected in common to the negative power terminal N (−).
　また、基本技術に係る疑似高電圧ＦＥＴモジュール１Ａは、図２に示すように、上記のＦＥＴ並列回路セル１０Ａを複数段直列接続したスイッチング回路４Ａと、スイッチング回路４Ａを構成する複数のＦＥＴ並列回路セル１０1Ａ、１０2Ａ、１０3Ａ、…、１０8Ａにそれぞれ光ファイバーケーブル１８1Ａ、１８2Ａ、１８3Ａ、…、１８8Ａを介して接続されたＥＯ変換器２２1Ａ、２２2Ａ、２２3Ａ、…、２２8Ａとを備える。光ファイバーケーブル１８1Ａ、１８2Ａ、１８3Ａ、…、１８8Ａは、光ファイバーケーブル束１８０Ａとしてバンドル化可能である。 Further, as shown in FIG. 2, the pseudo high voltage FET module 1A according to the basic technology includes a switching circuit 4A in which a plurality of FET parallel circuit cells 10A are connected in series, and a plurality of FET parallel circuits constituting the switching circuit 4A. cell 10 1 a, 10 2 a, 10 3 a, ..., 10 8 , respectively a fiber optic cable 18 1 a, 18 2 a, 18 3 a, ..., 18 8 via the a connected EO converter 22 1 A, 22 2 A, 22 3 A,..., 22 8 A. The optical fiber cables 18 1 A, 18 2 A, 18 3 A,..., 18 8 A can be bundled as an optical fiber cable bundle 180A.
　複数段直列接続したスイッチング回路４Ａは、ＦＥＴ並列回路セル１０1Ａのドレイン側においてグローバルドレイン端子Ｄ（＋）に接続され、ＦＥＴ並列回路セル１０8Ａのソース側においてグローバルソース端子Ｓ（－）に接続される。また、ＥＯ変換器２２1Ａ、２２2Ａ、２２3Ａ、…、２２8Ａの電気的入力側は、バッファ回路２１Ａを介して、グローバルゲート端子Ｇに接続される。 The switching circuit 4A connected in series in a plurality of stages is connected to the global drain terminal D (+) on the drain side of the FET parallel circuit cell 10 1 A, and the global source terminal S (−) on the source side of the FET parallel circuit cell 10 8 A. Connected to. The electrical input sides of the EO converters 22 1 A, 22 2 A, 22 3 A,..., 22 8 A are connected to the global gate terminal G through the buffer circuit 21A.
　基本技術に係る疑似高電圧ＦＥＴモジュール１Ａにおいては、図１・図２に示すように、Ｓｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6の多直列回路が構成されている。すなわち、
６並列のＳｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6を備えるＦＥＴ並列回路セル１０1Ａ、１０2Ａ、１０3Ａ、…、１０8Ａを８直列に接続して、疑似高電圧ＦＥＴモジュール１Ａを実現する。 In the pseudo high voltage FET module 1A according to the basic technology, as shown in FIGS. 1 and 2, a multi-series circuit of Si-MISFETs Q M1 , Q M2 , Q M3 ,..., Q M6 is configured. That is,
6 parallel Si-MISFETQ M1, Q M2, Q M3, ..., 1 FET parallel circuit cell 10 includes a Q M6 A, 10 2 A, 10 3 A, ..., a 10 8 A connected to the 8 series, the pseudo A high voltage FET module 1A is realized.
　ここで、基本技術に係る疑似高電圧ＦＥＴモジュール１Ａにおいて、Ｓｉ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6として、定格スイッチング電圧７００Ｖ、定格スイッチング電流１００ＡのＳｉ－ＭＩＳＦＥＴを適用した場合、定格スイッチング電圧５．６ｋＶ、定格スイッチング電流６００Ａのスイッチング性能を実現可能である。 Here, the pseudo-high-voltage FET module 1A according to the basic technique, Si-MISFETQ M1, Q M2 , Q M3, ..., as Q M6, rated switching voltage 700 V, is applied to Si-MISFET rated switching current 100A, Switching performance of a rated switching voltage of 5.6 kV and a rated switching current of 600 A can be realized.
　[第１の実施の形態]
（ＦＥＴ並列回路セル）
　第１の実施の形態に係るＦＥＴ並列回路セル１０は、図３に示すように、並列接続された複数のＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6と、複数のＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6のゲートにそれぞれ接続された複数のゲートドライブ回路１２1、１２2、１２3、…、１２6と、複数のゲートドライブ回路１２1、１２2、１２3、…、１２6にゲート駆動信号を供給するＯＥ変換器１４と、複数のゲートドライブ回路１２1、１２2、１２3、…、１２6とＯＥ変換器１４に電源を供給する絶縁型ＤＣ／ＤＣ変換器１６とを備える。ＯＥ変換器１４には、光ファイバーケーブル１８を介してＯＮ／ＯＦＦ信号が供給され、一方、絶縁型ＤＣ／ＤＣ変換器１６には、ゲートドライブ電圧供給線２０を介して、例えば、＋２４ＶのＤＣ電圧が供給される。ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6のドレインは、正側電力端子Ｐ（＋）に共通接続され、ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6のソースは、負側電力端子Ｎ（－）に共通接続されている。 [First embodiment]
(FET parallel circuit cell)
As shown in FIG. 3, the FET parallel circuit cell 10 according to the first embodiment includes a plurality of SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 and a plurality of SiC-MISFET Qs connected in parallel. A plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 respectively connected to the gates of S1 , Q S2 , Q S3 ,..., Q S6 , and a plurality of gate drive circuits 12 1 , 12 2 ,. 12 3, ..., 12 and the OE converter 14 supplies a gate drive signal to 6, a plurality of gate drive circuits 12 1, 12 2, 12 3, ..., 12 6 and insulated supplies power to OE converter 14 And a DC / DC converter 16. The OE converter 14 is supplied with an ON / OFF signal via an optical fiber cable 18, while the insulated DC / DC converter 16 is supplied with a DC voltage of, for example, + 24V via a gate drive voltage supply line 20. Is supplied. SiC-MISFETQ S1, Q S2, Q S3, ..., the drain of Q S6 are commonly connected to the positive power terminal P (+), SiC-MISFETQ S1, Q S2, Q S3, ..., the source of Q S6 is Are connected in common to the negative power terminal N (−).
　ＯＥ変換器１４は、光電変換素子であり、例えば、フォトカプラ、ファイバーカプラなどを適用可能である。 The OE converter 14 is a photoelectric conversion element, and for example, a photo coupler, a fiber coupler, or the like is applicable.
　ここで、適用可能なＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6の性能としては、例えば、一般の仕様書上での定格ドレイン・ソース間電圧１２００Ｖ、定格ドレインパルス電流８０Ａである。また、ドレイン・ソース間オン抵抗ＲDS(on)は、例えば、ゲート・ソース間電圧ＶGS＝１８Ｖ、ドレイン電流ＩD＝１０Ａにおいて、約８０ｍΩである。 Here, applicable SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 have, for example, a rated drain-source voltage of 1200 V and a rated drain pulse current of 80 A on a general specification. . Further, the drain-source on-resistance R DS (on) is about 80 mΩ at a gate-source voltage V GS = 18 V and a drain current I D = 10 A, for example.
　ＳｉＣ－ＭＩＳＦＥＴは定格ドレイン・ソース間電圧に対するアバランシェ降伏のマージンが大きい。例えば、１２００ＶのＳｉＣ－ＭＩＳＦＥＴでは、パルス状の電圧については、１７００Ｖ程度までアバランシェ降伏が起きることなく動作する。 SiC-MISFET has a large avalanche breakdown margin with respect to the rated drain-source voltage. For example, a 1200-V SiC-MISFET operates without avalanche breakdown up to about 1700 V with respect to a pulsed voltage.
　同様に、例えば、３３００ＶのＳｉＣ－ＭＩＳＦＥＴでは、パルス状の電圧については、４０００Ｖ程度までアバランシェ降伏が起きることなく動作する。 Similarly, for example, a 3300V SiC-MISFET operates without avalanche breakdown up to about 4000V for a pulsed voltage.
　ＳｉＣ－ＭＩＳＦＥＴにおいて、アバランシェ降伏電圧が高く設定されている理由は以下の通りである。ＳｉＣを酸化したＳｉＯ2で形成されるゲート絶縁膜（１３２：図１２・図１３参照）を形成する過程で、炭素（Ｃ）原子の一部がＳｉＣ／ＳｉＯ2界面に残留して界面準位密度を低下させる。このため、ゲート絶縁膜（ＳｉＯ2）の厚膜化が難しい。一方、継続・断続的に例えば１２００Ｖ耐圧デバイスに対して１７００Ｖが掛かることはゲート絶縁膜の信頼性上避けなければならないが、異常動作時に瞬間的に掛かることに対してはゲート絶縁膜の耐量が得られる。したがって、ゲート絶縁膜に継続・断続的に掛かる電界強度を抑制することを目的としてドリフト層（１２６・１２６Ｎ：図１２・図１３参照）の膜厚・キャリア濃度を設計したため、ＳｉＣ－ＭＩＳＦＥＴは定格ドレイン・ソース間電圧に対するマージンが大きく設定されている。 The reason why the avalanche breakdown voltage is set high in the SiC-MISFET is as follows. In the process of forming a gate insulating film (132: see FIG. 12 and FIG. 13) formed of SiO 2 obtained by oxidizing SiC, a part of carbon (C) atoms remains at the SiC / SiO 2 interface, and the interface state. Reduce density. For this reason, it is difficult to increase the thickness of the gate insulating film (SiO 2 ). On the other hand, for example, it is necessary to avoid applying 1700V to a 1200V withstand voltage device continuously / intermittently because of the reliability of the gate insulating film. can get. Therefore, since the thickness and carrier concentration of the drift layer (126 and 126N: see FIGS. 12 and 13) are designed for the purpose of suppressing the electric field strength applied continuously and intermittently to the gate insulating film, the SiC-MISFET is rated. A large margin for the drain-source voltage is set.
　（疑似高電圧ＦＥＴモジュール）
　第１の実施の形態に係る疑似高電圧ＦＥＴモジュール１は、図４に示すように、上記のＦＥＴ並列回路セル１０を複数段直列接続したスイッチング回路４と、スイッチング回路４を構成する複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8にそれぞれ光ファイバーケーブル１８1、１８2、１８3、…、１８8を介して接続される複数のＥＯ変換器２２1、２２2、２２3、…、２２8と、複数のＥＯ変換器２２1、２２2、２２3、…、２２8にそれぞれ接続され、スイッチング回路４を構成する複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を実質的に同時にオン／オフ制御可能な複数のパルスディレー回路２４1、２４2、２４3、…、２４8とを備える。光ファイバーケーブル１８1、１８2、１８3、…、１８8は、光ファイバーケーブル束１８０としてバンドル化可能である。パルスディレー回路２４1、２４2、２４3、…、２４8は、例えば、ＦＰＧＡ（Field Programmable Gate Array）回路などで構成可能である。 (Pseudo high voltage FET module)
As shown in FIG. 4, the pseudo high voltage FET module 1 according to the first embodiment includes a switching circuit 4 in which a plurality of FET parallel circuit cells 10 are connected in series, and a plurality of FETs constituting the switching circuit 4. parallel circuit cells 10 1, 10 2, 10 3, ..., 10 8 each optical fiber cable 18 1, 18 2, 18 3, ..., 18 a plurality of EO converter 22 connected 8 via a 1, 22 2, 22 3, ..., 22 8, a plurality of EO converter 22 1, 22 2, 22 3, ..., are connected to 22 8, more FET parallel circuit cells 10 1 constituting the switching circuit 4, 10 2, 10 3, ..., 10 8 substantially simultaneously oN / oFF controllable plurality of pulse delay circuit 24 1, 24 2, 24 3, ..., and a 24 8. The optical fiber cables 18 1 , 18 2 , 18 3 ,..., 18 8 can be bundled as an optical fiber cable bundle 180. The pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 can be configured by, for example, FPGA (Field Programmable Gate Array) circuits.
　複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を複数段直列接続したスイッチング回路４は、ＦＥＴ並列回路セル１０1のドレイン側においてグローバルドレイン端子Ｄ（＋）に接続され、ＦＥＴ並列回路セル１０8のソース側においてグローバルソース端子Ｓ（－）に接続される。また、パルスディレー回路２４1、２４2、２４3、…、２４8の入力側は、バッファ回路２１を介して、グローバルゲート端子Ｇに接続される。 The switching circuit 4 in which a plurality of FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 are connected in series is connected to the global drain terminal D (+) on the drain side of the FET parallel circuit cell 10 1. The FET parallel circuit cell 10 8 is connected to the global source terminal S (−) on the source side. In addition, the input sides of the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 are connected to the global gate terminal G through the buffer circuit 21.
　ここで、より一般化して、ｍ行ｎ列に配置するｍ×ｎ個のＳｉＣ－ＭＩＳＦＥＴの立ち上がり特性を測定して、立ち上がり時間が最も速いＳｉＣ－ＭＩＳＦＥＴからｍ番目に速いＳｉＣ－ＭＩＳＦＥＴまでを抽出し、最も速いＳｉＣ－ＭＩＳＦＥＴからｍ番目に速いＳｉＣ－ＭＩＳＦＥＴまでをそれぞれ異なるｍ個のＦＥＴ並列回路セルに配置することが望ましい。スイッチング回路４を構成する複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０mの立ち上がり時間を実質的に略均一化するためである。 Here, more generally, the rise characteristics of m × n SiC-MISFETs arranged in m rows and n columns are measured to extract from the SiC-MISFET having the fastest rise time to the m-th fastest SiC-MISFET. However, it is desirable to arrange the m-th fastest SiC-MISFET to the m-th fastest SiC-MISFET in different m FET parallel circuit cells. This is because the rise times of the plurality of FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 m constituting the switching circuit 4 are substantially uniformized.
　第１の実施の形態においては、図３・図４に示すように、ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6による複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を直列接続して、疑似高電圧ＦＥＴモジュール１を実現している。 In the first embodiment, FIG. 3 as shown in-Figure 4, SiC-MISFETQ S1, Q S2, Q S3, ..., a plurality of FET parallel circuit cells 10 1 by Q S6, 10 2, 10 3, ... 10 8 are connected in series to realize the pseudo high voltage FET module 1.
　ＳｉＣ－ＭＩＳＦＥＴは、Ｓｉ－ＭＩＳＦＥＴに比べて規格化オン抵抗が１／１０以下と小さく、各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を実質的に同時にオン／オフさせるためには特別の注意、対策を行う必要がある。もしもＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8のスイッチングのタイミングが異なる場合には、分圧のバランスが崩れ、特定のＦＥＴ並列回路セルに過大電圧が発生するからである。 SiC-MISFET is smaller the normalized on-resistance than 1/10 as compared with the Si-MISFET, each FET parallel circuit cells 10 1, 10 2, 10 3, ..., to substantially simultaneously turned on / off 10 8 Therefore, it is necessary to take special care and countermeasures. This is because if the FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 have different switching timings, the partial pressure balance is lost and an excessive voltage is generated in a specific FET parallel circuit cell. .
　第１の実施の形態においては、図４に示すように、各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8毎にパルスディレー回路２４1、２４2、２４3、…、２４8を設置して、オンディレー時間とオフディレー時間を調整することによって、各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8をプラスマイナス数ｎｓ以内、例えば、プラスマイナス１ｎｓ以内でオン／オフさせることができる。このため、各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を実質的に同時にオン／オフさせることができる。 In the first embodiment, as shown in FIG. 4, each FET parallel circuit cells 10 1, 10 2, 10 3, ..., the pulse delay circuit 24 1 for each 10 8, 24 2, 24 3, ..., 24 8 and adjusting the on-delay time and off-delay time, each FET parallel circuit cell 10 1 , 10 2 , 10 3 ,..., 10 8 is within plus or minus several ns, for example plus or minus 1 ns. Can be turned on / off within. Therefore, the FET parallel circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 can be turned on / off substantially simultaneously.
　ここで、第１の実施の形態において、ＳｉＣ－ＭＩＳＦＥＴＱM1、ＱM2、ＱM3、…、ＱM6として、定格ドレイン・ソース間電圧１２００Ｖ、定格ドレインパルス電流８０ＡのＳｉＣ－ＭＩＳＦＥＴを適用した場合、定格スイッチング電圧９．６ｋＶ、定格スイッチング電流４８０Ａの疑似高電圧ＦＥＴモジュール１を実現可能である。さらにＳｉＣはＳｉと比較して２００℃以上でもオフ状態が保持できるため、従来と同じ放熱システムのまま繰り返し周波数を高くすることができる。 Here, in the first embodiment, SiC-MISFETQ M1, Q M2 , Q M3, ..., as Q M6, rated drain-source voltage 1200 V, when applying the SiC-MISFET rated drain pulse current 80A, The pseudo high voltage FET module 1 having a rated switching voltage of 9.6 kV and a rated switching current of 480 A can be realized. Furthermore, since SiC can maintain an off state even at 200 ° C. or higher as compared with Si, the frequency can be increased repeatedly with the same heat dissipation system as in the prior art.
　第１の実施の形態によれば、このＦＥＴ並列回路セルを複数段直列化したスイッチング回路のＦＥＴ並列回路セルを実質的に同時にオン／オフ制御可能であり、ＦＥＴ並列回路セルの分圧バランスを良好に保持可能で、大電流をＭＨｚ級の周波数でスイッチング可能な疑似高電圧ＦＥＴモジュールを提供することができる。 According to the first embodiment, the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially simultaneously, and the partial pressure balance of the FET parallel circuit cell can be controlled. It is possible to provide a pseudo high voltage FET module that can be well maintained and can switch a large current at a frequency in the MHz range.
　［第２の実施の形態］
（ＦＥＴ並列回路セル）
　第２の実施の形態に係るＦＥＴ並列回路セル１０は、図５に示すように、ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6と並列接続され、サージ電圧を吸収するサージ吸収回路２６を備える。ここで、サージ吸収回路２６は、定電圧素子、アバランシェダイオード（ＡＢＤ:Avalanche Breakdown Diode）などを備えていても良い。その他の構成は、第１の実施の形態に係るＦＥＴ並列回路セル１０と同様である。 [Second Embodiment]
(FET parallel circuit cell)
As shown in FIG. 5, an FET parallel circuit cell 10 according to the second exemplary embodiment is connected in parallel with SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 and absorbs a surge voltage. 26. Here, the surge absorbing circuit 26 may include a constant voltage element, an avalanche diode (ABD: Avalanche Breakdown Diode), or the like. Other configurations are the same as those of the FET parallel circuit cell 10 according to the first exemplary embodiment.
　（疑似高電圧ＦＥＴモジュール）
　第２の実施の形態においても、図４と同様に、ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6およびサージ吸収回路２６を備える複数のＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を直列接続して、疑似高電圧ＦＥＴモジュール１を実現可能である。ＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6として、定格ドレイン・ソース間電圧１２００Ｖ、定格ドレインパルス電流８０ＡのＳｉＣ－ＭＩＳＦＥＴを適用した場合、定格スイッチング電圧９．６ｋＶ、定格スイッチング電流４８０Ａの疑似高電圧ＦＥＴモジュール１を実現可能である。 (Pseudo high voltage FET module)
In the second embodiment, similarly to FIG. 4, SiC-MISFETQ S1, Q S2, Q S3, ..., Q S6 and the surge absorption circuit more FET parallel circuit cells 10 1 with a 26, 10 2, 10 3 ,..., 10 8 can be connected in series to realize the pseudo high voltage FET module 1. When a SiC-MISFET having a rated drain-source voltage of 1200 V and a rated drain pulse current of 80 A is applied as the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 , the rated switching voltage is 9.6 kV and the rated switching current is 480 A The pseudo high voltage FET module 1 can be realized.
　ＳｉＣ－ＭＩＳＦＥＴは定格ドレイン・ソース間電圧に対するマージンが大きい。例えば、１２００Ｖ耐圧のＳｉＣ－ＭＩＳＦＥＴでは、パルス状の電圧については、１７００Ｖ程度までアバランシェ降伏が起きることなく動作する。 SiC-MISFET has a large margin for the rated drain-source voltage. For example, a SiC-MISFET with a withstand voltage of 1200 V operates without avalanche breakdown up to about 1700 V with respect to a pulse voltage.
　同様に、例えば、３３００ＶのＳｉＣ－ＭＩＳＦＥＴでは、パルス状の電圧については、４０００Ｖ程度までアバランシェ降伏が起きることなく動作する。 Similarly, for example, a 3300V SiC-MISFET operates without avalanche breakdown up to about 4000V for a pulsed voltage.
　ＳｉＣ－ＭＩＳＦＥＴにおいて、アバランシェ降伏電圧が高く設定されている理由は前述の通りである。 The reason why the avalanche breakdown voltage is set high in the SiC-MISFET is as described above.
　第２の実施の形態に係る疑似高電圧ＦＥＴモジュールにおいても各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8毎にパルスディレー回路２４1、２４2、２４3、…、２４8を設置して、オンディレー時間とオフディレー時間を調整することによって、各ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8を実質的に略同時にオン／オフさせる回路構成とすることができる。また、第２の実施の形態においては、ＦＥＴ並列回路セル１０1、１０2、１０3、…、１０8に、例えば、ＡＢＤ（avalanche breakdown diode)などによるサージ吸収回路２６を設置することで、各並列ＦＥＴ回路セル１０1、１０2、１０3、…、１０8が突発的に完全に同時にオン／オフしなくても、プラスマイナス数１０ｎｓ以内、例えば、プラスマイナス２０ｎｓ以内でオン／オフさせることで、正常動作可能な疑似高電圧ＦＥＴモジュール１を実現可能である。 The 2 FET also each in the exemplary pseudo-high-voltage FET module according to the parallel circuit cells 10 1, 10 2, 10 3, ..., the pulse delay circuit 24 every 10 8 1, 24 2, 24 3, ..., 24 8 by installing, by adjusting the on-delay time and oFF-delay time, the FET parallel circuit cells 10 1, 10 2, 10 3, ..., and the circuit is substantially almost simultaneously turned on / off configuration 10 8 can do. In the second embodiment, FET parallel circuit cells 10 1, 10 2, 10 3, ..., 10 8, for example, by installing a surge absorption circuit 26 due ABD (avalanche breakdown diode), Even if the parallel FET circuit cells 10 1 , 10 2 , 10 3 ,..., 10 8 are not suddenly completely turned on / off at the same time, they are turned on / off within ± 10 ns, for example, within ± 20 ns. Thus, the pseudo high voltage FET module 1 capable of normal operation can be realized.
　サージ吸収回路２６には、降伏電圧３５０Ｖ程度のＡＢＤを４個直列接続して、ＳｉＣ－ＭＩＳＦＥＴに１４００Ｖを超える過大電圧が印加されることを回避可能である。 In the surge absorbing circuit 26, four ABDs having a breakdown voltage of about 350V are connected in series, and it is possible to avoid applying an excessive voltage exceeding 1400V to the SiC-MISFET.
　同様に、降伏電圧３７０Ｖ程度のＡＢＤを１０個直列接続して、ＳｉＣ－ＭＩＳＦＥＴに３７００Ｖを超える過大電圧が印加されることを回避可能である。 Similarly, it is possible to avoid applying an excessive voltage exceeding 3700 V to the SiC-MISFET by connecting 10 ABDs having a breakdown voltage of about 370 V in series.
　第２の実施の形態によれば、ＡＢＤによってアバランシェ降伏電圧以上の電圧サージを吸収可能なＦＥＴ並列回路セルを提供することができる。 According to the second embodiment, it is possible to provide an FET parallel circuit cell capable of absorbing a voltage surge higher than an avalanche breakdown voltage by ABD.
　ＳｉＣ―ＭＩＳＦＥＴを使ったＦＥＴ並列回路セルを構築する際、ＡＢＤを並列接続すると単位ＦＥＴ並列回路セル当たりが受け持てる電圧値がＡＢＤのアバランシェ降伏電圧によって規定される。このため、ＡＢＤのアバランシェ降伏電圧をＳｉＣ－ＭＩＳＦＥＴの定格ドレイン・ソース間電圧以上で、かつＳｉＣ－ＭＩＳＦＥＴのアバランシェ降伏電圧以下になるように設計すると良い。このように設計することで、単位ＦＥＴ並列回路セル当たりが受け持てる電圧値を増加させ、擬似高電圧ＦＥＴモジュールに必要な電圧を確保するために直列接続するＦＥＴ並列回路セルの数を低減させることができる。結果として、疑似高電圧ＦＥＴモジュールの小型化、低コスト化が可能になる。 When an FET parallel circuit cell using SiC-MISFET is constructed, the voltage value per unit FET parallel circuit cell can be defined by the avalanche breakdown voltage of the ABD when ABDs are connected in parallel. For this reason, it is preferable that the avalanche breakdown voltage of the ABD is designed to be higher than the rated drain-source voltage of the SiC-MISFET and lower than the avalanche breakdown voltage of the SiC-MISFET. By designing in this way, the voltage value per unit FET parallel circuit cell can be increased, and the number of FET parallel circuit cells connected in series to reduce the voltage required for the pseudo high voltage FET module can be reduced. Can do. As a result, the pseudo high voltage FET module can be reduced in size and cost.
　また、第２の実施の形態によれば、このＦＥＴ並列回路セルを複数段直列化したスイッチング回路のＦＥＴ並列回路セルを実質的に略同時にオン／オフ制御可能であり、ＦＥＴ並列回路セルの分圧バランスを良好に保持可能で、大電流をＭＨｚ級の周波数でスイッチング可能な疑似高電圧ＦＥＴモジュールを提供することができる。 Further, according to the second embodiment, the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module that can maintain a good pressure balance and can switch a large current at a frequency in the MHz range.
　［第３の実施の形態］
（ＦＥＴ並列回路セル）
　絶縁型ＤＣ／ＤＣ変換器１６には、トランス絶縁型ＤＣ／ＤＣ変換器、或いはワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器を適用可能である。 [Third Embodiment]
(FET parallel circuit cell)
As the insulation type DC / DC converter 16, a transformer insulation type DC / DC converter or a wireless power feeding type insulation type DC / DC converter can be applied.
　トランス絶縁型ＤＣ／ＤＣ変換器２８Ａを適用した第３の実施の形態に係るＦＥＴ並列回路セル３４Ａの模式的ブロック構成は、図６に示すように表される。 A schematic block configuration of the FET parallel circuit cell 34A according to the third embodiment to which the transformer insulation type DC / DC converter 28A is applied is expressed as shown in FIG.
　ＦＥＴ並列回路セル３４Ａは、トランス絶縁型ＤＣ／ＤＣ変換器２８Ａと、トランス絶縁型ＤＣ／ＤＣ変換器２８Ａに接続されたＳｉＣ－ＭＩＳＦＥＴ駆動回路３０Ａと、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０Ａに接続された６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２Ａとを備える。トランス絶縁型ＤＣ／ＤＣ変換器２８Ａは、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０Ａに対して直流電圧ＶDDを供給し、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０Ａは、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２Ａに対してゲート駆動信号ＦＤを供給する。 The FET parallel circuit cell 34A includes a transformer insulated DC / DC converter 28A, a SiC-MISFET drive circuit 30A connected to the transformer insulated DC / DC converter 28A, and a 6 connected to the SiC-MISFET drive circuit 30A. And a parallel SiC-MISFET circuit 32A. The transformer-isolated DC / DC converter 28A supplies a DC voltage V DD to the SiC-MISFET drive circuit 30A, and the SiC-MISFET drive circuit 30A sends a gate drive signal FD to the 6-parallel SiC-MISFET circuit 32A. Supply.
　ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０Ａは、図１・図３・図５に示された複数のゲートドライブ回路１２1、１２2、１２3、…、１２6に対応している。また、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２Ａは、図１・図３・図５に示され、並列接続されたＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6に対応している。トランス絶縁型ＤＣ／ＤＣ変換器では、最大で数１０ｋＶの絶縁耐圧ＶBMとなる。 The SiC-MISFET drive circuit 30A corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32A corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS. In the transformer insulation type DC / DC converter, the insulation breakdown voltage V BM is several tens of kV at the maximum.
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８を適用した第３の実施の形態に係るＦＥＴ並列回路セル３４の模式的ブロック構成は、図７に示すように表される。 A schematic block configuration of the FET parallel circuit cell 34 according to the third embodiment to which the wireless power feeding type isolated DC / DC converter 28 is applied is expressed as shown in FIG.
　第３の実施の形態に係るＦＥＴ並列回路セル３４は、図７に示すように、ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８と、絶縁型ＤＣ／ＤＣ変換器２８に接続されたＳｉＣ－ＭＩＳＦＥＴ駆動回路３０と、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０に接続された６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２とを備える。絶縁型ＤＣ／ＤＣ変換器２８は、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０に対して直流電圧ＶDDを供給し、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０は、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２に対してゲート駆動信号ＦＤを供給する。 As shown in FIG. 7, the FET parallel circuit cell 34 according to the third embodiment includes a wireless power feeding type isolated DC / DC converter 28 and a SiC- connected to the insulated DC / DC converter 28. A MISFET drive circuit 30 and a 6 parallel SiC-MISFET circuit 32 connected to the SiC-MISFET drive circuit 30 are provided. The isolated DC / DC converter 28 supplies the DC voltage V DD to the SiC-MISFET drive circuit 30, and the SiC-MISFET drive circuit 30 supplies the gate drive signal FD to the 6-parallel SiC-MISFET circuit 32. Supply.
　ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０は、図１・図３・図５に示された複数のゲートドライブ回路１２1、１２2、１２3、…、１２6に対応している。また、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２は、図１・図３・図５に示され、並列接続されたＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6に対応している。 The SiC-MISFET drive circuit 30 corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32 corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS.
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８は、図７に示すように、発振回路３８と、発振回路３８に接続された１次側コイルＬ１と、１次側コイルＬ１からワイヤレス給電可能な２次側コイルＬ２と、２次側コイルＬ２に接続された整流回路４０とを備える。 As shown in FIG. 7, the wireless power feeding type isolated DC / DC converter 28 can wirelessly feed power from an oscillation circuit 38, a primary coil L1 connected to the oscillation circuit 38, and the primary coil L1. A secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided.
　ここで、１次側コイルＬ１と２次側コイルＬ２は、沿面距離ＬSだけ離隔して配置される。絶縁破壊電界の値に応じて、１次側コイルＬ１と２次側コイルＬ２間の沿面距離ＬSが設定される。 Here, the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S. The creepage distance L S between the primary coil L1 and the secondary coil L2 is set according to the value of the dielectric breakdown electric field.
　また、発振回路３８と１次側コイルＬ１を内蔵し、絶縁型ＤＣ／ＤＣ変換器２８の絶縁耐圧ＶBSを制御可能な収納器３６を備えていても良い。収納器３６は、樹脂もしくはセラミックスで形成されていても良い。樹脂もしくはセラミックスの厚さで絶縁耐圧値を制御することができる。例えば、ポリエチレン樹脂を使用する場合には、絶縁破壊電界は、約５０ｋＶ／ｍｍである。 Further, a housing 36 that includes the oscillation circuit 38 and the primary coil L1 and can control the withstand voltage V BS of the isolated DC / DC converter 28 may be provided. The container 36 may be formed of resin or ceramics. The withstand voltage value can be controlled by the thickness of the resin or ceramic. For example, when polyethylene resin is used, the dielectric breakdown electric field is about 50 kV / mm.
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８において、絶縁耐圧ＶBSの値は、最大数１００ｋＶ以上である。 In the wireless power supply type isolated DC / DC converter 28, the value of the insulation withstand voltage V BS is several hundred kV or more at the maximum.
　収納器３６として樹脂ボックスを使用し、絶縁破壊電界１ＭＶ／８ｍｍ、約１２０ｋＶ／ｍｍ以上を得ることも可能である。樹脂としては、例えば、テフロン（登録商標）、ポリエチレンなどを適用可能である。 It is also possible to obtain a dielectric breakdown electric field of 1 MV / 8 mm and about 120 kV / mm or more by using a resin box as the container 36. As the resin, for example, Teflon (registered trademark), polyethylene, or the like is applicable.
　（疑似高電圧ＦＥＴモジュール）
　第３の実施の形態においても、第１～第２の実施の形態と同様に、複数のＦＥＴ並列回路セルを直列接続して、疑似高電圧ＦＥＴモジュールを実現可能である。 (Pseudo high voltage FET module)
Also in the third embodiment, a pseudo high voltage FET module can be realized by connecting a plurality of FET parallel circuit cells in series as in the first and second embodiments.
　第３の実施の形態に係る疑似高電圧ＦＥＴモジュールにおいては、ワイヤレス給電回路を用いて超高耐圧の絶縁型ＤＣ／ＤＣ変換器を実装することで数１００ｋＶ以上の定格スイッチング電圧を有する疑似高電圧ＦＥＴモジュールを実現可能である。 In the pseudo high voltage FET module according to the third embodiment, a pseudo high voltage having a rated switching voltage of several hundred kV or more by mounting an ultra-high withstand voltage insulated DC / DC converter using a wireless power feeding circuit. An FET module can be realized.
　第３の実施の形態によれば、このＦＥＴ並列回路セルを複数段直列化したスイッチング回路のＦＥＴ並列回路セルを実質的に略同時にオン／オフ制御可能であり、ＦＥＴ並列回路セルの分圧バランスを良好に保持し、大電流をＭＨｚ級の周波数でスイッチング可能な超高耐圧用の疑似高電圧ＦＥＴモジュールを提供することができる。 According to the third embodiment, the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module for an ultra-high withstand voltage that can maintain a good current and can switch a large current at a frequency in the MHz range.
　また、第３の実施の形態において、ＡＢＤがＦＥＴ並列回路セルに接続されている場合、アバランシェ降伏電圧以上の電圧サージを吸収可能な超高耐圧のＦＥＴ並列回路セルを提供することができる。 Further, in the third embodiment, when the ABD is connected to the FET parallel circuit cell, it is possible to provide an ultra-high withstand voltage FET parallel circuit cell capable of absorbing a voltage surge higher than the avalanche breakdown voltage.
　（変形例）
（ＦＥＴ並列回路セル）
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８を適用した第３の実施の形態の変形例に係るＦＥＴ並列回路セル３４の模式的ブロック構成は、図８に示すように表される。 (Modification)
(FET parallel circuit cell)
A schematic block configuration of the FET parallel circuit cell 34 according to the modification of the third embodiment to which the wireless power supply type isolated DC / DC converter 28 is applied is expressed as shown in FIG.
　第３の実施の形態の変形例に係るＦＥＴ並列回路セル３４は、図８に示すように、ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８と、絶縁型ＤＣ／ＤＣ変換器２８に接続されたＳｉＣ－ＭＩＳＦＥＴ駆動回路３０と、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０に接続された６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２とを備える。 As shown in FIG. 8, the FET parallel circuit cell 34 according to the modification of the third embodiment is connected to a wireless power feeding type insulated DC / DC converter 28 and an insulated DC / DC converter 28. The SiC-MISFET drive circuit 30 and a 6 parallel SiC-MISFET circuit 32 connected to the SiC-MISFET drive circuit 30 are provided.
　ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０は、図１・図３・図５に示された複数のゲートドライブ回路１２1、１２2、１２3、…、１２6に対応している。また、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２は、図１・図３・図５に示され、並列接続されたＳｉＣ－ＭＩＳＦＥＴＱS1、ＱS2、ＱS3、…、ＱS6に対応している。 The SiC-MISFET drive circuit 30 corresponds to the plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 shown in FIGS. Further, the 6-parallel SiC-MISFET circuit 32 corresponds to the SiC-MISFETs Q S1 , Q S2 , Q S3 ,..., Q S6 shown in FIGS.
　絶縁型ＤＣ／ＤＣ変換器２８は、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０に対して直流電圧ＶDDを供給し、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０は、６並列ＳｉＣ－ＭＩＳＦＥＴ回路３２に対してゲート駆動信号ＦＤを供給する。 The isolated DC / DC converter 28 supplies the DC voltage V DD to the SiC-MISFET drive circuit 30, and the SiC-MISFET drive circuit 30 supplies the gate drive signal FD to the 6-parallel SiC-MISFET circuit 32. Supply.
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８は、図８に示すように、発振回路３８と、発振回路３８に接続された１次側コイルＬ１と、１次側コイルＬ１からワイヤレス給電可能な２次側コイルＬ２と、２次側コイルＬ２に接続された整流回路４０とを備える。 As shown in FIG. 8, the wireless power feeding type isolated DC / DC converter 28 can wirelessly feed power from the oscillation circuit 38, the primary coil L1 connected to the oscillation circuit 38, and the primary coil L1. A secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided.
　さらに、第３の実施の形態の変形例に係るＦＥＴ並列回路セル３４は、図８に示すように、整流回路４０の出力とＳｉＣ－ＭＩＳＦＥＴ駆動回路３０の入力間に接続された蓄電回路４２を備える。ここで、蓄電回路４２には、リチウムイオン電池、スーパーキャパシタ、もしくは電気二重槽キャパシタ（ＥＤＬＣ：Electric Double-Layer Capacitor）などを適用可能である。 Further, the FET parallel circuit cell 34 according to the modification of the third embodiment includes a storage circuit 42 connected between the output of the rectifier circuit 40 and the input of the SiC-MISFET drive circuit 30 as shown in FIG. Prepare. Here, a lithium ion battery, a super capacitor, an electric double tank capacitor (EDLC: Electric Double-Layer Capacitor), or the like can be applied to the power storage circuit 42.
　さらに、第３の実施の形態の変形例に係るＦＥＴ並列回路セル３４は、図８に示すように、整流回路４０の出力に第１アノードが接続され、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０の入力に第１カソードが接続された第１突合せダイオードＤＴ１と、蓄電回路４２を介して第２アノードが整流回路４０の出力に接続され、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０の入力に第２カソードが接続された第２突合せダイオードＤＴ２とを備えていても良い。 Further, in the FET parallel circuit cell 34 according to the modification of the third embodiment, the first anode is connected to the output of the rectifier circuit 40 and the input to the SiC-MISFET drive circuit 30 is the second as shown in FIG. A first butt diode DT1 connected to one cathode, a second anode connected to the output of the rectifier circuit 40 via the storage circuit 42, and a second cathode connected to the input of the SiC-MISFET drive circuit 30. A butt diode DT2 may be provided.
　ここで、１次側コイルＬ１と２次側コイルＬ２は、沿面距離ＬSだけ離隔して配置される。その他の構成は、第３の実施の形態に係るＦＥＴ並列回路セル３４と同様である。 Here, the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S. Other configurations are the same as those of the FET parallel circuit cell 34 according to the third embodiment.
　（疑似高電圧ＦＥＴモジュール）
　第３の実施の形態の変形例に係るＦＥＴ並列回路セル３４は、蓄電回路４２を設けることで、ＤＣ＋２４Ｖ電源喪失時においても各ＦＥＴ並列回路セルが同時にオフできるようになる。ＤＣ＋２４Ｖ電源喪失時においても回路内のＳｉＣ－ＭＩＳＦＥＴが異常電圧によって破壊されることを回避可能であるため、信頼性の高い疑似高電圧ＦＥＴモジュールを実現可能である。 (Pseudo high voltage FET module)
In the FET parallel circuit cell 34 according to the modification of the third embodiment, by providing the storage circuit 42, each FET parallel circuit cell can be turned off simultaneously even when the DC + 24V power supply is lost. Even when the DC + 24V power supply is lost, the SiC-MISFET in the circuit can be prevented from being destroyed by the abnormal voltage, so that a highly reliable pseudo high voltage FET module can be realized.
　第３の実施の形態の変形例に係るＦＥＴ並列回路セルを適用した疑似高電圧ＦＥＴモジュールにおいては、ワイヤレス給電回路を用いて超高耐圧の絶縁型ＤＣ／ＤＣ変換器を実装することで絶縁耐圧ＶBSとして最大数１００ｋＶ以上の定格スイッチング電圧を有する疑似高電圧ＦＥＴモジュールを実現可能である。 In the pseudo high voltage FET module to which the FET parallel circuit cell according to the modification of the third embodiment is applied, the insulation withstand voltage is achieved by mounting an ultra-high withstand voltage isolated DC / DC converter using a wireless power feeding circuit. it is possible to realize a pseudo-high-voltage FET module having a maximum number 100kV or more of the rated switching voltage as V BS.
　また、第３の実施の形態の変形例によれば、このＦＥＴ並列回路セルを複数段直列化したスイッチング回路のＦＥＴ並列回路セルを実質的に略同時にオン／オフ制御可能であり、ＦＥＴ並列回路セルの分圧バランスを良好に保持し、大電流をＭＨｚ級の周波数でスイッチング可能な超高耐圧用の疑似高電圧ＦＥＴモジュールを提供することができる。 Further, according to the modification of the third embodiment, the FET parallel circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serialized can be controlled on / off substantially simultaneously. It is possible to provide a pseudo high voltage FET module for an ultra-high withstand voltage capable of maintaining a good cell partial pressure balance and switching a large current at a frequency in the MHz range.
　また、第３の実施の形態の変形例において、ＡＢＤがＦＥＴ並列回路セルに接続されている場合、アバランシェ降伏電圧以上の電圧サージを吸収可能な超高耐圧のＦＥＴ並列回路セルを提供することができる。 Further, in the modification of the third embodiment, when the ABD is connected to the FET parallel circuit cell, it is possible to provide an ultra-high voltage FET parallel circuit cell capable of absorbing a voltage surge higher than the avalanche breakdown voltage. it can.
　［第４の実施の形態］
（ＭＩＳ型リレー回路セル）
　第１～第３の実施の形態に係るＦＥＴ並列回路セルを構成するＳｉＣ－ＭＩＳＦＥＴは、ＡＣ負荷をスイッチング可能なバイポーラ型であっても良い。 [Fourth Embodiment]
(MIS type relay circuit cell)
The SiC-MISFET constituting the FET parallel circuit cell according to the first to third embodiments may be a bipolar type capable of switching an AC load.
　第４の実施の形態に係るＭＩＳ型リレー回路セル４４は、図９に示すように、並列接続された複数のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6と、複数のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6のゲートにそれぞれ接続された複数のゲートドライブ回路１２1、１２2、１２3、…、１２6と、複数のゲートドライブ回路１２1、１２2、１２3、…、１２6にゲート駆動信号を供給するＯＥ変換器１４と、複数のゲートドライブ回路１２1、１２2、１２3、…、１２6とＯＥ変換器１４に電源を供給する絶縁型ＤＣ／ＤＣ変換器１６とを備える。 As shown in FIG. 9, the MIS relay circuit cell 44 according to the fourth embodiment includes a plurality of SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,. A plurality of gate drive circuits 12 1 , 12 2 , 12 3 ,..., 12 6 respectively connected to the gates of the plurality of SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,. the gate drive circuit 12 1, 12 2, 12 3, ..., 12 and the OE converter 14 supplies a gate drive signal to 6, a plurality of gate drive circuits 12 1, 12 2, 12 3, ..., 12 6 and OE conversion And an insulated DC / DC converter 16 for supplying power to the device 14.
　ＯＥ変換器１４には、光ファイバーケーブル１８を介してＯＮ／ＯＦＦ信号が供給され、一方、絶縁型ＤＣ／ＤＣ変換器１６には、ゲートドライブ電圧供給線２０を介して、例えば、＋２４ＶのＤＣ電圧が供給される。 The OE converter 14 is supplied with an ON / OFF signal via an optical fiber cable 18, while the insulated DC / DC converter 16 is supplied with a DC voltage of, for example, + 24V via a gate drive voltage supply line 20. Is supplied.
　ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6の一方のドレインは、正側ＡＣ端子ＴＡに共通接続され、ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6の他方のドレインは、負側ＡＣ端子ＴＢに共通接続されている。 One drain of each of the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 is commonly connected to the positive side AC terminal TA, and the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 , ..., the other drain of Q A6 is commonly connected to the negative AC terminal TB.
　また、第４の実施の形態に係るＭＩＳ型リレー回路セル４４のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6の回路構成例は、図１０（ａ）に示すように表され、別の回路構成例は、図１０（ｂ）に示すように表される。 Further, a circuit configuration example of the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 of the MIS type relay circuit cell 44 according to the fourth embodiment is as shown in FIG. Another circuit configuration example is expressed as shown in FIG.
　例えば、図１０（ａ）に示すように、２個のＳｉＣ－ＭＯＳＦＥＴをソース共通で直列化接続することで、ＡＣ負荷をスイッチング可能な双方向スイッチを実現可能である。 For example, as shown in FIG. 10A, a bidirectional switch capable of switching an AC load can be realized by connecting two SiC-MOSFETs in series with a common source.
　ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱAは、図１０（ａ）に示すように、第１のＳｉＣ－ＭＩＳＦＥＴＱSAと、第１のＳｉＣ－ＭＩＳＦＥＴＱSAと直列に接続され、第１のＳｉＣ－ＭＩＳＦＥＴＱSAの第１ソースと第２ソースが共通に接続され、第１のＳｉＣ－ＭＩＳＦＥＴＱSAの第１ゲートと第２ゲートが共通に接続された第２のＳｉＣ－ＭＩＳＦＥＴＱSBと、第１のＳｉＣ－ＭＩＳＦＥＴＱSAの主電極間に逆並列接続された第１ダイオードＤ１と、第２のＳｉＣ－ＭＩＳＦＥＴＱSBの主電極間に逆並列接続された第２ダイオードＤ２とを備える。ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱAは、第１のＳｉＣ－ＭＩＳＦＥＴＱSAの第１ドレインと第２のＳｉＣ－ＭＩＳＦＥＴＱSBの第２ドレイン間のＡＣ電流を制御可能である。２個のＳｉＣ－ＭＯＳＦＥＴＱSA・ＱSBのゲートを共通化し、２個のＳｉＣ－ＭＯＳＦＥＴＱSA・ＱSBを同時にオンさせる場合、ＡＣ電流は並列ダイオードＤ１・Ｄ２ではなく主に低オン抵抗を有するＳｉＣ－ＭＯＳＦＥＴＱSA・ＱSBを導通する。すなわち、ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱAは、ＡＣ端子ＴＡ・ＴＢ間のＡＣ電流をスイッチング制御可能である。 As shown in FIG. 10A, the SiC-MISFET AC load circuit Q A is connected in series with the first SiC-MISFET Q SA and the first SiC-MISFET Q SA , and the first SiC-MISFET Q SA is connected to the first SiC-MISFET Q SA . A first SiC-MISFET Q SB in which a first source and a second source are connected in common, and a first gate and a second gate of the first SiC-MISFET Q SA are connected in common, and a first SiC-MISFET Q SA It comprises a first diode D1 which are connected in antiparallel between the main electrodes, and a second diode D2 which are reverse-connected in parallel between the main electrodes of the second SiC-MISFET Q SB. The SiC-MISFET AC load circuit Q A can control the AC current between the first drain of the first SiC-MISFET Q SA and the second drain of the second SiC-MISFET Q SB . When the gates of two SiC-MOSFETs Q SA and Q SB are made common and the two SiC-MOSFETs Q SA and Q SB are simultaneously turned on, the AC current is not parallel diodes D1 and D2, but mainly SiC having a low on-resistance. -Conduct the MOSFET Q SA and Q SB . That is, the SiC-MISFET AC load circuit Q A can perform switching control of the AC current between the AC terminals TA and TB.
　第４の実施の形態に係るＭＩＳ型リレー回路セル４４のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路は、図１０（ｂ）に示すように、第１のＳｉＣ－ＭＩＳＦＥＴＱ１と第１のＳｉＣ－ＭＩＳＦＥＴＱ１に直列接続された第１のダイオードＤ１からなる第１の逆阻止型スイッチ５０1と、第２のＳｉＣ－ＭＩＳＦＥＴＱ２と第２のＳｉＣ－ＭＩＳＦＥＴＱ２に直列接続された第２のダイオードＤ２からなる第２の逆阻止型スイッチ５０2とを備えていても良い。この構成にすると、第１のＳｉＣ－ＭＩＳＦＥＴＱ１と第１のダイオードＤ１、および第２のＳｉＣ－ＭＩＳＦＥＴＱ２と第２のダイオードＤ２の間の電流経路の寄生インダクタンスを低減することができ、よりサージやノイズの少ない回路を形成することができる。図１０（ｂ）に示すＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱAは、ＡＣ端子ＴＡ・ＴＢ間のＡＣ電流をスイッチング制御可能である。 The SiC-MISFET AC load circuit of the MIS type relay circuit cell 44 according to the fourth embodiment is connected in series to the first SiC-MISFET Q1 and the first SiC-MISFET Q1, as shown in FIG. 10 (b). A first reverse blocking switch 50 1 comprising a first diode D1, and a second reverse blocking type comprising a second SiC-MISFET Q2 and a second diode D2 connected in series to the second SiC-MISFET Q2. it may be provided with a switch 50 2. With this configuration, it is possible to reduce the parasitic inductance of the current path between the first SiC-MISFET Q1 and the first diode D1, and between the second SiC-MISFET Q2 and the second diode D2, and more surge and noise. A circuit with less can be formed. The SiC-MISFET AC load circuit Q A shown in FIG. 10B is capable of switching control of the AC current between the AC terminals TA and TB.
　ここで、ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6に適用可能なＳｉＣ－ＭＩＳＦＥＴＱSA、ＱSB、Ｑ１、Ｑ２の性能としては、例えば、定格ドレイン・ソース間電圧１２００Ｖ、定格ドレインパルス電流８０Ａである。また、ドレイン・ソース間オン抵抗ＲDS(on)は、例えば、ＶGS＝１８Ｖ、ＩD＝１０Ａにおいて、約８０ｍΩである。 Here, as the performance of the SiC-MISFETs Q SA , Q SB , Q 1 , Q 2 applicable to the SiC-MISFET AC load circuits Q A1 , Q A2 , Q A3 ,..., Q A6 , for example, rated drain-source voltage 1200V, rated drain pulse current 80A. The drain-source on-resistance R DS (on) is about 80 mΩ, for example, when V GS = 18 V and I D = 10 A.
　絶縁型ＤＣ／ＤＣ変換器１６には、トランス絶縁型ＤＣ／ＤＣ変換器、或いはワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器を適用可能である。トランス絶縁型ＤＣ／ＤＣ変換器では、最大で数１０ｋＶの絶縁耐圧ＶBMとなる。ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器において、絶縁耐圧ＶBSの値は、最大数１００ｋＶ以上である。 As the insulation type DC / DC converter 16, a transformer insulation type DC / DC converter or a wireless power feeding type insulation type DC / DC converter can be applied. In the transformer insulation type DC / DC converter, the insulation breakdown voltage V BM is several tens of kV at the maximum. In the wireless power supply type insulated type DC / DC converter, the value of the breakdown voltage V BS is the maximum number of 100kV or higher.
　ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８は、図７と同様に、発振回路３８と、発振回路３８に接続された１次側コイルＬ１と、１次側コイルＬ１からワイヤレス給電可能な２次側コイルＬ２と、２次側コイルＬ２に接続された整流回路４０とを備える。ここで、１次側コイルＬ１と２次側コイルＬ２は、沿面距離ＬSだけ離隔して配置される。 As in the case of FIG. 7, the wireless power feeding type isolated DC / DC converter 28 has an oscillation circuit 38, a primary coil L <b> 1 connected to the oscillation circuit 38, and a wireless power feeding 2 from the primary coil L <b> 1. A secondary coil L2 and a rectifier circuit 40 connected to the secondary coil L2 are provided. Here, the primary side coil L1 and the secondary side coil L2 are spaced apart by a creeping distance L S.
　また、ワイヤレス給電型の絶縁型ＤＣ／ＤＣ変換器２８は、図７と同様に、発振回路３８と１次側コイルＬ１を内蔵し、絶縁型ＤＣ／ＤＣ変換器２８の絶縁耐圧ＶBSを制御可能な収納器３６を備えていても良い。収納器３６は、樹脂もしくはセラミックスで形成されていても良い。樹脂もしくはセラミックスの厚さで絶縁耐圧値を制御することができる。例えば、ポリエチレン樹脂を使用する場合には、絶縁破壊電界は、約５０ｋＶ／ｍｍである。 Also, the wireless power supply type isolated DC / DC converter 28 includes an oscillation circuit 38 and a primary side coil L1 as in FIG. 7, and controls the insulation withstand voltage V BS of the isolated DC / DC converter 28. A possible container 36 may be provided. The container 36 may be formed of resin or ceramics. The withstand voltage value can be controlled by the thickness of the resin or ceramic. For example, when polyethylene resin is used, the dielectric breakdown electric field is about 50 kV / mm.
　収納器３６として樹脂ボックスを使用し、絶縁破壊電界１ＭＶ／８ｍｍ、約１２０ｋＶ／ｍｍ以上を得ることも可能である。樹脂としては、例えば、テフロン（登録商標）、ポリエチレンなどを適用可能である。 It is also possible to obtain a dielectric breakdown electric field of 1 MV / 8 mm and about 120 kV / mm or more by using a resin box as the container 36. As the resin, for example, Teflon (registered trademark), polyethylene, or the like is applicable.
　さらに、第４の実施の形態に係るＭＩＳ型リレー回路セル４４は、図８と同様に、整流回路４０の出力と複数のゲートドライブ回路１２1、１２2、１２3、…、１２6の入力間に接続された蓄電回路４２を備えていても良い。ここで、蓄電回路４２には、リチウムイオン電池、スーパーキャパシタ、もしくは電気二重槽キャパシタ（ＥＤＬＣ）などを適用可能である。 Furthermore, MIS-type relay circuit cell 44 according to the fourth embodiment, similarly to FIG. 8, the gate drive circuit 12 1 outputs a plurality of rectifier circuits 40, 12 2, 12 3, ..., 12 6 input You may provide the electrical storage circuit 42 connected between. Here, a lithium ion battery, a super capacitor, an electric double tank capacitor (EDLC), or the like can be applied to the power storage circuit 42.
　さらに、第４の実施の形態に係るＭＩＳ型リレー回路セル４４は、図８と同様に、整流回路４０の出力に第１アノードが接続され、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０の入力に第１カソードが接続された第１突合せダイオードＤＴ１と、蓄電回路４２を介して第２アノードが整流回路４０の出力に接続され、ＳｉＣ－ＭＩＳＦＥＴ駆動回路３０の入力に第２カソードが接続された第２突合せダイオードＤＴ２とを備えていても良い。 Further, in the MIS type relay circuit cell 44 according to the fourth embodiment, the first anode is connected to the output of the rectifier circuit 40 and the first cathode is connected to the input of the SiC-MISFET drive circuit 30 as in FIG. The connected first butt diode DT1, and the second butt diode DT2 whose second anode is connected to the output of the rectifier circuit 40 via the storage circuit 42 and whose second cathode is connected to the input of the SiC-MISFET drive circuit 30. And may be provided.
　（疑似高電圧ＦＥＴモジュール：疑似高電圧ＭＩＳ型リレーモジュール）
　第４の実施の形態に係る疑似高電圧ＦＥＴモジュール２は、図１１に示すように、上記のＭＩＳ型リレー回路セル４４を複数段直列接続したスイッチング回路８と、スイッチング回路８を構成する複数のＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8にそれぞれ光ファイバーケーブル１８1、１８2、１８3、…、１８8を介して接続される複数のＥＯ変換器２２1、２２2、２２3、…、２２8と、複数のＥＯ変換器２２1、２２2、２２3、…、２２8にそれぞれ接続され、スイッチング回路４を構成する複数のＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8を同時にオン／オフ制御可能な複数のパルスディレー回路２４1、２４2、２４3、…、２４8とを備える。光ファイバーケーブル１８1、１８2、１８3、…、１８8は、光ファイバーケーブル束１８０としてバンドル化可能である。パルスディレー回路２４1、２４2、２４3、…、２４8は、例えば、ＦＰＧＡ回路などで構成可能である。 (Pseudo high voltage FET module: Pseudo high voltage MIS type relay module)
As shown in FIG. 11, the pseudo high voltage FET module 2 according to the fourth embodiment includes a switching circuit 8 in which a plurality of MIS type relay circuit cells 44 are connected in series, and a plurality of switching circuits 8. MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 each optical fiber cable 18 1, 18 2, 18 3, ..., a plurality of EO converter 22 which is connected through a 18 8 1, 22 2, 22 3, ..., 22 8, a plurality of EO converter 22 1, 22 2, 22 3, ..., are connected to 22 8, more MIS type relay circuit cells 44 1 constituting the switching circuit 4, 44 2, 44 3, ..., at the same time oN / oFF controllable plurality of pulse delay circuit 44 8 24 1, 24 2, 24 3, ..., and a 24 8. The optical fiber cables 18 1 , 18 2 , 18 3 ,..., 18 8 can be bundled as an optical fiber cable bundle 180. The pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 can be configured by, for example, FPGA circuits.
　複数のＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8を複数段直列接続したスイッチング回路４は、ＭＩＳ型リレー回路セル４４1の一方のドレイン側においてグローバルＡＣ端子Ｔ１に接続され、ＭＩＳ型リレー回路セル４４8の他方のドレイン側においてグローバルＡＣ端子Ｔ２に接続される。また、パルスディレー回路２４1、２４2、２４3、…、２４8の入力側は、バッファ回路２１を介して、グローバルゲート端子Ｇに接続される。 A plurality of MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., switching circuit 4 to 44 8 and a plurality of stages connected in series, connected to the global AC terminal T1 at one of the drain side of the MIS-type relay circuit cells 44 1 It is, is connected to the global AC terminal T2 at the other drain side of the MIS-type relay circuit cell 44 8. In addition, the input sides of the pulse delay circuits 24 1 , 24 2 , 24 3 ,..., 24 8 are connected to the global gate terminal G through the buffer circuit 21.
　第４の実施の形態においては、図９～図１１に示すように、ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路ＱA1、ＱA2、ＱA3、…、ＱA6による複数のＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8を直列接続して、疑似高電圧ＦＥＴモジュール２を実現している。 In the fourth embodiment, FIG. 9, as shown in-FIG. 11, SiC-MISFET AC load circuit Q A1, Q A2, Q A3 , ..., a plurality of MIS-type by Q A6 relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 are connected in series, thereby realizing the pseudo-high-voltage FET module 2.
　第４の実施の形態においては、図１１に示すように、各ＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8毎にパルスディレー回路２４1、２４2、２４3、…、２４8を設置して、オンディレー時間とオフディレー時間を調整することによって、各ＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8をプラスマイナス数ｎｓ以内、例えば、プラスマイナス１ｎｓ以内でオン／オフさせることができる。このため、各ＭＩＳ型リレー回路セル４４1、４４2、４４3、…、４４8を略同時にオン／オフさせることができる。 In the fourth embodiment, as shown in FIG. 11, the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 the pulse delay circuit 24 1 for each 8, 24 2, 24 3, ... , by installing 24 8, by adjusting the on-delay time and oFF-delay time, the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., 44 8 within plus or minus the number ns, for example, plus It can be turned on / off within minus 1 ns. Therefore, the MIS-type relay circuit cells 44 1, 44 2, 44 3, ..., it is possible to substantially turn on / off simultaneously 44 8.
　ここで、第４の実施の形態において、定格ドレイン・ソース間電圧１２００Ｖ、定格ドレインパルス電流８０ＡのＳｉＣ－ＭＩＳＦＥＴを適用した場合、定格スイッチング電圧９．６ｋＶ、定格スイッチング電流４８０Ａの疑似高電圧ＦＥＴモジュール２を実現可能である。 Here, in the fourth embodiment, when a SiC-MISFET having a rated drain-source voltage of 1200 V and a rated drain pulse current of 80 A is applied, a pseudo high voltage FET module having a rated switching voltage of 9.6 kV and a rated switching current of 480 A 2 can be realized.
　また、第４の実施の形態の変形例によれば、このＦＥＴ並列回路セルを複数段直列化したスイッチング回路のＭＩＳ型リレー回路セルを実質的に略同時にオン／オフ制御可能であり、ＭＩＳ型リレー回路セルの分圧バランスを良好に保持可能な高速スイッチング性能の疑似高電圧ＦＥＴモジュール（疑似高電圧ＭＩＳ型リレーモジュール）を提供することができる。 Further, according to the modification of the fourth embodiment, the MIS type relay circuit cell of the switching circuit in which a plurality of FET parallel circuit cells are serially connected can be controlled on / off substantially at the same time. It is possible to provide a pseudo high voltage FET module (pseudo high voltage MIS type relay module) having a high speed switching performance capable of satisfactorily maintaining the partial pressure balance of the relay circuit cell.
　また、第４の実施の形態において、ＡＢＤがＦＥＴ並列回路セルに接続されている場合、アバランシェ降伏電圧以上の電圧サージを吸収可能なＭＩＳ型リレー回路セルを提供することができる。 Further, in the fourth embodiment, when the ABD is connected to the FET parallel circuit cell, it is possible to provide a MIS type relay circuit cell that can absorb a voltage surge higher than the avalanche breakdown voltage.
　（半導体デバイスの構成例）
　―ＳｉＣ　ＤＩＭＩＳＦＥＴ―
　第１～第４の実施の形態に係る疑似高電圧ＦＥＴモジュール１・２に適用可能な半導体デバイス１００の例であって、ＳｉＣ　ＤＩ（Double Implanted）ＭＩＳＦＥＴの模式的断面構造は、図１２に示すように表される。 (Configuration example of semiconductor device)
-SiC DMISFET-
FIG. 12 shows an example of a semiconductor device 100 applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments, and a schematic cross-sectional structure of a SiC DI (Double Implanted) MISFET. It is expressed as follows.
　第１～第４の実施の形態に係る疑似高電圧ＦＥＴモジュール１・２に適用可能なＳｉＣ　ＤＩＭＩＳＦＥＴは、図１２に示すように、ｎ+ＳｉＣ基板１２４と、ｎ+ＳｉＣ基板１２４上にエピタキシャル成長されたｎ-ドリフト層１２６と、ｎ-ドリフト層１２６の表面側に形成されたｐボディ領域１２８と、ｐボディ領域１２８の表面に形成されたｎ+ソース領域１３０と、ｐボディ領域１２８間のｎ-ドリフト層１２６の表面上に配置されたゲート絶縁層１３２と、ゲート絶縁層１３２上に配置されたゲート電極１３８と、ｎ+ソース領域１３０およびｐボディ領域１２８に電気的に接続されたソース電極１３４と、ｎ+ＳｉＣ基板１２４の、ｎ-ドリフト層１２６と反対側の表面に電気的に接続されたドレイン電極１３６とを備える。 The SiC DIMISFET applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments is epitaxially grown on an n + SiC substrate 124 and an n + SiC substrate 124 as shown in FIG. N − drift layer 126, p body region 128 formed on the surface side of n − drift layer 126, n + source region 130 formed on the surface of p body region 128, and n between p body region 128 - a gate insulating layer 132 disposed on the surface of the drift layer 126, a gate electrode 138 disposed on the gate insulating layer 132, electrically connected to the source electrode to the n + source region 130 and the p-body region 128 134 and a drain electrode 136 electrically connected to the surface of the n + SiC substrate 124 opposite to the n − drift layer 126.
　図１２では、半導体デバイス１００は、ｐボディ領域１２８と、ｐボディ領域１２８の表面に形成されたｎ+ソース領域１３０が、ダブルイオン注入（ＤＩ）で形成され、ソースパッド電極ＳＰは、ｎ+ソース領域１３０およびｐボディ領域１２８に接続されたソース電極１３４に接続される。ゲートパッド電極ＧＰ（図示省略）は、ゲート絶縁層１３２上に配置されたゲート電極１３８に接続される。また、ソースパッド電極ＳＰ・ソース電極１３４およびゲートパッド電極ＧＰ（図示省略）は、図１２に示すように、半導体デバイス１００の表面を覆うパッシベーション用の層間絶縁膜１４４上に配置される。 In FIG. 12, in the semiconductor device 100, a p body region 128 and an n + source region 130 formed on the surface of the p body region 128 are formed by double ion implantation (DI), and the source pad electrode SP is n +. Connected to source electrode 134 connected to source region 130 and p body region 128. The gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating layer 132. The source pad electrode SP / source electrode 134 and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144 that covers the surface of the semiconductor device 100 as shown in FIG.
　―ＳｉＣ　ＴＭＩＳＦＥＴ―
　第１～第４の実施の形態に係る疑似高電圧ＦＥＴモジュール１・２に適用可能な半導体デバイス１００の例であって、ＳｉＣ　ＴＭＩＳＦＥＴの模式的断面構造は、図１３に示すように表される。 ―SiC TMISFET―
13 is an example of the semiconductor device 100 applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments, and a schematic cross-sectional structure of the SiC TMISFET is expressed as shown in FIG. .
　第１～第４の実施の形態に係る疑似高電圧ＦＥＴモジュール１・２に適用可能なＳｉＣ　ＴＭＩＳＦＥＴは、図１３に示すように、ｎ+ＳｉＣ基板１２４と、ｎ+ＳｉＣ基板１２４上にエピタキシャル成長されたｎ-ドリフト層１２６Ｎと、ｎ-ドリフト層１２６Ｎの表面側に形成されたｐボディ領域１２８と、ｐボディ領域１２８の表面に形成されたｎ+ソース領域１３０と、ｐボディ領域１２８を貫通し、ｎ-ドリフト層１２６Ｎまで形成されたトレンチの内にゲート絶縁層１３２および層間絶縁膜１４４Ｕ・１４４Ｂを介して形成されたトレンチゲート電極１３８ＴＧと、ソース領域１３０およびｐボディ領域１２８に接続されたソース電極１３４と、ｎ+ＳｉＣ基板１２４の、ｎ-ドリフト層１２６Ｎと反対側の表面に電気的に接続されたドレイン電極１３６とを備える。 The SiC TMISFET applicable to the pseudo high voltage FET modules 1 and 2 according to the first to fourth embodiments is epitaxially grown on an n + SiC substrate 124 and an n + SiC substrate 124 as shown in FIG. N − drift layer 126N, p body region 128 formed on the surface side of n − drift layer 126N, n + source region 130 formed on the surface of p body region 128, and p body region 128. , N − drift layer 126N, trench gate electrode 138TG formed through gate insulating layer 132 and interlayer insulating films 144U and 144B in the trench formed up to n − drift layer 126N, and source connected to source region 130 and p body region 128 an electrode 134, the n + SiC substrate 124, n - are electrically connected to the opposite side of the surface and the drift layer 126N And a drain electrode 136.
　図１３では、半導体デバイス１００は、ｐボディ領域１２８を貫通し、半導体基板１２６Ｎまで形成されたトレンチ内にゲート絶縁層１３２および層間絶縁膜１４４Ｕ・１４４Ｂを介して形成されたトレンチゲート電極１３８ＴＧが形成され、ソースパッド電極ＳＰは、ソース領域１３０およびｐボディ領域１２８に接続されたソース電極１３４に接続される。ゲートパッド電極ＧＰ（図示省略）は、ゲート層１３２上に配置されたゲート電極１３８に接続される。また、ソースパッド電極ＳＰ・ソース電極１３４およびゲートパッド電極ＧＰ（図示省略）は、図１３に示すように、半導体デバイス１００の表面を覆うパッシベーション用の層間絶縁膜１４４Ｕ上に配置される。 In FIG. 13, in the semiconductor device 100, a trench gate electrode 138TG formed through the gate insulating layer 132 and the interlayer insulating films 144U and 144B is formed in the trench formed through the p body region 128 to the semiconductor substrate 126N. The source pad electrode SP is connected to the source electrode 134 connected to the source region 130 and the p body region 128. The gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate layer 132. The source pad electrode SP / source electrode 134 and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144U that covers the surface of the semiconductor device 100 as shown in FIG.
　ＳｉＣ－ＴＭＩＳＦＥＴはドレイン電流経路にｐボディ領域１２８から伸張するジャンクション抵抗が存在しないため、ＳＩＣ　ＤＭＩＳＦＥＴと比較してさらに低オン抵抗のＦＥＴを提供することが可能であり、１素子当たりに１００Ａ以上のドレインパルス電流を許容することも可能になる。 Since the SiC-TMISFET does not have a junction resistance extending from the p body region 128 in the drain current path, it is possible to provide a FET having a lower on-resistance than SIC DMISFET, and more than 100 A per element can be provided. It is also possible to allow a drain pulse current.
　また、第１～第４の実施の形態に係る疑似高電圧ＦＥＴモジュール１・２に適用可能な半導体デバイス１００には、ＳｉＣ系ＭＩＳＦＥＴの代わりに、ＧａＮ系ＦＥＴなどを適用することもできる。 Also, a GaN-based FET or the like can be applied to the semiconductor device 100 applicable to the pseudo high- voltage FET modules 1 and 2 according to the first to fourth embodiments instead of the SiC-based MISFET.
　ＳｉＣデバイスは、高絶縁破壊電界（例えば、約３ＭＶ／ｃｍであり、Ｓｉの約３倍）であることから、Ｓｉに比べてドリフト層の膜厚を薄くし、かつキャリア濃度を高く設定しても耐圧が確保できる。絶縁破壊電界の違いから、ＳｉＣ－ＭＩＳＦＥＴのピーク電界強度は、Ｓｉ－ＭＩＳＦＥＴのピーク電界強度よりも高く設定可能である。 Since the SiC device has a high breakdown electric field (for example, about 3 MV / cm, about 3 times that of Si), the drift layer is made thinner and the carrier concentration is set higher than that of Si. Can withstand pressure. Due to the difference in the breakdown electric field, the peak electric field strength of the SiC-MISFET can be set higher than the peak electric field strength of the Si-MISFET.
　ＳｉＣ－ＭＩＳＦＥＴにおいては、必要なｎ-ドリフト層１２６・１２６Ｎの膜厚が薄く、キャリア濃度と膜厚の双方のメリットによって、ｎ-ドリフト層１２６・１２６Ｎの抵抗値を低減し、オン抵抗Ｒonを低くすることができ、チップ面積を縮小化（小チップ化）可能である。さらにユニポーラデバイスであるＭＩＳＦＥＴ構造のままで、Ｓｉ　ＩＧＢＴに比肩し得る耐圧を実現可能であることから、高耐圧でかつ高速スイッチングできるとされ、スイッチング損失の低減が期待できる。 In SiC-MISFET, required n - thin thickness of the drift layer 126 · 126N, by both the benefits of carrier concentration and thickness, n - reducing the resistance of the drift layer 126 · 126N, resistance R on The chip area can be reduced (smaller chip). Further, since the MISFET structure which is a unipolar device can be used, a breakdown voltage comparable to that of a Si IGBT can be realized, so that a high breakdown voltage and high-speed switching can be realized, and a reduction in switching loss can be expected.
　以上説明したように、本発明によれば、ＳｉＣ―ＭＩＳＦＥＴ並列回路セルおよびこのＦＥＴ並列回路セルを複数段直列化した、大電流をＭＨｚ級の周波数でスイッチング可能な疑似高電圧ＦＥＴモジュールを提供することができる。 As described above, according to the present invention, a SiC-MISFET parallel circuit cell and a pseudo high voltage FET module capable of switching a large current at a frequency in the MHz class, in which a plurality of FET parallel circuit cells are serialized, are provided. be able to.
　[その他の実施の形態]
　上記のように、第１～第４の実施の形態によって記載したが、この開示の一部をなす論述および図面は例示的なものであり、この発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例および運用技術が明らかとなろう。 [Other embodiments]
As described above, the first to fourth embodiments have been described. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. Absent. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
　また、ＦＥＴの高速化動作、もしくは誤動作回避を目的として、ゲートオフ時のゲート・ソース間電圧を負電圧側に引いても良い。 Also, the gate-source voltage at the gate-off time may be pulled to the negative voltage side for the purpose of speeding up the FET operation or avoiding malfunction.
　このように、本発明はここでは記載していない様々な実施の形態などを含む。 Thus, the present invention includes various embodiments that are not described herein.
　本発明のＦＥＴ並列回路セルおよび疑似高電圧ＦＥＴモジュールは、パワーＳｉＣ－ＭＩＳＦＥＴを用いた高電圧高速スイッチを有するパルスパワー発生装置、高繰り返し高電圧パルスパワー発生装置など幅広い応用分野に適用可能である。 The FET parallel circuit cell and pseudo high voltage FET module of the present invention can be applied to a wide range of application fields such as a pulse power generator having a high voltage high speed switch using a power SiC-MISFET and a high repetition voltage high voltage pulse power generator. .
１、１Ａ、２…疑似高電圧ＦＥＴモジュール
４、８…スイッチング回路
１０、１０1、１０2、１０3、…、１０8、３４、３４Ａ…ＦＥＴ並列回路セル
１２、１２1、１２2、１２3、…、１２6…ゲートドライブ回路
１４…ＯＥ変換器
１６、２８、２８Ａ…絶縁型ＤＣ／ＤＣ変換器
１８、１８1、１８2、１８3、…、１８8…光ファイバーケーブル
２０…ゲートドライブ電圧供給線
２１…バッファ回路
２２、２２1、２２2、２２3、…、２２6…ＥＯ変換器
２４1、２４2、２４3、…、２４6…パルスディレー回路
２６…サージ吸収回路
３０、３０Ａ…ＳｉＣ－ＭＩＳＦＥＴ駆動回路
３２、３２Ａ…６並列ＳｉＣ－ＭＩＳＦＥＴ回路
３６…樹脂ボックス
３８…発振回路
４０…整流回路
４４、４４1、４４2、４４3、…、４４6…ＭＩＳ型リレー回路セル
５０1、５０2…逆阻止型スイッチ
１００、ＱSA、ＱSB、Ｑ１、Ｑ２…半導体デバイス（ＳｉＣ－ＭＩＳＦＥＴ）
１２４…ｎ+ＳｉＣ基板
１２６、１２６Ｎ…ｎ-ドリフト層
１２８…ｐボディ領域
１３０…ソース領域
１３２…ゲート絶縁膜
１３４…ソース電極
１３６…ドレイン電極
１３８、１３８ＴＧ…ゲート電極
１４４、１４４Ｕ、１４４Ｂ…層間絶縁膜
１８０、１８０Ａ…光ファイバーケーブル束
ＱS1、ＱS2、ＱS3、…、ＱS6…ＳｉＣ－ＭＩＳＦＥＴ
ＱM1、ＱM2、ＱM3、…、ＱM6…Ｓｉ－ＭＩＳＦＥＴ
ＱA1、ＱA2、ＱA3、…、ＱA6…ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路
Ｇ…グローバルゲート端子
Ｄ（＋）…グローバルドレイン端子
Ｓ（－）…グローバルソース端子
ＤＴ１、ＤＴ２…突合せダイオード
Ｄ１、Ｄ２…ダイオード
Ｐ(＋)…正側電力端子
Ｎ(－)…負側電力端子
ＴＡ、ＴＢ・・・ＡＣ端子
Ｔ１、Ｔ２・・・グローバルＡＣ端子
Ｌ１…１次側コイル
Ｌ２…２次側コイル
ＬS…沿面距離
 
  1, 1A, 2 ... pseudo-high- voltage FET modules 4,8 ... switching circuit 10,10 1, 10 2, 10 3 , ..., 10 8, 34,34A ... FET parallel circuit cells 12, 12 1, 12 2, 12 3, ..., 12 6 ... gate drive circuit 14 ... OE converter 16,28,28A ... insulated type DC / DC converter 18 1, 18 2, 18 3, ..., 18 8 ... optical fiber cable 20 ... gate drive Voltage supply line 21... Buffer circuit 22, 22 1 , 22 2 , 22 3 ,..., 22 6 ... EO converters 24 1 , 24 2 , 24 3 , ..., 24 6 ... pulse delay circuit 26. 30A ... SiC- MISFET drive circuit 32, 32A ... 6 parallel SiC-MISFET circuit 36 ... resin box 38 ... oscillation circuit 40 ... rectifying circuit 44 1, 44 2, 44 3, ..., 44 6 ... IS type relay circuit cells 50 1, 50 2 ... reverse blocking switch 100, Q SA, Q SB, Q1, Q2 ... semiconductor device (SiC-MISFET)
124 ... n + SiC substrates 126, 126N ... n - drift layer 128 ... p body region 130 ... source region 132 ... gate insulating film 134 ... source electrode 136 ... drain electrode 138, 138TG ... gate electrodes 144, 144U, 144B ... interlayer insulation Membrane 180, 180A ... Optical fiber cable bundle Q S1 , Q S2 , Q S3 , ..., Q S6 ... SiC-MISFET
Q M1 , Q M2 , Q M3 , ..., Q M6 ... Si-MISFET
Q A1 , Q A2 , Q A3 ,..., Q A6 ... SiC-MISFET AC load circuit G ... Global gate terminal D (+) ... Global drain terminal S (-) ... Global source terminals DT1, DT2 ... Butting diodes D1, D2 ... Diode P (+) ... Positive power terminal N (-) ... Negative power terminal TA, TB ... AC terminals T1, T2 ... Global AC terminal L1 ... Primary coil L2 ... Secondary coil L S … Creepage distance

Claims (17)

  1. 　並列接続された複数のＳｉＣ－ＭＩＳＦＥＴと、
    　複数の前記ＳｉＣ－ＭＩＳＦＥＴのゲートにそれぞれ接続された複数のゲートドライブ回路と、
    　複数の前記ゲートドライブ回路にゲート駆動信号を供給するＯＥ変換器と、
    　複数の前記ゲートドライブ回路と前記ＯＥ変換器に電源を供給する絶縁型ＤＣ／ＤＣ変換器と
    　を備えることを特徴とするＦＥＴ並列回路セル。     A plurality of SiC-MISFETs connected in parallel;
    A plurality of gate drive circuits respectively connected to gates of the plurality of SiC-MISFETs;
    An OE converter for supplying a gate drive signal to the plurality of gate drive circuits;
    An FET parallel circuit cell comprising: a plurality of the gate drive circuits and an insulated DC / DC converter that supplies power to the OE converter.
  2. 　前記ＳｉＣ－ＭＩＳＦＥＴと並列接続され、サージ電圧を吸収するサージ吸収回路を備えることを特徴とする請求項１に記載のＦＥＴ並列回路セル。 The FET parallel circuit cell according to claim 1, further comprising a surge absorption circuit connected in parallel with the SiC-MISFET and absorbing a surge voltage.
  3. 　前記絶縁型ＤＣ／ＤＣ変換器は、
    　発振回路と、
    　前記発振回路に接続された１次側コイルと、
    　前記１次側コイルと沿面距離離隔して配置され、前記１次側コイルからワイヤレス給電可能な２次側コイルと、
    　前記２次側コイルに接続された整流回路と
    　を備える
    　ることを特徴とする請求項１または２に記載のＦＥＴ並列回路セル。     The insulated DC / DC converter is
    An oscillation circuit;
    A primary coil connected to the oscillation circuit;
    A secondary coil disposed at a creeping distance from the primary coil and capable of wireless power feeding from the primary coil;
    The FET parallel circuit cell according to claim 1, further comprising: a rectifier circuit connected to the secondary coil.
  4. 　前記整流回路の出力と前記ゲートドライブ回路の入力間に接続された蓄電回路と、
    　前記整流回路の出力に第１アノードが接続され、前記ゲートドライブ回路の入力に第１カソードが接続された第１突合せダイオードと、
    　前記蓄電回路を介して第２アノードが前記整流回路の出力に接続され、前記ゲートドライブ回路の入力に第２カソードが接続された第２突合せダイオードと
    　を備えることを特徴とする請求項３に記載のＦＥＴ並列回路セル。     A storage circuit connected between the output of the rectifier circuit and the input of the gate drive circuit;
    A first butt diode having a first anode connected to the output of the rectifier circuit and a first cathode connected to an input of the gate drive circuit;
    4. A second butt diode having a second anode connected to the output of the rectifier circuit via the power storage circuit and a second cathode connected to an input of the gate drive circuit. 5. FET parallel circuit cell.
  5. 　前記蓄電回路は、リチウムイオン電池、スーパーキャパシタ、もしくは電気二重槽キャパシタのいずれかを備えることを特徴とする請求項４に記載のＦＥＴ並列回路セル。 5. The FET parallel circuit cell according to claim 4, wherein the storage circuit includes any one of a lithium ion battery, a super capacitor, and an electric double tank capacitor.
  6. 　前記発振回路と前記１次側コイルを内蔵し、前記絶縁型ＤＣ／ＤＣ変換器の絶縁耐圧を制御可能な収納器を備えることを特徴とする請求項３～５のいずれか１項に記載のＦＥＴ並列回路セル。 6. The storage device according to claim 3, further comprising a container that includes the oscillation circuit and the primary side coil and that can control a withstand voltage of the insulation type DC / DC converter. FET parallel circuit cell.
  7. 　前記収納器は、樹脂もしくはセラミックスで形成されていることを特徴とする請求項６に記載のＦＥＴ並列回路セル。 The FET parallel circuit cell according to claim 6, wherein the container is made of resin or ceramics.
  8. 　請求項１～７のいずれか１項に記載のＦＥＴ並列回路セルを複数段直列接続したスイッチング回路と、
    　前記スイッチング回路を構成する複数の前記ＦＥＴ並列回路セルにそれぞれに光ファイバーケーブルを介して接続される複数のＥＯ変換器と、
    　複数の前記ＥＯ変換器にそれぞれ接続され、前記スイッチング回路を構成する複数の前記ＦＥＴ並列回路セルを実質的に同時にオン／オフ制御可能な複数のパルスディレー回路と
    　を備えることを特徴とする疑似高電圧ＦＥＴモジュール。     A switching circuit in which a plurality of FET parallel circuit cells according to any one of claims 1 to 7 are connected in series;
    A plurality of EO converters connected to the plurality of FET parallel circuit cells constituting the switching circuit via optical fiber cables;
    A plurality of pulse delay circuits connected to each of the plurality of EO converters and capable of simultaneously controlling on / off of the plurality of FET parallel circuit cells constituting the switching circuit. Voltage FET module.
  9. 　ｍ行ｎ列に配置するｍ×ｎ個のＳｉＣ－ＭＩＳＦＥＴの立ち上がり特性を測定して、立ち上がり時間が最も速いＳｉＣ－ＭＩＳＦＥＴからｍ番目に速いＳｉＣ－ＭＩＳＦＥＴまでを抽出し、最も速いＳｉＣ－ＭＩＳＦＥＴからｍ番目に速いＳｉＣ－ＭＩＳＦＥＴまでをそれぞれ異なるｍ個のＦＥＴ並列回路セルに配置することを特徴とする請求項８に記載の疑似高電圧ＦＥＴモジュール。 The rise characteristics of m × n SiC-MISFETs arranged in m rows and n columns are measured to extract from the fastest rise time SiC-MISFET to the mth fastest SiC-MISFET, and from the fastest SiC-MISFET 9. The pseudo high voltage FET module according to claim 8, wherein the m-th fastest SiC-MISFET is arranged in m different FET parallel circuit cells.
  10. 　並列接続された複数のＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路と、
    　複数の前記ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路のゲートにそれぞれ接続された複数のゲートドライブ回路と、
    　複数の前記ゲートドライブ回路にゲート駆動信号を供給するＯＥ変換器と、
    　複数の前記ゲートドライブ回路と前記ＯＥ変換器に電源を供給する絶縁型ＤＣ／ＤＣ変換器と
    　を備えることを特徴とするＭＩＳ型リレー回路セル。     A plurality of SiC-MISFET AC load circuits connected in parallel;
    A plurality of gate drive circuits respectively connected to gates of the plurality of SiC-MISFET AC load circuits;
    An OE converter for supplying a gate drive signal to the plurality of gate drive circuits;
    An MIS type relay circuit cell comprising: a plurality of the gate drive circuits and an insulated DC / DC converter that supplies power to the OE converter.
  11. 　前記ＳｉＣ－ＭＩＳＦＥＴ　ＡＣ負荷回路は、
    　第１のＳｉＣ－ＭＩＳＦＥＴと、
    　前記第１のＳｉＣ－ＭＩＳＦＥＴと直列に接続され、前記第１のＳｉＣ－ＭＩＳＦＥＴの第１ソースと第２ソースが接続され、前記第１のＳｉＣ－ＭＩＳＦＥＴの第１ゲートと第２ゲートが共通に接続された第２のＳｉＣ－ＭＩＳＦＥＴと、
    　前記第１のＳｉＣ－ＭＩＳＦＥＴの主電極間に逆並列接続された第１ダイオードと、
    　前記第２のＳｉＣ－ＭＩＳＦＥＴの主電極間に逆並列接続された第２ダイオードと
    　を備え、
    　前記第１のＳｉＣ－ＭＩＳＦＥＴの第１ドレインと前記第２のＳｉＣ－ＭＩＳＦＥＴの第２ドレイン間のＡＣ電流を制御可能であることを特徴とする請求項１０に記載のＭＩＳ型リレー回路セル。     The SiC-MISFET AC load circuit is
    A first SiC-MISFET;
    The first SiC-MISFET is connected in series, the first source of the first SiC-MISFET is connected to the second source, and the first gate and the second gate of the first SiC-MISFET are shared. A second connected SiC-MISFET;
    A first diode connected in antiparallel between main electrodes of the first SiC-MISFET;
    A second diode connected in reverse parallel between the main electrodes of the second SiC-MISFET,
    11. The MIS type relay circuit cell according to claim 10, wherein an AC current between the first drain of the first SiC-MISFET and the second drain of the second SiC-MISFET can be controlled.
  12. 　前記絶縁型ＤＣ／ＤＣ変換器は、
    　発振回路と、
    　前記発振回路に接続された１次側コイルと、
    　前記１次側コイルと沿面距離離隔して配置され、前記１次側コイルからワイヤレス給電可能な２次側コイルと、
    　前記２次側コイルに接続された整流回路と
    　を備える
    　ることを特徴とする請求項１０または１１に記載のＭＩＳ型リレー回路セル。     The insulated DC / DC converter is
    An oscillation circuit;
    A primary coil connected to the oscillation circuit;
    A secondary coil disposed at a creeping distance from the primary coil and capable of wireless power feeding from the primary coil;
    The MIS relay circuit cell according to claim 10, further comprising: a rectifier circuit connected to the secondary coil.
  13. 　前記整流回路の出力と前記ゲートドライブ回路の入力間に接続された蓄電回路と、
    　前記整流回路の出力に第１アノードが接続され、前記ゲートドライブ回路の入力に第１カソードが接続された第１突合せダイオードと、
    　前記蓄電回路を介して第２アノードが前記整流回路の出力に接続され、前記ゲートドライブ回路の入力に第２カソードが接続された第２突合せダイオードと
    　を備えることを特徴とする請求項１２に記載のＭＩＳ型リレー回路セル。     A storage circuit connected between the output of the rectifier circuit and the input of the gate drive circuit;
    A first butt diode having a first anode connected to the output of the rectifier circuit and a first cathode connected to an input of the gate drive circuit;
    13. A second butt diode having a second anode connected to the output of the rectifier circuit via the power storage circuit and a second cathode connected to an input of the gate drive circuit. MIS type relay circuit cell.
  14. 　前記蓄電回路は、リチウムイオン電池、スーパーキャパシタ、もしくは電気二重槽キャパシタのいずれかを備えることを特徴とする請求項１３に記載のＭＩＳ型リレー回路セル。 14. The MIS type relay circuit cell according to claim 13, wherein the power storage circuit includes any one of a lithium ion battery, a super capacitor, and an electric double tank capacitor.
  15. 　前記発振回路と前記１次側コイルを内蔵し、前記絶縁型ＤＣ／ＤＣ変換器の絶縁耐圧を制御可能な収納器を備えることを特徴とする請求項１２～１４のいずれか１項に記載のＭＩＳ型リレー回路セル。 15. The storage device according to claim 12, further comprising a housing that includes the oscillation circuit and the primary side coil and that can control a withstand voltage of the insulation type DC / DC converter. MIS type relay circuit cell.
  16. 　前記収納器は、樹脂もしくはセラミックスで形成されていることを特徴とする請求項１５に記載のＭＩＳ型リレー回路セル。 The MIS type relay circuit cell according to claim 15, wherein the container is made of resin or ceramics.
  17. 　請求項１０～１６のいずれか１項に記載のＭＩＳ型リレー回路セルを複数段直列接続したスイッチング回路と、
    　前記スイッチング回路を構成する複数の前記ＭＩＳ型リレー回路セルにそれぞれに光ファイバーケーブルを介して接続される複数のＥＯ変換器と、
    　複数の前記ＥＯ変換器にそれぞれ接続され、前記スイッチング回路を構成する複数の前記ＭＩＳ型リレー回路セルを実質的に同時にオン／オフ制御可能な複数のパルスディレー回路と
    　を備えることを特徴とする疑似高電圧ＦＥＴモジュール。     A switching circuit in which a plurality of stages of the MIS type relay circuit cells according to any one of claims 10 to 16 are connected in series;
    A plurality of EO converters connected to the plurality of MIS relay circuit cells constituting the switching circuit via optical fiber cables, respectively;
    A plurality of pulse delay circuits which are respectively connected to the plurality of EO converters and capable of substantially simultaneously controlling on / off of the plurality of MIS relay circuit cells constituting the switching circuit. High voltage FET module.
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