WO2015129481A1

WO2015129481A1 - Reception device and reception method

Info

Publication number: WO2015129481A1
Application number: PCT/JP2015/053927
Authority: WO
Inventors: 田中　勝之; 均富山; 卓寳地
Original assignee: ソニー株式会社
Priority date: 2014-02-28
Filing date: 2015-02-13
Publication date: 2015-09-03

Abstract

This disclosure pertains to a reception device and a reception method that make it possible to reduce power consumption without reducing how often positioning is performed. A frequency conversion unit converts a received RF signal to an IF signal of a lower intermediate frequency by multiplying the RF signal by a local-oscillator signal generated by a local oscillator circuit. A control unit controls the frequency conversion unit such that each part of the RF-signal path therein, i.e. the pathway that the RF signal follows within the frequency conversion unit, operates intermittently. This technology can be applied, for example, to a reception device that receives signals from GPS satellites.

Description

Receiving apparatus and receiving method

The present disclosure relates to a receiving device and a receiving method, and more particularly, to a receiving device and a receiving method that can reduce power without reducing the positioning frequency.

Car navigation equipment is equipped with a GPS receiver that receives signals from GPS (Global Positioning System) satellites and measures the current location. The basic function of the GPS receiver is to receive signals from four or more GPS satellites, calculate the position of the receiver from the received signals, and inform the user. That is, the GPS receiver demodulates the signal from each GPS satellite to acquire the orbit data of the GPS satellite, and calculates the three-dimensional position of the receiver from simultaneous equations using the GPS satellite orbit and time information and the delay time of the received signal. derive. The reason why four reception satellites are required is that there is an error between the time inside the receiver and the time of the satellite, and the influence of the error is removed.

GPS receivers are now installed in mobile phones and digital still cameras (hereinafter referred to as DSC), and the market for GPS receivers tends to expand.

In recent years, GPS receivers are also mounted on battery-powered products, and the power consumption of GPS receivers has been reduced. Recently, applications are spreading to wristwatches and wearable sports / health-oriented products, so-called wearable products, but unlike mobile phones and DSCs that have relatively large battery capacities, the relationship between required size and weight Therefore, since the battery capacity cannot be secured, further reduction in power consumption is expected.

There is a GPS receiver in which almost the entire operation of the GPS receiver is stopped at predetermined time intervals for the purpose of low power consumption (see, for example, Patent Document 1).

Japanese Patent No. 2959470

The operation of stopping almost the entire operation of the GPS receiver at a predetermined time interval is not a problem when the frequency of positioning is low, but the positioning frequency is not so high as represented by the use of behavior logs in recent years. If you do not want to drop it, the operation starts from the initial operation every time. Therefore, it is desired to reduce the power without reducing the positioning frequency.

The present disclosure has been made in view of such a situation, and is capable of reducing the power without reducing the positioning frequency.

A receiving device according to one aspect of the present disclosure multiplies a received RF signal by a local oscillation signal generated by a local oscillation circuit, thereby converting the RF signal into an IF signal having a lower intermediate frequency. And a control unit that performs control to intermittently operate each part of the RF signal path that is the signal path of the RF signal in the frequency converter.

In the reception method of one aspect of the present disclosure, the frequency conversion unit of the reception device including the frequency conversion unit and the control unit multiplies the received RF signal by the local oscillation signal generated by the local oscillation circuit. The RF signal is converted into an IF signal having a lower intermediate frequency, and the control unit performs control to intermittently operate each part of the RF signal path that is a signal path of the RF signal in the frequency conversion unit.

In one aspect of the present disclosure, the RF signal is converted to an IF signal having a lower intermediate frequency by multiplying the received RF signal by a local oscillation signal generated by a local oscillation circuit, and the frequency conversion is performed. Each part of the RF signal path which is the signal path of the RF signal in the part is intermittently operated.

The receiving device may be an independent device, or may be an internal block or a module constituting one device.

According to one aspect of the present disclosure, the power can be reduced without reducing the positioning frequency.

It should be noted that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram showing an embodiment of a receiving device concerning this indication. It is a figure which shows the example of an enable signal and IF signal corresponding to it. It is a figure explaining the received signal received with a receiver. It is a block diagram which shows the structural example of a synchronous acquisition part. It is a figure explaining the process of a synchronous acquisition part. It is a figure which shows the structural example of the channel circuit in a synchronous holding | maintenance part. It is a flowchart explaining the reception process by a receiver. It is a figure explaining the synchronous holding | maintenance part in intermittent operation | movement. It is a figure explaining the synchronous holding | maintenance part in intermittent operation | movement. It is a figure which shows the example of the demodulation result by a receiver. It is a figure which shows the relationship between C / N ratio and ranging error. It is a figure which shows the relationship between an intermittent rate and deterioration of C / N ratio. It is a figure which shows the relationship between an intermittent rate and power consumption. It is a figure explaining the intermittent operation | movement of a synchronous holding | maintenance part. It is a figure explaining the intermittent operation | movement of a synchronous holding | maintenance part. It is a figure explaining the intermittent operation | movement of a synchronous holding | maintenance part.

<Configuration example of receiving device>
FIG. 1 is a block diagram illustrating an embodiment of a reception device according to the present disclosure.

The receiving device 1 shown in FIG. 1 is a GPS receiver that receives a transmission signal transmitted from a GPS (Global Positioning System) satellite and measures the current location.

The receiving apparatus 1 includes an antenna 11, a frequency converter 12, a demodulator 13, an enable signal generator 14, an XO (crystal oscillator, X'talｔOscillator) 15, a TCXO (Temperature Compensated X'tal Oscillator) 16, and a multiplication / minute. A peripheral 17 is provided.

The antenna 11 receives a high-frequency transmission signal (hereinafter referred to as an RF signal) including a navigation message transmitted from a GPS satellite and supplies it to the frequency conversion unit 12.

The frequency converter 12 converts the frequency of the RF signal received by the antenna 11 into an IF signal (intermediate frequency signal) of an intermediate frequency (IF) and outputs the IF signal to the demodulator 13.

The frequency converter 12 includes an LNA (LowＬNoise Amplifier) 41, a BPF (Band Pass Filter) 42, an amplifier 43, a local oscillation circuit (LO) 44, an amplifier 45, a multiplier 46, an amplifier 47, and an LPF (Low Pass Filter) 48. , And ADC (Analog Digital Converter) 49.

The LNA 41 amplifies the RF signal supplied from the antenna 11 and supplies it to the BPF 42. The BPF 42 is composed of, for example, a SAW filter (Surface Acoustic Wave Filter), extracts only a specific frequency component of the RF signal amplified by the LNA 41, and supplies it to the amplifier 43.

The amplifier 43 amplifies an RF signal having a specific frequency component output from the BPF 42 and supplies the amplified RF signal to the multiplier 46. The amplifier 43 can be configured by, for example, a MOSFET (Metal Oxide Semiconductor Field effect transistor) differential amplifier, but is not limited thereto.

The local oscillation circuit 44 is constituted by, for example, a PLL (Phase Lock Loop) circuit, and generates a local oscillation signal having a predetermined frequency based on an oscillation signal supplied from a TCXO 16 described later. The local oscillation circuit 44 is controlled by, for example, the CPU 63 included in the demodulation unit 13, but is not limited to the above, and may be controlled by a control unit of an external device or the like.

The amplifier 45 amplifies the local oscillation signal supplied from the local oscillation circuit 44 and supplies the amplified signal to the multiplier 46.

The multiplier 46 multiplies the RF signal supplied from the amplifier 43 by the local oscillation signal supplied from the local oscillation circuit 44 via the amplifier 45, so that an intermediate frequency lower than the carrier frequency is obtained according to the local oscillation signal. An IF signal down-converted to a frequency (IF) is output. Typical intermediate frequencies are, for example, 4.092 MHz, 1.023 MHz, 0 Hz, and the like, but are not limited thereto.

The amplifier 47 amplifies the IF signal down-converted by the multiplier 46 and supplies the amplified IF signal to the LPF 48. The amplifier 47 can be composed of, for example, an operational amplifier, but is not limited to the above.

The LPF 48 extracts a low frequency component from the frequency components of the IF signal amplified by the amplifier 47 and supplies a signal having the extracted low frequency component to the ADC 49. 1 illustrates the example in which the LPF 48 is disposed between the amplifier 47 and the ADC 49, but a BPF may be disposed between the amplifier 47 and the ADC 49.

The ADC 49 samples the analog IF signal supplied from the LPF 48 to convert it into a digital format, and converts the IF signal converted into the digital format bit by bit into the demodulator 13 (the synchronization acquisition unit 61 and the synchronization holding unit 62). ). An analog circuit that performs signal processing in an analog format from the reception by the antenna 11 to the ADC 49 is an analog circuit, and the demodulator 13 subsequent to the ADC 49 is a digital circuit that performs signal processing in a digital format.

The demodulator 13 demodulates the IF signal output from the frequency converter 12 and outputs the position of the receiving device 1 as a processing result.

The demodulation unit 13 includes a synchronization acquisition unit 61, a synchronization holding unit 62, a CPU 63, an RTC 64, a timer 65, and a memory 66.

The synchronization acquisition unit 61 is controlled by the CPU 63 under the control of the CPU 63 based on the multiplied and / or frequency-divided oscillation signal supplied from the multiplier / divider 17 to generate a pseudo-random (PRN) IF signal output from the frequency converter 12. : Pseudo-Random Noise) code acquisition. In addition, the synchronization acquisition unit 61 detects the carrier frequency of the IF signal. Then, the synchronization acquisition unit 61 supplies the phase of the PRN code, the carrier frequency of the IF signal, and the like to the synchronization holding unit 62 and the CPU 63.

The synchronization holding unit 62 uses the signal supplied from the multiplier / divider 17 based on the control of the CPU 63 to hold the synchronization of the PRN code of the IF signal supplied from the ADC 49 and the carrier. More specifically, the synchronization holding unit 62 operates using the phase of the PRN code supplied from the synchronization acquisition unit 61 and the carrier frequency of the IF signal as initial values. Then, the synchronization holding unit 62 demodulates the navigation message included in the IF signal supplied from the ADC 49, and supplies the demodulated navigation message, the phase of the highly accurate PRN code, and the carrier frequency to the CPU 63.

The CPU 63 calculates the position and velocity of each GPS satellite based on the navigation message supplied from the synchronization holding unit 62, the phase of the PRN code, and the carrier frequency, and calculates the position of the receiving device 1.

Further, the CPU 63 controls the enable signal generation unit 14 based on the reception state of the reception signal, and controls the generation of the enable signal by the enable signal generation unit 14.

The CPU 63 is connected to a control terminal, an I / O terminal, an additional function terminal, and the like, and data and control signals necessary for processing are input / output via each terminal.

The RTC (Real Time Clock) 64 measures time based on the oscillation signal supplied from the XO 15. The time information measured by the RTC 64 is substituted, for example, until the GPS satellite time information is obtained. When the GPS satellite time information is obtained, the CPU 63 controls the timer 65. Corrected as appropriate.

The timer 65 is used, for example, to generate various timing signals for controlling the operation of each unit of the receiving device 1 in the CPU 63 and to refer to the time.

The memory 66 includes, for example, a ROM (Read Only Memory) or a RAM (Random Access Memory). The ROM constituting the memory 66 records control data such as programs and calculation parameters used by the CPU 63. The RAM temporarily stores programs executed by the CPU 63.

The enable signal generation unit 14 generates an enable signal in accordance with control from the CPU 63 and supplies the enable signal to the frequency conversion unit 12. The generated enable signal is a portion surrounded by a broken line in the frequency converter 12 in FIG. 1, that is, an amplifier 45, and an LNA 41, BPF 42, amplifier 43, and multiplication which are RF signal signal paths (RF signal paths). Is supplied to the unit 46, the amplifier 47, the LPF 48, and the ADC 49.

The enable signal generator 14 is supplied with information such as the intermittent rate (= off time / cycle) and cycle of the enable signal from the CPU 63. The enable signal generation unit 14 supplies an enable signal generated based on information from the CPU 63 to each unit of the RF signal path and the amplifier 45. Each part of the RF signal path and the amplifier 45 turn on / off the bias current or the power supply according to the enable signal. As a result, as shown in FIG. 2, the IF signal that is the output of the frequency converter 12 is intermittently output corresponding to the enable signal.

Here, the intermittent period of the enable signal is set to a period shorter than the 1-bit length of the RF signal. Since the 1-bit length of the transmission signal transmitted from the GPS satellite is 20 milliseconds as will be described later with reference to FIG. 3, in this embodiment, for example, 1 as shown in FIG. In the millisecond cycle, the frequency converter 12 performs an intermittent operation with an enable signal having an intermittent rate of 50%.

Referring back to FIG. 1, the XO 15 generates an oscillation signal having a predetermined oscillation frequency such as 32.768 kHz. Then, the XO 15 supplies the generated oscillation signal to the RTC 64.

The TCXO 16 generates an oscillation signal having a frequency different from that of the oscillation signal generated by the XO 15, such as 18.414 MHz. Then, the TCXO 16 supplies the generated oscillation signal to the multiplier / divider 17 or the local oscillation circuit 44 of the frequency conversion unit 12.

The multiplier / divider 17 multiplies or divides the oscillation signal supplied from the TCXO 16 based on an instruction from the CPU 63, or both. The multiplier / divider 17 supplies a signal that has been multiplied, divided, or both to the demodulator 13 or the like.

The receiving apparatus 1 configured as described above receives a spread spectrum signal called a C1 / A (Clear and Acquisition) code transmitted from a GPS satellite, and performs a positioning calculation. The transmission signal called the L1 band and C / A code has a transmission signal speed, that is, a chip rate of 1.023 MHz, and a pseudo-random noise (Pseudo-random Noise; PN) having a code length of 1023 such as a so-called Gold code. ) A 2-phase phase modulation method (Binary Phase Shift Keying; hereinafter referred to as BPSK modulation method) for a carrier having a frequency of 1575.42 MHz (hereinafter referred to as a carrier) using a signal obtained by directly spreading 50 bps data with a sequence spreading code. ).

<Received signal format>
FIG. 3 is a diagram for explaining a received signal transmitted from a GPS satellite and received by the receiving device 1.

The transmission signal called the L1 band and C / A code has a chip rate of 1.023 MHz and a code length of 1023. Therefore, the C / A code is spread as shown in the first row of FIG. The code is repeated with 1023 chips as one cycle, that is, 1 cycle = 1 millisecond (msec).

The spread code of this C / A code is different for each GPS satellite, but which GPS satellite uses which spread code can be detected in advance by the receiving device 1. In addition, the receiving device 1 is configured to be able to grasp which GPS satellite can receive a signal from that point and at that point by the navigation message. Therefore, for example, in the case of three-dimensional positioning, the receiving device 1 receives radio waves from at least four or more GPS satellites that can be acquired at that point and at that time, performs spectrum despreading, and performs positioning calculation. Thus, the position of itself is calculated.

Further, as shown in the second stage of FIG. 3, one bit of the signal data from the GPS satellite is transmitted for 20 cycles of the spread code, that is, in units of 20 milliseconds. That is, the data transmission rate is 50 bps as described above. Further, 1023 chips for one cycle of the spread code are inverted when the bit is “1” and when it is “0”.

Furthermore, as shown in the third row of FIG. 3, the signal from the GPS satellite forms one word with 30 bits, that is, 600 milliseconds. Furthermore, as shown in the fourth row of FIG. 3, the signal from the GPS satellite forms one subframe in 10 words, that is, 6 seconds. In the signal from the GPS satellite, as shown in the fifth row of FIG. 3, a preamble that always has a prescribed bit pattern even when data is updated to the first word of one subframe. Is inserted, and data is transmitted following this preamble.

Furthermore, the signal from the GPS satellite forms 5 subframes, that is, 1 frame in 30 seconds. In the signal from the GPS satellite, the navigation message is transmitted in the data unit of one frame.

The first three subframes of this one frame of data are information specific to GPS satellites called ephemeris information. The ephemeris information includes a parameter for obtaining the orbit of the GPS satellite and a transmission time of the signal from the GPS satellite.

All GPS satellites use the common time information by providing an atomic clock, and the transmission time of the signal from the GPS satellite included in the ephemeris information is in units of one second of the atomic clock. Further, the spread codes of GPS satellites are generated in synchronization with the atomic clock.

The trajectory information included in the ephemeris information is updated every few hours, but is the same information until the update is performed. Therefore, the receiving apparatus 1 can use the same orbit information accurately for several hours by holding the orbit information included in the ephemeris information in the memory. Note that the signal transmission time from the GPS satellite is updated every second.

On the other hand, the navigation messages of the remaining two subframes in one frame of data are information transmitted in common from all GPS satellites called almanac information. This almanac information is required for 25 frames in order to acquire all information, and is composed of approximate position information of each GPS satellite, information indicating which GPS satellite can be used, and the like. This almanac information is updated every several months, but is the same information until the update is performed. Therefore, the receiving apparatus 1 can use the same information accurately for several months by holding the almanac information in the memory.

In order to receive the signal from the GPS satellite and obtain the above-mentioned data, the receiving device 1 first removes the carrier and then uses the same spreading code as the C / A code used in the GPS satellite to be received. Using the signal from the GPS satellite, the signal from the GPS satellite is captured by phase-synchronizing the C / A code and the spectrum is despread. When the receiver 1 performs spectrum despreading in phase synchronization with the C / A code, the bits are detected, and a navigation message including time information and the like can be acquired based on a signal from a GPS satellite. Become.

The receiving device 1 captures a signal from a GPS satellite by a phase synchronization search of a C / A code. As this phase synchronization search, a correlation between a spreading code generated by itself and a spreading code of a reception signal from a GPS satellite is performed. For example, when the correlation value of the correlation detection result is larger than a predetermined value, it is determined that the two are synchronized.

<Configuration example of the synchronization acquisition unit>
FIG. 4 is a block diagram illustrating a configuration example of the synchronization capturing unit 61.

The synchronization acquisition unit 61 can be configured by a digital matched filter using a fast Fourier transform (FFT: Faster Fourier Transform) as shown in FIG. 4, for example, in order to perform synchronization acquisition of the spreading code at high speed. .

The synchronization acquisition unit 61 includes a memory 81, an FFT unit 82, a memory 83, a spreading code generator 84, an FFT unit 85, a memory 86, a multiplier 87, an IFFT (Inverted Fast Fourier Transform) unit 88, and a peak detector 89. .

The memory 81 buffers the IF signal sampled by the ADC 49 of the frequency conversion unit 12. The FFT unit 82 reads the IF signal buffered by the memory 81 and performs a fast Fourier transform. The memory 83 buffers the frequency domain signal converted from the time domain IF signal by the fast Fourier transform in the FFT unit 82.

On the other hand, the spread code generator 84 generates the same spread code as the spread code in the RF signal from the GPS satellite. The FFT unit 85 performs fast Fourier transform on the spreading code generated by the spreading code generator 84. The memory 86 buffers the frequency domain spreading code converted from the time domain spreading code by the fast Fourier transform in the FFT unit 85.

Multiplier 87 multiplies the frequency domain signal buffered in memory 83 by the frequency domain spreading code buffered in memory 86. The IFFT unit 88 performs inverse fast Fourier transform on the frequency domain signal after multiplication output from the multiplier 87. Thereby, a correlation signal in the time domain between the spread code in the RF signal from the GPS satellite and the spread code generated by the spread code generator 84 is acquired. The peak detector 89 detects the peak of the correlation signal output from the IFFT unit 88.

The synchronization acquisition unit 61 is software that executes processing of each unit of the

FFT units

82 and 85, the spread code generator 84, the multiplier 87, the IFFT unit 88, and the peak detector 89 using a DSP (Digital SignalＤProcessor). It may be realized.

FIG. 5 is a diagram illustrating an example of a peak of a correlation signal captured by the synchronization capturing unit 61.

Referring to FIG. 5, a peak P1 with a prominent correlation level is detected in the output waveform of the correlation signal for one period. The position of the peak P1 on the time axis corresponds to the beginning of the spread code. That is, the synchronization acquisition unit 61 can detect the synchronization of the received signal received from the GPS satellite (that is, detect the phase of the spread code) by detecting such a peak P1.

<Configuration example of synchronization holding unit>
On the other hand, the synchronization holding unit 62 can perform synchronization holding of a plurality of GPS satellites in parallel by providing a plurality of channel circuits 100 shown in FIG.

FIG. 6 is a diagram illustrating a configuration example of the channel circuit 100.

The channel circuit 100 is divided into a Costas loop 101 that performs carrier synchronization and a DLL (Delay Lock Loop) 102 that performs spreading code synchronization.

The IF signal output from the frequency converter 12 is multiplied by a spreading code whose phase is P (Prompt) in the multiplier 104 and input to the Costas loop 101. A spreading code whose phase is set to P (Prompt) is generated by a spreading code generator (PN Generator; hereinafter referred to as PNG) 154 to be described later, and is supplied to the multiplier 104. On the other hand, the IF signal output from the frequency converter 12 is input to the DLL 102.

In the Costas loop 101, the multiplier 108 multiplies the input signal by the cosine component of the reproduced carrier generated by the NCO (Numerical Controlled Oscillator) 106. On the other hand, the multiplier 110 multiplies the input signal by the sine component of the reproduced carrier generated by the NCO 106.

A predetermined frequency band component of the in-phase component signal obtained by the multiplier 108 is passed by the LPF 112, and this signal is supplied to the phase detector 118, the binarization circuit 120 and the square sum calculation circuit 122. As will be described later with reference to FIG. 16, the LPF 112 can be configured by an integrator that integrates the signal output from the multiplier 108 for the integration time given from the CPU 63. The same applies to other LPF 114, LPF 132, LPF 134, LPF 142, and LPF 144 described later.

On the other hand, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 110 is passed by the LPF 114, and this signal is supplied to the phase detector 118 and the square sum calculation circuit 122.

The phase information detected by the phase detector 118 based on the signals output from the

LPFs

112 and 114 is supplied to the NCO 106 via the loop filter 116. The phase information from the loop filter 116 to the NCO 106 is supplied, for example, every 1 millisecond.

In the square sum calculation circuit 122, the square sum (I ² + Q ² ) of the signals output from the

LPFs

112 and 114 is output as a correlation value (P) for a spreading code whose phase is P.

Furthermore, the signal output from the LPF 112 is also supplied to the binarization circuit 120, and information obtained by binarization in the binarization circuit 120 is output as a navigation message.

On the other hand, in the DLL 102, the input IF signal is supplied to the multiplier 124 and the multiplier 126.

In the multiplier 124, the input IF signal is multiplied by a spreading code that is E (Early) whose phase is ahead of P, and is supplied to the multiplier 128 and the multiplier 130. A spreading code whose phase is E ahead of P is generated by PNG 154 and supplied to multiplier 124.

In the multiplier 126, the input IF signal is multiplied by a spread code whose phase is L (Late) delayed from P, and supplied to the multiplier 1138 and the multiplier 140. A spreading code whose phase is L later than P is generated by PNG 154 and supplied to multiplier 126.

Then, the signal obtained by the multiplier 124 is multiplied by the multiplier 128 by the cosine component of the regenerated carrier generated by the NCO 106 in the Costas loop 101. In addition, the signal obtained by the multiplier 124 is multiplied by the multiplier 130 by the sine component of the reproduced carrier generated by the NCO 106.

A predetermined frequency band component of the in-phase component signal obtained by the multiplier 128 is passed by the LPF 132, and this signal is supplied to the square sum calculation circuit 136. On the other hand, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 130 is passed by the LPF 134, and this signal is supplied to the square sum calculation circuit 136.

In the DLL 102, the multiplier 138 multiplies the signal obtained by the multiplier 126 with the cosine component of the regenerated carrier generated by the NCO 106 in the Costas loop 101. In addition, the signal obtained by the multiplier 126 is multiplied by the multiplier 140 by the sine component of the reproduced carrier generated by the NCO 106.

A predetermined frequency band component of the in-phase component signal obtained by the multiplier 138 is passed by the LPF 142, and this signal is supplied to the square sum calculation circuit 146. On the other hand, a predetermined frequency band component of the orthogonal component signal obtained by the multiplier 140 is passed by the LPF 144, and this signal is supplied to the square sum calculation circuit 146.

Signals output from the sum of

squares calculation circuits

136 and 146 are supplied to the phase detector 148, and phase information detected by the phase detector 148 based on these signals is supplied to the NCO 152 via the loop filter 150. Is done. The phase information from the loop filter 150 to the NCO 152 is supplied, for example, every 20 milliseconds.

Further, based on a signal having a predetermined frequency generated by the NCO 152, a spreading code of each phase E, P, L is generated by the PNG 154.

The sum of squares (I ² + Q ² ) calculated by the sum-of-squares calculation circuit 136 is output as a correlation value (E) for a spreading code whose phase is E. Then, the square sum (I ² + Q ² ) calculated by the square sum calculation circuit 146 is output as a correlation value (L) for a spreading code whose phase is L.

In the synchronization holding unit 62 having the channel circuit 100 configured as described above, the GPS satellite number, the spread code phase, and the carrier frequency are set as initial values before the operation is started. Then, the synchronization holding unit 62 performs the phase of the spread code and the carrier frequency with high accuracy using the given initial value. The initial value is set by communicating directly between the synchronization capturing unit 61 and the synchronization holding unit 62 or via the CPU 63.

<Reception processing flow>
Next, reception processing by the reception device 1 will be described with reference to the flowchart of FIG. This process is started, for example, when an instruction to start reception is input via a control terminal or the like.

First, in step S1, the receiving device 1 performs initial setting. That is, the synchronization acquisition unit 61 of the demodulation unit 13 detects information such as the satellite number of the GPS satellite, the phase of the spreading code, and the carrier frequency. Then, the synchronization acquisition unit 61 supplies information such as the detected satellite number of the GPS satellite, the phase of the spreading code, and the carrier frequency to the synchronization holding unit 62 via the CPU 63 as initial values. At the beginning of reception, the intermittent rate of the enable signal generated by the enable signal generation unit 14 is 0%, and a continuous IF signal is input to the demodulation unit 13.

The synchronization acquisition unit 61 stops the operation after supplying the detected information to the synchronization holding unit 62.

In step S2, the receiving apparatus 1 starts tracking the phase of the spreading code and the carrier frequency. In other words, the synchronization holding unit 62 of the demodulation unit 13 uses the initial value supplied from the synchronization acquisition unit 61 to track the phase of the spread code and the carrier frequency.

In step S3, the CPU 63 determines whether or not the reception state is good. Specifically, the CPU 63 calculates a C / N (Carrier to Noise) ratio of the received signal and determines whether or not the C / N ratio is larger than a predetermined threshold value. The C / N ratio of the received signal can be calculated using a correlation value obtained by the synchronization holding unit 62, for example. A method for calculating the C / N ratio using the correlation value is disclosed in, for example, InsideGNSS, 2009, 9-10, pp. 20-29, but is not limited thereto.

If it is determined in step S3 that the reception state is good, the process proceeds to step S4, and the CPU 63 causes the frequency converter 12 to operate intermittently.

Specifically, the CPU 63 supplies control information representing, for example, a cycle of 1 millisecond and an intermittent rate of 50% to the enable signal generation unit 14, and the enable signal generation unit 14 provides an enable signal corresponding to the control information from the CPU 63. It is generated and supplied to each part of the frequency converter 12 except for the local oscillator circuit 44. Each part of the frequency converter 12 except the local oscillation circuit 44 performs an intermittent operation by turning on and off the bias current or the power supply based on the enable signal.

On the other hand, if it is determined in step S3 that the reception state is not good, the process proceeds to step S5, and the CPU 63 causes the frequency conversion unit 12 to operate continuously.

Specifically, the CPU 63 supplies control information indicating continuous operation to the enable signal generation unit 14, and the enable signal generation unit 14 generates an enable signal (an enable signal without intermittent) corresponding to the control information from the CPU 63. And supplied to each part of the frequency converter 12 except for the local oscillator circuit 44. Each part of the frequency converter 12 except the local oscillation circuit 44 performs continuous operation based on the enable signal.

In step S4 or step S5, when the operation currently being executed is the same as the operation after the change, the operation currently being executed is continued as it is.

After step S4 or step S5, the process returns to step S2, and the subsequent processes are repeated.

7 is executed until, for example, a reception end instruction is supplied via the control terminal or the like.

<Operation of the synchronization holding unit during intermittent operation>
Next, the operation of the synchronization holding unit 62 when the frequency conversion unit 12 is intermittently operated will be described.

FIG. 8 is a diagram for explaining the operation of the DLL 102 when the frequency conversion unit 12 is intermittently operated.

As described with reference to FIG. 3, one bit of the signal data from the GPS satellite is 20 milliseconds. Further, the intermittent period of the frequency conversion unit 12 is set to a period shorter than the 1-bit length of the RF signal, and in this embodiment, the period is 1 millisecond.

Therefore, as shown in FIG. 8, the IF signal that is intermittent in a cycle of 1 millisecond within 20 milliseconds is input to the DLL 102.

However, even if the frequency conversion unit 12 is intermittently operating, the NCO 106 and NCO 152 of the synchronization holding unit 62 are continuously operating, so that the spreading code generated by the PNG 154 of the DLL 102 is discontinuous. Absent. Therefore, even if the frequency converter 12 is intermittently operated, the phase of the spread code is not shifted.

Next, carrier synchronization will also be described with reference to FIG.

The second stage signal in FIG. 9 indicates a carrier when the intermittent operation is not performed after the multiplier 46 of the frequency converter 12 multiplies the received signal by the local oscillation signal generated by the local oscillation circuit 44. ing.

The signal in the third stage in FIG. 9 is output from the multiplier 46 when the other parts of the frequency converter 12 are intermittently operated based on the enable signal while the local oscillation circuit 44 is continuously operated. Shows career.

On the other hand, the signal in the fourth stage in FIG. 9 indicates the carrier output from the multiplier 46 when all the frequency converters 12 including the local oscillator circuit 44 are intermittently operated based on the enable signal.

When all the frequency conversion units 12 including the local oscillation circuit 44 are intermittently operated based on the enable signal, the operation of the local oscillation circuit 44 is also stopped, and when restarted, the PLL circuit starts from the initial operation every time. As shown in FIG. 9, the carrier and phase consistency at the previous ON time is not maintained. Therefore, carrier synchronization cannot be performed, and it becomes considerably unstable. As a result, positioning may not be possible.

However, when the local oscillation circuit 44 is continuously operated and the other parts of the frequency conversion unit 12 are intermittently operated based on the enable signal as the frequency conversion unit 12 performs, the local oscillation circuit 44 is Because of the continuous operation, it is possible to maintain the consistency of the carrier and phase at the previous ON time.

When the input IF signal is an intermittent signal, the

LPFs

112 and 114 of the Costas loop 101 of the synchronization holding unit 62 do not perform significant integration during a period in which no carrier is input, and therefore integration when the intermittent rate is 50%. The value is half that of continuous operation.

However, since the carrier phase is consistent, the frequency control of the NCO 106 does not become discontinuous by setting the integration time of the

LPFs

112 and 114 of the Costas loop 101 longer than the intermittent period. Can be kept in sync.

The integration time given to the

LPFs

112 and 114 of the Costas loop 101 can be, for example, 2 milliseconds, 5 milliseconds, 10 milliseconds, 20 milliseconds, etc., assuming that the intermittent period is 1 millisecond. .

<Effects of intermittent operation>
FIG. 10 shows an example of a demodulation result when the reception apparatus 1 operates the RF signal path intermittently and a demodulation result when the reception apparatus 1 operates continuously without performing the intermittent operation.

As shown in FIG. 10, when the RF signal path is intermittently operated, the C / N ratio is deteriorated by the intermittent time ratio.

However, as shown in FIG. 11, when the reception place is indoors or outdoors where there are many obstacles, the C / N ratio is greatly deteriorated, but the so-called open like outdoors where there are almost no obstacles. Under favorable conditions of sky (OpenＯSky), even if the C / N ratio is somewhat deteriorated, the influence on the position accuracy is small.

Therefore, according to the receiving apparatus 1, by intermittently operating the RF signal path, power consumption can be reduced without affecting the positioning accuracy, for example, the battery can be made longer.

Although the C / N ratio of the demodulated signal is deteriorated by intermittently operating the RF signal path, as shown in FIG. 11, there are factors other than the deterioration of the C / N ratio as the factors of ranging errors. Therefore, when the reception state is good, the influence of the C / N ratio deterioration is small.

Therefore, the CPU 63 of the receiving device 1 may control (change) the intermittent rate as well as turning on / off the intermittent operation based on the reception state of the received signal.

FIG. 12 is a diagram showing the relationship between the intermittent rate and the deterioration of the C / N ratio.

The deterioration of the C / N ratio can be expressed by ₁₀ Log ₁₀ (1-intermittent rate) [dB]. For example, when the intermittent rate is 50%, the C / N ratio deteriorates by 3 dB.

FIG. 13 is a diagram showing the relationship between the intermittent rate and the power consumption.

The decrease in power consumption is represented by the total power consumption of the intermittent operation unit that performs intermittent operation × intermittent rate.

As shown in FIG. 12 and FIG. 13, the greater the intermittent rate, the greater the deterioration of the C / N ratio. However, since the power consumption can be further reduced, the CPU 63 reduces the C / N ratio of the received signal. Whether the intermittent rate is calculated when the reception state is good and the intermittent rate is low when the reception state is bad, based on the C / N ratio, calculated using the correlation value obtained by the synchronization holding unit 62 Alternatively, the intermittent operation can be controlled to stop.

Alternatively, when the receiving device 1 includes a plurality of operation modes such as a power saving mode and the user can set a desired operation mode, the intermittent rate may be changed according to the operation mode set by the user. . For example, in the first operation mode, the intermittent operation may be performed at an intermittent rate of 20%, and in the second operation mode, the intermittent operation may be performed at an intermittent rate of 40%. it can. The mode for changing the intermittent rate based on the C / N ratio may be one of a plurality of operation modes.

<Modification>
In the above-described embodiment, during the intermittent operation, only each part of the frequency conversion unit 12 except the local oscillation circuit 44 is configured to turn on / off the operation according to the enable signal.

However, when the intermittent operation is performed, not only the frequency conversion unit 12 but also the Costas loop 101 and the multiplier of the DLL 102 and the LPF in the synchronization holding unit 62 may be intermittently operated.

Specifically, in the channel circuit 100 of FIG. 14, the multiplier 104, the multiplier 108, the multiplier 110, the multiplier 124, the multiplier 126, the multiplier 128, and the multiplier 130 are arranged on the left side of the broken line. The multiplier 138, the multiplier 140, and the LPF 112, LPF 114, LPF 132, LPF 134, LPF 142, and LPF 144 can be intermittently operated.

As shown in FIG. 14, the operation clock frequency on the left side of the broken line is higher than that on the right side. The power consumption of the holding part 62 can also be reduced effectively.

A case where the Costas loop 101, the multiplier of the DLL 102, and the LPF intermittently operate will be described with reference to FIGS.

FIG. 15 shows a detailed configuration example of the LPF 112 of the Costas loop 101. The operation of the LPF 112 will be described below, but the same applies to other LPFs.

The LPF 112 includes an adder 181, a selector 182, an accumulating unit 183, a holding unit 184, and a control unit 185.

The adder 181 adds the signal (clock signal) output from the multiplier 108 and the signal supplied from the integrating unit 183 and outputs the result to the selector 182.

The selector 182 selects one of the two input signals based on the control signal supplied from the control unit 185, and outputs the selected signal to the integrating unit 183. Specifically, when the supplied control signal is 1 (“Hi”), the selector 182 outputs the signal input from the adder 181 to the integrating unit 183, and the supplied control signal is 0 ( In the case of “Low”), the selector 182 selects the reset signal (0) that is the other input, and outputs it to the integrating unit 183.

The integrating unit 183 adds the signal supplied from the selector 182 to the previous integrated value, and outputs the addition result. When the signal from the adder 181 is supplied from the selector 182 to the accumulating unit 183, the supplied signal is added to the integration value so far. On the other hand, when a reset signal is supplied from the selector 182 to the integrating unit 183, the integrated value stored in the integrating unit 183 is reset. The signal output from the accumulating unit 183 is fed back to the adder 181 in addition to being supplied to the holding unit 184.

The holding unit 184 holds the signal (integrated value) supplied from the integrating unit 183, and the signal (integrated value) held when a control signal of 0 (“Low”) is supplied from the control unit 185. ) Is output.

The control unit 185 supplies a control signal of 1 (“Hi”) or 0 (“Low”) to the selector 182 and the holding unit 184 in accordance with the integration time supplied from the CPU 63.

FIG. 16 shows an enable signal, a control signal output from the control unit 185, a signal supplied from the multiplier 108 to the adder 181, and an integral value accumulated in the holding unit 184.

When the synchronization holding unit 62 performs an intermittent operation, the signal supplied from the multiplier 108 to the adder 181 is also an intermittent signal corresponding to the enable signal as shown in FIG. However, even in that case, the integrated values stored in the integrating unit 183 and the holding unit 184 are held without being reset, and thus the integrated value becomes smaller than that during continuous operation. There is no problem in itself.

Then, when the integration time has elapsed, a control signal of 0 (“Low”) is supplied to the selector 182 and the holding unit 184, and the integrated value up to that time is output from the holding unit 184 and also to the integrating unit 183. The stored integral value is reset.

As described above, the power consumption can be further reduced by intermittently operating not only the frequency conversion unit 12 but also the Costas loop 101 and the multipliers of the DLL 102 and the LPF in the synchronization holding unit 62.

In the example of FIG. 16, the intermittent operation of the multiplier of the Costas loop 101, the DLL 102, and the LPF is synchronized with the enable signal, but it is not always necessary to synchronize.

As described above, according to the receiving device 1, the enable signal is generated, and the positioning is performed by intermittently operating the RF signal path of the frequency converter 12 with a cycle shorter than the 1-bit length of the RF signal based on the generated enable signal. Power consumption can be reduced without reducing the frequency.

In addition, by always operating the local oscillation circuit 44 of the frequency converter 12, the carrier and the phase can be kept consistent before and after the operation is stopped, and continuous positioning is possible.

Furthermore, by controlling the intermittent rate according to the reception state, it is possible to reduce the power consumption in consideration of the deterioration of the C / N ratio. In other words, it is possible to perform reception with a balance between power consumption and reception sensitivity degradation adjusted.

In the above-described embodiment, the receiving apparatus 1 has been described as a GPS receiver that receives a transmission signal transmitted from a GPS satellite and measures the current location.

However, the technology according to the present disclosure is not limited to a receiving device that receives a transmission signal transmitted from a GPS satellite, but receives a spread spectrum signal transmitted from another GNSS (Global Navigation Satellite System) satellite. It is also applicable to the device.

Other GNSS include GLONASS (Global Navigation Satellite Systems) operated by Russia, BeiDou operated by China, Galileo operated by EU (European Union), and Japan's Quasi-Zenith Satellite as a complementary satellite.

For example, a transmission signal transmitted from a GLONASS satellite uses a carrier wave of 1602 MHz + p × 0.5625 MHz (p is the frequency channel number of each satellite) based on a spread spectrum signal having a code length of 511 and a chip rate of 0.511 MHz. This is a BPSK modulated signal.

Furthermore, the technology according to the present disclosure can be applied to a receiving apparatus that receives a plurality of GNSS transmission signals, such as a receiving apparatus that receives transmission signals from GPS satellites and GLONASS satellites.

The embodiment of the present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present disclosure.

For example, it is possible to adopt a form in which all or a part of the plurality of embodiments described above are combined.

Further, each step described in the above flowchart can be executed by one device or can be shared by a plurality of devices.

Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

It should be noted that the effects described in this specification are merely examples and are not limited, and there may be effects other than those described in this specification.

In addition, the technique of this indication can also take the following structures.
(1)
A frequency converter that converts the RF signal into an IF signal having a lower intermediate frequency by multiplying the received RF signal by a local oscillation signal generated by a local oscillation circuit;
A control unit that performs control to intermittently operate each part of the RF signal path that is the signal path of the RF signal in the frequency conversion unit.
(2)
The frequency converter has an amplifier that amplifies the local oscillation signal before multiplying the local oscillation signal by the RF signal,
The receiving device according to (1), wherein the control unit causes the amplifier to intermittently operate in addition to each unit of the RF signal path.
(3)
The receiving device according to (1) or (2), wherein in the frequency conversion unit, the local oscillation circuit continuously operates during intermittent operation of each part of the RF signal path.
(4)
The receiving device according to any one of (1) to (3), wherein the control unit also controls an intermittent rate of the intermittent operation.
(5)
The receiving device according to (4), wherein the control unit controls the intermittent rate according to a reception state of the RF signal.
(6)
The receiving apparatus according to (5), wherein the reception state of the RF signal is a C / N ratio.
(7)
The receiving device according to any one of (4) to (6), wherein the control unit controls the intermittent rate according to an operation mode.
(8)
A demodulator that demodulates the IF signal converted by the frequency converter;
The reception device according to any one of (1) to (7), wherein the control unit also causes the multiplier and the LPF in the demodulation unit to intermittently operate during intermittent operation of each unit of the RF signal path.
(9)
The receiving device according to any one of (1) to (8), wherein the control unit causes each unit of the RF signal path to intermittently operate at a cycle shorter than a 1-bit length of the RF signal.
(10)
The frequency converter of the receiving device including the frequency converter and the control unit multiplies the received RF signal by the local oscillation signal generated by the local oscillation circuit, thereby reducing the RF signal to a lower intermediate frequency. To IF signal,
A receiving method in which the control unit performs control to intermittently operate each part of an RF signal path that is a signal path of an RF signal in the frequency converter.

1 receiver, 12 frequency converter, 13 demodulator, 14 enable signal generator, 41 LNA, 42 BPF, 43 amplifier, 44 local oscillator (LO), 45 amplifier, 46 multiplier, 47 amplifier, 48 LPF, 49 ADC, 61 synchronization acquisition unit, 62 synchronization holding unit, 63 CPU, 66 memory

Claims

A frequency converter that converts the RF signal into an IF signal having a lower intermediate frequency by multiplying the received RF signal by a local oscillation signal generated by a local oscillation circuit;
A control unit that performs control to intermittently operate each part of the RF signal path that is the signal path of the RF signal in the frequency conversion unit.
The frequency converter has an amplifier that amplifies the local oscillation signal before multiplying the local oscillation signal by the RF signal,
The receiving device according to claim 1, wherein the control unit intermittently operates the amplifier in addition to each unit of the RF signal path.
The receiving device according to claim 1, wherein in the frequency conversion unit, the local oscillation circuit continuously operates during intermittent operation of each part of the RF signal path.
The receiving device according to claim 1, wherein the control unit also controls an intermittent rate of the intermittent operation.
The receiving device according to claim 4, wherein the control unit controls the intermittent rate according to a reception state of the RF signal.
The receiving apparatus according to claim 5, wherein the reception state of the RF signal is a C / N ratio.
The receiving device according to claim 4, wherein the control unit controls the intermittent rate according to an operation mode.
A demodulator that demodulates the IF signal converted by the frequency converter;
The receiving device according to claim 1, wherein the control unit also causes the multiplier and the LPF in the demodulation unit to intermittently operate during intermittent operation of each unit of the RF signal path.
The receiving device according to claim 1, wherein the control unit causes each unit of the RF signal path to intermittently operate at a cycle shorter than a 1-bit length of the RF signal.
The frequency converter of the receiving device including the frequency converter and the control unit multiplies the received RF signal by the local oscillation signal generated by the local oscillation circuit, thereby reducing the RF signal to a lower intermediate frequency. To IF signal,
A receiving method in which the control unit performs control to intermittently operate each part of an RF signal path that is a signal path of an RF signal in the frequency converter.