WO2015128360A1

WO2015128360A1 - Circuit assembly and method for controlling a junction field-effect transistor

Info

Publication number: WO2015128360A1
Application number: PCT/EP2015/053901
Authority: WO
Inventors: Ashot Melkonyan
Original assignee: Siemens Aktiengesellschaft
Priority date: 2014-02-28
Filing date: 2015-02-25
Publication date: 2015-09-03
Also published as: DE102014203655A1; CN106031040A; CN106031040B

Abstract

The invention relates to a circuit assembly for controlling a junction field-effect transistor (10) comprising a control connection (G), as well as a first main connection (D) and a second main connection (S), between which a channel is formed. The circuit assembly comprises a unit (21, 22, 24, 25, 26, 27, 28) for generating a control signal, via which the junction field-effect transistor (10) can be alternately switched back and forth between a first switching state (ON) and a second switching state (OFF). The circuit assembly comprises a current analysis unit (23) connected between the control connection (G) and the second main connection (S). The current analysis unit (23) is designed to measure the inverse current (I_g) flowing through the control connection (G), and to determine the absolute temperature of the junction field-effect transistor (10) from the magnitude of the measured current (Ig), when or as soon as the control signal-generating unit (21, 22, 24, 25, 26, 27, 28) has controlled the voltage (V_gs) applied between the control connection (G) and the second main connection (S) beyond the punch-through voltage, when transitioning from the first switching state (ON) to the second switching state (OFF).

Description

description

Circuit arrangement and method for driving a junction field effect transistor

The invention relates to a circuit arrangement and a method for driving semiconductor switching ^element in the form ei ^¬ nes junction-field effect transistor having a first main terminal and a second main terminal, between which a channel is formed.

Semiconductor switching elements are used for example as a power ^¬ switching elements. In these, there is the necessary ^¬ ness, chen to monitor the temperature of the semiconductor switching element to a safe operation of the semiconductor switching element and a semiconductor switching element module comprising (also referred to as a system) as a whole to enable. In the case of too high a temperature must be ensured by a semicon ^¬ ter switching element driving circuitry safe shutdown.

For this example, external temperature sensors, eg NTC temperature sensors, are used. These are arranged, for example, in the semiconductor ^switching element-containing module on a support plate on which the semiconductor ^{switching ¬} element is arranged. Alternatively, the external Tempe ^¬ ratursensoren also be arranged directly on a heat sink in unmittelba ^¬ rer proximity to the semiconductor switching element. In both cases, however, the temperature measurement is associated with great imponderabilities. This results primarily from the thermal capacity of the carrier plate or the heat sink and their thermal behavior. The time constant of thermal inertia reduces the reaction rate of a temperature monitoring circuit. This can lead to dynamic overheating of the module and even to thermal failure. To avoid this, the detection of the actual temperature of the semiconductor of the semiconductor switching element would he ^¬ conducive. However, this can not be done by the above-mentioned external temperature sensor.

For example, it is known from power metal oxide semiconductor field effect transistors (MOSFETs) to use the inherent pn-junction temperature characteristic to determine the chip temperature. The reverse diode (so-called body diode) is used as the temperature sensor. For the actual operation, this procedure is not suitable because the body diode during operation wheeling or return ^¬ Windwärts streams carries. Thus, the temperature can be measured by these Me ^¬ Thode only after the disconnection of the load, for which purpose a measuring signal is used by the body diode. The measuring method is currently used in the production before installation of the semiconductor switching element in a module for determining data sheet information. It is also known to use this method for characterizing the aging behavior.

It is an object of the present invention, a circuit arrangement and a method for driving a semiconductor switching element to specify which a more precise determination of the temperature during operation of the semiconductor switching element made ^¬ union.

These objects are achieved by a circuit arrangement according to the features of claim 1 and a method according to the features of claim 8. Advantageous Aus ^¬ designs emerge from the dependent claims.

The invention is based on the finding that the pn junction characteristic in a junction field effect transistor ^¬ transistor (junction field effect transistor, JFET) can be used to determine its temperature. Therefore, a circuit arrangement for driving a junction field-effect transistor is proposed which comprises a control terminal and a first main terminal and a second main terminal, between which a conductive channel is formed. The circuit arrangement comprises a unit for generating a drive signal, by which the junction field effect transistor between a first

Switching state and a second switching state alternately switched back and forth. The circuit arrangement further comprises a unit for current evaluation, which is connected between the control terminal and the second main terminal. The unit for evaluating the current is designed to measure the inverse current flowing through the control terminal and to determine the absolute temperature of the junction field effect transistor from the level of the measured current, as soon as the unit for generating the drive signal at the transition from the the first switching state to the second switching state, the voltage applied between the control terminal and the two ^¬ th main terminal voltage has controlled beyond the punch-through voltage addition.

It is further proposed a method for driving a junction field effect transistor comprising a STEU ^¬ eranschluss and a first main terminal and a second main terminal, between which a channel is formed. The circuit arrangement comprises a unit for He generation ^¬ a driving signal by which the junction field effect transistor is reciprocated alternately between a first switching state and a second switching state and action switches, and a unit for current evaluation circuit which is connected between the control terminal and the second main terminal , In the proposed method, the unit measures the current evaluation circuit the current flowing through the control terminal inverse current, and determined from the magnitude of the measured current, the absolute temperature of the junction Feldeffekttransis ^¬ gate when or as soon as the unit for generating the check-in control signal during the transition from the first switching state to the second switching state between the control terminal and the voltage applied to the second main terminal has exceeded the punch-through voltage.

According to the idea of the invention, the temperature dependence of the gate diode of the junction field-effect transistor is used for the temperature measurement. As a result, a direct highly dynamic and accurate temperature monitoring currency ^¬ rend the operation of the semiconductor switching element junction field effect transistors allows.

Use is made use of the fact that the resistance of the pn junction, that is, the gate diode, depending on the prevailing temperature is ge ^¬ rade. By evaluating the inverse current, that is the gate current, which in turn is dependent on the currently prevailing off resistance, so that a conclusion can be drawn about the prevailing at the pn junction Tempe ^¬ ture. This procedure is generally possible with such semiconductor switching elements during the operation of the semiconductor switching element, in which the control terminal (the gate) is not separated from the channel by an oxide.

In order to be able to measure the inverse current, which is also referred to below as the inverse gate current, in order to determine the temperature which is just ahead, it is provided that during the period in which the semiconductor switching element is switched off, this via the punch-through Control voltage beyond. From reaching the punch-through voltage, a reverse current from the second main terminal, i. the source terminal, towards the control terminal, i. the gate terminal on which is used for the determination of the temperature. The reverse current occurring, unless it exceeds a certain value, does not damage the semiconductor switching element since it is reversible.

The advantage of the procedure is that the measurement is basically independent of that, via the channel of the semiconductor terschaltelements flowing load current takes place and is made at ei ^¬ nem time, to which no load current flows. Thus the measurement can be carried out with high precision. Ins ^¬ particular interruptions of the semiconductor terschaltelement-containing module can be avoided due to Übertempe ^¬ temperatures. Another advantage is that the operating range of the semiconductor switching element on the basis of the ^¬ precise temperature determination with respect to a semiconductor switching element having a conventional measuring ER- weitert can be. In addition, the continuous

Monitoring the temperature of the pn junction can be used to determine the reliability, the aging behavior and a Lebenszyklusend (end-of-life) and vorherzusa ^¬ gen.

According to an expedient embodiment of the circuit arrangement, the unit for generating the drive signal is designed to control the voltage applied between the control terminal and the second main terminal to a maximum voltage, in which the current through the control terminal does not exceed a predetermined maximum value. The

Punch-through voltage is referred to as a par- allel breakthrough or "primary breakthrough." If the voltage applied between the control terminal and the second main terminal, ie, source-gate voltage, significantly exceeds the punch-through voltage, overcurrent would cause irreversible destruction This can be avoided by limiting the maximum voltage that may be used for the measurement.

According to a further expedient embodiment, the unit for generating the drive signal is designed to keep the voltage applied between the control terminal and the second main terminal constant for the duration of the measurement of the inverse current. This allows a precise ^{measurement of} the current when the semiconductor switching element is turned off and the gate diode is controlled in the reverse direction. Conveniently, the junction field effect transistor is silicon carbide. In a further embodiment, the unit for generating the drive signal comprises a microprocessor for generating a pulse width modulated (PWM) signal. Further, the unit for generating the drive signal includes a ^¬ A standardized for detecting whether the JFET assumes the second switching state to disconnect the unit for power ^¬ evaluation for the duration of the second switching state of the microprocessor. In particular, the unit for detecting whether the junction field effect transistor assumes the second switching state is adapted to disconnect the unit for evaluating the current for the duration of the measurement of the inverse current from the microprocessor.

The invention is explained in more detail below with reference to an exporting ^¬ approximately embodiment in the drawing. Show it:

1 is a schematic representation of an inventive ^¬ Shen circuitry for driving a junction field effect transistor, which allows a Tempera ^¬ turbestimmung the semiconductor,

Fig. 2 is a diagram showing the typical characteristic of

Gate current as a function of the gate-source voltage illustrated,

3 is a diagram showing the inverse gate current as a function of the gate-source voltage in the off state of a semiconductor switching element, and

Fig. 4 is a diagram showing that for the temperature-dependent

Determining the inverse gate current as a function of the voltage range of the gate-source voltage used for the measurement shows. 1 shows an exemplary embodiment of a circuit arrangement 20 according to the invention for driving a junction field effect transistor 10. For example, the junction field effect transistor 10 may be a silicon-carbon field-effect transistor (SiC-JFET). The junction field effect transistor 10 comprises a control terminal G (gate) and a first main terminal D (drain) and ei ^¬ nen second main terminal S (source). Between the first main connection D and the second main connection S, a channel is formed, via which a current can flow when the

Junction field effect transistor 10 is turned on. One between the second main terminal (S) and the first main connection (D) existing body diode is labeled in ^¬ characterized by 11.

For example, the control terminal G of the junction field effect transistor is connected to a p-type region disposed in an n-type (substrate) material. The area of the p-conductive type forms a p-n diode to the n-type material of the junction field effect transistor ^¬. A junction field effect transistor (JFET) is a semiconductor switching element that is turned on without a drive signal. Such a device is referred to as a "normally-on" semiconductor switching element, In order to prevent a current from flowing through the channel, it is necessary to apply a negative voltage to the control terminal G with respect to the second main terminal S to the semiconductor switching element The circuit ^arrangement 20, described in more detail below in detail, makes it possible to determine the temperature at the abovementioned pn junction, ie, the gate-source diode, whereby the temperature during operation of the semiconductor ^{switching element} can be determined.

The circuit arrangement 20 comprises a unit 21 for detecting a desaturation, an error memory 22, a unit 23 for current detection and evaluation, a switching element 24, a driver 25, a gate 26 and a drive signal generating microprocessor 28. The drive signal is a pulse width modulated signal (PWM signal) which is output from the microprocessor 28. Via the gate 26, which is further connected on the input side to an output of the fault memory 22, the PWM signal is applied via the switching element 24 and the current detection and evaluation unit 23 to the control terminal G of the junction field effect transistor 10, whereby the barrier layer Field effect transistor is switched in accordance with the drive signal alternately blocking and conducting.

The current detection and evaluation unit 23 is connected between the control terminal G and the second main terminal S. In the usual way, a resistor 27 (gate resistance) is provided between the current detection and evaluation unit 23 and the control terminal G. The desaturation detection unit 21 is connected to the first main terminal D (drain terminal). The desaturation detection unit 21 detects which state

(blocking or conducting) of the junction field effect transistor 10 has. This information is used to control the switching ^¬ elements 24. The switching element 24 is opened when the junction field effect transistor 10 is turned off (ie, JFET = OFF or OFF).

On the output side, the unit 21 for detecting a

Desaturation connected to the driver 25, which controls the switching position of the switching element 24 for switching on and off of the junction field effect transistor 10. Further, the desaturation detection unit 21 is coupled to the error memory 22. If an error occurs, a corresponding error signal is applied to the gate 26, so that the signal present at the output of the gate 26 ensures the blocking of the junction field effect transistor 10. The unit 29 for masking overcurrent spikes (so-called.

"Blanking time") also receives the output signal of the gate 26. The unit 29 is used to fade out to the overcurrent peaks, eg during the commutation. On the output side, the unit 29 with the unit 21 for detecting a

Linked to desaturation. The circuit ^arrangement shown in FIG. 1 corresponds to a conventional driver of a junction field effect transistor. Compared to the conventional junction field effect transistor ^¬ transistor driver only the unit 23 for current detection and evaluation is additionally provided. This can be provided for example as a simple operational amplifier circuit.

During operation of the junction field-effect transistor 10 can, when the semiconductor switching element turned off, that is turned off is (switching element 24 is opened), an inverse current is detected by the unit 23, wel ^¬ cher flows from the second main terminal S to the control terminal D. The current flows when the gate diode, ie the pn junction between control terminal G and second main terminal S, is controlled backwards and the (negative) gate-source voltage is controlled beyond the pinch-off voltage. This is the case immediately after the switching off of the semiconductor switching element and the termination of the commutation process. Meanwhile, the (negative) gate current can then be measured and used to determine the absolute temperature at the pn junction. For this it is necessary to know the behavior of the junction field effect transistor.

FIG. 2 shows a diagram showing the (positive) gate current I _g as a function of the gate-source voltage V _gs for a SiC junction field-effect transistor. In the diagram, three experimentally determined IV curves in dependence of the temperature from ^¬ are shown in pn junction. It can be clearly seen that the higher the temperature at the pn junction, the current increases with a lower gate-source voltage. While at a temperature of 25 ° C. (dash-dotted line), the gate current I _g begins to rise only at a gate-source voltage V _gs , the current I _{g is} at a a temperature of 75 ° C (dashed line) about 5 mA and at 125 ° C (solid line) about 20 mA.

Fig. 3 is a diagram showing the inverse gate current (-I _g ) versus the negative gate-source voltage (-V _gs ). In this diagram, three experimentally he ^¬ mittelte curves for two different SiC junction field effect transistors are exemplarily shown, wherein the associated with a ers ^¬ th SiC-JFET curves 310 and belonging to a second silicon carbide junction field effect transistor curves labeled 320. There are each measured curves for a prevailing at the pn junction temperature of 25 ° C, 125 ° C and 200 ° C turned ^¬ distinguished. The curves can be determined by any method.

As shown in Fig. 4, a control of the gate-source voltage V _gs is carried out by the circuit ^arrangement such that it is above the punch-through voltage U _PT. For a given gate-source voltage V _gs = measuring voltage U _{me S} s ^¬ speaks a certain inverse gate current -I _gs (= measuring current Imes s) a certain temperature (eg at -5mA at 25 ° C). For example, if the chip temperature increases to 125 ° C, V _gs = U _{me S} s increased current I _{gs will} flow at the same voltage (eg, -15mA). This current change (in the example: increase from -5 to -15mA) is evaluated.

The measurement of the inverse gate current I _gs can take place in the voltage range labeled III, which ranges from the punch-through voltage U _PT (eg -28V) up to a maximum permissible voltage U _max . The maximum measuring voltage

U _me ss ⁼ U _max is dependent on a predetermined maximum value of the current flowing through the control terminal. Would measuring ^¬ purposes the maximum measurement voltage U _me ss ⁼ V _ma x exceeded advertising the so consists in marked with an IV range, the risk of a secondary breakdown which would result for destruc ^¬ tion of the junction field effect transistor. Typically, to turn off the junction field ^¬ effect transistor, the gate-source voltage is controlled in the ge ^¬ marked with II area, ie the voltage is in the range between the pinch-off voltage U _P0 (in the example: - 22V) and the Punch-through voltage U _PT (in the example: -28V). If the voltage applied between gate and source lies in this region marked II, then the field-effect transistor is nonconductive, ie blocked. In contrast, the junction field effect transistor is conductive when it is in the region marked I, ie the gate-source voltage V _{gs is} smaller than the pinch-off voltage U _P0 .

If the reference values are known, the actual current at the p-n junction of the junction field effect transistor 10 can be inferred by the unit 23 for current detection and evaluation by a simple comparison of the measured negative gate current with the measured curves stored in a memory.

This can be done precisely and with a virtually non-existent time delay. As a result, it is possible, in particular, to prevent a shutdown of a module containing the arrangement due to overtemperature. The method can be used for DA, the reliability, the Alterungsver ^¬ hold and ermit ^¬ stuffs the expected end of life.

Claims

claims

1. Circuit arrangement for driving a junction field effect transistor (10) comprising a control terminal (G) and a first main terminal (D) and a second main terminal (S), between which a channel is formed, comprising:

a unit (21, 22, 24, 25, 26, 27, 28) for generating a drive signal, by which the junction field effect transistor (10) between a first switching state (ON) and a second switching state (OFF) alternately hin- and forth is switched ^¬ ;

a unit (23) for current evaluation, which is connected between the control terminal (G) and the second main terminal (S);

wherein the unit (23) to be constituting ^¬ for the current evaluation, the through the control terminal (G) flowing domestic verses current (I _g) to be measured and from the height of the measured current (I g) is the absolute temperature of the junction field- - Effect transistor (10) to determine if / when the unit (21, 22, 24, 25, 26, 27, 28) for generating the Ansteuersig- nals at the transition from the first switching state (ON) to the second switching state (OFF) the voltage (V _gs ) applied between the control terminal (G) and the second main terminal (S) has been controlled beyond the punch-through voltage.

2. A circuit arrangement according to claim 1, characterized in that the unit (21, 22, 24, 25, 26, 27, 28) is designed for the generation ^¬ supply of the driving signal to between the control terminal (G) and the second main connection ( S) applied voltage (V _gs ) maximum up to a voltage at which the current through the control terminal does not exceed a predetermined maximum value.

3. Circuit arrangement according to claim 1 or 2, characterized in that the unit (21, 22, 24, 25, 26, 27, 28) is designed for generating the drive signal to the between the control terminal (G) and the second main end (S) applied voltage (V _gs ) for the duration of Mes ^¬ solution of the inverse current (I _g ) to keep constant.

4. che Circuit arrangement according to one of the preceding Ansprü-, characterized in that the junction field effect transistor ^¬ (10) consists of silicon carbide.

5. Circuit arrangement according to one of the preceding claims, characterized in that the unit (21, 22, 24, 25, 26, 27, 28) for generating the drive signal comprises a Mik ^¬ roprozessor (28) for generating a PWM signal.

6. Circuit arrangement according to claim 5, characterized in that the unit (21, 22, 24, 25, 26, 27, 28) for generating the drive signal is a unit (21, 25) for detecting whether the junction field effect transistor ( 10) assumes the second switching state (OFF), to disconnect the current evaluation unit (23) for the duration of the second switching state (OFF) from the microprocessor.

7. Circuit arrangement according to claim 6, characterized in that the unit (21, 25) for detecting whether the junction field-effect transistor (10) assumes the second switching state (OFF), is adapted to the unit for current evaluation (23). for the duration of the measurement of the inverse current (I g) to be separated from the microprocessor.

8. A method for driving a junction field effect ^¬ transistor (10) having a control terminal (G) and a first main terminal (D) and a second main terminal

(S), between which a channel is formed, comprises, with egg ^¬ ner circuitry, the

a unit (21, 22, 24, 25, 26, 27, 28) for generating a drive signal, by which the junction field effect transistor (10) between a first switching state (ON) and a second switching state (OFF) alternately hin- and forth ge ^¬ is switched on, and a unit (23) for current ^evaluation , which is ver ^¬ switched between the control terminal (G) and the second main terminal (S)

comprising, wherein the unit (23) for the current evaluation to by the control terminal (G) flowing inverse current (I _g) measures and from the height of the measured current (I _g) the absolu ^¬ te temperature of the junction field effect transistor (10) be ^¬ true, if / as soon as the unit (21, 22, 24, 25, 26, 27, 28) for generating the drive signal at the transition from the first switching state (ON) to the second switching state (OFF) between the control terminal ( G) and the second main terminal (S) voltage (V _gs ) has been controlled beyond the punch-through voltage addition.

9. The method of claim 8, wherein the unit (21, 22, 24, 25, 26, 27, 28) for generating the drive signal between the control terminal (G) and the second main terminal (S) voltage applied (V _gs ) is controlled up to a voltage at which the current through the control connection does not exceed a predetermined maximum value.

10. The method according to claim 8 or 9, characterized in that the unit (21, 22, 24, 25, 26, 27, 28) for generating the drive signal between the control terminal (G) and the second main terminal (S) voltage applied (V _gs ) for the duration of the measurement of the inverse current (I _g ) keeps constant.