WO2015123534A1

WO2015123534A1 - Group iii-n substrate and transistor with implanted buffer layer

Info

Publication number: WO2015123534A1
Application number: PCT/US2015/015842
Authority: WO
Inventors: Mark J. Loboda; Gilyong Chung
Original assignee: Dow Corning Corporation
Priority date: 2014-02-14
Filing date: 2015-02-13
Publication date: 2015-08-20
Also published as: TW201539751A

Abstract

A device substrate suitable for forming a group III - N semiconductor device, the device substrate comprises a crystalline silicon wafer (100), an optional layer of CVD 3C-SiC (105) of thickness 50-1000 nm formed over the silicon substrate, a layer (110) of AIN of thickness 10-250 nm formed over the silicon substrate, or over the 3C-SiC layer when used, a buffer layer (115) formed of a plurality of films selected from the group of GaN, AIN and Al_xGa_(1-X)N (0<x<0.8) and having an ion implant layer (180) buried in the buffer. A barrier (electron supply) layer (125) of Al_xGa_(1-X)N (0.4>x>0.2) is formed over the buffer layer. A passivation layer (130) of GaN layer or silicon nitride layer may be deposited over the barrier layer. The layer are deposited in the MOCVD chamber.

Description

GROUP lll-N SUBSTRATE AND TRANSISTOR WITH IMPLANTED BUFFER LAYER

BACKGROUND

1. Field of the Application

[0001] The invention relates to Group lll-N substrates and electronic devices, such as high electron mobility transistor (HEMT), made with such substrates.

2. Related Art

[0002] Gallium nitride (GaN) is a wide band gap material that has attracted interest for fabrication of power transistors. Like silicon carbide (SiC), the fabrication of power devices using gallium nitride will result in faster switching speeds, less energy losses and greater blocking voltage compared to silicon-based power devices. Recently, new focus on GaN has developed as a result of technology to grow group Ill-nitride (lll-N) films, like GaN and AIGaN, epitaxially on silicon substrates. The combination of the silicon substrates and GaN material creates the opportunity to make power devices capable to compete with power devices made from silicon carbide but at a lower cost. For similar reasons, the integration of lll-N materials and silicon substrates has also been explored for fabrication of light emitting diodes.

[0003] Films of lll-N materials are typically deposited on substrates such as, e.g., silicon, sapphire, SiC, etc., using metal organic chemical vapor deposition (MOCVD). Organometallic molecules of aluminum and gallium are injected into an MOCVD system along with ammonia, nitrogen and hydrogen. When the substrate is heated to sufficient temperature, typically 900-1200°C, the heated surface will break down the molecules, and the reactants then condense on the surface and form crystalline films of Al-Ga-N, with the relative amounts of Al and Ga determined by the composition of the gas stream into the MOCVD system. Typically a layer of aluminum nitride (AIN) is deposited first on the silicon substrate, in order to prevent adverse reactions that can occur between the silicon and gallium vapors in the MOCVD system.

[0004] The term "substrate" is sometimes used rather loosely. In the context of this disclosure, the term "substrate" standing alone refers to the starting material upon which layers are to be deposited. The term "silicon substrate" refers to a substrate made of silicon, sometimes referred to in the art as silicon wafer. On the other hand, the term "device substrate" refers to a substrate having other layers deposited thereupon in preparation for forming electronic devices therein. For example, a silicon substrate having an AIN barrier layer and a buffer layer deposited thereupon is referred to herein as a "device substrate."

[0005] The integration of lll-N materials and silicon substrates is not without its challenges. There is large difference in the values of coefficient of thermal expansion and crystal lattice spacing between lll-N materials and silicon. The mismatch in these parameters will lead to high values of mechanical stress in the lll-N layers on silicon. If the stress is too high the substrates will bow significantly and the deposited films can form cracks.

[0006] Combinations of different crystalline film layers applied to a substrate with the intent to reduce final stress and to match lattice constants to the target final layers are often referred to as "buffer" layers. The appropriate combinations of layers and compositions are used in a sequential fashion, where each successive layer transitions the coefficient of thermal expansion and/or crystal lattice spacing values from values of that close to the substrate, to that close to the desired top crystalline film, and the result is a final system with low mechanical stress and good crystal quality.

[0007] Various combinations of lll-N crystalline films are formed on the silicon substrate to produce electronic devices like diodes and transistors. A common epitaxy structure for a GaN/Si transistor is called a high electron mobility transistor (HEMT). Generally, the structure for a lll-N HEMT on a silicon wafers sequentially consists first of a silicon substrate, a layer of SiC and/or AIN which protects the silicon from reacting with gallium vapor, a series of films deposited to form a "buffer," and then layer of material, called the barrier layer, whose bandgap energy is higher than the material at the top layer of the buffer. This combination will form a "two-dimensional electron gas" (2DEG), just below the interface of the barrier and the buffer. The 2DEG is a very thin volume region below the barrier layer, parallel to the substrate, where the electron current will flow when a voltage is applied. This structure is shown in Figure 1. Sometimes an additional layer, called a channel layer, will be deposited on the buffer layer before the barrier layer. This channel layer can be optimized to positively influence the 2DEG properties.

[0008] It is desirable to engineer the transistor so that the 2DEG current is confined to flow within the smallest volume and does not leak into the buffer layers and thence to, e.g., neighboring device. Ideally this goal is accomplished by forming the 2DEG channel over a material with near infinite resistance. In GaN devices fabricated on a silicon substrate this is somewhat challenging, since the silicon substrate is somewhat conductive.

[0009] Ion implantation has been used to make high resistivity regions in lll-N materials, so as to generate isolated "island" and thereby prevent current from leaking from one device to its neighboring devices. The ion beam is directed at the target device at angles of incidence from zero to several degrees to insure that the ion beam properly lodges the ions in the samples and damages the crystal structure of the GaN. In these examples the region with high resistivity extends from the top of the lll-N layers down towards the substrate onto which the lll-N was deposited. An example is illustrated in Figure 1 , wherein device 150, e.g., a field effect transistor (FET), is surrounded by vertical isolation barrier 155.

[0010] Ion implantation of heavy ions, such as, e.g., argon, krypton, zinc, magnesium and iron, was also used to create defects in the GaN layer and thereby form a high resistivity volume at the bottom of the channel layer of the HEMT device. This increases the ability of the device to withstand high voltage without undesirable current leakage from the channel. The leakage current in the device structure is the current which flows outside the volume of the confined 2DEG. It is characterized by placing an electric field from the top of the epitaxy film and the substrate and measuring a current that flows in a direction toward the substrate. The electric field at a given voltage is assigned by the ratio of the applied voltage to the film thickness between the metal surface contact and the substrate. The voltage is measured at a predefined value of leakage current.

[0011] In lateral transistors and diodes where the desired current in the on/off-state flows parallel to the substrate/film interface, the current density is often defined by the ratio of the current to the perimeter of the metal contact, expressed as amperes/mm. In vertical transistors and diodes where the desired current in the on/off-state flows perpendicular to the substrate/film interface, the current density is often defined by the ratio of the current to the area of the metal contact, expressed as amperes/cm².

[0012] The critical electric field can be defined as the electric field value corresponding to the largest leakage current allowed for a transistor or diode with voltage applied so the device is in the off state. If the sample or device is designed well, effects like surface leakage and current spreading will be minimized and the critical field value will be impacted by the properties of the epitaxial films. The objective is to control the MOCVD processes to develop material with the maximum value of critical field.

[0013] Figure 2 shows a schematic of the critical field test as applied to a buffer structure or diode. The cap and barrier layers must be removed to facilitate the test since the presence of the barrier layer above the channel creates the two dimensional electron gas, and current can flow parallel to the substrate, leading to current spreading. Alternatively, the critical field of the channel and buffer material can be assessed by stopping the growth after the channel layer is deposited and forming a metal contact on the surface of the channel.

[0014] The test is performed by connecting the substrate to ground potential, as shown, then applying a voltage to the metal contact. Sometimes a metal layer is deposited on the back of the substrate to improve the ability to make a low resistance contact to ground. As the voltage is applied to the top contact 160, the current is read using an ammeter in series connection with the metal contact. When a positive voltage is applied the condition is called forward bias, and when a negative voltage is applied it is called reverse bias. The leakage current will flow as indicated in Figure 2.

[0015] A similar test can be performed on a fully fabricated HEMT transistor and it does not require the need to make a metal contact directly to the channel. This is shown in Fig 3. In the case of the transistor there are metal contacts made to the top surface or to just below the top surface of the barrier layer. These would be the source and drain contacts. Either one can be used for the critical field test described above. The test arrangement is the same as the case of the diode or buffer/channel sample, but requires that an additional voltage be connected to the gate contact. The voltage connected to the gate is set such that it prevents the formation of the two dimensional electron gas, often called the "pinch-off" condition, and the current flow under the gate is driven to near zero value. In the typical case of a GaN HEMT, the voltage applied the gate is zero or a negative voltage value. When this gate voltage condition is satisfied, the measurement can be performed and leakage current will flow as indicated in Figure 3.

[0016] For lll-N materials such as GaN, the theoretical value of the critical field is often cited as 3.3 MV/cm. This value is hard to achieve in practice due to crystal defects (dislocations) which incorporate into the film when it is grown on a dissimilar material substrate like silicon, and chemical impurities which will make the epitaxial layers undesirably more conductive.

[0017] Electronics applications for lll-N based transistors or diodes include power switching and RF amplifiers. Regardless of the application, the transistor has the same basic design (HEMT) and the diode can be a lateral diode or vertical diode. In the applications of lll-N HEMT devices for power electronics, the challenge of new designs is to increase the ability to stop current flow at high voltages (100 V to more than 1000V). RF transistors must also stop current flow at high instanteous voltage values and leakage from high bias voltage. Minimizing leakage currents in both RF and Power applications requires thick buffer layers (2-10 urn) to block current flow from the channel to the substrate. The values of the thickness must be inflated compared to what is expected theoretically since the materials quality is limited by crystal defects and chemical impurities. These thick lll-N epitaxial buffer films can cause the wafer to bow and films to crack, especially when silicon is used as a substrate. Also, thicker lll-N buffer layers substantially increase the cost to produce a transistor or diode.

[0018] What is needed in the art is the ability to produce group lll-N devices having low current leakage.

SUMMARY

[0019] The following summary of the invention is included in order to provide a basic understanding of some aspects and features of the invention. This summary is not an extensive overview of the invention and as such it is not intended to particularly identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented below. [0020] Embodiments of the invention provide a large area, low cost substrate suitable for fabrication of a group lll-N transistor or diode. Another embodiment provides a group lll-N transistor or diode capable to operate high voltage with low current leakage.

[0021] In the disclosed embodiments, a device substrate suitable for forming a group lll-N semiconductor device is provided, the device substrate comprises a crystalline silicon wafer, an optional layer of CVD 3C-SiC of thickness 50-1000 nm formed over the silicon substrate, a layer of AIN of thickness 10-250 nm formed over the silicon substrate, or over the 3C-SiC layer when used, a buffer layer section formed of a plurality of films selected from the group of GaN, AIN and Al_xGa₍i_-X) (0<x<0.8) and having an ion implant layer buried in the buffer layer. An undoped Al_xGa₍i_-X)N layer (x<0.25) is formed over the buffer layer and a barrier (electron supply) layer of Al_xGa₍i-_X)N (0.4>x>0.2) is formed over the undoped Al_xGa₍i-_x)N layer. A passivation layer of GaN layer or silicon nitride layer may be deposited over the barrier layer. The various layers are deposited in the MOCVD chamber.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other aspects and features of the invention would be apparent from the detailed description, which is made with reference to the following drawings. It should be appreciated that the detailed description and the drawings provides various non-limiting examples of various embodiments of the invention, which is defined by the appended claims.

[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, exemplify the embodiments of the present invention and, together with the description, serve to explain and illustrate principles of the invention. The drawings are intended to illustrate features of the exemplary embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of actual embodiments nor relative dimensions of the depicted elements, and are not drawn to scale.

[0024] Figure 1 illustrates a prior art device.

[0025] Figures 2 and 3 illustrate prior art testing arrangements.

[0026] Figures 4A and 4B illustrate two implanted device substrates according to embodiments of the invention.

[0027] Figure 5 is a plot illustrating implant depth versus ion energy for nitrogen ions.

[0028] Figures 6A, 6B, 7A and 7B are plots of applied bias.

[0029] Figure 8 is a table showing thickness ranges for various layers of a device substrate according to embodiments of the invention.

[0030] Figures 9A-9C illustrate examples of a transistor formed with isolation according to embodiments of the invention. DETAILED DESCRIPTION

[0031] It is discovered that by forming a buried implantation layer in the buffer region of the 111— ISJ multilayer film structure, without causing crystallographic damage, it effectively suppresses creation of leakage current in the direction normal to the substrate when a high voltage is applied at the surface of the epitaxial film. For a 111— ISJ structure consisting of at least a silicon wafer, and AIN layer, a series of buffer layers Al_xGa₍i-x₎N where each layer above the substrate/AIN film is a step of lower Al concentration, a GaN layer to include a channel to confine the 2-D electron gas and a barrier (electron supply layer), by implanting light ions, e.g., nitride, into the Al_xGa₍i-x₎N buffer section improves the ability of the structure to withstand high voltage and have lower leakage current. The amount of the leakage current suppression can be maximized by locating the buried layer in the higher aluminum concentration layers of the Al_xGa₍i-x₎N section of the buffer (closer to the substrate). As a result the net thickness of the epitaxial layers can be decreased relative to a structure/device without the buried ion implant layer. This benefit reduces product cost and reduces wafer bow relative to designs that require the thicker layers. The inventors believe that the approach described can also be used with buffers based on alternating layers of GaN/AIN, alternating layers of AIGaN/GaN, AIGaN/AIN/GaN, etc.

[0032] The implantation process can be performed on the substrate with the epitaxial films before any device processing, and as such this helps eliminate costly additional steps usually associated with implantation steps on wafers with an incomplete epitaxy structure or during the fabrication of devices. Elements such as N and Ar/Group VINA elements can be implanted to achieve the effect. The invention is compatible with large area silicon substrates up to 450 mm diameter. The implant process generally does not require annealing after implantation to maximize the resistivity, since the ion implantation process is designed so as not to generate defects or create carriers for counter-doping. In some embodiments, when using higher implant voltages, the implant step may be followed by rapid thermal anneal to recover the channel while preserving the implant effect in the buffer. Another advantage of the invention is that the ions are implanted from the top surface of the epitaxial films of a full transistor or diode structure, resulting in simplified process, and there's no need to interrupt the epitaxy process to facilitate the implantation step. This is shown in Figures 4A and 4B. Figure 4A shows an implant layer 180 made in the buffer layer well below the channel region, while Figure 4B shows an implant layer 180 made at the bottom of the buffer layer, at the interface between the buffer layer and the AIN layer. According to embodiments of the invention, the implanted ions are at a depth of at least 500nm below the top surface of the passivation layer. The inventive method places the buried implant blanket layer deep in the buffer, generally more than 500nm below the top surface of the epilayers. The subject inventors have noted that when the depth of the buried implant is pushed down in the buffer, closer to the silicon substrate, the blocking voltage of the device is increased. For example, the embodiment of Figure 4A has lower blocking voltage than that of Figure 4B.

[0033] As the method is implemented after epitaxy but before device fabrication, it can be implemented with other techniques used to improve the operating capability of a lll-N diode or HEMT such as SiN passivation, substrate removal or localized substrate removal below the device, as well as in conjunction with ion implantation schemes that generate vertical isolation.

Examples:

[0034] lll-N layers were formed in a commercially available showerhead type MOCVD system. The system is loaded with 3 pieces of Si<1 1 1 > substrate wafers, 675 um in thickness, 150 mm diameter, doping with boron to 1-10 ohm cm resistivity.

[0035] Prior to growth of lll-N films, the wafers are heated to a temperature of over 1 100°C in an H2 ambient at 500 torr to clean the surface of the silicon. Next an AIN layer approximately 200 nm thick is deposited using a gas mixture containing H2, N2, NH3 and trimethylaluminum. In the AIN growth the pressure is typically 15 torr and control temperature is 1 150°C. Following the AIN growth, the chamber is evacuated and the next step forms 3 successive layers of AIGaN, deposited using a gas mixture containing H2, N2, NH3, trimethylgallium and trimethylaluminum, pressure of 40 torr, control temperature of 1 100°C. The configuration of the three AIGaN layers was Al concentration/thickness targets of 75%/0.5 um, 50%/0.5 um and 25%/0.5 um. Following the AIGaN growth, the chamber is evacuated of the AIGaN process gases and the next step forms an undoped GaN layer using a gas mixture containing H2, N2, NH3, and trimethylgallium, pressure of 40 torr, control temperature of 1 100°C. The thickness target of the GaN layer is 1 .0 um. The barrier layer and passivation/cap layer typical of a full HEMT device were omitted in some samples to facilitate high voltage leakage current measurements in the direction normal to the substrate. Other samples which include the barrier layer and passivation/cap layer were evaluated to assess the impact of the implant on the carrier mobility and sheet resistance of the 2-DEG region.

[0036] The wafers were removed from the CVD system. The total film thickness was measured using a spectroscopic ellipsometer. Each wafer was split in sections, some sections were reserved for implantation, and some would not receive implantation.

[0037] Nitrogen implantation was performed on wafer sections with different ion doses and energies at room temperature and at 700°C. Table I below shows implantation conditions for each sample. All samples were collected from a growth run (N1_1306XJK0202). Wafer IDs are 82394183SEB7 and 82394015SEB7.

Table I: sample IDs and implantation conditions

[0038] TRIM software (Transport of Ions In Matter) was used to simulate implanted ion depth profiles in the samples as shown in Figure 5. Figure 5 is a plot of nitrogen atom concentration depth profiles corresponding to various ion implantation energy levels. The plotted lines are the theoretical ion concentration profiles corresponding to implantation energy settings from 0.75, 2.1 and 4.15 MeV, respectively. From Figure 5 it can be seen that in order to implant the nitrogen ions at defined depth well below the channel and towards the silicon substrate, the implant energy should be at about 2MeV to 4.5MeV. The selection of the implant energy is determined by the target location for the buried implant in the buffer. For this example, it is also seen that by using implant energy above 4MeV the nitrogen ions would be implanted at the interface of the buffer layer and AIN layer and at the interface between the AIN layer and the silicon substrate. Moreover, it is seen that using sufficiently high implant energy the nitrogen ions can be partially implanted in the silicon substrate. Also, since light nitrogen ions are implanted at normal incidence, no damage crystallographic has been observed in the channel or buffer layers.

[0039] After ion implantation, Al metal gates were formed (thickness of -0.35 urn and gate sizes are 0.5 ~ 1 mm diameter) on the surface of the samples by sputter deposition through a shadow mask. Sample wafer sections without implant were used for reference points for breakdown voltages and leakage currents.

[0040] Electrical l-V (current vs. voltage) testing was performed with a SMU (source measure unit) and a wafer probe station. Two bias directions were employed to measure vertical breakdown and leakage current values. Forward bias means applying positive polarity bias on the Al metal dot and grounding the backside of the sample. Reverse bias means applying negative polarity bias on the Al metal dot and grounding the backside of the sample. Leakage current at different bias values from the Al metalized samples are plotted at both electrical polarities in Figures 6A and 6B.

[0041] Figures 6A and 6B are plots of the leakage current curves at different electrical field for samples implanted at room temperature. Figure 6A is a plot of positive polarity and Figure 6B is a plot of negative polarity on the metal contacts. The electrical field values are calculated from dividing the applied bias values by the total film thickness. Forward and reverse bias plots are from sample 5 and sample 3, respectively. Both sample 5 and 3 are collected from the wafer 82394183SEB7. As-grown sample is also collected from the wafer 82394183SEB7.

[0042] Figures 7A and 7B are plots of leakage current curves at different electrical fields for samples implanted at 700°C. The electrical field values are calculated from dividing the applied bias values by the total film thickness. Both forward and reverse bias plots are from sample 6. Sample 6 is collected from the wafer 82394183SEB7. As-grown sample is also collected from the wafer 82394183SEB7.

[0043] In the disclosed embodiments, light ions, such as nitrogen ions, are implanted, so that they do not cause damage in the implanted layer. Also, the implant process is performed so as to avoid damage. For example, the implant is performed by accelerating the ions in a direction perpendicular to the surface of the implanted layer. The implant process is further configured such that the ions pass through the channel layer and are implanted well below the channel and as close to the silicon substrate as possible, i.e., at the bottom of the buffer layer or at the buffer and AIN interface. In addition to providing beneficial isolation results, these methods minimize damage to the channel/2DEG region of the epitaxy.

[0044] In the examples performed, after performing TEM and x-ray investigation, no crystallographic damage was found and no stresses were measured. Only the electrical properties of the layer were changed. It is postulated that the nitrogen may be changing the electrical property of electron traps within the layers they pass through and or the layers where the ions lodge, without causing any crystallographic damage.

[0045] In the disclosed embodiments, the ion implant was performed from the front, i.e., from the side opposite the silicon substrate. The implanted ions were light ions, such as nitrogen ions. The implanted ions pass through the channel and are lodged into buffer region below the channel, such that no ions are implanted in the channel. The ions are implanted at the bottom of the buffer layer and at the buffer/AIN interface or the AIN/Si interface. The implanted ions form a buried blanket which is implant under the entire active device region and resides below the channel. In various embodiments it the buried blanket implant was positioned to be situated at depths greater than 150 nm below the barrier/buffer interface.

[0046] In applications where higher ion dose is desired (for example >5E12/cm2) there may be low concentrations of vacancies generated in the channel/2DEG region of the epitaxial films. Creation of vacancies in the 2DEG region will degrade the channel mobility. The mobility value can be recovered by annealing the wafer in an ambient containing one or more of the following gases - nitrogen, argon, ammonia, hydrogen. Typical anneal temperatures are in the range of from 400 to 800°C. A rapid thermal anneal system can be used for this process. [0047] According to aspects described above, a transistor can be fabricated in a device substrate, wherein the leakage current density value measured from a metal electrode provided on or below the barrier layer or on the buffer layer equals or is less than 5 mA/cm², wherein the silicon substrate is held at zero potential and the metal electrode is biased at a voltage which equates to an electric field of equal or larger than 2MV/cm and whose direction is parallel with the normal to the substrate surface, and wherein the value of the electric field is determined from the ratio of the absolute value of the voltage to the total film thickness. The transistor has a buffer structure which in includes an implant of nitrogen, argon, or other Group VINA ions. The implant is performed using implant energy in the range of from 10 keV to 10 MeV. The dosage of implanted ions can range 1 E12/cm2 to greater than 1 E14/cm2. The implanted atoms impinge on the top of the epitaxy surface at normal incidence, and will be lodged in the buffer region, and essentially no atoms are implanted in the channel layer.

[0048] From the above investigation, it is postulated that the current goes down through the structure and then at an interface between two layers it shoots across parallel to the structure along the interface. Accordingly, in various embodiments the implanted ions are implanted using such energy so as to implant the ions in an interface, e.g., in the interface between the buffer layer and the AIN layer and/or at the interface between the AIN layer and the silicon substrate. It is possible that the nitrogen block this current, possibly by being implanted as substitution, thus causing no crystallographic damage.

[0049] In the disclosed embodiments the method includes implanting nitrogen, i.e., light rather than heavy elements, so as to avoid causing crystallographic damage to the channel and the buffer layers. Also, rather than implanting as high and close to the channel, in the embodiments the implant is as low and as close as possible to the silicon substrate, so as not to disturb the channel. This acts somewhat like removing the substrate, which is desirable since leakage paths can occur at the substrate film interface or at the near surface of the substrate.

[0050] In the disclosed embodiments, a device substrate suitable for forming a group lll-N semiconductor device is provided, the device substrate comprises a crystalline silicon wafer, an optional layer of CVD 3C-SiC of thickness 50-1000 nm formed over the silicon substrate, a layer of AIN of thickness 10-250 nm formed over the silicon substrate, or over the 3C-SiC layer when used, a buffer layer section formed of a plurality of films selected from the group of GaN, AIN and Al_xGa_(1-x) (0<x<0.8) and having an ion implant layer buried in the buffer layer. An undoped Al_xGa_(1-x)N layer (x<0.25) is formed over the buffer layer and a barrier (electron supply) layer of Al_xGa_(1-x)N (0.4>x>0.2) is formed over the undoped Al_xGa_(1-x)N layer. A passivation layer of GaN layer or silicon nitride layer may be deposited over the barrier layer. The various layers are deposited in the MOCVD chamber and in general the thickness of the various layers is illustrated in Figure 8.

[0051] Figure 9A illustrates a transistor formed with the ion implant isolation according to one embodiment. The layers of the device are similar to that shown in Figure 4A, so that their description is omitted. An implant layer 180 is formed at a depth of at least 500nm below the interface between the buffer layer 1 15 and the barrier layer 125, such that it is situated well below the 2DEG 120. The implant layer forms a "slice" of the buffer layer and "buried" inside the buffer layer away from the 2DEG and towards the silicon substrate. Once the implant layer has been formed, the device is fabricated by forming a source, a gate and a drain, 92, 92, 94 respectively. Thus, a GaN FET is formed.

[0052] Figure 9B illustrates another embodiment of a transistor formed with ion implant isolation. This embodiment is similar to that of Figure 9A, except that a vertical isolation implant 95 is also formed around the FET. The vertical isolation implant is very much like the one illustrated as implant 155 in Figure 1. Thus, in this case the FET is surrounded by implant isolation to prevent "cross-talk" with other devices, and also has implant isolation 180 to prevent leakage by vertical current flow. Figure 9C illustrates yet another embodiment of FET, which is very similar to that of Figure 9B. However, in the embodiment of Figure 9C the vertical implant 97 is made sufficiently deep so that it contacts the buried blanket implant 180.

[0053] With the above description, disclosure is provided for a group lll-N device comprising a crystalline silicon substrate; a layer of AIN formed over the silicon substrate; a buffer layer section formed of a plurality of films selected from the group consisting of GaN, AIN and Al_xGa_(1-x), wherein 0<x<0.8, the buffer layer further comprising an ion implanted nitrogen layer buried in a defined depth within the buffer layer to thereby overlap with a depth-wise slice of the buffer and cover over entire surface area of the buffer layer; a barrier layer of Al_xGa₍i-_X)N, wherein 0.4>x>0.2; and, a passivation layer. The buffer layer comprises minimal damage, which does not limit the device performance, caused by the ion implanted nitrogen layer. The buffer layer is formed directly over the AIN layer and the implanted nitrogen layer is positioned at interface between the AIN and the buffer layer. The ion implanted nitrogen layer may extend from lower part of the buffer layer into to the AIN layer and to the silicon substrate. The total thickness of the buffer layer is from 1000nm to 10000 nm. In some embodiments, the device may further comprise a layer of CVD 3C-SiC interposed between the silicon substrate and the AIN layer. The passivation layer comprises a GaN layer or a silicon nitride layer, and may further comprise a second passivation layer selected from SiOx, SiNx, or carbon polymers. In some embodiments the device is a transistor and comprise ohmic contacts defining a gate, a drain, and a source. In further embodiments, the thickness of the AIN layer is from 10nm to 250 nm, the thickness of the buffer layer is from 1000nm to 10000 nm, the thickness of the barrier layer is 10nm to 50 nm, and the ion implanted nitrogen layer is at least 150 nm below an interface between the barrier layer and the buffer layer.

[0054] Also, the above disclosure provides a method for fabricating a device substrate, comprising the steps: preparing a silicon substrate for deposition process; depositing a layer of AIN over the silicon substrate; depositing a buffer layer over the AIN layer; depositing a barrier layer over the buffer layer; and, implanting nitrogen ions such that nitrogen ions are implanted over entire surface area of the buffer layer at a depth of at least 150 nm below an interface between the barrier layer and the buffer layer. The implanting step is performed at a direction perpendicular to front surface of the barrier layer, such that the implanted nitrogen ions cause minimal damage to the barrier layer or the buffer layer. Also, the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be implanted at an interface between the buffer layer and the AIN layer. In some embodiments, the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be partially implanted in the silicon substrate. Alternatively, the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be implanted partially at the silicon substrate and partially at the AIN layer. The implanting step may be configured to utilize implantation energy of 10 keV to 10 MeV, or 2 MeV to 6.0 MeV. IN some embodiments the concentration of Al in the barrier layer is configured to be greater than the concentration of Al at the top of the buffer layer. The method may further comprise forming an electron device in the device substrate, wherein the electron device exhibits leakage current density value measured from a metal electrode on or below the barrier layer or on the buffer layer equals or is less than 5 mA/cm2 when the silicon substrate is held at zero potential and the metal electrode is biased at a voltage which equates to an electric field of or larger than 2MV/cm whose direction is parallel with the normal to the silicon substrate surface, wherein the value of the electric field is determined from ratio of absolute value of the voltage to total film thickness. The method may also comprise forming a passivation layer over an undoped Al_xGa₍i-x₎N layer, wherein the passivation layer comprises a GaN layer of thickness from 2 to 5 nm or a silicon nitride layer of thickness from 10 to 200 nm. Additionally, the wafer may be processed with thermal anneal to remove vacancies generated from the implant process. In some embodiments, the implanting is performed so as to provide ion dose of at least 5.00E+13/cm².

[0055] It should be understood that processes and techniques described herein are not inherently related to any particular apparatus and may be implemented by any suitable combination of components. Further, various types of general purpose devices may be used in accordance with the teachings described herein. It may also prove advantageous to construct specialized apparatus to perform the method steps described herein. [0056] The present invention has been described in relation to particular examples, which are intended in all respects to be illustrative rather than restrictive. Those skilled in the art will appreciate that many different combinations of hardware, software, and firmware will be suitable for practicing the present invention. Moreover, other implementations of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

[0057] Furthermore, it is contemplated that any features from any embodiment can be combined with any features from any other embodiment. In this fashion, hybrid configurations of the illustrated embodiments are well within the scope of the present invention.

[0058] Various aspects of the disclosure may be described through the use of flowcharts. Often, a single instance of an aspect of the present disclosure may be shown. As is appreciated by those of ordinary skill in the art, however, the protocols, processes, and procedures described herein may be repeated continuously or as often as necessary to satisfy the needs described herein.

Claims

1. A group 111— ISJ device comprising:

a crystalline silicon substrate;

a layer of AIN formed over the silicon substrate;

a buffer layer section formed of a plurality of films selected from the group consisting of GaN, AIN and Al_xGa₍i_-X), wherein 0<x<0.8, the buffer layer further comprising an ion implanted nitrogen layer buried in a defined depth within the buffer layer to thereby overlap with a depth-wise slice of the buffer and cover over entire surface area of the buffer layer; a barrier layer of Al_xGa₍i_-X)N, wherein 0.4>x>0.2; and,

a passivation layer.

2. The device of claim 1 , wherein the buffer layer comprises minimal damage, which does not limit the device performance, caused by the ion implanted nitrogen layer.

3. The device of claim 2, wherein the buffer layer is formed directly over the AIN layer and wherein the implanted nitrogen layer is positioned at interface between the AIN and the buffer layer.

4. The device of claim 2, wherein the ion implanted nitrogen layer extends from lower part of the buffer layer into to the AIN layer and to the silicon substrate.

5. The device of claim 2, wherein total thickness of the buffer layer is from 1000nm to 10000 nm.

6. The device of claim 1 , further comprising a layer of CVD 3C-SiC interposed between the silicon substrate and the AIN layer.

7. The device of claim 1 , wherein the passivation layer comprises a GaN layer or a silicon nitride layer.

8. The device of claim 5, further comprising a second passivation layer selected from SiOx, SiNx, or carbon polymers.

9. The device of claim 1 , further comprising ohmic contacts defining a gate, a drain, and a source.

10. The device of claim 1 , wherein the thickness of the AIN layer is from 10nm to 250 nm, the thickness of the buffer layer is from 1000nm to 10000 nm, the thickness of the barrier layer is 10nm to 50 nm, and the ion implanted nitrogen layer is at least 150 nm below an interface between the barrier layer and the buffer layer.

1 1 . A method for fabricating a device substrate, comprising the steps: preparing a silicon substrate for deposition process;

depositing a layer of AIN over the silicon substrate;

depositing a buffer layer over the AIN layer;

depositing a barrier layer over the buffer layer; and,

implanting nitrogen ions such that nitrogen ions are implanted over entire surface area of the buffer layer at a depth of at least 150 nm below an interface between the barrier layer and the buffer layer.

12. The method of claim 1 1 , wherein the implanting step is performed at a direction perpendicular to front surface of the barrier layer, such that the implanted nitrogen ions cause minimal damage to the barrier layer or the buffer layer.

13. The method of claim 12, wherein the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be implanted at an interface between the buffer layer and the AIN layer.

14. The method of claim 12, wherein the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be partially implanted in the silicon substrate.

15. The method of claim 12, wherein the implanting step is configured to utilize implantation energy sufficient to cause the nitrogen ions to be implanted partially at the silicon substrate and partially at the AIN layer.

16. The method of claim 12, wherein the implanting step is configured to utilize implantation energy of 10 keV to 10 MeV.

17. The method of claim 12, wherein the implanting step is configured to utilize implantation energy of 2 MeV to 6.0 MeV.

18. The method of claim 1 1 , wherein the concentration of Al in the barrier layer is configured to be greater than the concentration of Al at the top of the buffer layer.

19. The method of claim 1 1 , further comprising forming an electron device in the device substrate, wherein the electron device exhibits leakage current density value measured from a metal electrode on or below the barrier layer or on the buffer layer equals or is less than 5 mA/cm2 when the silicon substrate is held at zero potential and the metal electrode is biased at a voltage which equates to an electric field of or larger than 2MV/cm whose direction is parallel with the normal to the silicon substrate surface, wherein the value of the electric field is determined from ratio of absolute value of the voltage to total film thickness.

20. The method of claim 1 1 , further comprising forming a passivation layer over an undoped Al_xGa_(1-x)N layer, wherein the passivation layer comprises a GaN layer of thickness from 2 to 5 nm or a silicon nitride layer of thickness from 10 to 200 nm.

21 . The method of claim 1 1 wherein the wafer is processed with thermal anneal to remove vacancies generated from the implant process.

22. The method of claim 1 1 , the implanting is performed so as to provide ion dose of at least 5.00E+13/cm².