WO2015122925A1 - Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante - Google Patents

Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante Download PDF

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Publication number
WO2015122925A1
WO2015122925A1 PCT/US2014/016634 US2014016634W WO2015122925A1 WO 2015122925 A1 WO2015122925 A1 WO 2015122925A1 US 2014016634 W US2014016634 W US 2014016634W WO 2015122925 A1 WO2015122925 A1 WO 2015122925A1
Authority
WO
WIPO (PCT)
Prior art keywords
transaction
update
cache
count
transactions
Prior art date
Application number
PCT/US2014/016634
Other languages
English (en)
Inventor
Boris Zuckerman
Alistair Veitch
Douglas L VOIGT
Harold Woods
Original Assignee
Hewlett-Packard Development Company, L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company, L.P. filed Critical Hewlett-Packard Development Company, L.P.
Priority to PCT/US2014/016634 priority Critical patent/WO2015122925A1/fr
Publication of WO2015122925A1 publication Critical patent/WO2015122925A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1008—Correctness of operation, e.g. memory ordering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction

Abstract

L'invention concerne une méthode pour qu'un dispositif assure l'atomicité des mises à jour dans une mémoire persistante avec la circulation libre des mises à jour par de multiples caches. La méthode consiste, dans un premier cache, à affecter un ID de transaction à une transaction comprenant un ensemble de mises à jour qui seront validées ou abandonnées ensemble en tant qu'unité, incrémenter un compte de mises à jour pour chaque mise à jour de la transaction transférée dans le premier cache. La méthode consiste de plus, pour chaque mise à jour de la transaction transférée du premier cache à un deuxième cache basé sur une mémoire persistante, à décrémenter le compte de mises à jour, marquer la mise à jour comme clôturée dans une demande de mise à jour après la clôture de la transaction, et inclure l'ID de transaction et le compte de mise à jour dans une demande de mise à jour pour transférer la mise à jour du premier cache au deuxième cache.
PCT/US2014/016634 2014-02-14 2014-02-14 Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante WO2015122925A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2014/016634 WO2015122925A1 (fr) 2014-02-14 2014-02-14 Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/016634 WO2015122925A1 (fr) 2014-02-14 2014-02-14 Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante

Publications (1)

Publication Number Publication Date
WO2015122925A1 true WO2015122925A1 (fr) 2015-08-20

Family

ID=53800505

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2014/016634 WO2015122925A1 (fr) 2014-02-14 2014-02-14 Assurance d'atomicité de multiples mises à jour en circulation libre dans une mémoire persistante

Country Status (1)

Country Link
WO (1) WO2015122925A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018118040A1 (fr) * 2016-12-21 2018-06-28 Hewlett-Packard Development Company, L.P. Mise à jour d'une mémoire permanente

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020103815A1 (en) * 2000-12-12 2002-08-01 Fresher Information Corporation High speed data updates implemented in an information storage and retrieval system
US20080104332A1 (en) * 2006-10-31 2008-05-01 Gaither Blaine D Cache memory system and method for providing transactional memory
US20090106494A1 (en) * 2007-10-19 2009-04-23 Patrick Knebel Allocating space in dedicated cache ways
US20140040550A1 (en) * 2011-09-30 2014-02-06 Bill Nale Memory channel that supports near memory and far memory access

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020103815A1 (en) * 2000-12-12 2002-08-01 Fresher Information Corporation High speed data updates implemented in an information storage and retrieval system
US20080104332A1 (en) * 2006-10-31 2008-05-01 Gaither Blaine D Cache memory system and method for providing transactional memory
US20090106494A1 (en) * 2007-10-19 2009-04-23 Patrick Knebel Allocating space in dedicated cache ways
US20140040550A1 (en) * 2011-09-30 2014-02-06 Bill Nale Memory channel that supports near memory and far memory access

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IULIAN MORAU ET AL.: "Persistent, Protected and Cached: Building Blocks for Main Memory Data Stores", CMU-PDL-11-114, November 2012 (2012-11-01), Carnegie Mellon University, XP055219254, Retrieved from the Internet <URL:http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.252.7301&rep=repl&type=pdf> *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018118040A1 (fr) * 2016-12-21 2018-06-28 Hewlett-Packard Development Company, L.P. Mise à jour d'une mémoire permanente
US10860246B2 (en) 2016-12-21 2020-12-08 Hewlett-Packard Development Company, L.P. Persistent memory updating

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