WO2015107616A1 - Circuit board and manufacturing method for same, as well as electronic device - Google Patents

Circuit board and manufacturing method for same, as well as electronic device Download PDF

Info

Publication number
WO2015107616A1
WO2015107616A1 PCT/JP2014/050422 JP2014050422W WO2015107616A1 WO 2015107616 A1 WO2015107616 A1 WO 2015107616A1 JP 2014050422 W JP2014050422 W JP 2014050422W WO 2015107616 A1 WO2015107616 A1 WO 2015107616A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating layer
circuit board
wiring
core
layer
Prior art date
Application number
PCT/JP2014/050422
Other languages
French (fr)
Japanese (ja)
Inventor
水谷　大輔
正輝 小出
健一郎 阿部
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to PCT/JP2014/050422 priority Critical patent/WO2015107616A1/en
Publication of WO2015107616A1 publication Critical patent/WO2015107616A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0133—Elastomeric or compliant polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

Definitions

  • the present invention relates to a circuit board, a manufacturing method thereof, and an electronic device.
  • solder bump connection when the temperature of the package substrate is heated above the melting temperature of the solder, if the package substrate is deformed and the flatness is impaired, the solder bumps partially float and are not connected to the terminals of the package substrate. The problem occurs.
  • the allowable warpage amount of the package substrate is about 30 ⁇ m in the region where the semiconductor element is mounted and about 100 ⁇ m in the entire substrate, and an extremely high level planarization technique is required.
  • This build-up multilayer circuit board is formed by forming build-up layers formed by alternately laminating thin insulating layers and conductor layers on the front and back surfaces of a rigid core multilayer wiring board.
  • the following measures are taken. In other words, it is natural to make the ratio of the wiring layers arranged on the front and back surfaces of the board uniform by design, and it is natural to increase the rigidity of the core multilayer wiring board by increasing the thickness of the rigid core multilayer wiring board or changing the material Is planned.
  • the substrate A is a four-layer board (four-layer board) in which a conductor layer is formed on a resin (hereinafter referred to as a glass-reinforced resin) in which a core multilayer wiring board is provided with reinforced fiber glass (glass cloth) having a thickness of 0.4 mm.
  • a glass-reinforced resin in which a core multilayer wiring board is provided with reinforced fiber glass (glass cloth) having a thickness of 0.4 mm.
  • a thin glass cloth is pasted on the front and back surfaces of the (wiring structure), each buildup layer is a laminate of six wiring structures, and the thickness is 1.35 mm.
  • the substrate B is formed by attaching a thin glass cloth to the front and back surfaces of a 4-layer board made of glass reinforced resin having a thickness of 0.6 mm as a core multilayer wiring board, and each of the build-up layers is laminated with a wiring structure of 6 layers.
  • the thickness is 1.55 mm.
  • the substrate C is formed by attaching a thin glass cloth to the front and back surfaces of a 4-layer board of glass reinforced resin having a thickness of 0.8 mm as a core multilayer wiring board, and each build-up layer is laminated with a wiring structure of 6 layers.
  • the thickness is 1.75 mm.
  • the core multilayer wiring board is made of an 8-layer board (8-layer wiring structure) made of glass-reinforced resin, and each build-up layer is formed by stacking 6-layer wiring structures. It is a thing of structure, Comprising: Thickness shall be 1.95 mm.
  • the amount of warpage (temperature 240 ° C.) of each build-up multilayer circuit board was 135 ⁇ m for board A, 99 ⁇ m for board B, 76 ⁇ m for board C, and 71 ⁇ m for board D. From this experimental result, the thickness of the rigid core multilayer wiring board is increased (boards A to D), and the rigidity of the board is higher (board D (the number of conductor layers is greater)), the amount of warpage of the board is reduced. It was confirmed.
  • a capacitor is mounted on the back surface (the surface of the lower build-up layer).
  • the core multilayer wiring board is made thicker in order to improve the flatness of the substrate as described above, the substrate thickness increases accordingly, and the distance between the semiconductor chip and the capacitor increases. Then, there is a problem that the inductance of the build-up multilayer circuit board increases.
  • the present invention has been made in view of the above problems, has a highly flat surface, can be mounted on electronic components that are larger and finer, and reduce inductance, It is an object of the present invention to provide a highly reliable circuit board, a manufacturing method thereof, and an electronic device that sufficiently suppress power supply noise and stabilize the power supply.
  • the circuit board includes a core layer and a pair of build-up layers that sandwich the core layer.
  • the core layer includes a first insulating layer having a wiring inside, and the first insulating layer. And a second insulating layer having an elastic modulus lower than that of the first insulating layer.
  • One aspect of the electronic device includes a circuit board that includes a core layer, a pair of build-up layers that sandwich the core layer, and an electronic component that is mounted on the circuit board. And a second insulating layer disposed inside the first insulating layer to embed the wiring and having a lower elastic modulus than the first insulating layer.
  • One embodiment of a method for manufacturing a circuit board includes a step of forming a core layer and a step of forming a pair of buildup layers sandwiching the core layer, and the step of forming the core layer includes wiring on the inside.
  • FIG. 1 is a characteristic diagram showing the result of measuring DMA (Dynamic mechanical analysis) for a conventional build-up multilayer circuit board.
  • FIG. 2A is a schematic cross-sectional view showing the method of manufacturing the buildup multilayer circuit board according to the first embodiment in the order of steps.
  • FIG. 2B is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 2A.
  • FIG. 2C is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 2B.
  • FIG. 2A is a schematic cross-sectional view showing the method of manufacturing the buildup multilayer circuit board according to the first embodiment in the order of steps.
  • FIG. 2B is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 2B.
  • FIG. 3A is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps following FIG. 2C.
  • FIG. 3B is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 3A.
  • FIG. 4 is a schematic cross-sectional view showing the core multilayer wiring board of the buildup multilayer circuit board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view schematically showing the semiconductor device according to the second embodiment.
  • the build-up multilayer circuit board adopts a configuration in which a core multilayer wiring board is sandwiched between a pair of build-up layers.
  • the flatness of the buildup multilayer circuit board depends on the flatness of the core multilayer wiring board when each buildup layer is laminated so as to have a wiring structure of four or more layers. .
  • the conventional build-up multilayer circuit board has a structure in which the stress generated in the build-up layer is received as a support by the core multilayer wiring board and the warp of the board is suppressed. Therefore, in order to suppress the warpage of the substrate, it has been considered effective to use a thicker core multilayer wiring board having higher rigidity.
  • FIG. 1 is a characteristic diagram showing the results of measuring DMA (Dynamic Mechanical Analysis) for substrates A to D.
  • DMA Dynamic Mechanical Analysis
  • the flatness of the build-up multilayer circuit board in which the ratio of the conductor layers on the front and back sides of the board is made uniform by design has little temperature dependence, and there is a difference between the flatness in the room temperature state of the finished product and the flatness at the melting temperature of the solder. Is hardly observed, and the flatness at room temperature is considered to be improved.
  • the flatness of the completed build-up multilayer circuit board is compared with the flatness of the core multilayer wiring board used for forming the build-up layer before the build-up layer is formed, the flatness of both is substantially the same. I found out.
  • the core multilayer wiring board of the buildup multilayer circuit board used in this experiment will be described.
  • the core A is formed by forming all the insulating layers with a glass reinforced resin having a high elastic modulus.
  • the core B is formed by arranging an insulating layer of a low elastic modulus epoxy resin for the purpose of relaxing internal stress at a central portion and attaching an insulating layer of a high elastic modulus glass reinforced resin so as to sandwich the insulating layer.
  • the core C is obtained by placing an insulating layer of a high elastic modulus glass reinforced resin at a central portion and attaching an insulating layer of an epoxy resin having a low elastic modulus so as to sandwich the insulating layer.
  • the core D is formed by forming all the insulating layers with a low elastic epoxy resin.
  • the cores A to D all have the same thickness.
  • the amount of warpage (room temperature (25 ° C.)) of each build-up multilayer circuit board was 115 ⁇ m for the board with the core A, 122 ⁇ m for the board with the core C, and 307 ⁇ m for the board with the core D.
  • substrate provided with the core B, it was restrained to 58 micrometers. From this experimental result, it was confirmed that the flatness of the build-up multilayer circuit board is remarkably improved by sandwiching the core multilayer wiring board with a low elastic modulus insulating layer between a pair of high elastic modulus insulating layers. It was.
  • the first insulating layer having the wiring inside, and the wiring is embedded inside the first insulating layer and has a lower elastic modulus than the first insulating layer.
  • a build-up multilayer circuit board comprising a core multilayer wiring board having a second insulating layer and a pair of build-up layers sandwiching the core multilayer wiring board is disclosed.
  • the first insulating layer and the second insulating layer it is preferable to use one having an elastic modulus of the former of 5 or more times that of the latter. With this configuration, sufficient flatness of the build-up multilayer circuit board can be obtained.
  • the build-up layer is preferably laminated with four or more wiring structures. By using four or more layers, the dominance of the core multilayer wiring board in the flatness of the buildup multilayer circuit board is relaxed, and sufficient flatness of the buildup multilayer circuit board can be obtained.
  • the wiring embedability can be improved as compared with the case where the wiring is embedded with a glass reinforced resin that has been conventionally used. Will improve. Accordingly, the degree of freedom of the thickness of the wiring is increased, and the wiring can be surely embedded in the second insulating layer even if the wiring has an intended thickness (for example, 35 ⁇ m or more). Therefore, even if the build-up multilayer circuit board is thinned to reduce inductance, sufficient flatness of the board can be ensured.
  • a build-up multilayer circuit board which is a package board on which a plurality of wiring layers are stacked and an electronic component such as a semiconductor chip is mounted, is disclosed, and its configuration will be described together with a manufacturing method.
  • 2A to 3B are schematic cross-sectional views showing the manufacturing method of the build-up multilayer circuit board according to the present embodiment in the order of steps.
  • a core multilayer wiring board 10 as a core layer is formed.
  • a pair of first insulating layers 12 is provided. Specifically, a pair of first insulating layers 12 each having a conductor layer 11 formed on the front and back surfaces are prepared. The thickness of the first insulating layer 12 is, for example, about 100 ⁇ m. Lithography and dry etching are used for the conductive layer 11 on the front surface in the first insulating layer 12 on the lower side (in the drawing) and the conductive layer 11 on the back surface in the first insulating layer 12 on the other side (upper in the drawing). Pattern. By this patterning, wirings 11a are formed on the surface of one first insulating layer 12 and the back surface of the other first insulating layer 12, respectively.
  • the conductor layer 11 is formed using copper (Cu) or a Cu alloy as a material.
  • the first insulating layer 12 is formed using a rigid insulating material having a high elastic modulus, for example, a reinforced fiber glass or a reinforced fiber plastic material, here an insulating resin (glass reinforced resin) having reinforced fiber glass.
  • a rigid insulating material having a high elastic modulus for example, a reinforced fiber glass or a reinforced fiber plastic material, here an insulating resin (glass reinforced resin) having reinforced fiber glass.
  • a trade name E679FGR manufactured by Hitachi Chemical Co., Ltd. is used as a material for the first insulating layer 12.
  • the elastic modulus of the first insulating layer 12 is, for example, about 23.3 GPa.
  • the second insulating layer 13 is attached to the first insulating layer 12. Specifically, the second insulating layer 13 is attached to the front surface of one first insulating layer 12 and the back surface of the other first insulating layer 12 so as to embed the wiring 11a, and here, vacuum lamination is performed. .
  • the thickness of each second insulating layer 13 is, for example, about 30 ⁇ m.
  • the second insulating layer 13 is formed of an insulating material such as a thermoplastic resin having isotropic mechanical properties having a lower elastic modulus than that of the first insulating layer 12.
  • the elastic modulus of the second insulating layer 13 is, for example, 1/5 or less of the elastic modulus of the first insulating layer 12.
  • the product name GX-13 manufactured by Ajinomoto Co., Inc. is used as the material of the second insulating layer 13.
  • the elastic modulus of the second insulating layer 13 is, for example, about 3.96 GPa.
  • the pair of first insulating layers 12 are bonded to each other with the second insulating layer 13.
  • the pair of first insulating layers 12 that are opposed to each other by the second insulating layer 13 that embeds the wiring 11a is bonded to each other via the second insulating layer 13 and heated.
  • the three second insulating layers 13 are cured and integrated.
  • the second insulating layer 13 used for bonding is the same insulating material as the second insulating layer 13 in which the wiring 11a is embedded, and the thickness is about 30 ⁇ m.
  • a through via 15 is formed in the core multilayer wiring board 10. Specifically, first, a through hole 15a is formed in the structure of the first insulating layer 12 and the second insulating layer 13 bonded together in FIG. 2C, using a drill having a diameter of about 150 ⁇ m to 300 ⁇ m, for example. . Next, the side wall surface of the through hole 15a is subjected to an electrolytic plating process or an electroless plating process to form a Cu plating film 16, for example. The plating film 16 is formed to a thickness of about 10 ⁇ m to 30 ⁇ m, for example. Next, the inside of the through hole 15 a through the plating film 16 is filled with the resin 17. Thereby, the through via 15 is formed.
  • the core multilayer wiring board 10 having the layer 13 and having the through vias 15 is formed.
  • the conductor layer 11 on the back surface is patterned in one first insulating layer 12 and the conductor layer 11 on the front surface is patterned in the other first insulating layer 12 by lithography and dry etching, respectively.
  • wirings 11b are formed on the back surface of one first insulating layer 12 and on the surface of the other first insulating layer 12, respectively.
  • the wiring 11b formed in one first insulating layer 12 and the wiring 11b formed in the other first insulating layer 12 are electrically connected through the plated film 16 of the through via 15.
  • the wiring 11 a formed on the first insulating layer 12 is embedded in the second insulating layer 13 by laminating the second insulating layer 13.
  • the wiring 11a since the wiring is embedded in a hard glass reinforced resin, when the wiring is thick, unevenness is formed on the surface of the core multilayer wiring board, resulting in flatness. Deteriorate. Therefore, the allowable range of the wiring thickness is narrow.
  • the allowable range of the thickness of the wiring 11a is wide. For example, a thick wiring having a thickness of about 35 mm may be applied. it can. As a result, the surface flatness of the core multilayer wiring board can be ensured, the desired thickness of the wiring 11a can be increased without causing warpage of the substrate, and the power supply can be stabilized.
  • the core multilayer wiring board 10 As for the core multilayer wiring board 10, the case where the first insulating layer 12 and the second insulating layer 13 constituting the core multilayer wiring board 10 having the above thicknesses are used is illustrated.
  • the soft second insulating layer 13 is excellent in embedding property of the wiring 11a and the degree of freedom of the thickness of the wiring 11a is high, the wiring 11a, the first insulating layer 12, and The thickness of the second insulating layer 13 can be defined.
  • the thickness of the wiring 11a, the first insulating layer 12 and the second insulating layer 13 is the sum of the thickness of the wiring 11a, the thickness of the first insulating layer 12 and the first insulating layer 12. It is defined by the ratio R 1 to the total thickness of the two insulating layers 13.
  • the thickness T 1 of the wire 11a, in order to stabilize the reduction and power supply noise in the build-up multilayer circuit board 10 is formed as thick as possible, for example, about 35 [mu] m.
  • the thickness T 2 of the first insulating layer 12 can be set to a minimum value T 2min equal to the thickness of the wiring 11a, for example, about 35 ⁇ m.
  • the maximum value T2max may be about 50 ⁇ m.
  • the thickness T 3 of the second insulating layer 13, considering that and insulation reliability can be ensured a sufficient embedding of the wiring 11a, the minimum value T 3min, the second insulating layer 13 which exists between opposing wires 11a It can be formed so that the thickness (gap thickness) is about 35 ⁇ m.
  • the maximum value T3max may be about 50 ⁇ m, for example.
  • the ratio R 1 is T 1 ⁇ 2 / (T 1 ⁇ 2 + T 2max ⁇ 2 + T 3max ) ⁇ R1 ⁇ T 1 ⁇ 2 / (T 1 ⁇ 2 + T 2min ⁇ 2 + T 3min ) And 7/22 ⁇ R 1 ⁇ 2/5 It becomes.
  • the sufficient flatness of the build-up multilayer circuit board is ensured, but the core multilayer wiring board is thinned, and the ratio of the thickness of the wiring in the core multilayer wiring board is set to the conventional core multilayer wiring board. It can be greatly increased compared to.
  • a pair of buildup layers 20 is formed so as to sandwich the core multilayer wiring board 10.
  • an insulating layer 22 such as a thermoplastic resin on which the wiring 21 is formed is laminated on the front surface and the back surface of the core multilayer wiring board 10.
  • the insulating layer 22 is formed of the same insulating material as the second insulating layer 13.
  • the laminate is formed on the front and back surfaces of the core multilayer wiring board 10 so as to have a wiring structure of four layers or more, for example, six layers.
  • FIG. 3B illustrates a four-layer wiring structure in which the wiring 11b and the three-layer wiring 21 are stacked as each stacked body.
  • a pair of buildup layers 20 sandwiching the core multilayer wiring board 10 are formed.
  • the buildup multilayer circuit board according to the present embodiment is formed through various processes such as forming a protective film on the surface of each buildup layer 20.
  • the flatness of the build-up multilayer circuit board completed according to the present embodiment was compared with that of a conventional build-up multilayer circuit board (using a glass reinforced resin for an insulating layer in which wiring is embedded with a core multilayer wiring board). As a result, the flatness of this embodiment was about 29 ⁇ m in terms of the amount of warpage of the substrate. On the other hand, the flatness of the prior art was about 62 ⁇ m. Thus, since a result equivalent to the comparison between the present embodiment and the prior art for the core multilayer wiring board was obtained, a build-up multilayer circuit board excellent in flatness can be obtained by the present embodiment. confirmed.
  • a highly reliable thin build-up multilayer circuit board that has a highly flat surface, reduces inductance, sufficiently suppresses power supply noise, and stabilizes the power supply. Is realized.
  • FIG. 5 is a schematic cross-sectional view schematically showing the semiconductor device according to the second embodiment.
  • a build-up multilayer circuit board is formed by the processes shown in FIGS.
  • the formed build-up multilayer circuit board 1 is illustrated in FIG.
  • a semiconductor chip 2 is disposed on the front surface, and a capacitor 3 is disposed on the back surface.
  • the wiring 21 and the connection terminals 2 a of the semiconductor chip 2 are electrically connected by solder bumps 23.
  • the wiring 21 and the connection terminal 3 a of the capacitor 3 are electrically connected by solder bumps 24.
  • the capacitor 3 is further connected to a mother board or the like (not shown).
  • the present embodiment it is possible to mount a semiconductor chip 2 having a highly flat surface and having a larger size and a smaller size, while reducing inductance and sufficiently suppressing power supply noise.
  • a semiconductor device including the highly reliable build-up multilayer circuit board 1 for stabilization is realized.
  • the present invention it is possible to mount a larger and finer electronic component having a highly flat surface, further reducing inductance, sufficiently suppressing power supply noise, and stabilizing the power supply.
  • a highly reliable circuit board and electronic device are realized.

Abstract

A circuit board of superior flatness, which can mount an electronic component of greater size or miniaturization, even reduces inductance, sufficiently suppresses power supply noise, provides power supply stability, and is of high reliability, is achieved, said circuit board including a core layer (10), and a pair of build-up layers (20) which sandwich the core layer (10) therebetween, wherein the core layer (10) is configured so as to comprise: first insulating layers (12) comprising wiring (11a) inside; and second insulating layers (13) which are disposed inside the first insulating layers (12), embed the wiring (11a) therein, and are of a lower modulus of elasticity than the first insulating layers (12). Also achieved is an electronic device therefor.

Description

回路基板及びその製造方法、並びに電子装置Circuit board, method for manufacturing the same, and electronic device
　本発明は、回路基板及びその製造方法、並びに電子装置に関する。 The present invention relates to a circuit board, a manufacturing method thereof, and an electronic device.
　近年では、電子機器の高性能化に伴い、特にＬＳＩ等の半導体素子の大型化及び多ピン化の要請が高まっている。この要請に応えるべく、半導体素子を実装するパッケージ基板における平坦性の向上が求められている。 In recent years, with increasing performance of electronic equipment, there has been a growing demand for larger semiconductor devices such as LSIs and more pins. In order to meet this demand, improvement in flatness in a package substrate on which a semiconductor element is mounted is required.
　半導体素子をパッケージ基板に実装する際には、半導体素子の表面に配された微細な格子状のハンダバンプを、一括してパッケージ基板の表面に配された端子に接続することが必要である。
　ハンダバンプの接続には、パッケージ基板の温度をハンダの溶融温度以上に加熱するところ、パッケージ基板が変形して平坦性が損なわれると、部分的にハンダバンプが浮いてしまい、パッケージ基板の端子と接続されないという問題が発生する。パッケージ基板の許容反り量は、半導体素子を実装する領域で約３０μｍ、基板全体で約１００μｍとされており、極めて高度な平坦化技術が要求される。 When mounting a semiconductor element on a package substrate, it is necessary to connect the fine grid-shaped solder bumps arranged on the surface of the semiconductor element to the terminals arranged on the surface of the package substrate in a lump.
For solder bump connection, when the temperature of the package substrate is heated above the melting temperature of the solder, if the package substrate is deformed and the flatness is impaired, the solder bumps partially float and are not connected to the terminals of the package substrate. The problem occurs. The allowable warpage amount of the package substrate is about 30 μm in the region where the semiconductor element is mounted and about 100 μm in the entire substrate, and an extremely high level planarization technique is required.
特開２０１１－８２３６１号公報JP 2011-82361 A
　パッケージ基板としては、より大型化、微細化された半導体素子を実装するために、いわゆるビルドアップ多層回路基板が開発されている。このビルドアップ多層回路基板は、剛直なコア多層配線板の表裏面に、薄い絶縁層と導体層とを交互に積層してなるビルドアップ層を形成してなるものである。 As a package substrate, a so-called build-up multilayer circuit substrate has been developed in order to mount a larger and finer semiconductor element. This build-up multilayer circuit board is formed by forming build-up layers formed by alternately laminating thin insulating layers and conductor layers on the front and back surfaces of a rigid core multilayer wiring board.
　ビルドアップ多層回路基板の平坦性を向上させるためには、以下のような工夫がなされている。即ち、基板表裏面に配される配線層の割合を設計によって均一化することは当然として、剛直なコア多層配線板を厚くしたり、材料の変更によってコア多層配線板の剛性を上げる等の改善が図られている。 In order to improve the flatness of the build-up multilayer circuit board, the following measures are taken. In other words, it is natural to make the ratio of the wiring layers arranged on the front and back surfaces of the board uniform by design, and it is natural to increase the rigidity of the core multilayer wiring board by increasing the thickness of the rigid core multilayer wiring board or changing the material Is planned.
　ビルドアップ多層回路基板の平坦性向上について、具体的に調べた実験結果について説明する。
　この実験で使用した、コア多層配線板とこれを挟む一対のビルドアップ層とからなるビルドアップ多層回路基板について説明する。基板Ａは、コア多層配線板が厚み０．４ｍｍの強化繊維ガラス（ガラスクロス）を備えた樹脂（以下、ガラス強化樹脂と言う。）に導体層が形成されてなる４層板（４層の配線構造）の表裏面に薄いガラスクロスを貼付してなるものであり、各ビルドアップ層が６層の配線構造が積層されたものであって、厚みが１．３５ｍｍとされている。
　基板Ｂは、コア多層配線板が厚み０．６ｍｍのガラス強化樹脂の４層板の表裏面に薄いガラスクロスを貼付してなるものであり、各ビルドアップ層が６層の配線構造が積層されたものであって、厚みが１．５５ｍｍとされている。
　基板Ｃは、コア多層配線板が厚み０．８ｍｍのガラス強化樹脂の４層板の表裏面に薄いガラスクロスを貼付してなるものであり、各ビルドアップ層が６層の配線構造が積層されたものであって、厚みが１．７５ｍｍとされている。
　基板Ｄは、コア多層配線板がガラス強化樹脂の８層板（８層の配線構造）からなるものであり、各ビルドアップ層が６層の配線構造が積層されたものであって、６層構成のものであって、厚みが１．９５ｍｍとされている。 The experimental results specifically examined for improving the flatness of the build-up multilayer circuit board will be described.
A buildup multilayer circuit board composed of a core multilayer wiring board and a pair of buildup layers sandwiching the core multilayer wiring board used in this experiment will be described. The substrate A is a four-layer board (four-layer board) in which a conductor layer is formed on a resin (hereinafter referred to as a glass-reinforced resin) in which a core multilayer wiring board is provided with reinforced fiber glass (glass cloth) having a thickness of 0.4 mm. A thin glass cloth is pasted on the front and back surfaces of the (wiring structure), each buildup layer is a laminate of six wiring structures, and the thickness is 1.35 mm.
The substrate B is formed by attaching a thin glass cloth to the front and back surfaces of a 4-layer board made of glass reinforced resin having a thickness of 0.6 mm as a core multilayer wiring board, and each of the build-up layers is laminated with a wiring structure of 6 layers. The thickness is 1.55 mm.
The substrate C is formed by attaching a thin glass cloth to the front and back surfaces of a 4-layer board of glass reinforced resin having a thickness of 0.8 mm as a core multilayer wiring board, and each build-up layer is laminated with a wiring structure of 6 layers. The thickness is 1.75 mm.
In the substrate D, the core multilayer wiring board is made of an 8-layer board (8-layer wiring structure) made of glass-reinforced resin, and each build-up layer is formed by stacking 6-layer wiring structures. It is a thing of structure, Comprising: Thickness shall be 1.95 mm.
　各ビルドアップ多層回路基板の反り量（温度２４０℃）は、基板Ａが１３５μｍ、基板Ｂが９９μｍ、基板Ｃが７６μｍ、基板Ｄが７１μｍであった。この実験結果より、剛直なコア多層配線板を厚くするほど（基板Ａ～Ｄ）、基板の剛性が高いほど（基板Ｄ（導体層の積層数が多い。））、基板の反り量は低減することが確認された。 The amount of warpage (temperature 240 ° C.) of each build-up multilayer circuit board was 135 μm for board A, 99 μm for board B, 76 μm for board C, and 71 μm for board D. From this experimental result, the thickness of the rigid core multilayer wiring board is increased (boards A to D), and the rigidity of the board is higher (board D (the number of conductor layers is greater)), the amount of warpage of the board is reduced. It was confirmed.
　ビルドアップ多層回路基板では、その裏面（下方のビルドアップ層の面）にコンデンサが搭載される。この場合、上記のように基板の平坦性向上を図るべくコア多層配線板を厚くすると、その分だけ基板厚が増加し、半導体チップとコンデンサとの距離が増大する。そうすると、ビルドアップ多層回路基板のインダクタンスが増加するという問題がある。 In the build-up multilayer circuit board, a capacitor is mounted on the back surface (the surface of the lower build-up layer). In this case, if the core multilayer wiring board is made thicker in order to improve the flatness of the substrate as described above, the substrate thickness increases accordingly, and the distance between the semiconductor chip and the capacitor increases. Then, there is a problem that the inductance of the build-up multilayer circuit board increases.
　一方、ビルドアップ多層回路基板における電源ノイズの低減及び電源の安定化を図るための対策として、基板内の導体層を厚くすることが求められている。しかしながら、厚い導体層で配線を形成し、多層化した場合、絶縁層による配線の埋め込みが不十分となり、配線と絶縁層との間で生じる凹凸によって内部応力が増加し、コア多層配線板の平坦性が悪くなる。そのため、配線を厚く形成すれば、それに応じて絶縁層も厚く形成する必要があり、ひいては基板厚の増加を招来するという問題がある。 On the other hand, as a measure for reducing power supply noise and stabilizing the power supply in the build-up multilayer circuit board, it is required to increase the thickness of the conductor layer in the board. However, when the wiring is formed with a thick conductor layer and the layers are made multi-layered, the embedding of the wiring by the insulating layer becomes insufficient, the internal stress increases due to the unevenness generated between the wiring and the insulating layer, and the core multilayer wiring board is flattened. Sexuality gets worse. For this reason, if the wiring is formed thick, it is necessary to form the insulating layer correspondingly, resulting in an increase in the substrate thickness.
　以上のように、ビルドアップ多層回路基板において、電源の安定化を図り、平坦性を向上させるためには、基板厚を厚くすることを要する。一方、ビルドアップ多層回路基板のインダクタンスを抑えるには、基板厚を薄くすることを要する。このように、ビルドアップ多層回路基板への諸要求を満たすことは、基板厚についてトレードオフの関係となることから、極めて困難な現況にある。 As described above, in the build-up multilayer circuit board, it is necessary to increase the board thickness in order to stabilize the power supply and improve the flatness. On the other hand, to suppress the inductance of the build-up multilayer circuit board, it is necessary to reduce the board thickness. As described above, satisfying various requirements for the build-up multilayer circuit board is in a very difficult situation because it has a trade-off relationship with respect to the board thickness.
　本発明は、上記の課題に鑑みてなされたものであり、平坦性の高い表面を有し、より大型化・微細化された電子部品を実装することが可能であり、しかもインダクタンスを低減し、電源ノイズを十分に抑えて電源安定化を図る信頼性の高い回路基板及びその製造方法、並びに電子装置を提供することを目的とする。 The present invention has been made in view of the above problems, has a highly flat surface, can be mounted on electronic components that are larger and finer, and reduce inductance, It is an object of the present invention to provide a highly reliable circuit board, a manufacturing method thereof, and an electronic device that sufficiently suppress power supply noise and stabilize the power supply.
　回路基板の一態様は、コア層と、前記コア層を挟持する一対のビルドアップ層とを含み、前記コア層は、配線を内側に有する第１の絶縁層と、前記第１の絶縁層の内側に配されて前記配線を埋め込み、前記第１の絶縁層よりも弾性率の低い第２の絶縁層とを有する。 One aspect of the circuit board includes a core layer and a pair of build-up layers that sandwich the core layer. The core layer includes a first insulating layer having a wiring inside, and the first insulating layer. And a second insulating layer having an elastic modulus lower than that of the first insulating layer.
　電子装置の一態様は、コア層と、前記コア層を挟持する一対のビルドアップ層とを備えた回路基板と、前記回路基板上に実装された電子部品とを含み、前記コア層は、配線を内側に有する第１の絶縁層と、前記第１の絶縁層の内側に配されて前記配線を埋め込み、前記第１の絶縁層よりも弾性率の低い第２の絶縁層とを有する。 One aspect of the electronic device includes a circuit board that includes a core layer, a pair of build-up layers that sandwich the core layer, and an electronic component that is mounted on the circuit board. And a second insulating layer disposed inside the first insulating layer to embed the wiring and having a lower elastic modulus than the first insulating layer.
　回路基板の製造方法の一態様は、コア層を形成する工程と、前記コア層を挟持する一対のビルドアップ層を形成する工程とを含み、前記コア層を形成する工程は、配線を内側に有する第１の絶縁層を配する工程と、前記第１の絶縁層の内側に、前記配線を埋め込むように、前記第１の絶縁層よりも弾性率の低い第２の絶縁層を配する工程とを有する。 One embodiment of a method for manufacturing a circuit board includes a step of forming a core layer and a step of forming a pair of buildup layers sandwiching the core layer, and the step of forming the core layer includes wiring on the inside. A step of providing a first insulating layer, and a step of providing a second insulating layer having a lower elastic modulus than the first insulating layer so as to embed the wiring inside the first insulating layer. And have.
　上記の諸態様によれば、平坦性の高い表面を有し、より大型化・微細化された電子部品を実装することが可能であり、しかもインダクタンスを低減し、電源ノイズを十分に抑えて電源安定化を図る信頼性の高い回路基板及び電子装置が実現する。 According to the above aspects, it is possible to mount a larger and finer electronic component having a highly flat surface, further reducing inductance, and sufficiently suppressing power supply noise. A highly reliable circuit board and electronic device for stabilization are realized.
図１は、従来のビルドアップ多層回路基板について、ＤＭＡ(Dynamicmechanical analysis)を測定した結果を示す特性図である。FIG. 1 is a characteristic diagram showing the result of measuring DMA (Dynamic mechanical analysis) for a conventional build-up multilayer circuit board. 図２Ａは、第１の実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。FIG. 2A is a schematic cross-sectional view showing the method of manufacturing the buildup multilayer circuit board according to the first embodiment in the order of steps. 図２Ｂは、図２Ａに引き続き、第１の実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。FIG. 2B is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 2A. 図２Ｃは、図２Ｂに引き続き、第１の実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。FIG. 2C is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 2B. 図３Ａは、図２Ｃに引き続き、第１の実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。FIG. 3A is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps following FIG. 2C. 図３Ｂは、図３Ａに引き続き、第１の実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。FIG. 3B is a schematic cross-sectional view illustrating the manufacturing method of the build-up multilayer circuit board according to the first embodiment in the order of steps, following FIG. 3A. 図４は、第１の実施形態によるビルドアップ多層回路基板のコア多層配線板を示す概略断面図である。FIG. 4 is a schematic cross-sectional view showing the core multilayer wiring board of the buildup multilayer circuit board according to the first embodiment. 図５は、第２の実施形態による半導体装置を模式的に示す概略断面図である。FIG. 5 is a schematic cross-sectional view schematically showing the semiconductor device according to the second embodiment.
　以下、本実施形態における基本骨子について説明する。
　ビルドアップ多層回路基板は、コア多層配線板を一対のビルドアップ層で挟持する構成を採る。本実施形態では、各ビルドアップ層が４層以上の配線構造となるように積層された場合には、ビルドアップ多層回路基板の平坦性はコア多層配線板の平坦性に依存することを見出した。 Hereinafter, the basic outline in the present embodiment will be described.
The build-up multilayer circuit board adopts a configuration in which a core multilayer wiring board is sandwiched between a pair of build-up layers. In the present embodiment, it was found that the flatness of the buildup multilayer circuit board depends on the flatness of the core multilayer wiring board when each buildup layer is laminated so as to have a wiring structure of four or more layers. .
　従来のビルドアップ多層回路基板では、ビルドアップ層において発生する応力をコア多層配線板が支持体として受け止め、基板の反りを抑制する構造を採っている。従って、基板の反りを抑制するためには、より剛性の高い、より厚いコア多層配線板を用いることが有効と考えられていた。 The conventional build-up multilayer circuit board has a structure in which the stress generated in the build-up layer is received as a support by the core multilayer wiring board and the warp of the board is suppressed. Therefore, in order to suppress the warpage of the substrate, it has been considered effective to use a thicker core multilayer wiring board having higher rigidity.
　上述の実験に用いたビルドアップ多層回路基板である基板Ａ～基板Ｄについて、機械特性（弾性率）について調べた。図１は、基板Ａ～基板ＤについてＤＭＡ(Dynamic mechanical analysis)を測定した結果を示す特性図である。このように、ビルドアップ多層回路基板の完成体としては、コア多層配線板の材質・厚みの違いを見ることはできず、完成体の厚みの違いだけを見ることができる。 The mechanical properties (elastic modulus) of the substrates A to D, which are the build-up multilayer circuit boards used in the above-described experiment, were examined. FIG. 1 is a characteristic diagram showing the results of measuring DMA (Dynamic Mechanical Analysis) for substrates A to D. FIG. As described above, as the completed body of the build-up multilayer circuit board, the difference in material and thickness of the core multilayer wiring board cannot be seen, and only the difference in thickness of the finished body can be seen.
　また、基板表裏の導体層割合を設計によって均一化されたビルドアップ多層回路基板の平坦性では温度依存が小さく、完成体の室温状態の平坦性とハンダの溶融温度における平坦性との間に差異は殆ど見られず、改善すべきは室温状態の平坦性と考えられる。 In addition, the flatness of the build-up multilayer circuit board in which the ratio of the conductor layers on the front and back sides of the board is made uniform by design has little temperature dependence, and there is a difference between the flatness in the room temperature state of the finished product and the flatness at the melting temperature of the solder. Is hardly observed, and the flatness at room temperature is considered to be improved.
　本実施形態では、ビルドアップ多層回路基板の完成体の平坦性と、それに用いる、ビルドアップ層を形成する前のコア多層配線板の平坦性とを比較したところ、両者の平坦性が略同一であることを見出した。 In this embodiment, when the flatness of the completed build-up multilayer circuit board is compared with the flatness of the core multilayer wiring board used for forming the build-up layer before the build-up layer is formed, the flatness of both is substantially the same. I found out.
　そこで、コア多層配線板の内部応力の低減を実現すべく、以下の実験を行った。
　この実験で使用する、ビルドアップ多層回路基板のコア多層配線板について説明する。
　コアＡは、全ての絶縁層を高弾性率のガラス強化樹脂で形成したものである。
　コアＢは、中心部位に内部応力緩和を目的とした低弾性率のエポキシ樹脂の絶縁層を配し、これを挟むように高弾性率のガラス強化樹脂の絶縁層を貼付したものである。
　コアＣは、中心部位に高弾性率のガラス強化樹脂の絶縁層を配し、これを挟むように低弾性率のエポキシ樹脂の絶縁層を貼付したものである。
　コアＤは、全ての絶縁層を低弾性率のエポキシ樹脂で形成したものである。
　コアＡ～コアＤは、全て同じ厚みとした。 Therefore, the following experiment was conducted in order to reduce the internal stress of the core multilayer wiring board.
The core multilayer wiring board of the buildup multilayer circuit board used in this experiment will be described.
The core A is formed by forming all the insulating layers with a glass reinforced resin having a high elastic modulus.
The core B is formed by arranging an insulating layer of a low elastic modulus epoxy resin for the purpose of relaxing internal stress at a central portion and attaching an insulating layer of a high elastic modulus glass reinforced resin so as to sandwich the insulating layer.
The core C is obtained by placing an insulating layer of a high elastic modulus glass reinforced resin at a central portion and attaching an insulating layer of an epoxy resin having a low elastic modulus so as to sandwich the insulating layer.
The core D is formed by forming all the insulating layers with a low elastic epoxy resin.
The cores A to D all have the same thickness.
　各ビルドアップ多層回路基板の反り量（室温（２５℃））は、コアＡを備えた基板が１１５μｍ、コアＣを備えた基板が１２２μｍ、コアＤを備えた基板が３０７μｍと各々大きい値であったのに対して、コアＢを備えた基板では５８μｍに抑えられていた。
　この実験結果より、コア多層配線板を低弾性率の絶縁層を一対の高弾性率の絶縁層で挟持する構成とすることにより、ビルドアップ多層回路基板の平坦性が著しく向上することが確認された。 The amount of warpage (room temperature (25 ° C.)) of each build-up multilayer circuit board was 115 μm for the board with the core A, 122 μm for the board with the core C, and 307 μm for the board with the core D. On the other hand, in the board | substrate provided with the core B, it was restrained to 58 micrometers.
From this experimental result, it was confirmed that the flatness of the build-up multilayer circuit board is remarkably improved by sandwiching the core multilayer wiring board with a low elastic modulus insulating layer between a pair of high elastic modulus insulating layers. It was.
　本実施形態では、上記の実験結果を踏まえ、配線を内側に有する第１の絶縁層と、第１の絶縁層の内側に配されて配線を埋め込み、第１の絶縁層よりも低弾性率の第２の絶縁層とを有するコア多層配線板と、このコア多層配線板を挟持する一対のビルドアップ層と備えたビルドアップ多層回路基板を開示する。 In the present embodiment, based on the experimental results described above, the first insulating layer having the wiring inside, and the wiring is embedded inside the first insulating layer and has a lower elastic modulus than the first insulating layer. A build-up multilayer circuit board comprising a core multilayer wiring board having a second insulating layer and a pair of build-up layers sandwiching the core multilayer wiring board is disclosed.
　第１の絶縁層及び第２の絶縁層としては、前者の弾性率が後者の弾性率の５倍以上となるものを用いることが好ましい。この構成により、ビルドアップ多層回路基板の十分な平坦性を得ることができる。 As the first insulating layer and the second insulating layer, it is preferable to use one having an elastic modulus of the former of 5 or more times that of the latter. With this configuration, sufficient flatness of the build-up multilayer circuit board can be obtained.
　ビルドアップ層は、配線構造を４層以上に積層することが好ましい。４層以上とすることにより、ビルドアップ多層回路基板の平坦性におけるコア多層配線板の支配性が緩和され、ビルドアップ多層回路基板の十分な平坦性を得ることができる。 The build-up layer is preferably laminated with four or more wiring structures. By using four or more layers, the dominance of the core multilayer wiring board in the flatness of the buildup multilayer circuit board is relaxed, and sufficient flatness of the buildup multilayer circuit board can be obtained.
　コア多層配線板の中心部位に第１の絶縁層よりも低弾性率の第２の絶縁層を配することにより、配線を従来用いられているガラス強化樹脂で埋め込む場合に比べて配線の埋め込み性が向上する。従って、配線の厚みの自由度が増し、配線を所期の厚み（例えば３５μｍ以上）としても、第２の絶縁層で配線を確実に埋め込むことが可能となる。よって、ビルドアップ多層回路基板を薄くしてインダクタンスの低減を図るも、基板の十分な平坦性を確保することができる。 By placing a second insulating layer having a lower elastic modulus than that of the first insulating layer at the central portion of the core multilayer wiring board, the wiring embedability can be improved as compared with the case where the wiring is embedded with a glass reinforced resin that has been conventionally used. Will improve. Accordingly, the degree of freedom of the thickness of the wiring is increased, and the wiring can be surely embedded in the second insulating layer even if the wiring has an intended thickness (for example, 35 μm or more). Therefore, even if the build-up multilayer circuit board is thinned to reduce inductance, sufficient flatness of the board can be ensured.
　（第１の実施形態）
　以下、回路基板及びその製造方法の好適な実施形態について、図面を参照しながら詳細に説明する。本実施形態では、複数の配線層が積層されてなり、半導体チップ等の電子部品が実装されるパッケージ基板であるビルドアップ多層回路基板を開示し、その構成を製造方法と共に説明する。
　図２Ａ～図３Ｂは、本実施形態によるビルドアップ多層回路基板の製造方法を工程順に示す概略断面図である。 (First embodiment)
Hereinafter, a preferred embodiment of a circuit board and a method for manufacturing the circuit board will be described in detail with reference to the drawings. In the present embodiment, a build-up multilayer circuit board, which is a package board on which a plurality of wiring layers are stacked and an electronic component such as a semiconductor chip is mounted, is disclosed, and its configuration will be described together with a manufacturing method.
2A to 3B are schematic cross-sectional views showing the manufacturing method of the build-up multilayer circuit board according to the present embodiment in the order of steps.
　図２Ａ～図２Ｃにおいて、コア層であるコア多層配線板１０を形成する。
　先ず、図２Ａに示すように、一対の第１の絶縁層１２を配する。
　詳細には、表裏面にそれぞれ導体層１１が形成された一対の第１の絶縁層１２を用意する。第１の絶縁層１２の厚みは、例えば１００μｍ程度である。一方（図中、下側）の第１の絶縁層１２では表面の導体層１１を、他方（図中、上側）の第１の絶縁層１２では裏面の導体層１１をそれぞれリソグラフィー及びドライエッチングによりパターニングする。このパターニングにより、一方の第１の絶縁層１２の表面、及び他方の第１の絶縁層１２の裏面にそれぞれ配線１１ａが形成される。 2A to 2C, a core multilayer wiring board 10 as a core layer is formed.
First, as shown in FIG. 2A, a pair of first insulating layers 12 is provided.
Specifically, a pair of first insulating layers 12 each having a conductor layer 11 formed on the front and back surfaces are prepared. The thickness of the first insulating layer 12 is, for example, about 100 μm. Lithography and dry etching are used for the conductive layer 11 on the front surface in the first insulating layer 12 on the lower side (in the drawing) and the conductive layer 11 on the back surface in the first insulating layer 12 on the other side (upper in the drawing). Pattern. By this patterning, wirings 11a are formed on the surface of one first insulating layer 12 and the back surface of the other first insulating layer 12, respectively.
　導体層１１は、銅（Ｃｕ）又はＣｕ合金を材料として形成されている。
　第１の絶縁層１２は、弾性率の高い剛直な絶縁材料、例えば強化繊維ガラス又は強化繊維プラスチック材料、ここでは強化繊維ガラスを有する絶縁樹脂（ガラス強化樹脂）を材料として形成されている。本実施形態では、第１の絶縁層１２の材料として、日立化成株式会社製の商品名E679FGRを用いる。この場合、第１の絶縁層１２の弾性率は例えば２３．３ＧＰａ程度である。 The conductor layer 11 is formed using copper (Cu) or a Cu alloy as a material.
The first insulating layer 12 is formed using a rigid insulating material having a high elastic modulus, for example, a reinforced fiber glass or a reinforced fiber plastic material, here an insulating resin (glass reinforced resin) having reinforced fiber glass. In the present embodiment, as a material for the first insulating layer 12, a trade name E679FGR manufactured by Hitachi Chemical Co., Ltd. is used. In this case, the elastic modulus of the first insulating layer 12 is, for example, about 23.3 GPa.
　次に、図２Ｂに示すように、第１の絶縁層１２に第２の絶縁層１３を貼付する。
　詳細には、一方の第１の絶縁層１２の表面、及び他方の第１の絶縁層１２の裏面に、配線１１ａを埋め込むように、それぞれ第２の絶縁層１３を貼付、ここでは真空ラミネートする。各第２の絶縁層１３の厚みは、例えば３０μｍ程度である。 Next, as shown in FIG. 2B, the second insulating layer 13 is attached to the first insulating layer 12.
Specifically, the second insulating layer 13 is attached to the front surface of one first insulating layer 12 and the back surface of the other first insulating layer 12 so as to embed the wiring 11a, and here, vacuum lamination is performed. . The thickness of each second insulating layer 13 is, for example, about 30 μm.
　第２の絶縁層１３は、第１の絶縁層１２よりも弾性率の低い等方的な機械物性を有する熱可塑性樹脂等の絶縁材料を材料として形成されている。第２の絶縁層１３の弾性率は、第１の絶縁層１２の弾性率の例えば１／５以下である。本実施形態では、第２の絶縁層１３の材料として、味の素株式会社製の商品名GX-13を用いる。この場合、第２の絶縁層１３の弾性率は例えば３．９６ＧＰａ程度である。 The second insulating layer 13 is formed of an insulating material such as a thermoplastic resin having isotropic mechanical properties having a lower elastic modulus than that of the first insulating layer 12. The elastic modulus of the second insulating layer 13 is, for example, 1/5 or less of the elastic modulus of the first insulating layer 12. In the present embodiment, the product name GX-13 manufactured by Ajinomoto Co., Inc. is used as the material of the second insulating layer 13. In this case, the elastic modulus of the second insulating layer 13 is, for example, about 3.96 GPa.
　次に、図２Ｃに示すように、一対の第１の絶縁層１２を第２の絶縁層１３で貼り合わせる。
　詳細には、配線１１ａを埋め込む第２の絶縁層１３により対向配置された一対の第１の絶縁層１２を、第２の絶縁層１３を介して貼り合わせて加熱する。加熱により、３層の第２の絶縁層１３が硬化して一体化する。貼り合わせに用いられる第２の絶縁層１３は、配線１１ａを埋め込む第２の絶縁層１３と同じ絶縁材料であり、厚みも同じ３０μｍ程度である。 Next, as illustrated in FIG. 2C, the pair of first insulating layers 12 are bonded to each other with the second insulating layer 13.
Specifically, the pair of first insulating layers 12 that are opposed to each other by the second insulating layer 13 that embeds the wiring 11a is bonded to each other via the second insulating layer 13 and heated. By heating, the three second insulating layers 13 are cured and integrated. The second insulating layer 13 used for bonding is the same insulating material as the second insulating layer 13 in which the wiring 11a is embedded, and the thickness is about 30 μm.
　続いて、図３Ａに示すように、コア多層配線板１０に貫通ビア１５を形成する。
　詳細には、先ず、例えば１５０μｍ程度～３００μｍ程度の径のドリルを用いて、図２Ｃで貼り合わせられた第１の絶縁層１２及び第２の絶縁層１３の構造体に貫通孔１５ａを形成する。
　次に、貫通孔１５ａの側壁面を電解メッキ処理又は無電解メッキ処理し、例えばＣｕのメッキ膜１６を形成する。メッキ膜１６は、例えば１０μｍ程度～３０μｍ程度の厚みに形成される。
　次に、メッキ膜１６を介した貫通孔１５ａ内を樹脂１７で充填する。これにより、貫通ビア１５が形成される。 Subsequently, as shown in FIG. 3A, a through via 15 is formed in the core multilayer wiring board 10.
Specifically, first, a through hole 15a is formed in the structure of the first insulating layer 12 and the second insulating layer 13 bonded together in FIG. 2C, using a drill having a diameter of about 150 μm to 300 μm, for example. .
Next, the side wall surface of the through hole 15a is subjected to an electrolytic plating process or an electroless plating process to form a Cu plating film 16, for example. The plating film 16 is formed to a thickness of about 10 μm to 30 μm, for example.
Next, the inside of the through hole 15 a through the plating film 16 is filled with the resin 17. Thereby, the through via 15 is formed.
　以上により、配線１１ａを内側に有する第１の絶縁層１２と、第１の絶縁層１２の内側に配されて配線１１ａを埋め込み、第１の絶縁層１２よりも弾性率の低い第２の絶縁層１３とを有し、貫通ビア１５が形成されてなるコア多層配線板１０が形成される。 As described above, the first insulating layer 12 having the wiring 11a on the inner side and the second insulating layer disposed on the inner side of the first insulating layer 12 so as to embed the wiring 11a and having a lower elastic modulus than the first insulating layer 12 The core multilayer wiring board 10 having the layer 13 and having the through vias 15 is formed.
　次に、一方の第１の絶縁層１２では裏面の導体層１１を、他方の第１の絶縁層１２では表面の導体層１１をそれぞれリソグラフィー及びドライエッチングによりパターニングする。このパターニングにより、一方の第１の絶縁層１２の裏面、及び他方の第１の絶縁層１２の表面にそれぞれ配線１１ｂが形成される。一方の第１の絶縁層１２に形成された配線１１ｂと他方の第１の絶縁層１２に形成された配線１１ｂとは、貫通ビア１５のメッキ膜１６を介して電気的に接続される。 Next, the conductor layer 11 on the back surface is patterned in one first insulating layer 12 and the conductor layer 11 on the front surface is patterned in the other first insulating layer 12 by lithography and dry etching, respectively. By this patterning, wirings 11b are formed on the back surface of one first insulating layer 12 and on the surface of the other first insulating layer 12, respectively. The wiring 11b formed in one first insulating layer 12 and the wiring 11b formed in the other first insulating layer 12 are electrically connected through the plated film 16 of the through via 15.
　本実施形態では、第１の絶縁層１２上に形成された配線１１ａは、第２の絶縁層１３のラミネートにより、第２の絶縁層１３内に埋め込まれる。これに対して従来のコア多層配線板では、配線を硬質のガラス強化樹脂に埋め込み形成することから、配線が厚いとその影響を受けてコア多層配線板の表面に凹凸が形成され、平坦性が悪くなる。そのため、配線の厚みの許容範囲が狭い。本実施形態では、従来技術とは異なり、配線１１ａが軟質な第２の絶縁層１３内に埋め込まれるため、配線１１ａの厚みの許容範囲が広く、例えば厚み３５ｍｍ程度の厚い配線を適用することもできる。これにより、コア多層配線板の表面平坦性を確保し、基板の反りを生ぜしめることなく、配線１１ａの所期の厚膜化を図ることができ、電源の安定化が達成される。 In this embodiment, the wiring 11 a formed on the first insulating layer 12 is embedded in the second insulating layer 13 by laminating the second insulating layer 13. On the other hand, in the conventional core multilayer wiring board, since the wiring is embedded in a hard glass reinforced resin, when the wiring is thick, unevenness is formed on the surface of the core multilayer wiring board, resulting in flatness. Deteriorate. Therefore, the allowable range of the wiring thickness is narrow. In this embodiment, unlike the prior art, since the wiring 11a is embedded in the soft second insulating layer 13, the allowable range of the thickness of the wiring 11a is wide. For example, a thick wiring having a thickness of about 35 mm may be applied. it can. As a result, the surface flatness of the core multilayer wiring board can be ensured, the desired thickness of the wiring 11a can be increased without causing warpage of the substrate, and the power supply can be stabilized.
　コア多層配線板１０について、これを構成する第１の絶縁層１２及び第２の絶縁層１３について、上記の厚みのものを用いた場合を例示した。本実施形態では、軟質な第２の絶縁層１３が配線１１ａの埋め込み性に優れており、配線１１ａの厚みの自由度が高いことから、以下のように配線１１ａ、第１の絶縁層１２及び第２の絶縁層１３の厚みを規定することができる。 As for the core multilayer wiring board 10, the case where the first insulating layer 12 and the second insulating layer 13 constituting the core multilayer wiring board 10 having the above thicknesses are used is illustrated. In the present embodiment, since the soft second insulating layer 13 is excellent in embedding property of the wiring 11a and the degree of freedom of the thickness of the wiring 11a is high, the wiring 11a, the first insulating layer 12, and The thickness of the second insulating layer 13 can be defined.
　本実施形態では、図４に示すように、配線１１ａ、第１の絶縁層１２及び第２の絶縁層１３の厚みを、配線１１ａの厚みの合算値と第１の絶縁層１２の厚み及び第２の絶縁層１３の厚みの合算値との比Ｒ１で規定する。
　配線１１ａの厚みＴ１は、ビルドアップ多層回路基板１０における電源ノイズの低減及び電源の安定化を図るべく、できるだけ厚く、例えば３５μｍ程度に形成する。
　第１の絶縁層１２の厚みＴ２は、絶縁信頼性を考慮すると、最小値Ｔ２ｍｉｎを配線１１ａの厚みと同等、例えば３５μｍ程度に形成することができる。最大値Ｔ２ｍａｘとしては、例えば５０μｍ程度とすれば良い。
　第２の絶縁層１３の厚みＴ３は、配線１１ａの十分な埋め込みを確保できること及び絶縁信頼性を考慮して、最小値Ｔ３ｍｉｎとして、対向する配線１１ａ間に存する第２の絶縁層１３の厚み（ギャップの厚み）が３５μｍ程度となるように形成することができる。最大値Ｔ３ｍａｘとしては、例えば５０μｍ程度とすれば良い。 In the present embodiment, as shown in FIG. 4, the thickness of the wiring 11a, the first insulating layer 12 and the second insulating layer 13 is the sum of the thickness of the wiring 11a, the thickness of the first insulating layer 12 and the first insulating layer 12. It is defined by the ratio R 1 to the total thickness of the two insulating layers 13.
The thickness T 1 of the wire 11a, in order to stabilize the reduction and power supply noise in the build-up multilayer circuit board 10 is formed as thick as possible, for example, about 35 [mu] m.
In consideration of insulation reliability, the thickness T 2 of the first insulating layer 12 can be set to a minimum value T 2min equal to the thickness of the wiring 11a, for example, about 35 μm. For example, the maximum value T2max may be about 50 μm.
The thickness T 3 of the second insulating layer 13, considering that and insulation reliability can be ensured a sufficient embedding of the wiring 11a, the minimum value T 3min, the second insulating layer 13 which exists between opposing wires 11a It can be formed so that the thickness (gap thickness) is about 35 μm. The maximum value T3max may be about 50 μm, for example.
　以上を勘案すると、比Ｒ１は、
　Ｔ１×２／（Ｔ１×２＋Ｔ２ｍａｘ×２＋Ｔ３ｍａｘ）≦Ｒ１≦Ｔ１×２／（Ｔ１×２＋Ｔ２ｍｉｎ×２＋Ｔ３ｍｉｎ）
　となり、
　７／２２≦Ｒ１≦２／５
　となる。 Considering the above, the ratio R 1 is
T 1 × 2 / (T 1 × 2 + T 2max × 2 + T 3max ) ≦ R1 ≦ T 1 × 2 / (T 1 × 2 + T 2min × 2 + T 3min )
And
7/22 ≦ R 1 ≦ 2/5
It becomes.
　これに対して、従来のコア多層配線板では、配線を埋め込む絶縁層として硬質のガラス強化樹脂を用いているため、例えば３５μｍの厚みの配線を埋め込むには、ガラス強化樹脂は０．１ｍｍ程度の厚みを要する。配線間を隔てる絶縁層も同様に０．１ｍｍ程度の厚みであるとする。そうすると、本実施形態と同様に２層の配線を埋め込む場合、配線の厚みの合算値と絶縁層の厚みの合算値との比Ｒ２は、
　Ｒ２≒３５×２／（３５×２＋１００×３）＝７／３７
　となる。 On the other hand, in the conventional core multilayer wiring board, since a hard glass reinforced resin is used as an insulating layer for embedding wiring, for example, in order to embed wiring having a thickness of 35 μm, Thickness is required. Similarly, the insulating layer separating the wirings is assumed to have a thickness of about 0.1 mm. Then, when embedding two layers of wiring as in this embodiment, the ratio R 2 between the total value of the wiring thickness and the total thickness of the insulating layer is:
R 2 ≈35 × 2 / (35 × 2 + 100 × 3) = 7/37
It becomes.
　このように、本実施形態では、ビルドアップ多層回路基板の十分な平坦性を確保するも、コア多層配線板を薄くし、しかもコア多層配線板における配線の厚みの割合を従来のコア多層配線板に比べて大幅に増加させることができる。 As described above, in this embodiment, the sufficient flatness of the build-up multilayer circuit board is ensured, but the core multilayer wiring board is thinned, and the ratio of the thickness of the wiring in the core multilayer wiring board is set to the conventional core multilayer wiring board. It can be greatly increased compared to.
　続いて、図３Ｂに示すように、コア多層配線板１０を挟むように、一対のビルドアップ層２０を形成する。
　詳細には、コア多層配線板１０の表面及び裏面にそれぞれ、配線２１が形成された熱可塑性樹脂等の絶縁層２２を積層する。絶縁層２２は、第２の絶縁層１３と同じ絶縁材料で形成される。本実施形態では、コア多層配線板１０の表面及び裏面にそれぞれ４層以上、例えば６層の配線構造となるように積層体を形成する。
　なお、図示の都合上、図３Ｂでは、各積層体として、配線１１ｂ及び３層の配線２１が積層された４層の配線構造を例示する。
　以上により、コア多層配線板１０を挟む一対のビルドアップ層２０が形成される。 Subsequently, as shown in FIG. 3B, a pair of buildup layers 20 is formed so as to sandwich the core multilayer wiring board 10.
Specifically, an insulating layer 22 such as a thermoplastic resin on which the wiring 21 is formed is laminated on the front surface and the back surface of the core multilayer wiring board 10. The insulating layer 22 is formed of the same insulating material as the second insulating layer 13. In the present embodiment, the laminate is formed on the front and back surfaces of the core multilayer wiring board 10 so as to have a wiring structure of four layers or more, for example, six layers.
For convenience of illustration, FIG. 3B illustrates a four-layer wiring structure in which the wiring 11b and the three-layer wiring 21 are stacked as each stacked body.
Thus, a pair of buildup layers 20 sandwiching the core multilayer wiring board 10 are formed.
　しかる後、各ビルドアップ層２０の表面に保護膜を形成する等の諸工程を経て、本実施形態によるビルドアップ多層回路基板が形成される。 Thereafter, the buildup multilayer circuit board according to the present embodiment is formed through various processes such as forming a protective film on the surface of each buildup layer 20.
　本実施形態により完成したビルドアップ多層回路基板について、従来技術によるビルドアップ多層回路基板（コア多層配線板で配線を埋め込む絶縁層にガラス強化樹脂を用いたもの）との平坦性を比較した。その結果、本実施形態の平坦性が基板の反り量で２９μｍ程度であった。これに対して、従来技術の平坦性は６２μｍ程度であった。このように、コア多層配線板についての本実施形態と従来技術との比較と同等の結果が得られたことから、本実施形態により、平坦性に優れたビルドアップ多層回路基板が得られることが確認された。 The flatness of the build-up multilayer circuit board completed according to the present embodiment was compared with that of a conventional build-up multilayer circuit board (using a glass reinforced resin for an insulating layer in which wiring is embedded with a core multilayer wiring board). As a result, the flatness of this embodiment was about 29 μm in terms of the amount of warpage of the substrate. On the other hand, the flatness of the prior art was about 62 μm. Thus, since a result equivalent to the comparison between the present embodiment and the prior art for the core multilayer wiring board was obtained, a build-up multilayer circuit board excellent in flatness can be obtained by the present embodiment. confirmed.
　以上説明したように、本実施形態によれば、平坦性の高い表面を有し、しかもインダクタンスを低減し、電源ノイズを十分に抑えて電源安定化を図る信頼性の高い薄いビルドアップ多層回路基板が実現する。 As described above, according to the present embodiment, a highly reliable thin build-up multilayer circuit board that has a highly flat surface, reduces inductance, sufficiently suppresses power supply noise, and stabilizes the power supply. Is realized.
　（第２の実施形態）
　以下、電子装置の好適な実施形態について、図面を参照しながら詳細に説明する。本実施形態では、電子装置として、第１の実施形態によるビルドアップ多層回路基板に、電子部品として半導体チップを搭載してなる半導体装置を開示し、その構成を製造方法と共に説明する。
　図５は、第２の実施形態による半導体装置を模式的に示す概略断面図である。 (Second Embodiment)
Hereinafter, preferred embodiments of an electronic device will be described in detail with reference to the drawings. In this embodiment, a semiconductor device in which a semiconductor chip is mounted as an electronic component on the build-up multilayer circuit board according to the first embodiment is disclosed as an electronic device, and the configuration thereof will be described together with a manufacturing method.
FIG. 5 is a schematic cross-sectional view schematically showing the semiconductor device according to the second embodiment.
　本実施形態では、第１の実施形態と同様に、図２～図３の諸工程により、ビルドアップ多層回路基板を形成する。形成されたビルドアップ多層回路基板１を図５に例示する。 In the present embodiment, as in the first embodiment, a build-up multilayer circuit board is formed by the processes shown in FIGS. The formed build-up multilayer circuit board 1 is illustrated in FIG.
　ビルドアップ多層回路基板１においては、その表面には半導体チップ２が、その裏面にはコンデンサ３がそれぞれ対向配置される。
　ビルドアップ多層回路基板１の表面では、その配線２１と半導体チップ２の接続端子２ａとがハンダバンプ２３により電気的に接続されている。
　ビルドアップ多層回路基板１の裏面では、その配線２１とコンデンサ３の接続端子３ａとがハンダバンプ２４により電気的に接続されている。
　コンデンサ３は、更に不図示のマザーボード等に接続される。 In the build-up multilayer circuit board 1, a semiconductor chip 2 is disposed on the front surface, and a capacitor 3 is disposed on the back surface.
On the surface of the build-up multilayer circuit board 1, the wiring 21 and the connection terminals 2 a of the semiconductor chip 2 are electrically connected by solder bumps 23.
On the back surface of the build-up multilayer circuit board 1, the wiring 21 and the connection terminal 3 a of the capacitor 3 are electrically connected by solder bumps 24.
The capacitor 3 is further connected to a mother board or the like (not shown).
　本実施形態によれば、平坦性の高い表面を有し、より大型化・微細化された半導体チップ２を実装することが可能であり、しかもインダクタンスを低減し、電源ノイズを十分に抑えて電源安定化を図る信頼性の高いビルドアップ多層回路基板１を備えた半導体装置が実現する。 According to the present embodiment, it is possible to mount a semiconductor chip 2 having a highly flat surface and having a larger size and a smaller size, while reducing inductance and sufficiently suppressing power supply noise. A semiconductor device including the highly reliable build-up multilayer circuit board 1 for stabilization is realized.
　本発明によれば、平坦性の高い表面を有し、より大型化・微細化された電子部品を実装することが可能であり、しかもインダクタンスを低減し、電源ノイズを十分に抑えて電源安定化を図る信頼性の高い回路基板及び電子装置が実現する。 According to the present invention, it is possible to mount a larger and finer electronic component having a highly flat surface, further reducing inductance, sufficiently suppressing power supply noise, and stabilizing the power supply. Thus, a highly reliable circuit board and electronic device are realized.

Claims (13)

  1. 　コア層と、
    　前記コア層を挟持する一対のビルドアップ層と
    　を含み、
    　前記コア層は、配線を内側に有する第１の絶縁層と、前記第１の絶縁層の内側に配されて前記配線を埋め込み、前記第１の絶縁層よりも弾性率の低い第２の絶縁層とを有することを特徴とする回路基板。     The core layer,
    A pair of build-up layers sandwiching the core layer,
    The core layer includes a first insulating layer having a wiring inside and a second insulating layer disposed inside the first insulating layer to embed the wiring and having a lower elastic modulus than the first insulating layer. And a circuit board.
  2. 　前記コア層において、前記配線の厚みの合算値と前記第１の絶縁層の厚み及び前記第２の絶縁層の厚みの合算値との比が、７／２２～２／５の範囲内の値であることを特徴とする請求項１に記載の回路基板。 In the core layer, the ratio of the sum of the thicknesses of the wirings to the sum of the thicknesses of the first insulating layer and the second insulating layer is within a range of 7/22 to 2/5. The circuit board according to claim 1, wherein:
  3. 　前記第１の絶縁層は、前記第２の絶縁層の５倍以上の弾性率を有することを特徴とする請求項１又は２に記載の回路基板。 3. The circuit board according to claim 1, wherein the first insulating layer has a modulus of elasticity five times or more that of the second insulating layer.
  4. 　前記第１の絶縁層は、強化繊維ガラス又は強化繊維プラスチック材料を有することを特徴とする請求項１～３のいずれか１項に記載の回路基板。 The circuit board according to any one of claims 1 to 3, wherein the first insulating layer comprises a reinforced fiber glass or a reinforced fiber plastic material.
  5. 　前記第２の絶縁層は、等方的な機械物性を有することを特徴とする請求項１～４のいずれか１項に記載の回路基板。 5. The circuit board according to claim 1, wherein the second insulating layer has isotropic mechanical properties.
  6. 　コア層と、
    　前記コア層を挟持する一対のビルドアップ層と
    　を備えた回路基板と、
    　前記回路基板上に実装された電子部品と
    　を含み、
    　前記コア層は、配線を内側に有する第１の絶縁層と、前記第１の絶縁層の内側に配されて前記配線を埋め込み、前記第１の絶縁層よりも弾性率の低い第２の絶縁層とを有することを特徴とする電子装置。     The core layer,
    A circuit board comprising: a pair of buildup layers sandwiching the core layer;
    An electronic component mounted on the circuit board,
    The core layer includes a first insulating layer having a wiring inside and a second insulating layer disposed inside the first insulating layer to embed the wiring and having a lower elastic modulus than the first insulating layer. And an electronic device.
  7. 　前記コア層において、前記配線の厚みの合算値と前記第１の絶縁層の厚み及び前記第２の絶縁層の厚みの合算値との比が、７／２２～２／５の範囲内の値であることを特徴とする請求項６に記載の電子装置。 In the core layer, the ratio of the sum of the thicknesses of the wirings to the sum of the thicknesses of the first insulating layer and the second insulating layer is within a range of 7/22 to 2/5. The electronic device according to claim 6, wherein:
  8. 　前記第１の絶縁層は、前記第２の絶縁層の５倍以上の弾性率を有することを特徴とする請求項６又は７に記載の電子装置。 8. The electronic device according to claim 6, wherein the first insulating layer has an elastic modulus that is five times or more that of the second insulating layer.
  9. 　コア層を形成する工程と、
    　前記コア層を挟持する一対のビルドアップ層を形成する工程と
    　を含み、
    　前記コア層を形成する工程は、
    　配線を内側に有する第１の絶縁層を配する工程と、
    　前記第１の絶縁層の内側に、前記配線を埋め込むように、前記第１の絶縁層よりも弾性率の低い第２の絶縁層を配する工程と
    　を有することを特徴とする回路基板の製造方法。     Forming a core layer;
    Forming a pair of build-up layers sandwiching the core layer,
    The step of forming the core layer includes:
    Disposing a first insulating layer having wiring inside;
    Providing a second insulating layer having a lower elastic modulus than that of the first insulating layer so as to embed the wiring inside the first insulating layer. Method.
  10. 　前記コア層において、前記配線の厚みの合算値と前記第１の絶縁層の厚み及び前記第２の絶縁層の厚みの合算値との比が、７／２２～２／５の範囲内の値であることを特徴とする請求項９に記載の回路基板の製造方法。 In the core layer, the ratio of the sum of the thicknesses of the wirings to the sum of the thicknesses of the first insulating layer and the second insulating layer is within a range of 7/22 to 2/5. The method for manufacturing a circuit board according to claim 9, wherein:
  11. 　前記第１の絶縁層は、前記第２の絶縁層の５倍以上の弾性率を有することを特徴とする請求項９又は１０に記載の回路基板の製造方法。 11. The method for manufacturing a circuit board according to claim 9, wherein the first insulating layer has an elastic modulus that is five times or more that of the second insulating layer.
  12. 　前記第１の絶縁層は、強化繊維ガラス又は強化繊維プラスチック材料を有することを特徴とする請求項９～１１のいずれか１項に記載の回路基板の製造方法。 12. The method for manufacturing a circuit board according to claim 9, wherein the first insulating layer includes a reinforced fiber glass or a reinforced fiber plastic material.
  13. 　前記第２の絶縁層は、等方的な機械物性を有することを特徴とする請求項９～１２のいずれか１項に記載の回路基板の製造方法。 The method of manufacturing a circuit board according to any one of claims 9 to 12, wherein the second insulating layer has isotropic mechanical properties.
PCT/JP2014/050422 2014-01-14 2014-01-14 Circuit board and manufacturing method for same, as well as electronic device WO2015107616A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/050422 WO2015107616A1 (en) 2014-01-14 2014-01-14 Circuit board and manufacturing method for same, as well as electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2014/050422 WO2015107616A1 (en) 2014-01-14 2014-01-14 Circuit board and manufacturing method for same, as well as electronic device

Publications (1)

Publication Number Publication Date
WO2015107616A1 true WO2015107616A1 (en) 2015-07-23

Family

ID=53542541

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/050422 WO2015107616A1 (en) 2014-01-14 2014-01-14 Circuit board and manufacturing method for same, as well as electronic device

Country Status (1)

Country Link
WO (1) WO2015107616A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002111226A (en) * 2000-09-26 2002-04-12 Tdk Corp Composite multilayer board and module using it
WO2004064467A1 (en) * 2003-01-16 2004-07-29 Fujitsu Limited Multilayer wiring board, method for producing the same, and method for producing fiber reinforced resin board
JP2008098599A (en) * 2006-09-13 2008-04-24 Fujitsu Ltd Coreless multilayer printed circuit board and semiconductor device, and method of manufacturing the same
JP2010129942A (en) * 2008-12-01 2010-06-10 Fujitsu Ltd Circuit board and its production process, as well as semiconductor device and its production process

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002111226A (en) * 2000-09-26 2002-04-12 Tdk Corp Composite multilayer board and module using it
WO2004064467A1 (en) * 2003-01-16 2004-07-29 Fujitsu Limited Multilayer wiring board, method for producing the same, and method for producing fiber reinforced resin board
JP2008098599A (en) * 2006-09-13 2008-04-24 Fujitsu Ltd Coreless multilayer printed circuit board and semiconductor device, and method of manufacturing the same
JP2010129942A (en) * 2008-12-01 2010-06-10 Fujitsu Ltd Circuit board and its production process, as well as semiconductor device and its production process

Similar Documents

Publication Publication Date Title
JP6561745B2 (en) Inductor components, package components, and switching regulators
US9331011B2 (en) Electronic component built-in substrate and method of manufacturing the same
US9478343B2 (en) Printed wiring board
US20100224397A1 (en) Wiring board and method for manufacturing the same
US9247646B2 (en) Electronic component built-in substrate and method of manufacturing the same
US8212365B2 (en) Printed wiring board and manufacturing method thereof
US9560770B2 (en) Component built-in board and method of manufacturing the same, and mounting body
JPWO2019130746A1 (en) Semiconductor composite device and package substrate used for it
WO2012098616A1 (en) Wiring substrate having built-in component
JP2015122545A (en) Multilayer wiring board and manufacturing method of the same
US8186042B2 (en) Manufacturing method of a printed board assembly
KR102186148B1 (en) Embedded board and method of manufacturing the same
JP6226168B2 (en) Multilayer wiring board
US9601422B2 (en) Printed wiring board, semiconductor package, and method for manufacturing printed wiring board
JP4954824B2 (en) Wiring board with built-in components, capacitor for wiring board
WO2014162478A1 (en) Component-embedded substrate and manufacturing method for same
JP6742682B2 (en) Multilayer wiring board
US20170006699A1 (en) Multilayer circuit board, semiconductor apparatus, and method of manufacturing multilayer circuit board
JP6423313B2 (en) Electronic component built-in substrate, method for manufacturing the same, and electronic apparatus
KR101167429B1 (en) Method for manufacturing the semiconductor package
JP2013219204A (en) Core board for wiring board manufacturing and wiring board
JP6096538B2 (en) Wiring board, mounting structure using the same, and method of manufacturing wiring board
JP2013183015A (en) Electronic component containing multilayer wiring board and method for manufacturing the same
WO2015107616A1 (en) Circuit board and manufacturing method for same, as well as electronic device
US20150101846A1 (en) Printed circuit board and method of manufacturing the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14878582

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14878582

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP