WO2015092991A1

WO2015092991A1 - Information processing device, method for starting up information processing device, and information processing device startup program product

Info

Publication number: WO2015092991A1
Application number: PCT/JP2014/006001
Authority: WO
Inventors: 徳志高平; 一博高須
Original assignee: 株式会社デンソー
Priority date: 2013-12-20
Filing date: 2014-12-02
Publication date: 2015-06-25
Also published as: JP2015121837A

Abstract

　An information processing device is provided with a plurality of devices (10, 11, 12) connected by a PCI Express (registered trademark) interface, at least one of the plurality of devices (10, 11, 12) continuing, at startup, to execute a recognition process for recognizing a connection-destination device connected to the PCI Express interface until the connection-destination device is recognized. According to this information processing device, even when a PCIe initialization process extends over a long time in a configuration where a plurality of devices are connected by a PCIe, the initialization process can reliably be completed.

Description

Information processing apparatus, information processing apparatus activation method, and information processing apparatus activation program product

Cross-reference of related applications

This disclosure is based on Japanese Patent Application No. 2013-263852 filed on December 20, 2013, the contents of which are incorporated herein.

The present disclosure relates to an information processing apparatus including a plurality of devices connected by a predetermined interface, in particular, a PCI Express (registered trademark) interface, an information processing device activation method, and an information processing device activation program product.

2. Description of the Related Art A plurality of CPUs such as a so-called multiprocessor system, that is, an information processing apparatus including a plurality of devices is known (see, for example, Patent Document 1). In an information processing apparatus including such a plurality of devices, it has been required to perform data communication between the devices efficiently and at high speed. For this reason, in recent years, a PCI Express (registered trademark) interface (hereinafter referred to as PCIe for convenience) is employed to perform data communication between devices at high speed. Here, PCI is an abbreviation for Peripheral Component Component Interconnect.

In the case of PCIe, since the transmission side and the reception side communicate one-to-one, when starting up, that is, when the reset of each device is released, data called a training sequence order set is exchanged between the devices, A processing process called a training sequence for setting an available data rate, a physical polarity of a signal line, the number of lanes to be used, and the like is performed.

By the way, in the PCIe specification, although there are provisions such as the type and meaning of data used in the training sequence and the procedure for exchanging data, there is no restriction on the time required to complete the training sequence. For this reason, as a general method, an upper limit time that is assumed to complete the training sequence is set, and when the upper limit time is exceeded, an error is processed.

However, the information processing apparatus adopting PCIe has a problem that the time required for the training sequence may exceed the above upper limit time depending on the situation, and is processed as an error before the training sequence is completed. .

JP-A-6-332864

The present disclosure has been made in view of the above circumstances, and an object thereof is information that can reliably complete the PCIe initialization process in a configuration in which a plurality of devices are connected by PCIe that is a predetermined interface. The object is to provide a processing apparatus, an information processing apparatus activation method, and an information processing apparatus activation program product.

An information processing apparatus according to the first aspect of the present disclosure includes a plurality of devices connected by a predetermined interface, and at least one of the plurality of devices is connected to the predetermined interface at startup. The recognition process for recognizing the destination device is continued until the connection destination device is recognized.

According to the information processing apparatus described above, in a configuration in which a plurality of apparatuses are connected with a predetermined interface, even if the initialization process of the predetermined interface becomes longer, the initialization process can be completed reliably.

An information processing apparatus activation method for activating an information processing apparatus including a plurality of apparatuses connected by a predetermined interface according to the second aspect of the present disclosure is connected to the predetermined interface when the information processing apparatus is activated. A recognition step for continuously executing the recognition process for recognizing the connected device, until the connected device is recognized.

According to the above activation method, even in a configuration in which a plurality of devices are connected by a predetermined interface, the initialization process can be completed reliably even if the initialization process of the predetermined interface becomes longer.

An information processing apparatus activation program product stored in a computer-readable persistent and tangible storage medium according to a third aspect of the present disclosure activates an information processing apparatus including a plurality of apparatuses connected by a predetermined interface In this case, the connection destination device recognizes a recognition process for recognizing the connection destination device connected to the predetermined interface at the time of activation with respect to at least one of the plurality of devices. Including computer-implemented instructions for continuing execution until executed.

According to the above startup program product, in a configuration in which a plurality of devices are connected by a predetermined interface, the initialization process can be completed reliably even if the initialization process of the predetermined interface is prolonged.

In the above, the predetermined interface is a registered PCI Express interface.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a diagram schematically illustrating an electrical configuration of an information processing apparatus according to an embodiment of the present disclosure. FIG. 2 is a diagram schematically illustrating a normal operation flow in the information processing apparatus according to the embodiment of the present disclosure. FIG. 3A is a diagram schematically illustrating a state in which the recognition process is normally completed in the information processing apparatus according to the conventional technique, and FIG. Is a diagram schematically showing an embodiment, FIG. 4 is a diagram schematically illustrating a flow of initialization processing of the sub-microcomputer that configures the information processing apparatus according to the embodiment of the present disclosure. FIG. 5 is a diagram schematically showing a flow of processing at the time of starting the main microcomputer configuring the information processing apparatus according to the embodiment of the present disclosure. FIG. 6 is a diagram schematically illustrating an operation flow when an error occurs in the recognition process in the information processing apparatus according to the embodiment of the present disclosure. FIG. 7 is a diagram schematically illustrating an example of an electrical configuration of an information processing apparatus according to another embodiment of the present disclosure.

(One embodiment)
Hereinafter, an embodiment of the present disclosure will be described with reference to FIGS. 1 to 6.

As shown in FIG. 1, an information processing apparatus (a navigation ECU 2 described later) of this embodiment is applied to a vehicle system 1 used for a vehicle. The vehicle system 1 is provided with a navigation ECU 2, a battery 3, and another ECU 4. In the vehicle system 1, a navigation ECU 2 (Electronic Control Unit) as an information processing device constitutes a so-called navigation system. The other ECUs 4 may be connected to a plurality of ECUs instead of one.

The navigation ECU 2 has a main microcomputer 10, a sub-microcomputer 11 as a second device, and an IOH 12 (Input （Output Hub) as a third device. The main microcomputer 10 and the IOH 12 are connected to the sub-microcomputer 11 on a one-to-one basis via PCIe bus B1 and bus B2. The descriptions of “main” and “sub” are used for convenience to indicate that there are two microcomputers, and do not indicate a master-slave relationship such as so-called master and slave. Absent.

The main microcomputer 10 of the navigation ECU 2 includes a microcomputer having a CPU, a ROM, a RAM, and the like (not shown). The main microcomputer 10 is connected to a flash memory 13 (shown as “FLASH” in FIG. 1), a reset circuit 14 and the like. In the case of the present embodiment, the main microcomputer 10 performs navigation functions such as map matching and route search. At this time, as will be described in detail later, the main microcomputer 10 first reads and executes the activation program from the flash memory 13 when the reset is released at the time of activation.

The main microcomputer 10 reads map data and the like from an SD card 15 (shown as “built-in SD” in FIG. 1) provided in the IOH 12, and executes a navigation function such as map matching and route search. That is, the main microcomputer 10 executes a data acquisition process for acquiring data used for its own operation from the SD card 15 which is a storage device provided in the IOH corresponding to the connection destination device connected by the PCIe. In addition, the main microcomputer 10 outputs a reset instruction to the reset circuit 14 and executes a reset process for resetting the entire navigation ECU 2 in relation to the present embodiment. Therefore, the main microcomputer 10 and the reset circuit 14 are connected by a signal line R1 for self-reset.

That is, the main microcomputer 10 is a device that executes data acquisition processing and reset processing, and corresponds to a first device that operates using data acquired from the connection destination device side, in this embodiment, the IOH 12 side.

The flash memory 13 is composed of a readable / writable semiconductor memory, and stores data such as Japanese fonts displayed on the navigation screen. A large amount of data that cannot be stored in the flash memory 13 such as the above-described map data is stored in the SD card 15.

The reset circuit 14 has a known power-on reset function such as reset timing control of each device when the power is turned on. The reset circuit 14 also has a function of resetting the entire navigation ECU 2 based on a reset instruction from the main microcomputer 10 as described above.

The sub-microcomputer 11 is configured as a main body that initializes PCIe. That is, in the present embodiment, the sub-microcomputer 11 executes PCIe initialization, that is, recognition processing for recognizing a connection destination device connected to the PCIe. Although details will be described later, the sub-microcomputer 11 executes a PCIe training sequence between the main microcomputer 10 and the IOH 12 corresponding to the connection destination device. That is, the sub-microcomputer 11 is a device that executes recognition processing, and corresponds to a second device connected to the main microcomputer 10 corresponding to the first device via PCIe.

The IOH 12 is a device that provides various input / output interfaces, and in this embodiment, an SD card 15 that is a large-capacity storage medium is provided. That is, the IOH 12 is a storage device that is connected to the sub-microcomputer 11 corresponding to the second device via the PCIe and stores data used in the main microcomputer 10 corresponding to the first device. This corresponds to a third device in which the SD card 15 is provided.

The input / output interface provided in the IOH 12 is not limited to the interface for the SD card 15. For example, it may be an interface for another storage medium such as a CD-ROM, DVD, or CF card, or may be provided with a plurality of interfaces. Further, the SD card 15 may be fixedly provided in the navigation ECU 2 or may be provided detachably. Further, the SD card 15 may be fixedly provided in the navigation ECU 2 and a removable storage medium may be further provided.

Next, the operation of the above configuration will be described.

First, the basic processing flow of the navigation ECU 2 as an information processing apparatus will be described with reference to FIG. In the navigation ECU 2, when the reset state is released, for example, when the power is turned on, initialization is performed in the main microcomputer 10, the sub microcomputer 11, and the IOH 12, respectively. At this time, in the navigation ECU 2, as described above, the sub-microcomputer 11 executes the PCIe training sequence (corresponding to a recognition process described later), that is, initialization of PCIe. If the initialization of PCIe is normally completed, the main microcomputer 10 can access the IOH 12.

Therefore, when the initialization of the main microcomputer 10 is completed, the main microcomputer 10 executes data acquisition processing for acquiring data from the SD card 15 provided in the IOH 12. Specifically, the main microcomputer 10 transmits a data request to the IOH 12 when its initialization is completed. This data request is relayed by the sub-microcomputer 11 and transmitted to the IOH 12. When the IOH 12 receives the data request, the IOH 12 reads corresponding data such as map data from the SD card 15 and transmits the read data to the main microcomputer 10. The data transmitted from the IOH 12 is relayed by the sub microcomputer 11 and acquired by the main microcomputer 10. The process from the transmission of this data request until the corresponding data is acquired corresponds to the data acquisition process.

When the data is acquired, the main microcomputer 10 starts a scheduled operation using the acquired data, that is, an operation for executing the navigation function in the present embodiment. In this way, the navigation ECU 2 realizes a function as a navigation device while each device shares a role. Note that the main microcomputer 10 executes data acquisition processing as needed not only during startup but also during execution of the navigation function.

By the way, in the navigation ECU 2 of the present embodiment, it is assumed that the main microcomputer 10 has already completed the initialization of the PCIe when the initialization of the main microcomputer 10 is completed. This is because the time required for initialization of PCIe is longer than the processing time required for initialization of the main microcomputer 10, that is, the time required for completion of processing such as reading of the Japanese font described above in this embodiment. This is because it is assumed to be completed in a relatively short time. However, if the PCIe initialization is not completed normally, the main microcomputer 10 cannot acquire data from the IOH 12 side.

Here, the flow of the PCIe initialization process in the information processing apparatus having the conventional configuration will be briefly described with reference to FIG. If the reset state is canceled at time t0, the sub-microcomputer 11 executes initialization. This initialization includes initialization of the sub-microcomputer 11 itself and initialization of PCIe, that is, processing for recognizing other devices connected to the PCIe. Since the PCIe initialization process is standardized, detailed description thereof is omitted.

Suppose that the sub-microcomputer 11 starts IOH recognition processing for recognizing the IOH 12 at time t1, for example, after its initialization is completed. At this time, in the conventional information processing apparatus, an upper limit time for IOH recognition processing, that is, an upper limit time for waiting for a response from the IOH 12 is set. FIG. 3 shows a state where the assumed upper limit time (= time t1 + upper limit time) is set at time t2.

Now, the sub-microcomputer 11 executes the above-described training sequence (hereinafter referred to as “TS” for the sake of convenience. In FIG. 3, “TS” is also indicated) in the IOH recognition process. This TS has standardized data types and transmission / reception procedures, but has no time restrictions.

Therefore, as shown as case 1 in FIG. 3A, when TS is completed in a relatively short period, more specifically, TS is completed at time t3 prior to time t2, which is the assumed upper limit time. In this case, the IOH recognition process is completed normally. If the IOH recognition process is normally completed, since the IOH 12 is recognized by the sub-microcomputer 11, the access to the IOH 12 becomes possible thereafter. In other words, the IOH 12 can be accessed from the PCIe side after time t3.

On the other hand, as shown as case 2 in FIG. 3B, when the TS becomes relatively long for some reason, more specifically, even if the TS exceeds the time t2 that is the assumed upper limit time, the process is completed. If not, an error occurs in the IOH recognition process in the information processing apparatus having the conventional configuration. In this case, since the IOH recognition processing has not been completed, the IOH 12 cannot be recognized by the sub-microcomputer 11, and thereafter, access to the IOH 12 becomes impossible. In other words, the IOH 12 that has not been recognized by the time t2 cannot be accessed from the PCIe side thereafter. Since the data cannot be acquired from the IOH 12 side, the main microcomputer 10 cannot execute the scheduled operation.

As described above, if there is a time restriction on the recognition process for recognizing PCIe, there is a possibility that a device connected to the PCIe cannot be recognized if the TS becomes long term for some reason. On the other hand, in the PCIe where the upper limit time of the TS is not defined, even if the TS becomes long as described above, it is not classified as a failure. In this case, it is assumed that if the upper limit time can be set so that all the assumed conditions can be cleared, it becomes possible to prevent the IOH 12 from being unrecognizable. However, in the case of an information processing apparatus used for a vehicle such as the navigation ECU 2 of the present embodiment, as shown in FIG. 1, the battery 3 is connected to another EUC 4 or the like, the number of ECUs 4 or the like, Since power consumption varies depending on the vehicle model, and there are too many assumed situations such as the lighting conditions of room lights and headlamps and the consumption state of the battery 3 even in the same vehicle model, all conditions must be set in advance. It is almost impossible to cover it.

Therefore, in the navigation ECU 2 of the present embodiment, the PCIe initialization process performed by the sub-microcomputer 11 can be surely completed as described below.

As shown in FIG. 4, the sub-microcomputer 11 performs initialization of the built-in circuit and the like in the initialization process after the reset state is released (S21). Subsequently, the sub-microcomputer 11 executes a recognition process for recognizing the connection destination device (recognition process). This recognition process is one of the initialization processes of PCIe. At this time, the sub-microcomputer 11 determines whether or not the device can be recognized (S22). If the device cannot be recognized (S22: NO), the recognition processing is continued until it can be recognized. That is, the sub-microcomputer 11 waits for completion of the TS until it can recognize a device connected to the PCIe, for example, the IOH 12. As a result, even if the TS becomes longer for some reason, it is possible to wait for the completed TS. On the other hand, if the sub-microcomputer 11 can recognize the device (S22: YES), the initialization process ends.

In this way, by waiting for the completion of TS at the initialization of the sub-microcomputer 11, in other words, by continuing to execute the recognition process without providing time constraints such as the assumed upper limit time, it is connected to PCIe. Can be reliably recognized. TS is a process performed individually for each device connected to the PCIe. Therefore, the sub-microcomputer 11 similarly waits for the completion of the TS without providing time restrictions even when the device to be recognized is the main microcomputer 10.

Now, by eliminating the time restriction as described above, it becomes possible to cope with the inability to recognize the device due to the delay of TS (longer period). On the other hand, it is also necessary to cope with the inability to recognize the device for other reasons that do not depend on the PCIe specification, such as physical damage. In particular, in the case of an information processing device used in a vehicle, it is not preferable that the operation remains unstable just because the device has no direct troubles such as the navigation ECU 2 of the present embodiment.

Therefore, the navigation ECU 2 takes further measures to prevent the device from being recognized. This countermeasure is performed not by the sub-microcomputer 11 but by the main microcomputer 10. That is, in the navigation ECU 2, a device (main microcomputer 10) different from the device that initializes PCIe (sub-microcomputer 11) is used to deal with the inability to recognize the device for other reasons that do not depend on the PCIe specification. Hereinafter, a description will be given with reference to FIGS. 5 and 6.

As shown in FIG. 5, the main microcomputer 10 performs its own initialization in the process at the start-up after the reset state is released (S1). In the initialization of step S1, after initializing the built-in circuit and the like, the preparation process for performing the scheduled operation such as the above-described Japanese font reading process is performed. For this reason, in the case of the main microcomputer 10, the time required for the initialization to be completed after the reset state is disclosed, that is, the time required for completing Step S1 is about several seconds. In general devices, it is often assumed that the time required to complete the TS is approximately several milliseconds to several tens of milliseconds. The time required for this is considered to be sufficiently long.

When the initialization is completed, the main microcomputer 10 executes the data acquisition process described above (S2). Subsequently, the main microcomputer 10 determines whether data has been acquired (S3). At this time, if the data can be acquired (S3: YES), the main microcomputer 10 starts the scheduled operation using the acquired data (S4). This flow is the same as the sequence of FIG.

On the other hand, if the sub-microcomputer 11 cannot recognize the apparatus in the initialization process shown in FIG. 4, for example, if the sub-microcomputer 11 cannot recognize the IOH 12 as shown in FIG. Cannot get data from.

Therefore, if the main microcomputer 10 cannot acquire data in the startup process shown in FIG. 5 (S3: NO), the main microcomputer 10 stores the number of trials of the data acquisition process (S5), and the number of trials is three. It is determined whether it has been exceeded (S6). That is, in the present embodiment, the main microcomputer 10 repeats the data acquisition process with the retry upper limit number of times set in advance as three as the upper limit. That is, the data acquisition process is retried. At this time, if the number of trials does not exceed 3 (S6: NO), the main microcomputer 10 proceeds to step S2 and reattempts data acquisition. Hereinafter, the process of repeating the data acquisition process is referred to as a data reacquisition process for convenience.

On the other hand, if the main microcomputer 10 cannot acquire data even after repeating the data acquisition process three times as shown in FIG. 6, the number of trials of the data acquisition process is three in the start-up process shown in FIG. (S3: NO, and S5, S6: YES), the number of reset processing trials is stored (S7), and it is determined whether the number of reset processing trials exceeds five (S8). Here, the reset process is to reset (restart) the entire navigation ECU 2 including the sub-microcomputer 11 and the IOH 12 by outputting a reset instruction from the main microcomputer 10 to the reset circuit 14 via the signal line R1 for self-reset. ).

The main microcomputer 10 executes the reset process (S10) if the reset process has not been attempted more than 5 times (S8: NO). When this reset process is executed, the main microcomputer 10 is in the same state as when the power is turned on, and therefore, the startup process is executed from the initialization in step S1. In FIG. 5, for simplification of description, the transition destination after the reset process is executed in step S <b> 10 is set as step S <b> 1.

That is, the main microcomputer 10 repeats the reset process for resetting the entire navigation ECU 2 with the upper limit number of resets set in advance as five as the upper limit in this embodiment. Note that the number of reset processing trials is stored in the flash memory 13 so that the number of trials is not cleared at the time of resetting.

When the reset process is executed, the main microcomputer 10 initializes itself (S1) and executes a data acquisition process (S2) to determine whether data has been acquired (S3). If data cannot be acquired even after resetting the entire navigation ECU 2 (S3: NO), the number of trials of the data acquisition process is stored again (S5), and the number of trials of the data acquisition process has exceeded three times. Is determined (S6). Note that the number of trials of the data acquisition process is initialized to zero at the time of reset.

Then, as shown in FIG. 6, when the main microcomputer 10 cannot acquire data in the data reacquisition process after executing the first reset process, the main microcomputer 10 performs the data acquisition process in the startup process of FIG. Since the number of trials in step S3 has exceeded three (S6: YES), the number of trials for reset processing is memorized again (S7), and since the number of trials for reset processing is second (S8: NO), reset again. The process is executed (S10). Thereafter, the main microcomputer 10 executes a third startup process.

Now, such a system reset is repeated, and as shown in FIG. 6, when data cannot be acquired even in the data reacquisition process after the fifth reset process is executed, the main microcomputer 10 An error is reported. That is, the main microcomputer 10 reports an error (S9) because the number of trials of the reset process exceeds 5 in the startup process shown in FIG. 5 (S8: YES). This error notification corresponds to notification processing. In the case of the navigation ECU 2 as in this embodiment, an output device such as a display or a speaker (not shown) is provided. Therefore, for example, the main microcomputer 10 uses the display device as a notification device to notify the user of the occurrence of a failure by a message such as “data could not be read”.

As described above, the navigation ECU 2 can cope with both of the unrecognizable device due to the prolonged TS according to the PCIe specification and the unrecognizable device that seems to be due to other reasons. It is like that.

According to this embodiment described above, the following effects can be obtained.

The navigation ECU 2, which is an information processing apparatus according to an embodiment, includes a main microcomputer 10, a sub microcomputer 11, and an IOH 12, which are a plurality of devices connected by PCIe. Then, the sub-microcomputer 11 which is at least one of these devices performs a recognition process for recognizing the main microcomputer 10 and the IOH 12 corresponding to the connection-destination device connected to the PCIe at the time of activation. The execution continues until the main microcomputer 10 and the IOH 12 which are the devices are recognized. As a result, in a configuration in which a plurality of devices are connected by PCIe, the TS can be reliably completed even if the TS becomes longer in the PCIe initialization process. That is, the navigation ECU 2 can reliably recognize the connected device and can reliably perform the expected scheduled operation.

The navigation ECU 2 is a connection destination connected by PCIe at the time of activation in the sub microcomputer 11 that is at least one of the main microcomputer 10, the sub microcomputer 11, and the IOH 12 that constitute the navigation ECU 2. The activation method includes a recognition process that continues to execute recognition processing for recognizing the main microcomputer 10 and the IOH 12 until the connection destination device is recognized. As a result, as described above, the navigation ECU 2 can reliably complete the TS even if the TS becomes longer in the PCIe initialization process.

In addition, the navigation ECU 2 is connected to the sub microcomputer 11 that is at least one of the main microcomputer 10, the sub microcomputer 11, and the IOH 12, which are a plurality of devices constituting the navigation ECU 2, at the time of start-up. A startup program is used that continues to execute recognition processing for recognizing the main microcomputer 10 and IOH 12 that are the previous devices until the connected device is recognized. Thereby, similarly to the above-described activation method, the navigation ECU 2 can reliably complete the TS even if the TS becomes longer in the PCIe initialization process.

The activation program for activating the navigation ECU 2 includes instructions executed by a computer as a program product, and is stored in a computer-readable persistent and tangible storage medium, for example, the flash memory 13.

The navigation ECU 2 acquires data from the IOH 12 side, which is a connection destination device recognized by the recognition process, in the main microcomputer 10 that is at least one of the main microcomputer 10, the sub microcomputer 11, and the IOH 12. When the main microcomputer 10 that is a device that executes the data acquisition process and that executes the data acquisition process fails to acquire data from the IOH 12 side that is the connection destination device even if the data acquisition process is executed, The data acquisition process is repeated with a predetermined retry upper limit count (three times in the present embodiment) as the upper limit. Thereby, for example, it is possible to deal with an accidental or instantaneous unreadable state due to noise or the like.

If the main microcomputer 10 that is a device that executes the data acquisition process fails to acquire data from the IOH 12 that is the connection destination device even if the data acquisition process is repeated for the retry upper limit number of times, a predetermined reset upper limit is set. The reset process for resetting the entire navigation ECU 2 as the information processing apparatus is repeated with the number of times (5 times in the present embodiment) as an upper limit. As a result, the possibility of continuing to operate in an unstable state can be eliminated, which is particularly suitable for a vehicle information processing apparatus.

If the main microcomputer 10 that is a device that executes the data acquisition process cannot acquire data from the IOH 12 that is the connection destination device even if the reset process is repeated as many times as the reset upper limit, the main ECU 10 has an error in the navigation ECU 2 that is the information processing device. A notification process for notifying that the occurrence has occurred is executed. As a result, it is possible to deal with failures and the like, and it is possible to provide a highly reliable information processing apparatus.

The navigation ECU 2 is assigned functions in a plurality of main microcomputer 10, sub-microcomputer 11, and IOH 12. Specifically, the main microcomputer 10 corresponds to a first device, and is a device that executes data acquisition processing and reset processing, and operates using data acquired from the IOH 12 side that is a connection destination device. The sub-microcomputer 11 corresponds to a second device, and is a device that executes a recognition process, and is connected to the main microcomputer 10 and the IOH 12 via PCIe. The IOH 12 corresponds to a third device and is a device corresponding to a connection destination device. The IOH 12 is connected to the sub-microcomputer 11 via PCIe and stores data used by the main microcomputer 10. An SD card 15 as a storage device is provided. If the main microcomputer 10 cannot acquire data from the SD card 15 provided in the IOH 12 even after executing the data acquisition process, the main microcomputer 10 sets the retry upper limit number of times to a predetermined number. Repeat as. If the main microcomputer 10 cannot acquire data from the SD card 15 even after executing the reset process, the main microcomputer 10 repeats the reset process with the preset upper limit number of times as the upper limit.

In this way, by adopting a configuration in which the device that initializes PCIe and performs the recognition process (sub-microcomputer 11) and the device that executes the data acquisition process and the reset process (main microcomputer 10) are separated from each other. The ECU 2 can be made redundant. That is, a device (sub-microcomputer 11) that manages PCIe, which is a data transmission / reception path, and a device (main microcomputer 10) that determines whether or not the device is normal based on whether or not data transmission / reception is possible. ) Can be determined at a plurality of locations as to whether or not the navigation ECU 2 is operating normally as a whole. Therefore, the reliability as the information processing apparatus can be improved.

(Other embodiments)
The present disclosure is not limited to the one exemplified in the above-described embodiment, and can be arbitrarily modified or expanded or combined with those exemplified below without departing from the scope of the present disclosure.

For example, a configuration in which a microcomputer 21 is further connected to the sub-microcomputer 11 via a PCIe bus B3, such as an ECU 20 that is an information processing apparatus shown in FIG. That is, four or more devices may be included in the information processing device. In this case, the data acquisition process may be executed by the microcomputer 21 and the reset process may be executed when the data cannot be acquired. In that case, in order to avoid the reset instruction being output from a plurality of locations, the main microcomputer 10 and the microcomputer 21 are connected by the signal line R2, an error on the microcomputer 21 side is notified to the main microcomputer 10 side, and the reset instruction is You may make it output from the main microcomputer 10. FIG.

Although not shown, the information processing apparatus may be composed of two devices, the sub-microcomputer 11 and the IOH 12. In this case, the data acquisition process may be performed by the sub-microcomputer 11, or the reset process may be performed on condition that no data request comes after activation by the IOH 12.

In one embodiment, the navigation ECU 2 is exemplified as the information processing device, but the information processing device may be another ECU or a device that is not for a vehicle. That is, the present disclosure can be applied to any configuration as long as a plurality of devices are connected by PCIe. Of course, the present invention can also be applied to an information processing apparatus in which apparatuses are connected by a cable instead of printed wiring.

In one embodiment, an example in which data is acquired from the SD card 15 provided in the IOH 12 has been described. However, for example, the present disclosure can be applied to a configuration in which a storage device is provided in the sub-microcomputer 11 and data is acquired from the storage device. Can be applied.

In the embodiment, the configuration in which the recognition process is executed by the sub-microcomputer 11 and the reset process is executed by the main microcomputer 10 is exemplified, but the present invention is not limited to this. For example, a dedicated device connected to each device and in charge of the reset process may be provided.

All the numerical values and the like shown in the embodiment are examples and are not limited thereto. For example, for a retry (data reacquisition process) that is assumed to have a relatively short overall processing time, it is assumed that the retry upper limit number is set to 5 or the like, or the entire processing time is relatively long. The reset process can be changed as appropriate, for example, by setting the reset upper limit number of times to three.

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

A plurality of devices (10, 11, 12) connected by a predetermined interface;
At least one of the plurality of devices (10, 11, 12) performs a recognition process for recognizing a connection destination device connected to the predetermined interface at the time of activation. An information processing device that continues to run until it is recognized.
2. The information processing apparatus according to claim 1, wherein the predetermined interface is a registered PCI Express interface.
At least one of the plurality of devices (10, 11, 12) is a device that executes data acquisition processing for acquiring data from the connection destination device recognized by the recognition processing,
If the device that executes the data acquisition process fails to acquire data from the connection destination device even if the data acquisition process is executed, the data acquisition process is performed with a predetermined retry upper limit count as an upper limit. The information processing apparatus according to claim 2, which is repeated.
The devices (10, 11, 12) that execute the data acquisition process are reset in advance when data cannot be acquired from the connection destination device even if the data acquisition processing is repeated for the retry upper limit count. The information processing apparatus according to claim 3, wherein a reset process for resetting the entire information processing apparatus (2) is repeated with the upper limit number as an upper limit.
When the device (10, 11, 12) that executes the data acquisition process cannot acquire data from the connection destination device even after repeating the reset process for the reset upper limit number of times, the information processing device (2) The information processing apparatus according to claim 4, wherein notification processing for notifying that an abnormality has occurred is executed.
The plurality of devices (10, 11, 12) are:
A device that executes the data acquisition process and the reset process, the first device (10) operating using data acquired from the connection destination device;
A device that executes the recognition process, the second device (11) connected to the first device via the predetermined interface;
A storage device (equivalent to the connection destination device) connected to the second device via the predetermined interface and storing data used in the first device ( A third device (12) provided with 15),
If the first device (10) fails to acquire data from the storage device (15) provided in the third device (12) even after executing the data acquisition process, When the data acquisition process is repeated with the predetermined retry upper limit number as an upper limit, and the data cannot be acquired from the storage device (15) even if the reset process is executed, the reset process is determined in advance. The information processing apparatus according to claim 5, wherein the reset upper limit count is repeated as an upper limit.
A method for starting an information processing device (2) when starting an information processing device including a plurality of devices (10, 11, 12) connected by a predetermined interface,
When the information processing apparatus (2) is activated, a recognition process for recognizing a connection destination apparatus (10, 11, 12) connected to the predetermined interface is performed. 12) A method for starting up an information processing apparatus including a recognition step that continues to be executed until it is recognized.
The information processing apparatus activation method according to claim 7, wherein the predetermined interface is a registered PCI Express interface.
When starting the information processing apparatus (2) including a plurality of apparatuses (10, 11, 12) connected by a predetermined interface,
At least one device among the plurality of devices (10, 11, 12) is subjected to a recognition process for recognizing a connection destination device connected to the predetermined interface at the time of activation. An activation program product for an information processing device (2) that is stored on a computer-readable persistent and tangible storage medium that includes instructions implemented by a computer to continue execution until the device is recognized.
10. The information processing apparatus (2) activation program product according to claim 9, wherein the predetermined interface is a PCI Express interface which is a registered trademark.