WO2015089970A1

WO2015089970A1 - Ramp signal generation circuit and operation method therefor, ramp signal generator, array substrate and display device

Info

Publication number: WO2015089970A1
Application number: PCT/CN2014/076268
Authority: WO
Inventors: 王俪蓉; 段立业; 吴仲远
Original assignee: 京东方科技集团股份有限公司
Priority date: 2013-12-19
Filing date: 2014-04-25
Publication date: 2015-06-25
Also published as: CN103714773A; CN103714773B

Abstract

A ramp signal generation circuit and a signal generator, an array substrate and a display device. The ramp signal generation circuit comprises: a voltage reducing unit (13) which is connected to a power source input end (Vref) and a grounding end, respectively; a first shift register (11) which is connected to the voltage reducing unit (13) and used for controlling the voltage reducing unit (13) to stepwise and continuously reduce voltages input by the power source input end (Vref); a collection unit (14) which is provided with an output end (Vo) and is connected to the voltage reducing unit (13); and a second shift register (12) which is connected to the collection unit (14) and used for controlling the collection unit (14) to collect and output the continuously changed voltages output by the voltage reducing unit (13). Such a ramp signal generation circuit can reduce the area of a ramp signal generation circuit, thereby improving the degree of linearity of a ramp signal.

Description

Substrate and display device

Embodiments of the present invention relate to the field of electronic technologies, and in particular, to a ramp signal generating circuit and an operating method thereof, a ramp signal generator, an array substrate, and a display device.

With the continuous development of electronic technology, people not only have strict demands on the appearance and quality of electronic products, but also pay more attention to the price and practicality of products.

In order to meet the needs of the public, SOG (System on Glass) technology has been widely used in existing electronic products. SOG refers to the integration of the drive and system circuitry on the substrate. The emergence of this technology has greatly facilitated the production and design of products. Developers only need to simulate the TFT-based system circuit and implement it through a certain process, which greatly reduces the production cost of electronic products. In addition, the product can be further miniaturized with a highly integrated circuit design.

Especially for the display panel, SOG can effectively include the Gate Driver, the Data Driver, the Multiplexer (Mux), the DC Power Converter (DC DC), and the Digital-to-Analog Converter (DAC). The drive system of the module such as the sequence controller (TCON) is integrated on the glass substrate. This greatly reduces the cost while minimizing the screen bezel and solving the problem of IR Drop, noise, and reliability due to interconnecting different driver ICs. In order to achieve more system functions, SOG technology is moving toward more highly integrated and miniaturized, and the trend of developing low-cost, energy-saving, lightweight, and thin displays has become overwhelming. SOG technology is an inevitable trend in the development of system circuits.

In the existing display panel, the array substrate usually includes a plurality of modules including a digital-to-analog-to-digital converter and the like that need to be driven by a ramp signal. The existing SOG technology is still difficult to effectively integrate the ramp signal generator, and the additional ramp signal generator will greatly increase the area of the drive circuit, which limits the further miniaturization of the display device. On the other hand, the existing ramp signal generator is difficult to effectively generate a ramp signal output with good linearity, which will greatly limit the quality of the display device product. (1) Technical problems to be solved

Embodiments of the present invention provide a ramp signal generating circuit and an operating method thereof, a ramp signal generator, an array substrate, and a display device, which can reduce the occupied area/space of the ramp signal generating circuit and improve the linearity of the ramp signal.

(ii) Technical solutions

In order to solve the above technical problem, the embodiments of the present invention provide the following technical solutions:

An aspect of an embodiment of the present invention provides a ramp signal generating circuit, including: a voltage drop unit connected to a power input end and a ground end, respectively; a first shift register connected to the voltage drop unit, Controlling, by the voltage drop unit, a voltage continuous reduction of a voltage input to the power input terminal; an acquisition unit having an output, wherein the acquisition unit is connected to the voltage drop unit; and a second And a shift register connected to the collecting unit, configured to control the collecting unit to collect and output a continuously varying voltage output by the voltage drop unit.

In another aspect, embodiments of the present invention also provide a ramp signal generator comprising at least the ramp signal generating circuit as described above for use as a signal source, either alone or in combination with other electronic devices.

In addition, an embodiment of the present invention further provides an array substrate including at least a ramp signal generating circuit as described above to implement driving of the array substrate.

The embodiment of the invention further provides a display device comprising at least the array substrate as described above. The embodiment of the present invention also provides an operation method of a ramp signal generating circuit including any one of the ramp signal generating circuits as described above. The operating method includes: controlling the voltage drop unit to perform step-by-step continuous voltage reduction on a voltage input to the power input terminal; and controlling the acquisition unit to continuously output a voltage to the voltage drop unit Collect and output.

(3) Beneficial effects

The embodiments of the present invention have at least the following beneficial effects:

The ramp signal generating circuit and the operating method thereof, the ramp signal generator, the array substrate and the display device provided by the embodiment of the invention adopt the design of two shift register units, a voltage drop unit and an acquisition unit. Through different timing signal design, the two shift register units respectively drive the voltage drop unit and the acquisition unit, and realize that the first shift register controls the voltage drop unit to successively reduce the voltage input to the power input terminal step by step, and simultaneously The second shift register controls the acquisition unit pair The continuously varying voltage output from the voltage drop unit is collected and output. Such a structure of the ramp signal generating circuit has fewer constituent units and a high degree of circuit integration. Thereby, the occupied area/space of the ramp signal generating circuit can be effectively reduced. In addition, the ramp signal generating circuit of such a structure has a higher sampling frequency than the prior art, so that the linearity of the ramp signal can be effectively improved.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and those skilled in the art can obtain other drawings according to these drawings without any creative work.

1 is a block diagram showing the structure of a ramp signal generating circuit according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a circuit connecting structure of a ramp signal generating circuit according to an embodiment of the present invention; Schematic diagram of signal timing when the transistor is used; FIG. 4 is a simulation waveform diagram of the output signal of the ramp signal generating circuit shown in FIG. 2;

5 is a circuit diagram showing a circuit connection structure of another ramp signal generating circuit according to an embodiment of the present invention; FIG. 6 is a simulation waveform diagram of an output signal of the ramp signal generating circuit shown in FIG.

FIG. 7 is a schematic diagram of a circuit connection structure of another ramp signal generating circuit according to an embodiment of the present invention; FIG.

FIG. 8 is a schematic diagram of a circuit connection structure of still another ramp signal generating circuit according to an embodiment of the present invention; and

Fig. 9 is a timing chart showing the timing of a P-type transistor in the ramp signal generating circuit.

The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings and embodiments. The following examples are merely illustrative of the invention, but are not intended to limit the scope of the invention.

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the drawings of the embodiments of the present invention. Obviously, The described embodiments are a part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the present invention are not intended to indicate any order, quantity or importance, but merely to distinguish different components. Similarly, the words "a" or "an" do not mean a quantity limitation, but rather mean that there is at least one. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship ffi is changed accordingly.

The principles and features of the embodiments of the present invention are described below with reference to the accompanying drawings, which are used to illustrate the embodiments of the present invention.

The pixel circuit provided by the embodiment of the present invention, as shown in FIG. 1 , includes:

The first shift register 1 1, the second shift register 12, the voltage drop unit 13, and the acquisition unit 14. The voltage drop unit 13 is respectively connected to the power input terminal Vref and the ground terminal.

The first shift register 1 1 is connected to the voltage drop unit 13 for controlling the voltage drop unit 13 to successively lower the voltage input from the power input terminal Vref.

The acquisition unit 14 has an output Vo and the acquisition unit 14 is connected to the pressure drop unit 13.

The second shift register 12 is connected to the acquisition unit 14 for controlling the acquisition unit 14 to collect and output the continuously varying voltage output from the voltage drop unit 13.

According to the ramp signal generating circuit provided by the embodiment of the invention, two shift register units, a voltage drop unit and a design of the acquisition unit are employed. Through different timing signal design, the two shift register units respectively drive the voltage drop unit and the acquisition unit, and realize that the first shift register controls the voltage drop unit to successively reduce the voltage input to the power input terminal step by step, and simultaneously The second shift register controls the acquisition unit to collect and output a continuously varying voltage outputted by the voltage drop unit. Such a structure of the ramp signal generating circuit has fewer components and a high degree of circuit integration, and can effectively reduce the area/space occupied by the ramp signal generating circuit. In addition, compared with the prior art, the ramp signal generating circuit of such a structure has a higher sampling frequency, thereby effectively improving the line of the ramp signal. Sexuality.

Among them, the voltage drop unit 13 can employ various known circuit structures or electronic devices capable of achieving a gradual decrease in the input voltage. This embodiment of the present invention does not limit this.

Specifically, as shown in FIG. 2, the voltage drop unit 3 includes: a plurality of first crystal tubes M1, M2. . . . . Mn arranged in a matrix form. Hereinafter, if it is not necessary to distinguish these first transistors, the reference symbol M is used to indicate any one of the plurality of first transistors.

The gates of the first transistors M located in the same row are connected to one output terminal of the first shift register 11.

The first poles of the first transistor M in the same column are all connected to one input of the acquisition unit 14.

The second poles of the first transistors M in the same row are connected in series. And as shown in Fig. 2, except for the first row and the last row, the second pole of the first transistor M located in the last column of any row is in series with the second pole of the first transistor M of the first column of the next row.

In the first transistor M connected in series, a step-down resistor R1, R2. . . . . Rn is connected in series between the second poles of any two adjacent first transistors M. In the following, if it is not necessary to distinguish these buck resistors, the risk map R is used to indicate any of these buck resistors.

Further, as shown in FIG. 2, the acquisition unit 14 specifically includes a plurality of second transistors Ti, T2, . Hereinafter, if it is not necessary to distinguish these second transistors, the reference symbol T is used to indicate any one of the plurality of second transistors.

The gates of the second transistor T are respectively connected to different outputs of the second shift register 12, and the first poles of the second transistor T are connected to the output terminal Vo of the acquisition unit 14.

The second pole of each of the second transistors T is connected to the first pole of the first transistor M in the same column.

Further, in the ramp signal generating circuit shown in FIG. 2, the input end of the first shift register 11 can be connected to the first clock signal CLK1, the second clock signal CLKB i and the first mechanical start signal STV1, respectively. It is used to turn on the first transistor M row by row.

The input end of the second shift register 12 may be connected to the third clock signal CLK2, the fourth clock signal CLKB2 and the second frame start signal STV2, respectively, for controlling the acquisition unit 14 to be column by column during a turn-on period of the first transistor M. The voltage of the first pole of each of the first transistors M is collected. In the embodiment of the present invention, the first and second shift registers may be specifically GOA (Gate Driver on Array) circuits. The GOA circuit is a cascade shift register that receives the frame start signal STV of the originating input, and usually controls the GOA internal circuit TFT (Thin Film Transistor, thin film field effect transistor) by two clock signals (CL:, CLKB). On or off, the input signal is transmitted one level after another (step by step), wherein the CLKB signal controls the output of each stage.

It should be noted that, in the embodiment of the present invention, the first transistor M and the second transistor T may both be N-type transistors. When the first transistor M and the second transistor T are both N-type transistors, the first electrode of the transistor may be the source and the second electrode may be the drain.

The transistors employed in all embodiments of the present invention may each be a thin film transistor or a field effect transistor or other device having the same characteristics. Since the source and drain of the transistor used here are symmetrical, the source and drain are not required to be distinguished. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. In addition, according to the characteristics of the transistor, the transistor can be divided into an N-type and a P-type. The following embodiments are described with an N-type transistor as the inside. It is conceivable that those skilled in the art can implement it without using a P-type transistor. It is easily conceivable under the premise of making creative work, and thus is also within the scope of the embodiments of the present invention.

As can be seen in the ramp signal generating circuit shown in Fig. 2, the voltage drop unit 13 can be composed of a line II circuit. Each row of circuits includes n resistors and n TFT tubes M in series. The gate of the TFT tube M is connected to the output signal of the external GOA1 circuit. A drain of a TFT tube M is connected between every two resistors. The source of the same column TFT tube M is short-circuited and connected to the drain of the TFT tube T. The gate of the TFT tube T is connected to the output signal of the GOA2 circuit. The source of the TFT tube T is connected to the output terminal Vo.

A ramp signal generating circuit employing such a structure is used to generate a ramp signal. The timing of the drive signal can be as shown in Figure 3. The process of generating the ramp signal may specifically include two steps of transmitting the signal and acquiring the signal. The specific description is as follows:

Passing the signal: The input signal is input from the DC signal Vref from the resistor R1 at the first row. As shown in FIG. 3, the GOA1 circuit is controlled by clock signals CLKi, CLKB1. Where CLK1 is opposite to CLKB1. The first line of the GOA1 circuit first gives the output signal VoR1 to the TFTs M1 to Mn of the first row, turning on the TFTs of this row. The clock cycle of GOA1 is n times the GOA2 clock cycle. Thus, when the first row of TFTs M is turned on by GOA1, it is controlled by CLK2 and CLKB2. The GOA2 circuit turns on the ΤΊ~Τη tube in turn. Where CLK2 is opposite to CLKB2. Since the respective resistors and TFT tubes are the same, the voltage signals will be sequentially lowered. When the first line scan ends, the GOA1 circuit outputs an R2 signal for the second row of TFT transistors, and turns on the second row of TFT tubes M. The resistor Rn of the first row transmits the voltage signal to the electric ffi R1 of the second row, and the TFT A of the second row is opened, and the GOA2 circuit turns on the 'Π~Τn tube in turn. In this way, the signals are transmitted line by line (row by line) to the nth row until the end of the resistance Ri of the nth row is grounded.

It should be noted that, in the embodiment of the present invention, the clock period of the GOA circuit specifically refers to the length of time for continuously outputting a high level or a low level. The clock period of GOA1 is η times the clock period of GOA2. It can be understood that the length of time that GOA1 continuously outputs a high level is n times the length of time that GOA2 continues to output a high level. That is, in the length of time that GOA1 continuously outputs a high level to one row or one column, GOA2 can finish outputting a high level sequentially for n rows or n columns.

Acquire the signal: When the resistor R Rn and the TFT tube Μί'- in the first row, the GOA2 turns on the TFTs Τ1~Τη. The drain of the manifold is connected to the source of the manifold of each column, and the source of the manifold is connected to the output signal o. Thus Vo collects the ramp voltage signal that decreases linearly in the first row in chronological order. When the resistors R1 to Rn of the second row and the TFT tubes M1 to Mn are operated, the GOA2 sequentially turns on the TFT tubes T1 to Tr! Turn on and continue to collect the ramp voltage signal that is linearly falling in the second line. Until the ramp down signal of line 11 is taken to 0, the acquisition of a falling ramp signal is completed. This allows cyclic acquisition of the ramp signal.

The signal simulation of the output signal Vo of such a ramp signal generating circuit can be as shown in FIG. As can be seen from Figure 4, the output VoR1 of the first row of GOA1 completes a complete ramp signal acquisition between two high levels, a complete one frame scan period. GOA2's output signal VoCl~3⁄4Qi completes a scan in sequence at the first high level of \3⁄4R1. And when VoR2 comes, VoCi VoCri performs a second scan until one frame scan period is over. The signal simulation diagram shows that the ramp signal generating circuit provided by the embodiment of the present invention can generate a falling ramp waveform with good linearity.

It should be noted that the transistor M column in the embodiment of the present invention can select the number of rows and columns of the array according to actual conditions. It should be easily conceivable that when the number of rows and columns of the transistor M is increased, by increasing the scanning output terminal of the GOA circuit, the sampling frequency for the voltage signal can be further improved, so that the linearity of the ramp signal can be further improved. In the above embodiment, the drain of the first transistor M1 located in the first column of the first row is connected with the power input terminal Vref, and the drain of the first transistor Tn located at the last column of the last row is connected to the ground. instruction of.

Among them, the step-down resistor R can be made of a conductive material such as tantalum. The jumper connection between every two rows can be made of a metallic conductive material. Although the resistance of the metal is small, there is a certain jumper resistance. In order to obtain a ramp signal having a good linearity, in the embodiment of the present invention, the resistance of the adjacent two rows of step-down resistors R can be reduced by the jumper resistance equivalent from the first row to the last row. This results in a lower linearity ramp signal. In the actual application process, the value of the resistance reduction of the adjacent two rows of the step-down resistor R can be obtained by corresponding calculation according to the panel process of the actual application.

For example, the sheet resistance Rs of the metal conductive material can be found according to the process data, and the number of squares N=L/W is determined according to the length (L) and width (W) of the wire, then N*Rs is the connection of the two resistors. The value of the jumper resistance between the jumpers. In the embodiment of the present invention, from the first row to the last row, the resistance values of the two adjacent rows of step-down resistors R can be sequentially decreased by N*Rs. In this way, the influence of the voltage across the line on the voltage drop can be effectively overcome, and a falling linear signal with higher linearity can be formed.

Alternatively, the power input terminal Vref may also be connected to the drain of the first transistor M located in the last column of the last row, and the drain of the first transistor located in the first column of the first row may also be connected to the ground.

Specifically, as shown in FIG. 5, the input terminal of R1 in the first row is grounded, and the output terminal of Rii in the nth row is connected to the DC input signal Vref. Such a structured ramp signal generating circuit can form a rising ramp waveform signal. The drive signal can also be used. 3⁄4 The signal shown in Figure 3, the work process can also be divided into two processes of transmitting signals and acquiring signals. The working principle is similar to the falling ramp signal generating circuit shown in Figure 2, except that the voltage is rising.

The signal simulation of the output signal of such a ramp signal generating circuit can be as shown in Fig. 6. From the simulation results, the output VoR1 in the first line of GOAi completes the acquisition of a complete rising ramp signal between two high levels. The signal simulation diagram shows that the ramp signal generating circuit provided by the embodiment of the present invention can generate a rising ramp waveform with good linearity.

Similar to the falling ramp signal generating circuit shown in FIG. 2, in the ramp signal generating circuit shown in FIG. 5, the step-down resistor R can be made of a conductive material such as ITO. The jumper connection between every two rows can be made of a metallic conductive material. Although the resistance of the metal is small, there will be some cross Wiring electricity ffi. In order to obtain a ramp signal having a good linearity, in the embodiment of the present invention, the resistance of the adjacent two rows of step-down resistors R can be increased by the equivalent value of the jumper resistance from the first row to the last row, so that linearity can be formed. Higher rising ramp signal. In the actual application process, the value of the resistance of the adjacent two rows of step-down electric power ffi R can be obtained according to the panel process actually used. For the specific method, refer to the foregoing embodiment, and details are not described herein again.

In the above embodiments, the description has been made by taking the first transistor M and the second transistor T as N-type transistors as an example. In addition, the ramp signal generating circuit provided by the embodiment of the present invention can also be used in a p-type TFT. When the first transistor M and the second transistor T are both P-type transistors, the corresponding falling ramp signal generating circuit and the rising ramp signal generating circuit diagram are as shown in Figs. 7 and 8, respectively. Fig. 9 is a corresponding circuit timing diagram for driving the ramp signal generating circuit shown in Fig. 7 or Fig. 8. For the corresponding principle, reference may be made to the above description of the ramp signal generating circuit for the N-type TFT structure, which will not be described herein.

The ramp signal generating circuit of such a structure provided by the embodiment of the invention has fewer components and high circuit integration, and can effectively reduce the area/space occupied by the ramp signal generating circuit. In addition, compared with the prior art, the ramp signal generating circuit of such a structure has a higher sampling frequency and can effectively improve the linearity of the ramp signal.

Further, in the above-described ramp signal generating circuit, in consideration of the limited driving ability of the output signal of the output terminal Vo of the collecting unit 14, the amplifying unit 15 can be additionally provided inside or outside the ramp signal generating circuit. The input end of the amplifying unit 15 can be connected to the output end of the collecting unit 14 for power amplification of the voltage output from the collecting unit 14.

For example, in the ramp signal generating circuit shown in Fig. 2, the amplifying unit 15 may specifically employ a power amplifier or other circuits having the same function. The embodiments of the present invention do not limit this.

The ramp signal generating circuit provided by the embodiment of the invention has the advantage that the ramp signal is collected by setting the matrix resistor structure including the trace, and the driving mode of the GOA2 only needs one-way scanning. In addition, the circuit structure of the GOA2 is relatively simple, and the area/space occupied by the entire circuit is relatively small.

Embodiments of the present invention also provide a ramp signal generator comprising a ramp signal generating circuit as described above.

Such a ramp signal generator can be used as a signal source alone or in combination with other devices. It is used in a variety of devices or circuit structures that require ramp signal driving. The structure of the ramp signal generating circuit has been described in detail in the foregoing embodiments, and details are not described herein.

The ramp signal generator provided by the embodiment of the invention includes a ramp signal generating circuit. The circuit uses two shift register units, a voltage drop unit, and a design of the acquisition unit. The two timing register units are driven by the voltage drop unit and the acquisition unit by different timing signals. Therefore, the first shift register is controlled to control the voltage drop unit to successively reduce the voltage input from the power input terminal, and the second shift register controls the acquisition unit to collect and output the continuously varying voltage outputted by the voltage drop unit. Such a structure of the ramp signal generating circuit has fewer components and a high degree of circuit integration, and can effectively reduce the area/space occupied by the ramp signal generating circuit. In addition, the ramp signal generating circuit of such a structure has a higher sampling frequency than the prior art, so that the linearity of the ramp signal can be effectively improved.

The ramp signal generating circuit provided by the embodiment of the present invention can also be applied to an array substrate structure in a display panel. Among them, in the prior art array substrate, a circuit structure including a first shift register and a second shift register is often used.

The first shift register and the second shift register are respectively used to input a gate line scan signal or a data line scan signal to the display area pixel unit. The use of such a pixel array structure can effectively reduce the peripheral routing of the display device and realize the narrow bezel design of the display device.

Further, the ramp signal generating circuit included in the array substrate may further include a voltage drop unit and an acquisition unit.

The voltage drop unit is connected to the power input terminal and the ground terminal, respectively.

The first shift register is connected to the voltage drop unit, and the control voltage drop unit continuously reduces the voltage input to the power input terminal step by step.

The acquisition unit has an output and is connected to the pressure drop unit.

The second shift register is connected to the acquisition unit, and controls the acquisition unit to collect and output the continuously varying voltage outputted by the voltage drop unit.

With the array substrate of such a structure, the ramp signal generating circuit is formed by integrating the voltage drop unit and the collecting unit on the array substrate and using two existing shift registers on the array substrate. In this way, the ramp signal generating function can be realized on the surface of the array substrate without additionally adding a large number of components, thereby effectively controlling the area of the display panel driving circuit and ensuring the display. The display device is capable of achieving a narrow bezel setting.

The structure of the ramp signal generating circuit has been described in detail in the foregoing embodiments, and will not be described herein.

The array substrate provided by the embodiment of the invention comprises a ramp signal generating circuit, and the ramp signal generating circuit adopts two shift register units, a voltage drop unit and a design of the collecting unit. The two shift register units are driven by the voltage drop unit and the acquisition unit by different timing signal designs. Thereby, the first shift register is controlled to control the voltage drop unit to successively reduce the voltage input from the power input terminal, and the second shift register controls the collecting unit to collect and output the continuously varying voltage outputted by the voltage drop unit. Such a structure of the ramp signal generating circuit has fewer constituent units and a high degree of circuit integration, which can effectively reduce the area/space occupied by the ramp signal generating circuit. In addition, the ramp signal generating circuit of such a structure has a higher sampling frequency than the prior art, so that the linearity of the ramp signal can be effectively improved.

The display device provided by the embodiment of the invention includes at least the column substrate as described above.

It should be noted that the display device provided by the embodiment of the present invention may be: a liquid crystal panel, a electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like, any product or component having a display function.

The structure of the array substrate has been described in detail in the foregoing embodiments, and will not be described herein.

A display device of such a structure includes an array substrate. The array substrate includes a ramp signal generating circuit. The ramp signal generating circuit is designed using two shift register units, a voltage drop unit, and an acquisition unit. The two shift register units are driven by the voltage drop unit and the acquisition unit by different timing signal designs. The first shift register is controlled to control the voltage drop unit to continuously reduce the voltage input from the power input terminal, and the second shift register controls the acquisition unit to collect and output the continuously varying voltage outputted by the voltage drop unit. . Such a structure of the ramp signal generating circuit has fewer components and a high degree of circuit integration, and can effectively reduce the area/space occupied by the ramp signal generating circuit. In addition, the ramp signal generating circuit of such a structure has a more sturdy sampling frequency than the prior art, so that the linearity of the ramp signal can be effectively improved.

Those skilled in the art can understand that all or part of the process of implementing the above method embodiments can be completed by computer program related hardware. The aforementioned program can be stored in a calculation The machine can be read from the storage medium. When the program is executed, the steps including the above method embodiments are performed. The foregoing storage medium includes, for example, but not limited to: a ROM, a RAM, a magnetic disk, or an optical disk, and the like, which can store program codes.

The above is a specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Accordingly, the scope of the invention should be determined by the scope of the appended claims.

Claims

A ramp signal generating circuit comprising:

a voltage drop unit, which is respectively connected to the power input end and the ground end;

a first shift register connected to the voltage drop unit for controlling the voltage drop unit to continuously reduce the voltage input by the power input terminal step by step;

An acquisition unit having an output, and the acquisition unit is coupled to the pressure drop unit;

And a second shift register connected to the collecting unit, configured to control the collecting unit to collect and output a continuously varying voltage output by the voltage drop unit.

2. The ramp signal generating circuit according to claim 1, wherein the voltage drop unit comprises: a plurality of first transistors arranged in a matrix form;

The gates of the first transistors located in the same row are all connected to one output of the first shift register;

The first poles of the first transistors in the same column are each connected to one input of the acquisition unit;

The second poles of the first transistors in the same row are connected in series, and the second poles of the first transistors located in the last column of any row are in series with the second poles of the first transistors of the first row of the next row ; and

In the first transistor connected in series, a step-down resistor is connected in series between the second poles of any two adjacent ones of the first transistors.

The ramp signal generating circuit according to claim 1 or 2, wherein the collecting unit comprises: a plurality of: two transistors;

a gate of the second transistor is respectively connected to different output ends of the second shift register, and a first pole of the second transistor is connected to an output end of the acquisition unit;

A second pole of each of the second transistors is coupled to a first pole of the first transistor in the same column.

4. The ramp signal generating circuit according to claim 3, wherein

When the first transistor and the second transistor are both N-type transistors, the first crystal a first source of the tube and the second transistor, and a second drain.

5. The ramp signal generating circuit according to claim 3, wherein

When the first transistor and the second transistor are both Ρ-type transistors, the first transistor and the first transistor of the second transistor have a second source.

The ramp signal generating circuit according to any one of claims 25 to 5, wherein the power input terminal is connected to the second pole of the first transistor located in the first column of the first row, and is located at the last row of the last row A second pole of the first transistor of a column is coupled to the ground.

The ramp signal generating circuit according to any one of claims 2 to 5, wherein the power input terminal is connected to the second pole of the first transistor located in the last column of the last row, and is located in the first row A second pole of the first transistor of a column is coupled to the ground.

8. The ramp signal generating circuit according to claim 6, wherein

The bf resistors connected in series in the same row have the same ffi value;

When the power input terminal is connected to the second pole of the first transistor in the first row of the first row, and the second pole of the first transistor in the last row of the last row is connected to the ground terminal From the first row to the last row, the resistance values of the step-down resistors of the adjacent two rows are proportionally reduced.

9. The ramp signal generating circuit according to claim 7, wherein

The buck resistors connected in series in the same row have the same resistance;

When the power input terminal is connected to the second pole of the first transistor in the last column of the last row, and the second pole of the first transistor in the first row and the first column is connected to the ground terminal, From one row to the last row, the resistance of the step-down resistors in the adjacent two rows is proportionally increased.

The ramp signal generating circuit according to any one of claims 2-9, wherein the input end of the first shift register is respectively connected to the first clock signal, the second clock signal, and the first frame start signal , for turning on the first transistor row by row.

The ramp signal generating circuit according to any one of claims 2 to 10, wherein an input end of the second shift register is respectively connected to a third clock signal, a fourth clock signal, and a second frame start signal, And controlling the collecting unit to collect the voltage of each of the first poles of the first transistor column by column during a first transistor turn-on period.

The ramp signal generating circuit according to any one of claims 1 to 11, further comprising: an amplifying unit connected to an output end of the collecting unit, configured to input the collecting unit The voltage is amplified by power.

13. A ramp signal generator comprising at least the ramp signal generating circuit of any of claims -12 to be used as a signal source, either alone or in combination with other electronic devices.

An array substrate comprising a first shift register and a second shift register, wherein the array substrate further comprises a ramp signal generating circuit, the ramp signal generating circuit comprising a voltage drop unit and a meter w,兀

Wherein, the voltage drop unit is respectively connected to the power input end and the ground end;

The first shift register is connected to the voltage drop unit, and is configured to control the voltage drop unit to continuously reduce the voltage input by the power input terminal step by step;

The acquisition unit has an output and is connected to the pressure drop unit;

The second shift register is connected to the collecting unit, and is configured to control the collecting unit to collect and output a continuously varying voltage output by the voltage drop unit.

A display device comprising at least the array substrate of claim 14.

16. A method of operating a ramp signal generating circuit, wherein: the ramp signal generating circuit comprises: a voltage drop unit connected to a power input terminal and a ground terminal, respectively; a first shift register, and the voltage drop a unit connected; an acquisition unit having an output, and the acquisition unit is coupled to the voltage drop unit; and a second shift register coupled to the acquisition unit

The method of operation includes:

Controlling the voltage drop unit to continuously reduce the voltage input to the power input terminal step by step;

The acquisition unit is controlled to collect and output a continuously varying voltage output by the voltage drop unit.