WO2015089546A2

WO2015089546A2 - A phase cutting control dimmer arrangement and a method of operation thereof to minimise electro-magnetic interference (emi) noise to remain within regulatory requirements when powering a lamp

Info

Publication number: WO2015089546A2
Application number: PCT/AU2014/001121
Authority: WO
Inventors: Philip Tracy
Original assignee: Hendon Semiconductors Pty Ltd
Priority date: 2013-12-16
Filing date: 2014-12-15
Publication date: 2015-06-25
Also published as: WO2015089546A3

Abstract

A phase cutting control dimmer arrangement adapted to minimise electro-magnetic interference noise including a gate drive with an electrical input path to the connected gates of back-to-back FETs or IGBTs including a first resistor, a second resistor and a capacitor. The capacitor is adapted such that when at a first instant a switching voltage to turn OFF the FETs or IGBTs is first applied to the connected gates the capacitor is enabled to provide a current through the first resistor that adds to a current flowing into the second resistor thereby increasing a total gate drive current into the connected gates of the FETs or IGBTs minimising a time delay between an application of the pulse-enabled signal to the connected gates of the FETs or IGBTs and the switching OFF of the FETs or IGBTs.

Description

A PHASE CUTTING CONTROL DIMMER ARRANGEMENT AND A METHOD OF OPERATION THEREOF TO MINIMISE ELECTRO-MAGNETIC INTERFERENCE (EMI) NOISE TO REMAIN WITHIN REGULATORY REQUIREMENTS WHEN

POWERING A LAMP

FIELD OF THE INVENTION

[001] This invention relates to a phase cutting control dimmer arrangement that includes a unique drive arrangement tha provides a control input to the contro!iably conductive device that is configured to provide an adjustable duty cycle ratio of the AC mains supply voltage to control the amount of power delivered to the lamp.

[002] More particularly this invention relates to a drive arrangement for a dimmer with Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs) as a load switching element, in which the levels of radio frequency interference produced by the load switching element can be adapted to meet the requirements of regulatory Standards for the control of Electromagnetic Interference (EMI) noise without using low pass filters in the ac mains supply current path and where the delay time between operation of switching and the time at which its activation control signal is generated can be minimised,

BACKGROUND ART DISCUSSION

[003] Phase cut dimmers operate by switching AC mains supplies to the lamp or light load for only a chosen time portion of each AC mains supply half cycle. The instants at which the load switching element opens and closes becomes a source of radio frequency interference and maximum allowed levels of that interference are covered by national standards.

[004] Conventional methods used to reduce interference to the required levels have included the use of a low-pass filter in the ac mains current path that effectively requires the connection of an ac mains rated capacitor across the dimmer's terminals. Even when the dimmer's electronic switch is open the use of that capacitor provides a path for current, to flow in the controlled load. [005] As the efficiency of lamps has increased the power used by those lamps has decreased. Modem electronic iamps rated at just 5 W will produce significant lighting so modern dimmers must be able to work with lamp loads having power ratings about 10 times lower than traditional incandescent lamps. For example a 5 Watt lamp on a 230 Volts ac mains supply has a nominal operating current of less than 22 miiliamps. if that lamp is to be dimmed to 10% of its full brightness then the lamp current passed by the dimmers may need to be reduced to 2.2 miiliamps.

[006] Dimmers that are designed to operate in a series connected arrangement, between the ac mains suppiy and the lamp load, are conventionaily described as 'two terminal' devices. They do not require any separate provision of a non-switched ac mains supply or other ac power source and these dimmers derive the power required for operation from the load current that flows through them.

[007] in order to switch a light OFF", or make the light very dim, the current passing through the dimmer, used to power it, needs to be as small as possible. While it is possible to design a dimmer that requires very little current to be drawn through the iamp in order to power the dimmer, it can be difficult to achieve values less than 1 milliamp. It therefore becomes important to ensure that any current that flows in a filter capacitor is connected across the dimmer's terminals is minimised and ideally it wouid pass less than 1 mA to the lamp.

[008] The maximum value of capacitor, to pass less than 1 mA at 50 Hz is about 20 nF and such a small value cannot provide the degree of high frequency interference filtering needed to pass regulatory standards and limitations for EMI noise at the critical test frequency of 150 kHz.

[009] Accordingly EMI noise therefore must be reduced by other means and the obvious solution is to drive the FET switch in a way that will slow the rate of switching of the dimmer's terminal voltage instead of using fast switching and then relying on the conventional method of using separate low pass filtering. [0 0] Prior art solutions to this problem involve the use of resistors in series with the gates of the load switching element to slow the switching action of the load switching element sufficiently to meet the requirements of the E I noise Standards.

[011] As stated in United States Patent No. US7619365 if the switching time, the time when the semiconductor switch changes from the conductive state to the non- conductive state, and vice versa, is substantially short, the phase cutting control output wil! have a higher frequency component and the electro-magnetic interference noise will be increased.

[012] In an attempt to address this shortcoming a gate resistor (R_G) is placed in series with the load switching element thereby increasing the rise and fall times of the power flowing throug the load switching element such as a FET during switching time. Nonetheless, this increase in the rise and fall times of the current flowing through the load switching element during switching results in a compromise between the delay before the load switching element operates and the rate at which the load switching element then switches the load current

[013] Accordingly an object of this invention is to provide a phase cutting control dimmer arrangement with MOS Field Effect Transistors (FETs) or Insulated Gate Bipoiar Transistors (IGBTs) as the load switching element, in which the levels of radio frequency interference produced by the load switching element switch can be adapted to meet the requirements of the relevant regulatory Standards for the control of Electromagnetic Interference noise without using low pass filters in the ac mains supply current path.

[014] A further object of the invention is to provide a phase cutting control dimmer arrangement wherein the rate at which the MOS Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs) as the load switching element switch from the conducting to non-conducting state, or vice versa, have the delay time between operation of switching and the time at which its activation control signal is generated minimised as much as practically possible. [0 5] Further objects and advantages of the invention will become apparent from a complete reading of the specification.

SUMMARY OF THE INVENTION

[016] Accordingly in one form of the invention there is provided a phase cutting control dimmer arrangement adapted to minimise electro-magnetic interference (EMI) when powering a lamp, said arrangement including: a load control arrangement including back-to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates; a gate drive arrangement adapted to provide a pulse-enabled signal adapted to travel along an electrical input path to the connected gates of the back-to-back FETs or IGBTs with an adjustable duty cycle ratio of an AC mains power supply to control an amount of power deliverable to a lamp; the electrical input path to the connected gates of the back-to-back FETs or IGBTs including a first resistor, a second resistor and a capacitor; said first resistor in a first electrical path of said eiectrical input path, said first resistor connected between the connected gates of the FETs or IGBTs and a switchable first voltage source sufficient to turn ON said FETs or IGBTs; said second resistor in a second electrical path of said eiectricai input path, said second resistor connected between the connected gates of the FETs or IGBTs and a switchable second voitage source wherein the second voitage source is sufficient to turn OFF said FETs or IGBTs; said capacitor adapted such that when at a first instant a switching voltage to turn OFF said FETs or IGBTs is first applied from the pulse-enabled signal to the connected gates of the FETs or IGBTs, said capacitor is enabled to provide a current through the first resistor that adds to a current flowing into the second resistor thereby increasing a total gate drive current into the connected gates of the FETs or IGBTs minimising a time delay between an application of the pulse-enabled signal to the connected gates of the FETs or IGBTs and the switching OFF of the FETs or IGBTs to remove AC mains power supply from the lamp than otherwise would have been anticipated by including only a single gate resistor along the input path in series between the switchable first and second voltage sources and the connected gates of the FETs or IGBTs completed without increasing EMI noise beyond regulatory requirements. [0 7] in preference said capacitor is adapted such that when the connected gates of the FETs or IGBTs at a second instant when the switching voltage to turn OFF said FETs or IGBTs is reached, said capacitor is enabled to provide a current through the first resistor that opposes a current flowing into the second resistor thereby slowing the application of the pulse-enabled drive signal to the connected gates of the FETs or IGBTs during switching OFF of the FETs or IGBTs to AC mains power supply from the lamp to a rate slower than otherwise would have been anticipated by including only a single gate resistor along the input path in series between the switchable first and second voltage sources and the connected gates of the FETs or IGBTs completed without increasing a delay introduced prior to reaching the switching OFF instant of the FETs or IGBTs.

[018] in preference said capacitor is valued such that when the connected gates during the time when switching gate threshold voltage to turn OFF said FETs or IGBTs is reached, said capacitor becomes enabled to provide a current through the second resistor that opposes current flowing into the first resistor thereby decreasing the total gate drive current of the pulse-enabled drive signal to the connected gates and thereby slowing the actual switching OFF of the FETs or IGBTs to remove power from the lamp when compared with what otherwise would have been anticipated by including only a single gate resistor along the input path in series between the switchable first and second voltage sources and the connected gates of the FETs or IGBTs completed without increasing EMI noise beyond regulatory requirements.

[019] Advantageously this invention has provided a phase cutting control dimmer arrangement with MOS Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (IGBTs) as the load switching element, in which the levels of radio frequency interference produced by the load switching element switch are adapted to meet the requirements of the relevant regulatory Standards for the control of

Electromagnetic interference noise without using low pass filters in the ac mains supply current path.

[020] Still further, advantageously the invention provides a phase cutting control dimmer arrangement wherein the rate at which the MOS Field Effect Transistors (FETs) or Insulated Gate Bipolar Transistors (iGBTs) as the load switching element switch from the conducting to non-conducting state, or vice versa, have the delay time between operation of switching and the time at which its activation control signal is generated minimised as much as practically possible.

[021] in preference the capacitor is electrically connected between a first and a second switch.

[022] in preference each of the first resistor and second resistor include an end having an uninterrupted eiectricai path to opposing sides of the capacitor.

[023] in preference the first switch is electrically connected to a low voltage power supply.

[024] In preference the low voltage power supply is coupled to the AC power source and is adapted to provide a first voltage source switchabiy connectabie to the connected gates to turn ON said FETs or IGBTs.

[025] In preference the first resistor is in the electrical path between the connected gates of the FETs or IGBTs and the switchable first voltage source.

[026] In preference the second switch is electrically connected to the second voltage source having a voltage level relative to the connected gates to turn said FETs or IGBTs OFF.

[027] in preference the second resistor is included in an electrical path between the connected gates of the FETs or IGBTs and the switchable second voltage source.

[028] in preference the first switch and the second switch are configured such that at any one time only the first voltage source or second voltage source is connected to the connected gates of the FETs or IGBTs via the first resistor or second resistor respectively. [029] in preference the first switch and the second switch are gang switch operated simultaneously by the gate drive arrangement.

[030] in preference when the first switch is closed and the second switch is open, the first voltage source is connected to the connected gates and the FETs or IGBTs wherein the FETs or IGBTs are turned ON and wherein the first switch is open and the second switch is closed, the second voltage source is connected to the

connected gates of the FETs or IGBTs to turn said FETs or !GBTs OFF.

[031] Advantageously the arrangement provides for building a controllable AC mains voltage switch, using FETs or IGBTs as the load switching element, in which the levels of radio frequency interferences produced by the switching can be adapted to meet and not exceed the regulatory limits placed on the amount of electromagnetic interference that exists on the phase cutting control output of the dimmer.

[032] As introduced above, the phase cut dimmers operate by switching the AC mains supply to lamp load for only a pre-determined time portion of each mains half cycle. The instance at which the electric switch opens and closes, as introduced above, can become a source of radio frequency interference that exceeds maximum allowed regulatory levels covered under the relevant National Standards.

[033] Conventionally to reduce interference to the required levels, the phase cutting control dimming technique utilised a low pass filter in the AC mains supply input path that effectively required the connection of the AC mains supply rated capacitor across the dimmer's terminals. In this arrangement even when the dimmer's electronic switch was open the use of that capacitor provide a path for current to flow. As stated above this invention requires no use of such a capacitor across the terminals of the dimmer.

[034] Advantageously this invention provides a solution without using a low pass filter in the AC mains supply path and the electro-magnetic interference noise can be reduced by the unique arrangement of the first and second resistors and the capacitor so that the FETs or IGSTs can be driven at a rate that will not contribute to electro-magnetic interference but also at the same time producing a reduced time delay between the application of the puise-enab!ing signal to the connected gates of the FETs or IGBTs and the powering of the lamp.

[035] in preference the first switch and the second switch implement bipolar transistors to provide gang switched simultaneous operation of the first switch and the second switch,

[036] in preference the second voltage source connected to the second resistor has a value equal or thereabouts to the voltage on the source or emitter of the switching transistors.

[037] in preference the phase cutting control dimmer arrangement is a two-wire trailing edge control dimmer arrangement.

[038] in preference the load control arrangement for turning off electrical power to the load includes a control switch with back-to-back Field Effect Transistors.

[039] in preference the Field Effect Transistors are N-Channei enhancement mode MOSFETs with source terminals connected together with gates connected together and the drain terminals acting as two power terminals.

[040] in preference each Field Effect Transistor has an intrinsic body diode so as to allow conduction of current through the dimmer arrangement in one direction even if the Field Effect Transistor is switched OFF.

[041] in preference active and load dimmer terminal voltages are each bridge rectified by a corresponding diode.

[042] in preference the resistance value of the second resistor is larger than the resistive value of first resistor.

[043] in preference when the connected gates at an instant when switching voltage to turn ON said FETs or IGBTs is reached, said capacitor is enabled to provide a current through the first resistor that adds to the current flowing from the gate into the second resistor thereby minimising a time delay between the appiication of the pulse- enabled drive signal to the connected gates and actual switching ON of the FETs or IGBTs to power the lamp without causing any increase in electro-magnetic

interference.

BRIEF DESCRIPTION OF THE DRAWINGS

[044] in order now to describe the invention in greater detail, a preferred

embodiment will be presented assisted by the following figure and accompanying text.

[045] Figures 1 shows an electric circuit of a phase cutting control dimmer arrangement of a preferred embodiment of this invention,

DETAILED DESCRIPTION OF THE INVENTION

[046] Referring to Figures 1 wherein a phase cutting control dimmer arrangement circuit diagram is shown generally as (10). The phase cutting control dimmer arrangement is identifiable as two-wire trailing edge dimmer arrangement also referrable to as reverse phase cutting control dimmer arrangement adapted to remove power from the end or trailing edge of each AC mains power supply cycle. The dimmer terminals include ACTIVE (12) and LOAD (14).

[047] The dimmer terminal voltage is effectively bridged by rectified diodes (16) and (18) and the parasitic diodes (20), (22) which are contained in the Field Effect Transistors (24), (26) that comprise the load current switch. As illustrated FETs (24) and (26) are arranged back-to-back and operate in the N-Channel enhancement mode having source terminals (17), (19) connected together with the gates (29), (31) also connected along electrical path (25) and the drain terminals (21 ), (23) acting as two power terminals.

[048] The FETs (24) and (26), each have corresponding parasitic or sometimes referred to as intrinsic body diodes (20) and (22) that allow conduction of current in one direction as configured back-to-back arrangement of the FETs (24) and (26) allows load current to be controlled in either direction.

[049] Capacitor (52) having the opposing plates (53a) and (53b) are respectively connected to the ends of the first resistor (54) and the second resistor (56) such that the capacitor (52), first resistor (54) and the second resistor (56) are configured into the electrical path between the gate drive arrangement (58), wherein the gate drive arrangement (58) is adapted to provide the pulse-enabled signal that travels along the electrical input path to the connected gates (29) and (31 ) of the back-to-back FETs (24) and (26) with an adjustable duty cycle ratio of the AC mains power supply to control an amount of power deliverable to the lamp (not shown) under the control of the dimmer arrangement.

[050] The electrical input path includes pathway lines (60a), (60b), (60c) and (60d) wherein the pulse-enabled signal can travel from the gate drive arrangement (58) to the connected gates (29), (31) of the FETs (24) and (26).

[051] As can be seen the electrical input path including pathway lines (60a), (60b), (60c) and (60d) incorporates the first resistor (54) and the second resistor (56) wherein each of the first resistor (54) and the second resistor (56) are electrically connected shown by way of (57) and (59) at one end to the opposing plates (53a) and (53b) of the capacitor (52).

[052] The capacitor (52) is valued such that when the connected gates (29), (31 ) of the back-to-back FETs (24) and (26) at an instant when switching voltage to turn OFF the FETs (24) and (26) is applied, the capacitor (52) is firstly enabled to provide a current through the first resistor (54) that adds to the current flowing from the gate into the second resistor (56) thereby minimising any delay before the back-to-back FETs (24) and (26) operates and is secondly enabled to provide a current through the first resistor (54) that, during the time the FETs (24), (26) are actually switching the load current, the capacitor (52) has reversed in direction and decreases the current flowing from the gate drive (58) and the rate at which the FETs (28) and (31 ) will then switch the load current without exceeding any EMI noise regulatory requirements. [053] Generally the arrangement shown in figure 1 effectively provides through the gate drive arrangement the pulse enabled signal to the FETs (24) and (26) that changes with time, at a rate firstly greater and subsequently lesser than happens in the arrangement provided for in the prior art. That is, there is always a natural change caused by the changing voltage on the connected gates of the FETs (24) and (26) even when using a single gate drive resistor.

[054] The purpose of the arrangement shown in Figure 1 is to modify that change in the pu!se enabled signal provided by the gate drive arrangement (58) so that it is firstly increased, reducing the time taken to reach the connected gates (29) and (31 ) switching threshold, but, while th FETs (24) and (26) switching action happens, is significantly decreased.

[055] If the pulse enabled signal provided by the gate drive arrangement (58) for the connected gates (29) and (31) of the FETs (24) and (26) is arranged so level of the drive, around the time the FETs (24) and (26) are switching th load current, is smatler than the natural drive that would have occurred with a single drive resistor as is the case in many arrangements provided for in the prior art, when the FETs (24) and (26) have reached the point where they are switching the load current, then the load current will be switched more slowly.

[056] In Figure 1 the capacitor (52) has been added between the two switches (53) and (55). When turning the FETs (24) and (26) OFF it provides an effective gate drive resistance that is initially lower than the second resistor (56) but that increases so that, at the instant the FETs (24) and (26) are turning OFF, has a value effectively larger than second resistor (56) alone. That is, the gate drive current the connected gates (29) and (31) of the FETs (24) and (26) is initially higher but is later lower than it would have been if a single drive resistor arrangements as in the prior art had been used.

[057] When turning the FETs (24) and (26) ON there is a similar effect but, in practice, the degree of action of this arrangement will be greatly reduced because in practice the second resistor (56) will usually be larger than first resistor (54). In practical applications it is the switching OFF time that generates the majority of the radio frequency interference therefore the component values in the arrangement will be selected for maximum effect during the switch OFF time of the FETs (24) and (26).

[058] The broken line (48) appearing in Figure 1 represents that switches (53) and (55) are ganged and therefore operate simultaneously. The gate drive to turn the FETs (24) and (26) ON is through the low voltage power supply (42) switchable by switch (53). The low voltage power supply preferable would be 10 V.

[059] The gate drive that turns the FETs (24) and (26) OFF is connected via switch (55) to the required voltage to turn the FETs OFF.

[060] Bipolar junction transistors maybe used as for switches (55) and (53).

[061] in Figure 1 switching positions of the ganged switches (53) and (55) controlled by the pulse enabled signal provided by the gate drive arrangement (58) shows FETs (24) and (26) in the OFF configuration. FETs (24) and (26) change from the ON or conducting state to the OFF or high impedance state as the gate voltage at which the FETs (24) and (26) is designed to switch falls below the FETs (24) and (26) switching threshold.

[062] For the enhancement mode FETs (24) and (26) normally used for this purpose the switching voltage threshold would typically lie in the range of 2 V to 6 V. The effective gate capacitance of the FETs (24) and (26) is generally complex and nonlinear, but again for devices used for this purpose will be of the order of a few nanofarads.

[063] When describing the turn ON of the FETs (24) and (26), the effect of adding capacitor (52) is to make the effective value of the gate drive resistance, at the instant the switch (53) is closed and simultaneously switch (55) is opened, equal to the parallel combination of first resistor and second resistor. [064] That value, being lower than first resistor (54) alone, will charge the connected gates (29) and (31) of the FETs (24) and (26) towards the switching threshold more quickly than using the first resistor (54) alone.

[065] When describing the turn OFF of the FETs (24) and (26), the effect of adding capacitor (52) is to make the effective value of the gate drive resistance, at the instant the switch (55) is closed and simultaneously switch (53) is opened, equal to the parallel combination of first resistor (54) and the second resistor (58).

[066] That value, being lower tha the second resistor (56) alone, will charge the connected gates(29) and (31 ) of the FETs (24) and (26) towards the switching threshold more quickly than using the second resistor (56) alone. Using a single resistor to achieve the same load current switching rate, would be much longer, at least two fold. The reason for the improved switching characteristic of this invention is that, during that initial drive period, the capacitor (52) will be charged from its initial value of, for example 0 V to a value between 0V and the low power supply voltage (42), for example 10 V, that is used to drive the FETs (24) and (26) ON.

[067] The value of capacitor (52) and first resistor (54) can be chosen such that, at the instant the connected gates (29) and (31) of the FETs (24) and (26) reach the switching voltage, for example in this preferred embodiment 5 V, the capacitor (52) has become charged to more than 5 V. That means that, when the connected gates (29) and (31) of the FETs (24) and (26) are at 5 V, the capacitor (52) will be providing a current, the first resistor (54), that opposes the current flowing in the second resistor (56) and so will slow the switching action of the FETs (24) and (26) and RF interference will be reduced.

[068] When connected gates (29) and (31 ) voltage is above 9 V the FETs (24) and (26) are turned O and the terminal voltage is approximately zero volts. That zero voltage indicates that the relevant switch is closed and current can be passed from the AC mains power supply voltage to the load. When the connected gates (29) and (31) of the FETs (24) and (26) voltage is decreased below 5 V the electronic AC mains power supply voltage switch will open and the voltage across the terminals will increase up to the instantaneous value of the AC mains power supply at the time the relevant switch is opened. For example this could be at a voltage of about 320 V.

[069] The connected gates (29) and (31 ) voltage starts failing and when it reaches approximately 5 V the connected gates (29) and (31 ) of the FETs (24) and (26) has reached the value for switching and, after an internal FETs (24) and (26) delay, wherein the gate voltage remains constant, the FETs (24) and (26) will turn OFF. The rate at which the FETs (24) and (26) will turn OFF depends on the rate at which its connected gate voltage is decreasing around the time that the FETs (24) and (26) are actually switching.

[070] This rate can be selected, by selection of the gate drive components, to meet the EM! regulatory requirements. A single conventional single gate drive resistor may be selected to produce the same delay time before the switching starts but in those cases the load voltage increases at least at a rate 45% faster than in the improved arrangement of this invention and would likely fail to meet the EMI noise regulatory requirements.

Claims

THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

1. A phase cutting control dimmer arrangement adapted to minimise electromagnetic interference (EMI) when powering a lamp, said arrangement including: a load control arrangement including back-to-back field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs) with connected gates; a gate drive arrangement adapted to provide a pulse-enabled signal adapted to travel along an electrical input path to the connected gates of the back-to-back FETs or IGBTs with an adjustable duty cycle ratio of an AC mains power supply to control an amount of power deliverable to a lamp; the electrical input path to the connected gates of the back-to-back FETs or IGBTs including a first resistor, a second resistor and a capacitor; said first resistor in a first electrical path of said electrical input path, said first resistor connected between the connected gates of the FETs or IGBTs and a switchable first voltage source sufficient to turn ON said FETs or IGBTs; said second resistor in a second electrical path of said electrical input path, said second resistor connected between the connected gates of the FETs or IGBTs and a switchable second voltage source wherein the second voltage source is sufficient to turn OFF said FETs or IGBTs; said capacitor adapted such that when at a first instant a switching voltage to turn OFF said FETs or IGBTs is first applied from the pulse-enabled signal to the connected gates of the FETs or IGBTs, said capacitor is enabled to provide a current through the first resistor that adds to a current flowing into the second resistor thereby increasing a total gate drive current into the connected gates of the FETs or IGBTs minimising a time delay between an application of the pulse-enabled signal to the connected gates of the FETs or IGBTs and the switching OFF of the FETs or IGBTs to remove AC mains power supply from the lamp.

2. The phase cutting control dimmer arrangement of claim 1 wherei said capacitor is adapted such that when the connected gates of the FETs or iGBTs at a second instant when the switching voltage to turn OFF said FETs or IGBTs is reached, said capacitor is enabled to provide a current through the first resistor that opposes a current flowing into the second resistor thereby stowing the application of the pulse-enabled drive signal to the connected gates of the FETs or IGBTs during switching OFF of the FETs or IGBTs to AC mains power supply from the iamp.

3. The phase cutting control dimmer arrangement of claim 1 or 2 wherein a first plate of the capacitor is electrically connected to the first switchable voltage source and a second plate of the capacitor is connected to the second switchable voltage source.

4. The phase cutting control dimmer arrangement of claim 3 wherein a first end of the first resistor is directly electrically connected to the first plate of the capacitor and a first end of the second resistor is electrically connected to the second plate of the capacitor.

5. The phase cutting control dimmer arrangement of claim 4 wherein the first switchable voltage source is electrically connected to a low voltage power supply.

6. The phase cutting control dimmer arrangement of claim 5 wherein the low voltage power supply is coupled to the AC Mains power supply and wherein the low voltage power supply is adapted to provide a first voltage source switchable connectable to the connected gates of the FETs or IGBTs to turn ON said FETs or IGBTs.

7. The phase cutting control dimmer arrangement of claim 6 wherein a second end of said first resistor is electrically connected to the connected gates of the FETs or IGBTs and the first end of the first resistor in connected via a first switch to the first switchable voltage source.

8. The phase cutting control dimmer arrangement of claim 7 wherein a second switch is electrically connected to th second switchable voltage source, wherein the second switchable voltage source includes a voltage level relative to the connected gates of the FETs or IGBTs to turn said FETs or IGBTs OFF.

9. The phase cutting control dimmer arrangement of claim 8 wherein the first end of said second resistor is electrically connected via the second switch to the second switchable voltage source and a second end of said second resistor is electrically connected to the connected gates of the FETs or IGBTs.

10. The phase cutting control dimmer arrangement of claim 9 wherein the first switch and the second switch are arranged such that at any one time only the first switchable voltage source or second switchable voltage source is connectable to the connected gates of the FETs or IGBTs via the first resistor or second resistor respectively.

11. The phase cutting control dimmer arrangement of claim 10 wherein the first switch and the second switch are gang switch operatable simultaneously by the gate drive arrangement.

12. The phase cutting control dimmer arrangement of claim 11 wherein when the first switch is closed and the second switch is open, the first switchable voltage source is connected to the connected gates of the FETs or IGBTs and the FETs or IGBTs are turned ON and wherein the first switch is open and the second switch is closed, the second switchable voltage source is connected to the connected gates of the FETs or IGBTs to turn said FETs or IGBTs OFF.

13. The phase cutting control dimmer arrangement of claim 12 wherein the first switch and the second switch include bipolar transistors to provide a gang switched simultaneous operation of the first switch and the second switch.

14. The phase cutting control dimmer of any one of the preceding claims wherein arrangement the phase cutting control dimmer arrangement is a two-wire trailing edge controi dimmer arrangement