Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
  • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
  • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
  • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
  • G09G3/3275—Details of drivers for data electrodes
  • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
  • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
  • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
  • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
  • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/04—Maintaining the quality of display appearance
  • G09G2320/043—Preventing or counteracting the effects of ageing
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/06—Adjustment of display parameters
  • G09G2320/0693—Calibration of display systems

Definitions

• the present invention generally relates to active matrix organic light emitting device (AMOLED) displays, and particularly extracting parameters of the pixel circuits and light emitting devices in such displays.
• AMOLED active matrix organic light emitting device
• AMOLED active matrix organic light emitting device
• the quality of output in an OLED-based pixel is affected by the properties of the drive transistor, which is typically fabricated from materials including but not limited to amorphous silicon, polysilicon, or metal oxide, as well as the OLED itself.
• the drive transistor which is typically fabricated from materials including but not limited to amorphous silicon, polysilicon, or metal oxide, as well as the OLED itself.
• threshold voltage and mobility of the drive transistor tend to change as the pixel ages.
• changes in these parameters must be compensated for by adjusting the programming voltage. In order to do so, such parameters must be extracted from the driver circuit.
• the addition of components to extract such parameters in a simple driver circuit requires more space on a display substrate for the drive circuitry and thereby reduces the amount of aperture or area of light emission from the OLED.
• the I-V characteristic of a thin film drive transistor depends on mobility and threshold voltage which are a function of the materials used to fabricate the transistor.
• mobility and threshold voltage are a function of the materials used to fabricate the transistor.
• different thin film transistor devices implemented across the display panel may demonstrate non-uniform behavior due to aging and process variations in mobility and threshold voltage. Accordingly, for a constant voltage, each device may have a different drain current.
• An extreme example may be where one device could have low threshold-voltage and low mobility compared to a second device with high threshold-voltage and high mobility.
• An embodiment disclosed reads or extracts a desired circuit parameter from a pixel circuit that includes a light emitting device, a drive device to provide a programmable drive current to the light emitting device, a programming input, and a storage device to store a programming signal.
• the extraction method comprises turning off the drive device and supplying a predetermined voltage from an external source to the light emitting device, discharging the light emitting device until the light emitting device turns off, and then reading the voltage on the light emitting device while that device is turned off.
• the voltages on the light emitting devices in a plurality of pixel circuits are read via the same external line, at different times.
• the reading of the desired parameter may be effected by coupling the pixel circuit to a charge-pump amplifier, isolating the charge- pump amplifier from the pixel circuit to provide a voltage output either proportional to the charge level or integrating the current from the pixel circuit, reading the voltage output of the charge-pump amplifier; and determining at least one pixel circuit parameter from the voltage output of the charge-pump amplifier.
• Another embodiment extracts a circuit parameter from a pixel circuit by turning on the drive device so that the voltage of the light emitting device rises to a level higher than its turn-on voltage, turning off the drive device so that the voltage on the light emitting device is discharged through the light emitting device until the light emitting device turns off, and then reading the voltage on the light emitting device while that device is turned off.
• a further embodiment extracts a circuit parameter from a pixel circuit by programming the pixel circuit, turning on the drive device, and extracting a parameter of the drive device by either (i) reading the current passing through the drive device while applying a predetermined voltage to the drive device, or (ii) reading the voltage on the drive device while passing a predetermined current through the drive device.
• Another embodiment extracts a circuit parameter from a pixel circuit by turning on the drive device and measuring the current and voltage of the drive transistor while changing the voltage between the gate and the source or drain of the drive transistor to operate the drive transistor in the linear regime during one time interval and in the saturated regime during a second time interval, and extracting a parameter of the light emitting device from the relationship of the currents and voltages measured with the drive transistor operating in the two regimes.
• FIG. 1 is a block diagram of an AMOLED display with compensation control
• FIG. 2 is a circuit diagram of a data extraction circuit for a two-transistor pixel in the AMOLED display in FIG. 1;
• FIG. 3A is a signal timing diagram of the signals to the data extraction circuit to extract the threshold voltage and mobility of an n-type drive transistor in FIG. 2;
• FIG. 3B is a signal timing diagram of the signals to the data extraction circuit to extract the characteristic voltage of the OLED in FIG. 2 with an n-type drive transistor;
• FIG. 3C is a signal timing diagram of the signals to the data extraction circuit for a direct read to extract the threshold voltage of an n-type drive transistor in FIG. 2;
• FIG. 4A is a signal timing diagram of the signals to the data extraction circuit to extract the threshold voltage and mobility of a p-type drive transistor in FIG. 2;
• FIG. 4B is a signal timing diagram of the signals to the data extraction circuit to extract the characteristic voltage of the OLED in FIG. 2 with a p-type drive transistor;
• FIG. 4C is a signal timing diagram of the signals to the data extraction circuit for a direct read to extract the threshold voltage of a p-type drive transistor in FIG. 2;
• FIG. 4D is a signal timing diagram of the signals to the data extraction circuit for a direct read of the OLED turn-on voltage using either an n-type or p-type drive transistor in FIG. 2.
• FIG. 5 is a circuit diagram of a data extraction circuit for a three-transistor drive circuit for a pixel in the AMOLED display in FIG. 1 for extraction of parameters;
• FIG. 6A is a signal timing diagram of the signals to the data extraction circuit to extract the threshold voltage and mobility of the drive transistor in FIG. 5;
• FIG. 6B is a signal timing diagram of the signals to the data extraction circuit to extract the characteristic voltage of the OLED in FIG. 5;
• FIG. 6C is a signal timing diagram of the signals to the data extraction circuit for a direct read to extract the threshold voltage of the drive transistor in FIG. 5;
• FIG. 6D is a signal timing diagram of the signals to the data extraction circuit for a direct read to extract the characteristic voltage of the OLED in FIG. 5;
• FIG. 7 is a flow diagram of the extraction cycle to readout the characteristics of the drive transistor and the OLED of a pixel circuit in an AMOLED display;
• FIG. 8 is a flow diagram of different parameter extraction cycles and final applications.
• FIG. 9 is a block diagram and chart of the components of a data extraction system.
• FIG. 10 is a signal timing diagram of the signals to the data extraction circuit to extract the threshold voltage and mobility of the drive transistor in a modified version of the circuit in FIG. 5;
• FIG. 11 is a signal timing diagram of the signals to the data extraction circuit to extract the characteristic voltage of the OLED in a modified version of the circuit in FIG. 5;
• FIG. 12 is a circuit diagram of a data extraction circuit for reading the pixel charge from a drive circuit for a pixel in the AMOLED display in FIG. 1.
• FIG. 13 is a signal timing diagram of the signals to the data extraction circuit of FIG. 12 for reading pixel status by initializing the nodes externally;
• FIG. 14 is a flow diagram for reading the pixel status in the circuit of FIG. 12 by initializing the nodes externally;
• FIG. 15 is a signal timing diagram of the signals to the data extraction circuit of FIG. 12 for reading pixel status by initializing the nodes internally;
• FIG. 16 is a flow diagram for reading the pixel status in the circuit of FIG. 12 by initializing the nodes internally;
• FIG. 17 is a circuit diagram of a pair of circuits like the circuit of FIG. 12 used with a common monitor line for reading the pixel charge from two different pixels in the AMOLED display in FIG. 1;
• FIG. 18 is a signal timing diagram of the signals to the data extraction circuit of FIG. 17 for reading pixel charge when the monitor line is shared;
• FIG. 19 is a flow diagram for reading the pixel status of a pair of circuits like the circuit of FIG. 17, with a common monitor line.
• FIG. 20A is a schematic circuit diagram of a modified pixel circuit.
• FIG. 20B is a timing diagram illustrating the operation of the pixel circuit of FIG. 20 A with charge-based compensation.
• FIG. 21 is a timing diagram illustrating operation of the pixel circuit of FIG. 20 A to obtain a readout of a parameter of the drive transistor.
• FIG. 22 is a timing diagram illustrating operation of the pixel circuit of FIG. 20 A to obtain a readout of a parameter of the OLED.
• FIG. 23 is a timing diagram illustrating a modified operation of the pixel circuit of FIG. 20 A to obtain a readout of a parameter of the OLED.
• FIG. 24 is a circuit for extracting the parasitic capacitance from a pixel circuit using external compensation.
• FIG. 25 illustrates a pixel circuit that can be used for current measurement.
• FIG. 26 is an example pixel circuit that uses a charge-based in-pixel compensation implementation and its associated timing diagram.
• FIG. 27 shows the same pixel circuit as shown in FIG. 26 but using a different timing sequence.
• FIG. 28 is an example of another pixel circuit, in which the EM signal is divided into two signals to reset an internal node of the pixel circuit for compensation.
• FIG. 29 is another example of a pixel circuit and timing diagram, in which the OLED current or voltage can be read via a monitor line.
• FIG. 30 is another example charge-based compensation pixel circuit and timing diagram, which compensates for variation or aging of the drive transistor.
• FIG 31 is still another example of a pixel circuit and associated timing diagram having a discharge period to at least partially discharge the storage capacitor.
• FIG. 32 is similar to FIG. 31, except that the drive transistor Tl is programmed to act like a switch.
• FIG. 33 is a pixel circuit in which the OLED voltage or current is read out via a monitor line, which can also function as a reference line and/or a data line for programming information, and its associated timing diagram.
• FIG. 34 is another pixel circuit demonstrating another way of implementing the EM function, along with an associated timing diagram.
• FIG. 35 is a conventional pixel circuit.
• FIG. 36 is a pixel circuit in which one or more switches can be shared among rows and/or columns of the pixel array.
• FIG. 37 shows a similar pixel circuit to FIG. 36, but which uses a different programming operation.
• FIG. 38 illustrates another pixel circuit that shares one or more switches.
• FIGS. 39A and 39B illustrate a pixel circuit and associated timing diagram having a discharge cycle.
• FIGS. 40A and 40B illustrate another pixel circuit and associated timing diagram having a reset cycle.
• FIGS. 41 A and 4 IB illustrate yet another pixel circuit and associated timing diagram having a reset and readout cycle.
• FIGS. 42 A and 42B illustrate still another pixel circuit and associated timing diagram having a reset and readout cycle.
• FIGS. 43A and 43B illustrate another pixel circuit and associated timing diagram having a readout cycle following a programming cycle.
• FIGS. 44 A and 44B illustrate a further pixel circuit and associated timing diagram having a readout cycle following a programming cycle in which the pixel circuit is programmed with off current.
• FIGS. 45 A and 45B illustrate a still further pixel circuit and associated timing diagram having a discharge cycle.
• FIGS. 46 A and 46B illustrate another pixel circuit and associated timing diagram having a reset cycle.
• FIGS. 47 A and 47B illustrate yet another pixel circuit and associated timing diagram having a reset and readout cycle.
• FIGS. 48 A and 48B illustrate still another pixel circuit and associated timing diagram having a reset and readout cycle.
• FIGS. 49 A and 49B illustrate yet another pixel circuit and associated timing diagram having a readout cycle following a programming cycle.
• FIG. 1 is an electronic display system 100 having an active matrix area or pixel array 102 in which an n x m array of pixels 104 are arranged in a row and column configuration. For ease of illustration, only two rows and two columns are shown.
• a peripheral area 106 External to the active matrix area of the pixel array 102 is a peripheral area 106 where peripheral circuitry for driving and controlling the pixel array 102 are disposed.
• the peripheral circuitry includes an address or gate driver circuit 108, a data or source driver circuit 1 10, a controller 1 12, and an optional supply voltage (e.g., Vdd) driver 1 14.
• the controller 1 12 controls the gate, source, and supply voltage drivers 108, 1 10, 1 14.
• the gate driver 108 under control of the controller 1 12, operates on address or select lines SEL[i], SEL[i+l], and so forth, one for each row of pixels or pixel circuits 104 in the pixel array 102.
• the gate or address driver circuit 108 can also optionally operate on global select lines GSEL[j] and optionally /GSEL[j], which operate on multiple rows of pixels 104 in the pixel array 102, such as every two rows of pixels 104.
• the voltage data lines carry voltage programming information to each pixel 104 indicative of the brightness of each light emitting device in the pixel 104.
• a storage element, such as a capacitor, in each pixel 104 stores the voltage programming information until an emission or driving cycle turns on the light emitting device.
• the optional supply voltage driver 1 14, under control of the controller 1 12, controls a supply voltage (EL Vdd) line, one for each row or column of pixels 104 in the pixel array 102.
• the display system 100 further includes a current supply and readout circuit 120, which reads output data from data output lines, VD [k], VD [k+1], and so forth, one for each column of pixels 104 in the pixel array 102.
• each pixel or pixel circuit 104 in the display system 100 needs to be programmed with information (in the form of a current or a voltage or a charge) indicating the brightness of the light emitting device in the pixel 104.
• a frame defines the time period that includes: (i) a programming cycle or phase during which each and every pixel in the display system 100 is programmed with a programming voltage indicative of a brightness; and (ii) a driving or emission cycle or phase during which each light emitting device in each pixel is turned on to emit light at a brightness commensurate with the programming voltage stored in a storage element.
• a frame is thus one of many still images that compose a complete moving picture displayed on the display system 100.
• the components located outside of the pixel array 102 may be disposed in a peripheral area 106 around the pixel array 102 on the same physical substrate on which the pixel array 102 is disposed. These components include the gate driver 108, the source driver 110, the optional supply voltage driver 114, and a current supply and readout circuit 120. Alternately, some of the components in the peripheral area 106 may be disposed on the same substrate as the pixel array 102 while other components are disposed on a different substrate, or all of the components in the peripheral area can be disposed on a substrate different from the substrate on which the pixel array 102 is disposed. Together, the gate driver 108, the source driver 110, and the supply voltage driver 114 make up a display driver circuit.
• the display driver circuit in some configurations can include the gate driver 108 and the source driver 110 but not the supply voltage control 114.
• each transistor on the pixel matrix 102 may have a different drain current based on a non-deterministic mobility and threshold voltage:
• i and j are the coordinates (row and column) of a pixel in an nxm array of pixels such as the array of pixels 102 in FIG. 1.
• FIG. 2 shows a data extraction system 200 including a two-transistor (2T) driver circuit 202 and a readout circuit 204.
• the supply voltage control 1 14 is optional in a display system with 2T pixel circuit 104.
• the readout circuit 204 is part of the current supply and readout circuit 120 and gathers data from a column of pixels 104 as shown in FIG. 1.
• the readout circuit 204 includes a charge pump circuit 206 and a switch-box circuit 208.
• a voltage source 210 provides the supply voltage to the driver circuit 202 through the switch- box circuit 208.
• the charge-pump and switch-box circuits 206 and 208 are implemented on the top or bottom side of the array 102 such as in the voltage drive 114 and the current supply and readout circuit 120 in FIG. 1. This is achieved by either direct fabrication on the same substrate as the pixel array 102 or by bonding a microchip on the substrate or a flex as a hybrid solution.
• the driver circuit 202 includes a drive transistor 220, an organic light emitting device 222, a drain storage capacitor 224, a source storage capacitor 226, and a select transistor 228.
• a supply line 212 provides the supply voltage and also a monitor path (for the readout circuit 204) to a column of driver circuits such as the driver circuit 202.
• a select line input 230 is coupled to the gate of the select transistor 228.
• a programming data input 232 is coupled to the gate of the drive transistor 220 through the select transistor 228.
• the drain of the drive transistor 220 is coupled to the supply voltage line 212 and the source of the drive transistor 220 is coupled to the OLED 222.
• the select transistor 228 controls the coupling of the programming input 230 to the gate of the drive transistor 220.
• the source storage capacitor 226 is coupled between the gate and the source of the drive transistor 220.
• the drain storage capacitor 224 is coupled between the gate and the drain of the drive transistor 220.
• the OLED 222 has a parasitic capacitance that is modeled as a capacitor 240.
• the supply voltage line 212 also has a parasitic capacitance that is modeled as a capacitor 242.
• the drive transistor 220 in this example is a thin film transistor that is fabricated from amorphous silicon. Of course other materials such as polysilicon or metal oxide may be used.
• a node 244 is the circuit node where the source of the drive transistor 220 and the anode of the OLED 222 are coupled together.
• the drive transistor 220 is an n-type transistor.
• the system 200 may be used with a p-type drive transistor in place of the n-type drive transistor 220 as will be explained below.
• the readout circuit 204 includes the charge-pump circuit 206 and the switch-box circuit 208.
• the charge-pump circuit 206 includes an amplifier 250 having a positive and negative input.
• the negative input of the amplifier 250 is coupled to a capacitor 252 (Cin t ) in parallel with a switch 254 in a negative feedback loop to an output 256 of the amplifier 250.
• the switch 254 (S4) is utilized to discharge the capacitor 252 Cm t during the pre-charge phase.
• the positive input of the amplifier 250 is coupled to a common mode voltage input 258 (VCM).
• VCM common mode voltage input 258
• the output 256 of the amplifier 250 is indicative of various extracted parameters of the drive transistor 220 and OLED 222 as will be explained below.
• the switch-box circuit 208 includes several switches 260, 262 and 264 (SI, S2 and S3) to steer current to and from the pixel driver circuit 202.
• the switch 260 (SI) is used during the reset phase to provide a discharge path to ground.
• the switch 262 (S2) provides the supply connection during normal operation of the pixel 104 and also during the integration phase of readout.
• the switch 264 (S3) is used to isolate the charge-pump circuit 206 from the supply line voltage 212 (VD).
• the general readout concept for the two transistor pixel driver circuit 202 for each of the pixels 104 comes from the fact that the charge stored on the parasitic capacitance represented by the capacitor 240 across the OLED 222 has useful information of the threshold voltage and mobility of the drive transistor 220 and the turn-on voltage of the OLED 222.
• the extraction of such parameters may be used for various applications. For example, such parameters may be used to modify the programming data for the pixels 104 to compensate for pixel variations and maintain image quality. Such parameters may also be used to pre-age the pixel array 102. The parameters may also be used to evaluate the process yield for the fabrication of the pixel array 102. These and other parameters can be extracted by any of the pixel circuits described herein having a line, such as a Monitor line, connected to the pixel circuit for extracting or reading such parameters.
• V DATA - V OLED is a linear function of the threshold voltage (J3 ⁇ 4 of the drive transistor 220.
• the transient settling of such devices which is a function of both the threshold voltage and mobility, is considered. Assuming that the threshold voltage deviation among the TFT devices such as the drive transistor 220 is compensated, the voltage of the node 244 sampled at a constant interval after the beginning of integration is a function of mobility only of the TFT device such as the drive transistor 220 of interest.
• FIG. 3A-3C are signal timing diagrams of the control signals applied to the components in FIG. 2 to extract parameters such as voltage threshold and mobility from the drive transistor 220 and the turn on voltage of the OLED 222 in the drive circuit 200 assuming the drive transistor 220 is an n-type transistor.
• Such control signals could be applied by the controller 112 to the source driver 110, the gate driver 108 and the current supply and readout circuit 120 in FIG. 1.
• FIG. 3 A is a timing diagram showing the signals applied to the extraction circuit 200 to extract the threshold voltage and mobility from the drive transistor 220.
• FIG. 3A includes a signal 302 for the select input 230 in FIG.
• a signal 304 Oi) to the switch 260 a signal 306 ( ⁇ 2 ) for the switch 262, a signal 308 (fa) for the switch 264, a signal 310 ( ⁇ 4 ) for the switch 254, a programming voltage signal 312 for the programming data input 232 in FIG. 2, a voltage 314 of the node 244 in FIG. 2 and an output voltage signal 316 for the output 256 of the amplifier 250 in FIG. 2.
• FIG. 3 A shows the four phases of the readout process, a reset phase 320, an integration phase 322, a pre-charge phase 324 and a read phase 326.
• the process starts by activating a high select signal 302 to the select input 230.
• the select signal 302 will be kept high throughout the readout process as shown in FIG. 3 A.
• the input signal 304 ( ⁇ ) to the switch 260 is set high in order to provide a discharge path to ground.
• the signals 306, 308 and 310 ( ⁇ 2 , ⁇ ⁇ , ⁇ 4) to the switches 262, 264 and 250 are kept low in this phase.
• a high enough voltage level (V R S T TFT ) is applied to the programming data input 232 (Voa t a) to maximize the current flow through the drive transistor 220. Consequently, the voltage at the node 244 in FIG. 2 is discharged to ground to get ready for the next cycle.
• the signal 304 ( ⁇ 2 ) to the switch 262 stays high which provides a charging path from the voltage source 210 through the switch 262.
• the signals 304, 308 and 310 ( ⁇ , fo, ⁇ ) to the switches 260, 264 and 250 are kept low in this phase.
• the programming voltage input 232 (Voa t a) is set to a voltage level (V I N T TFT ) such that once the capacitor 240 (C ole d) is fully charged, the voltage at the node 244 is less than the turn-on voltage of the OLED 222. This condition will minimize any interference from the OLED 222 during the reading of the drive transistor 220.
• the signal 3 12 to the programming voltage input 232 (Voata) is lowered to VO EF in order to isolate the charge on the capacitor 240 (C oled ) from the rest of the circuit.
• the charge stored on capacitor 240 (C o i ed ) will be a function of the threshold voltage of the drive transistor 220.
• the voltage at the node 244 will experience an incomplete settling and the stored charge on the capacitor 240 (C oled ) will be a function of both the threshold voltage and mobility of the drive transistor 220. Accordingly, it is feasible to extract both parameters by taking two separate readings with short and long integration phases.
• the signals 304 and 306 ( ⁇ , ⁇ 2 ) to switches 260 and 262 are set low.
• the amplifier 250 is set in a unity feedback configuration.
• the signal 308 (fo) to the switch 264 goes high when the signal 306 ( ⁇ 2 ) to the switch 262 is set low.
• the switch 264 is closed, the parasitic capacitance 242 of the supply line is precharged to the common mode voltage, VCM.
• the common mode voltage, VCM is a voltage level which must be lower than the ON voltage of the OLED 222.
• the signal 3 10 ( ⁇ 4 ) to the switch 254 is set low to prepare the charge pump amplifier 250 for the read cycle.
• the signals 304, 306 and 3 10 ( ⁇ , ⁇ , ⁇ ) to the switches 260, 262 and 254 are set low.
• the signal 308 ( ⁇ 3 ) to the switch 264 is kept high to provide a charge transfer path from the drive circuit 202 to the charge-pump amplifier 250.
• a high enough voltage 3 12 (V RD _ TFT ) is applied to the programming voltage input 232 (Voata) to minimize the channel resistance of the drive transistor 220. If the integration cycle is long enough, the accumulated charge on the capacitor 252 (Ci nt ) is not a function of integration time. Accordingly, the output voltage of the charge-pump amplifier 250 in this case is equal to:
• the threshold voltage and the mobility of the drive transistor 220 may be extracted by reading the output voltage 256 of the amplifier 250 in the middle and at the end of the read phase 326.
• FIG. 3B is a timing diagram for the reading process of the threshold turn-on voltage parameter of the OLED 222 in FIG. 2.
• the reading process of the OLED 222 also includes four phases, a reset phase 340, an integration phase 342, a pre-charge phase 344 and a read phase 346.
• the reading process for OLED starts by activating the select input 230 with a high select signal 302.
• the timing of the signals 304, 306, 308, and 3 10 ( ⁇ , ⁇ 2 , (f>3, ⁇ ) to the switches 260, 262, 264 and 254 is the same as the read process for the drive transistor 220 in FIG. 3A.
• a programming signal 332 for the programming input 232, a signal 334 for the node 244 and an output signal 336 for the output of the amplifier 250 are different from the signals in FIG. 3 A.
• a high enough voltage level 332 (V R S T O LED ) is applied to the programming data input 232 (Vrja t a) to maximize the current flow through the drive transistor 220. Consequently, the voltage at the node 244 in FIG. 2 is discharged to ground through the switch 260 to get ready for the next cycle.
• the signal 306 ⁇ 2 ) to the switch 262 stays high which provides a charging path from the voltage source 210 through the switch 262.
• the programming voltage input 232 (V Dat a) is set to a voltage level 332 (V INT O LED ) such that once the capacitor 240 (C 0 ie d ) is fully charged, the voltage at the node 244 is greater than the turn- on voltage of the OLED 222.
• the drive transistor 220 is driving a constant current through the OLED 222.
• the drive transistor 220 is turned off by the signal 332 to the programming input 232.
• the capacitor 240 (C 0 ie d ) is allowed to discharge until it reaches the turn-on voltage of OLED 222 by the end of the pre-charge phase 344.
• a high enough voltage 332 (V RD O LED ) is applied to the programming voltage input 232 (Voa t a) to minimize the channel resistance of the drive transistor 220. If the pre-charge phase is long enough, the settled voltage across the capacitor 252 (Ci nt ) will not be a function of pre-charge time. Consequently, the output voltage 256 of the charge-pump amplifier 250 at the end of the read phase is given by:
• the signal 308 ( ⁇ 3) to the switch 264 is kept high to provide a charge transfer path from the drive circuit 202 to the charge-pump amplifier 250.
• the output voltage signal 336 may be used to determine the turn-on voltage of the OLED 220.
• FIG. 3C is a timing diagram for the direct reading of the drive transistor 220 using the extraction circuit 200 in FIG. 2.
• the direct reading process has a reset phase 350, a pre-charge phase 352 and an integrate/read phase 354.
• the readout process is initiated by activating the select input 230 in FIG. 2.
• the select signal 302 to the select input 230 is kept high throughout the readout process as shown in FIG. 3C.
• the signals 364 and 366 ( ⁇ , ⁇ 2 ) for the switches 260 and 262 are inactive in this readout process.
• the signals 368 and 370 ( ⁇ 3 , ⁇ ) for the switches 264 and 254 are set high in order to provide a discharge path to virtual ground.
• a high enough voltage 372 VR S T TFT
• VCM RST common-mode voltage 374
• the drive transistor 220 is turned off by applying an off voltage 372 (V OFF ) to the programming input 232 in FIG. 2.
• the common- mode voltage input 258 to the positive input of the amplifier 250 is raised to VCM RD in order to precharge the line capacitance.
• the signal 370 ( ⁇ 4 ) to the switch 254 is turned off to prepare the charge-pump amplifier 250 for the next cycle.
• the programming voltage input 232 (Voa t a) is raised to VINT TFT 372 to turn the drive transistor 220 on.
• the capacitor 240 (C O LED) starts to accumulate the charge until Voa t a minus the voltage at the node 244 is equal to the threshold voltage of the drive transistor 220.
• a proportional charge is accumulated in the capacitor 252 (C INT ). Accordingly, at the end of the read cycle 356, the output voltage 376 at the output 256 of the amplifier 250 is a function of the threshold voltage which is given by:
• the threshold voltage of the drive transistor 220 may be determined by the output voltage of the amplifier 250.
• the drive transistor 220 in FIG. 2 may be a p-type transistor.
• FIG. 4A-4C are signal timing diagrams of the signals applied to the components in FIG. 2 to extract voltage threshold and mobility from the drive transistor 220 and the OLED 222 when the drive transistor 220 is a p-type transistor.
• the source of the drive transistor 220 is coupled to the supply line 212 (VD) and the drain of the drive transistor 220 is coupled to the OLED 222.
• FIG. 4A is a timing diagram showing the signals applied to the extraction circuit 200 to extract the threshold voltage and mobility from the drive transistor 220 when the drive transistor 220 is a p-type transistor.
• FIG. 4A-4C are signal timing diagrams of the signals applied to the components in FIG. 2 to extract voltage threshold and mobility from the drive transistor 220 and the OLED 222 when the drive transistor 220 is a p-type transistor.
• FIG. 4A shows voltage signals 402-416 for the select input 232, the switches 260, 262, 264 and 254, the programming data input 230, the voltage at the node 244 and the output voltage 256 in FIG. 2.
• the data extraction is performed in three phases, a reset phase 420, an integrate/pre-charge phase 422, and a read phase 424.
• the select signal 402 is active low and kept low throughout the readout phases 420, 422 and 424.
• the signals 404 and 406 ( ⁇ , ⁇ ) to the switches 260 and 262 are kept low (inactive).
• the signals 408 and 410 ( ⁇ 3 , ⁇ 4 ) at the switches 264 and 254 are set to high in order to charge the node 244 to a reset common mode voltage level ⁇ ⁇ 1 .
• the common-mode voltage input 258 on the charge-pump input 258 (VCM ⁇ ) should be low enough to keep the OLED 222 off.
• the programming data input 232 Voa t a is set to a low enough value 412 (V R S T TFT ) to provide maximum charging current through the driver transistor 220.
• the common-mode voltage on the common voltage input 258 is reduced to VCM int and the programming input 232 (V Dat a) is increased to a level 412 (V INT TFT ) such that the drive transistor 220 will conduct in the reverse direction. If the allocated time for this phase is long enough, the voltage at the node 244 will decline until the gate to source voltage of the drive transistor 220 reaches the threshold voltage of the drive transistor 220. Before the end of this cycle, the signal 410 ( ⁇ 4 ) to the switch 254 goes low in order to prepare the charge-pump amplifier 250 for the read phase 424.
• the read phase 424 is initiated by decreasing the signal 412 at the programming input 232 (Voa t a) to V RD TFT SO as to turn the drive transistor 220 on.
• the charge stored on the capacitor 240 (CO LED ) is now transferred to the capacitor 254 (C INT ).
• the signal 408 ( ⁇ 3) to the switch 264 is set to low in order to isolate the charge-pump amplifier 250 from the drive circuit 202.
• the output voltage signal 416 Vout from the amplifier output 256 is now a function of the threshold voltage of the drive transistor 220 given by:
• FIG. 4B is a timing diagram for the in-pixel extraction of the threshold voltage of the OLED 222 in FIG. 2 assuming that the drive transistor 220 is a p-type transistor.
• the extraction process is very similar to the timing of signals to the extraction circuit 200 for an n-type drive transistor in FIG. 3 A.
• FIG. 4B shows voltage signals 432-446 for the select input 230, the switches 260, 262, 264 and 254, the programming data input 232, the voltage at the node 244 and the amplifier output 256 in FIG. 2.
• the extraction process includes a reset phase 450, an integration phase 452, a pre-charge phase 454 and a read phase 456. The major difference in this readout cycle in comparison to the readout cycle in FIG.
• V Dat a the programming data input 232
• the select signal 430 to the select input 232 is active low.
• the select input 232 is kept low throughout the readout process as shown in FIG. 4B.
• the readout process starts by first resetting the capacitor 240 (CO LED ) in the reset phase 450.
• the signal 434 ( ⁇ i) to the switch 260 is set high to provide a discharge path to ground.
• the signal 442 to the programming input 232 (Voa t a) is lowered to V R S T O LED in order to turn the drive transistor 220 on.
• the signals 434 and 436 ( ⁇ , ⁇ 2 ) to the switches 260 and 262 are set to off and on states respectively, to provide a charging path to the OLED 222.
• the capacitor 240 (CO LED ) is allowed to charge until the voltage 444 at node 244 goes beyond the threshold voltage of the OLED 222 to turn it on.
• the voltage signal 442 to the programming input 232 (Voa t a) is raised to VO EF to turn the drive transistor 220 off.
• the accumulated charge on the capacitor 240 (CO LED ) is discharged into the OLED 222 until the voltage 444 at the node 244 reaches the threshold voltage of the OLED 222.
• the signals 434 and 436 ( ⁇ , ⁇ 2 ) to the switches 260 and 262 are turned off while the signals 438 and 440 ( ⁇ 3 , ⁇ 4 ) to the switches 264 and 254 are set on. This provides the condition for the amplifier 250 to precharge the supply line 212 (VD) to the common mode voltage input 258 (VCM) provided at the positive input of the amplifier 250.
• the signal 430 ( ⁇ 4 ) to the switch 254 is turned off to prepare the charge-pump amplifier 250 for the read phase 456.
• the read phase 456 is initiated by turning the drive transistor 220 on when the voltage 442 to the programming input 232 (Voata) is lowered to V RD O LED -
• the charge stored on the capacitor 240 (CO LED ) is now transferred to the capacitor 254 (C INT ) which builds up the output voltage 446 at the output 256 of the amplifier 250 as a function of the threshold voltage of the OLED 220.
• FIG. 4C is a signal timing diagram for the direct extraction of the threshold voltage of the drive transistor 220 in the extraction system 200 in FIG. 2 when the drive transistor 220 is a p-type transistor.
• FIG. 4C shows voltage signals 462-476 for the select input 230, the switches 260, 262, 264 and 254, the programming data input 232, the voltage at the node 244 and the output voltage 256 in FIG. 2.
• the extraction process includes a precharge phase 480 and an integration phase 482.
• a dedicated final read phase 484 is illustrated which may be eliminated if the output of charge-pump amplifier 250 is sampled at the end of the integrate phase 482.
• the extraction process is initiated by simultaneous pre-charging of the drain storage capacitor 224, the source storage capacitor 226, the capacitor 240 (CO LED ) and the capacitor 242 in FIG. 2.
• the signals 462, 468 and 470 to the select line input 230 and the switches 264 and 254 are activated as shown in FIG. 4C.
• the signals 404 and 406 ( ⁇ , ⁇ 2 ) to the switches 260 and 262 are kept low.
• the voltage level of common mode voltage input 258 (VCM) determines the voltage on the supply line 212 and hence the voltage at the node 244.
• the common mode voltage (VCM) should be low enough such that the OLED 222 does not turn on.
• the voltage 472 to the programming input 232 (V Da ta) is set to a level (V R S T TFT ) low enough to turn the transistor 220 on.
• the signal 470 ( ⁇ 4 ) to the switch 254 is turned off in order to allow the charge-pump amplifier 250 to integrate the current through the drive transistor 220.
• the output voltage 256 of the charge-pump amplifier 250 will incline at a constant rate which is a function of the threshold voltage of the drive transistor 220 and its gate-to-source voltage.
• the signal 468 ( ⁇ 3 ) to the switch 264 is turned off to isolate the charge-pump amplifier 250 from the driver circuit 220. Accordingly, the output voltage 256 of the amplifier 250 is given by:
• ITFT is the drain current of the drive transistor 220 which is a function of the mobility and ty CM - V Data Ti nt is the length of the integration time.
• the signal 468 ( ⁇ 3 ) to the switch 264 is kept low to isolate the charge-pump amplifier 250 from the driver circuit 202.
• the output voltage 256 which is a function of the mobility and threshold voltage of the drive transistor 220, may be sampled any time during the read phase 484.
• FIG. 4D is a timing diagram for the direct reading of the OLED 222 in FIG. 2.
• the drive transistor 220 When the drive transistor 220 is turned on with a high enough gate-to-source voltage it may be utilized as an analog switch to access the anode terminal of the OLED 222. In this case, the voltage at the node 244 is essentially equal to the voltage on the supply line 212 (VD). Accordingly, the drive current through the drive transistor 220 will only be a function of the turn-on voltage of the OLED 222 and the voltage that is set on the supply line 212. The drive current may be provided by the charge-pump amplifier 250. When integrated over a certain time period, the output voltage 256 of the integrator circuit 206 is a measure of how much the OLED 222 has aged.
• FIG. 4D is a timing diagram showing the signals applied to the extraction circuit 200 to extract the turn-on voltage from the OLED 222 via a direct read.
• FIG. 4D shows the three phases of the readout process, a pre-charge phase 486, an integrate phase 487 and a read phase 488.
• FIG. 4D includes a signal 489n or 489p for the select input 230 in FIG. 2, a signal 490 ⁇ ⁇ ) to the switch 260, a signal 491 ( ⁇ 2 ) for the switch 262, a signal 492 ( ⁇ 3 ) for the switch 264, a signal 493 ( ⁇ 4 ) for the switch 254, a programming voltage signal 494n or 494p for the programming data input 232 in FIG. 2, a voltage 495 of the node 244 in FIG. 2 and an output voltage signal 496 for the output 256 of the amplifier 250 in FIG. 2.
• the process starts by activating the select signal corresponding to the desired row of pixels in array 102.
• the select signal 489n is active high for an n-type select transistor and active low for a p-type select transistor.
• a high select signal 489n is applied to the select input 230 in the case of an n-type drive transistor.
• a low signal 489p is applied to the select input 230 in the case of a p-type drive transistor for the drive transistor 220.
• the select signal 489n or 489p will be kept active during the pre-charge and integrate cycles 486 and 487.
• the ⁇ ⁇ and ⁇ 2 inputs 490 and 491 are inactive in this readout method.
• the switch signals 492 ⁇ 3 and 493 ⁇ are set high in order to provide a signal path such that the parasitic capacitance 242 of the supply line (C p ) and the voltage at the node 244 are pre-charged to the common-mode voltage (VCMO LED ) provided to the non-inverting terminal of the amplifier 250.
• a high enough drive voltage signal 494n or 494p (VON HTFT or VONJ TFT ) is applied to the data input 232 (V Da ta) to operate the drive transistor 220 as an analog switch. Consequently, the supply voltage 212 VD and the node 244 are pre-charged to the common-mode voltage (VCMO LED ) to get ready for the next cycle.
• the switch input 493 ⁇ is turned off in order to allow the charge-pump module 206 to integrate the current of the OLED 222.
• the output voltage 496 of the charge-pump module 206 will incline at a constant rate which is a function of the turn-on voltage of the OLED 222 and the voltage 495 set on the node 244, i.e. VCM 0LED -
• the switch signal 492 ⁇ 3 is turned off to isolate the charge-pump module 206 from the pixel circuit 202. From this instant beyond, the output voltage is constant until the charge-pump module 206 is reset for another reading.
• the output voltage of the integrator is given by:
• V ' out 1 1 OLED mt which is a measure of how much the OLED has aged.
• T int in this equation is the time interval between the falling edge of the switch signal 493 ( ⁇ 4 ) to the falling edge of the switch signal 492 ( ⁇ 3 ).
• the data extraction system 500 includes a drive circuit 502 and a readout circuit 504.
• the readout circuit 504 is part of the current supply and readout circuit 120 and gathers data from a column of pixels 104 as shown in FIG. 1 and includes a charge pump circuit 506 and a switch-box circuit 508.
• a voltage source 510 provides the supply voltage (VDD) to the drive circuit 502.
• the charge-pump and switch- box circuits 506 and 508 are implemented on the top or bottom side of the array 102 such as in the voltage drive 114 and the current supply and readout circuit 120 in FIG. 1. This is achieved by either direct fabrication on the same substrate as for the array 102 or by bonding a microchip on the substrate or a flex as a hybrid solution.
• the drive circuit 502 includes a drive transistor 520, an organic light emitting device 522, a drain storage capacitor 524, a source storage capacitor 526 and a select transistor 528.
• a select line input 530 is coupled to the gate of the select transistor 528.
• a programming input 532 is coupled through the select transistor 528 to the gate of the drive transistor 220.
• the select line input 530 is also coupled to the gate of an output transistor 534.
• the output transistor 534 is coupled to the source of the drive transistor 520 and a voltage monitoring output line 536.
• the drain of the drive transistor 520 is coupled to the supply voltage source 510 and the source of the drive transistor 520 is coupled to the OLED 522.
• the source storage capacitor 526 is coupled between the gate and the source of the drive transistor 520.
• the drain storage capacitor 524 is coupled between the gate and the drain of the drive transistor 520.
• the OLED 522 has a parasitic capacitance that is modeled as a capacitor 540.
• the monitor output voltage line 536 also has a parasitic capacitance that is modeled as a capacitor 542.
• the drive transistor 520 in this example is a thin film transistor that is fabricated from amorphous silicon.
• a voltage node 544 is the point between the source terminal of the drive transistor 520 and the OLED 522.
• the drive transistor 520 is an n-type transistor.
• the system 500 may be implemented with a p-type drive transistor in place of the drive transistor 520.
• the readout circuit 504 includes the charge-pump circuit 506 and the switch-box circuit 508.
• the charge-pump circuit 506 includes an amplifier 550 which has a capacitor 552 (Ci nt ) in a negative feedback loop.
• a switch 554 (S4) is utilized to discharge the capacitor 552 Ci nt during the pre-charge phase.
• the amplifier 550 has a negative input coupled to the capacitor 552 and the switch 554 and a positive input coupled to a common mode voltage input 558 (VCM).
• VCM common mode voltage input 558
• the amplifier 550 has an output 556 that is indicative of various extracted factors of the drive transistor 520 and OLED 522 as will be explained below.
• the switch-box circuit 508 includes several switches 560, 562 and 564 to direct the current to and from the drive circuit 502.
• the switch 560 is used during the reset phase to provide the discharge path to ground.
• the switch 562 provides the supply connection during normal operation of the pixel 104 and also during the integration phase of the readout process.
• the switch 564 is used to isolate the charge-pump circuit 506 from the supply line voltage source 510.
• the readout is normally performed through the monitor line 536.
• the readout can also be taken through the voltage supply line from the supply voltage source 510 similar to the process of timing signals in FIG. 3A-3C.
• Accurate timing of the input signals - ⁇ ) to the switches 560, 562, 564 and 554, the select input 530 and the programming voltage input 532 (V Da ta) is used to control the performance of the readout circuit 500.
• Certain voltage levels are applied to the programming data input 532 (VData) and the common mode voltage input 558 (VCM) during each phase of readout process.
• the three transistor drive circuit 502 may be programmed differentially through the programming voltage input 532 and the monitoring output 536. Accordingly, the reset and pre-charge phases may be merged together to form a reset/pre-charge phase and which is followed by an integrate phase and a read phase.
• FIG. 6A is a timing diagram of the signals involving the extraction of the threshold voltage and mobility of the drive transistor 520 in FIG. 5.
• the timing diagram includes voltage signals 602-618 for the select input 530, the switches 560, 562, 564 and 554, the programming voltage input 532, the voltage at the gate of the drive transistor 520, the voltage at the node 544 and the output voltage 556 in FIG. 5.
• the readout process in FIG. 6 A has a pre-charge phase 620, an integrate phase 622 and a read phase 624. The readout process initiates by simultaneous precharging of the drain capacitor 524, the source capacitor 526, and the parasitic capacitors 540 and 542.
• the select line voltage 602 and the signals 608 and 610 ( ⁇ 3 , ⁇ 4 ) to the switches 564 and 554 are activated as shown in FIG. 6A.
• the signals 604 and 606 ( ⁇ , ⁇ 2 ) to the switches 560 and 562 remain low throughout the readout cycle.
• the voltage level of the common mode input 558 determines the voltage on the output monitor line 536 and hence the voltage at the node 544.
• the voltage to the common mode input 558 (VCM TFT ) should be low enough such that the OLED 522 does not turn on.
• the voltage signal 612 to the programming voltage input 532 (V Da ta) is high enough (V R S T TFT ) to turn the drive transistor 520 on, and also low enough such that the OLED 522 always stays off.
• the voltage 602 to the select input 530 is deactivated to allow a charge to be stored on the capacitor 540 (CQ LED )-
• the voltage at the node 544 will start to rise and the gate voltage of the drive transistor 520 will follow that with a ratio of the capacitance value of the source capacitor 526 over the capacitance of the source capacitor 526 and the drain capacitor 524 [Csi/(Csi + Cs 2 )].
• the charging will complete once the difference between the gate voltage of the drive transistor 520 and the voltage at node 544 is equal to the threshold voltage of the drive transistor 520.
• the signal 610 ( ⁇ 4 ) to the switch 554 is turned off to prepare the charge-pump amplifier 550 for the read phase 624.
• the signal 602 to the select input 530 is activated once more.
• the voltage signal 612 on the programming input 532 (V RD TFT ) is low enough to keep the drive transistor 520 off.
• the charge stored on the capacitor 240 (C OLED ) is now transferred to the capacitor 254 (C INT ) and creates an output voltage 618 proportional to the threshold voltage of the drive transistor 520:
• V - ⁇ ° d _ (v - V )
• the signal 608 ( ⁇ 3 ) to the switch 564 turns off to isolate the charge-pump circuit 506 from the drive circuit 502.
• FIG. 6B is a timing diagram for the input signals for extraction of the turn- on voltage of the OLED 522 in FIG. 5.
• FIG. 6B includes voltage signals 632-650 for the select input 530, the switches 560, 562, 564 and 554, the programming voltage input 532, the voltage at the gate of the drive transistor 520, the voltage at the node 544, the common mode voltage input 558, and the output voltage 556 in FIG. 5.
• the readout process in FIG. 6B has a pre-charge phase 652, an integrate phase 654 and a read phase 656. Similar to the readout for the drive transistor 220 in FIG.
• the readout process starts with simultaneous pre- charging of the drain capacitor 524, the source capacitor 526, and the parasitic capacitors 540 and 542 in the pre-charge phase 652.
• the signal 632 to the select input 530 and the signals 638 and 640 ( ⁇ 3 , ⁇ ) to the switches 564 and 554 are activated as shown in FIG. 6B.
• the signals 634 and 636 ( ⁇ , ⁇ 2 ) remain low throughout the readout cycle.
• the input voltage 648 (VCM Pre ) to the common mode voltage input 258 should be high enough such that the OLED 522 is turned on.
• the voltage 642 (Vp re OLED ) to the programming input 532 (Voata) is low enough to keep the drive transistor 520 off.
• the signal 632 to the select input 530 is deactivated to allow a charge to be stored on the capacitor 540 (C OLED )-
• the voltage at the node 544 will start to fall and the gate voltage of the drive transistor 520 will follow with a ratio of the capacitance value of the source capacitor 526 over the capacitance of the source capacitor 526 and the drain capacitor 524 [Csi/(Csi + Cs 2 )].
• the discharging will complete once the voltage at node 544 reaches the ON voltage (VO LED ) of the OLED 522.
• the signal 640 ( ⁇ 4 ) to the switch 554 is turned off to prepare the charge-pump circuit 506 for the read phase 656.
• the signal 632 to the select input 530 is activated once more.
• the voltage 642 on the (V RD O LED ) programming input 532 should be low enough to keep the drive transistor 520 off.
• the charge stored on the capacitor 540 (CO LED ) is then transferred to the capacitor 552 (C INT ) creating an output voltage 650 at the amplifier output 556 proportional to the ON voltage of the OLED 522.
• the signal 638 ( ⁇ 3 ) turns off before the end of the read phase 656 to isolate the charge-pump circuit 508 from the drive circuit 502.
• the monitor output transistor 534 provides a direct path for linear integration of the current for the drive transistor 520 or the OLED 522.
• the readout may be carried out in a pre-charge and integrate cycle.
• FIG. 6C shows timing diagrams for the input signals for an additional final read phase which may be eliminated if the output of charge-pump circuit 508 is sampled at the of the integrate phase.
• FIG. 6C includes voltage signals 660-674 for the select input 530, the switches 560, 562, 564 and 554, the programming voltage input 532, the voltage at the node 544, and the output voltage 556 in FIG. 5.
• the readout process in FIG. 6C therefore has a pre-charge phase 676, an integrate phase 678 and an optional read phase 680.
• the direct integration readout process of the n-type drive transistor 520 in FIG. 5 as shown in FIG. 6C is initiated by simultaneous pre-charging of the drain capacitor 524, the source capacitor 526, and the parasitic capacitors 540 and 542.
• the signal 660 to the select input 530 and the signals 666 and 668 ( ⁇ 3 , ⁇ 4 ) to the switches 564 and 554 are activated as shown in FIG. 6C.
• the signals 662 and 664 ( ⁇ , ⁇ 2 ) to the switches 560 and 562 remain low throughout the readout cycle.
• the voltage level of the common mode voltage input 558 (VCM) determines the voltage on the monitor output line 536 and hence the voltage at the node 544.
• the voltage signal (VCM TFT ) of the common mode voltage input 558 is low enough such that the OLED 522 does not turn on.
• the signal 670 (VO N TFT ) to the programming input 532 (Voa t a) is high enough to turn the drive transistor 520 on.
• the signal 668 ( ⁇ 4 ) to the switch 554 is turned off in order to allow the charge-pump amplifier 550 to integrate the current from the drive transistor 520.
• the output voltage 674 of the charge-pump amplifier 550 declines at a constant rate which is a function of the threshold voltage, mobility and the gate-to-source voltage of the drive transistor 520.
• the signal 666 ( ⁇ 3 ) to the switch 564 is turned off to isolate the charge-pump circuit 508 from the drive circuit 502. Accordingly, the output voltage is given by:
• I TFT is the drain current of drive transistor 520 which is a function of the mobility and ( oata ⁇ V CM ⁇ h ) ⁇ Tint is the length of the integration time.
• the output voltage 674 which is a function of the mobility and threshold voltage of the drive transistor 520, may be sampled any time during the read phase 680.
• FIG. 6D shows a timing diagram of input signals for the direct reading of the on (threshold) voltage of the OLED 522 in FIG. 5.
• FIG. 6D includes voltage signals 682- 696 for the select input 530, the switches 560, 562, 564 and 554, the programming voltage input 532, the voltage at the node 544, and the output voltage 556 in FIG. 5.
• the readout process in FIG. 6C has a pre-charge phase 697, an integrate phase 698 and an optional read phase 699.
• the readout process in FIG. 6D is initiated by simultaneous precharging of the drain capacitor 524, the source capacitor 526, and the parasitic capacitors 540 and 542.
• the signal 682 to the select input 530 and the signals 688 and 690 ( ⁇ , ⁇ 4 ) to the switches 564 and 554 are activated as shown in FIG. 6D.
• the signals 684 and 686 ( ⁇ , ⁇ ) remain low throughout the readout cycle.
• the voltage level of the common mode voltage input 558 (VCM) determines the voltage on the monitor output line 536 and hence the voltage at the node 544.
• the voltage signal (VCMO LED ) of the common mode voltage input 558 is high enough such to turn the OLED 522 on.
• the signal 692 (VO EF TFT ) of the programming input 532 (V Da ta) is low enough to keep the drive transistor 520 off.
• the signal 690 ( ⁇ 4 ) to the switch 552 is turned off in order to allow the charge-pump amplifier 550 to integrate the current from the OLED 522.
• the output voltage 696 of the charge-pump amplifier 550 will incline at a constant rate which is a function of the threshold voltage and the voltage across the OLED 522.
• the signal 668 ( ⁇ 3) to the switch 564 is turned off to isolate the charge-pump circuit 508 from the drive circuit 502. Accordingly, the output voltage is given by:
• V T . T m
• IO LED is the OLED current which is a function of (V CM - V th ), and Ti nt is the length of the integration time.
• the output voltage which is a function of the threshold voltage of the OLED 522, may be sampled any time during the read phase 699.
• the controller 112 in FIG. 1 may be conveniently implemented using one or more general purpose computer systems, microprocessors, digital signal processors, microcontrollers, application specific integrated circuits (ASIC), programmable logic devices (PLD), field programmable logic devices (FPLD), field programmable gate arrays (FPGA) and the like, programmed according to the teachings as described and illustrated herein, as will be appreciated by those skilled in the computer, software and networking arts.
• ASIC application specific integrated circuits
• PLD programmable logic devices
• FPLD field programmable logic devices
• FPGA field programmable gate arrays
• controllers may be implemented on a computer system or systems that extend across any network environment using any suitable interface mechanisms and communications technologies including, for example telecommunications in any suitable form (e.g., voice, modem, and the like), Public Switched Telephone Network (PSTNs), Packet Data Networks (PDNs), the Internet, intranets, a combination thereof, and the like.
• PSTNs Public Switched Telephone Network
• PDNs Packet Data Networks
• the Internet intranets, a combination thereof, and the like.
• the flow diagram in FIG. 7 is representative of example machine readable instructions for determining the threshold voltages and mobility of a simple driver circuit that allows maximum aperture for a pixel 104 in FIG. 1.
• the machine readable instructions comprise an algorithm for execution by: (a) a processor, (b) a controller, and/or (c) one or more other suitable processing device(s).
• the algorithm may be embodied in software stored on tangible media such as, for example, a flash memory, a CD-ROM, a floppy disk, a hard drive, a digital video (versatile) disk (DVD), or other memory devices, but persons of ordinary skill in the art will readily appreciate that the entire algorithm and/or parts thereof could alternatively be executed by a device other than a processor and/or embodied in firmware or dedicated hardware in a well known manner (e.g., it may be implemented by an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable logic device (FPLD), a field programmable gate array (FPGA), discrete logic, etc.).
• ASIC application specific integrated circuit
• PLD programmable logic device
• FPLD field programmable logic device
• FPGA field programmable gate array
• any or all of the components of the extraction sequence could be implemented by software, hardware, and/or firmware.
• some or all of the machine readable instructions represented by the flowcharts herein, including FIG. 7, may be implemented manually.
• the example algorithm is described with reference to the flowcharts illustrated herein, including in FIG. 7, persons of ordinary skill in the art will readily appreciate that many other methods of implementing the example machine readable instructions may alternatively be used.
• the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.
• a pixel or pixel circuit 104 under study is selected by turning the corresponding select and programming lines on (700). Once the pixel 104 is selected, the readout is performed in four phases. The readout process begins by first discharging the parasitic capacitance across the OLED (C oled ) m the reset phase (702). Next, the drive transistor is turned on for a certain amount of time which allows some charge to be accumulated on the capacitance across the OLED C 0 ied (704). In the integrate phase, the select transistor is turned off to isolate the charge on the capacitance across the OLED C 0 ied and then the line parasitic capacitance (C P ) is precharged to a known voltage level (706).
• the drive transistor is turned on again to allow the charge on the capacitance across the OLED C 0 i e d to be transferred to the charge-pump amplifier output in a read phase (708).
• the amplifier's output represent a quantity which is a function of mobility and threshold voltage.
• the readout process is completed by deselecting the pixel to prevent interference while other pixels are being calibrated (710).
• FIG. 8 is a flow diagram of different extraction cycles and parameter applications for pixel circuits such as the two transistor circuit in FIG. 2 and the three transistor circuit in FIG. 5.
• One process is an in-pixel integration that involves charge transfer (800). A charge relevant to the parameter of interest is accumulated in the internal capacitance of the pixel (802). The charge is then transferred to the external read-out circuit such as the charge-pump or integrator to establish a proportional voltage (804).
• Another process is an off-pixel integration or direct integration (810). The device current is directly integrated by the external read-out circuit such as the charge-pump or integrator circuit (812).
• the generated voltage is post-processed to resolve the parameter of interest such as threshold voltage or mobility of the drive transistor or the turn- on voltage of the OLED (820).
• the extracted parameters may be then used for various applications (822). Examples of using the parameters include modifying the programming data according to the extracted parameters to compensate for pixel variations (824). Another example is to pre-age the panel of pixels (826). Another example is to evaluate the process yield of the panel of pixels after fabrication (828).
• FIG. 9 is a block diagram and chart of the components of a data extraction system that includes a pixel circuit 900, a switch box 902 and a readout circuit 904 that may be a charge pump/integrator.
• the building components (910) of the pixel circuit 900 include an emission device such as an OLED, a drive device such as a drive transistor, a storage device such as a capacitor and access switches such as a select switch.
• the building components 912 of the switch box 902 include a set of electronic switches that may be controlled by external control signals.
• the building components 914 of the readout circuit 904 include an amplifier, a capacitor and a reset switch.
• the parameters of interest may be stored as represented by the box 920.
• the parameters of interest in this example may include the threshold voltage of the drive transistor, the mobility of the drive transistor and the turn-on voltage of the OLED.
• the functions of the switch box 902 are represented by the box 922.
• the functions include steering current in and out of the pixel circuit 900, providing a discharge path between the pixel circuit 900 and the charge-pump of the readout circuit 904 and isolating the charge- pump of the readout circuit 904 from the pixel circuit 900.
• the functions of the readout circuit 904 are represented by the box 924.
• One function includes transferring a charge from the internal capacitance of the pixel circuit 900 to the capacitor of the readout circuit 904 to generate a voltage proportional to that charge in the case of in-pixel integration as in steps 800-804 in FIG. 8.
• Another function includes integrating the current of the drive transistor or the OLED of the pixel circuit 900 over a certain time in order to generate a voltage proportional to the current as in steps 810-814 of FIG. 8.
• FIG. 10 is a timing diagram of the signals involving the extraction of the threshold voltage and mobility of the drive transistor 520 in a modified version of the circuit of FIG. 5 in which the output transistor 534 has its gate connected to a separate control signal line RD rather than the SEL line.
• the readout process in FIG. 10 has a pre-charge phase 1001, an integrate phase 1002 and a read phase 1003. During the pre-charge phase 1001, the voltages VA and V B at the gate and source of the drive transistor 520 are reset to initial voltages by having both the SEL and RD signals high.
• the signal RD goes low, the gate voltage VA remains at V ⁇ t , and the voltage V B at the source (node 544) is charged back to a voltage which is a function of TFT characteristics (including mobility and threshold voltage), e.g., (Vini t - V T ). If the integrate phase 1002 is long enough, the voltage V B will be a function of threshold voltage (V T ) only.
• the signal SEL is low, VA drops to (V ⁇ t + Vb - Vt) and V B drops to Vb.
• the charge is transferred from the total capacitance C T at node 544 to the integrated capacitor (Ci nt ) 552 in the readout circuit 504.
• the output voltage V out can be read using an Analog-to-Digital Converter (ADC) at the output of the charge amplifier 550.
• ADC Analog-to-Digital Converter
• a comparator can be used to compare the output voltage with a reference voltage while adjusting V ⁇ t until the two voltages become the same.
• the reference voltage may be created by sampling the line without any pixel connected to the line during one phase and sampling the pixel charge in another phase.
• FIG. 11 is a timing diagram for the input signals for extraction of the turn- on voltage of the OLED 522 in the modified version of the circuit of FIG. 5.
• FIG. 12 is a circuit diagram of a pixel circuit for reading the pixel status by initializing the nodes externally.
• the drive transistor Tl has a drain connected to a supply voltage Vdd, a source connected to an OLED Dl, and a gate connected to a Vdata line via a switching transistor T2.
• the gate of the transistor T2 is connected to a write line WR.
• a storage capacitor Cs is connected between a node A (between the gate of the drive transistor Tl and the transistor T2) and a node B (between the source of the drive transistor Tl and the OLED).
• a read transistor T3 couples the node B to a Monitor line and is controlled by the signal on a read line RD.
• FIG. 13 is a timing diagram that illustrates an operation of the circuit of FIG. 12 that initializes the nodes externally.
• the drive transistor Tl is programmed with an OFF voltage V0, and the OLED voltage is set externally to Vrst via the Monitor line.
• the read signal RD turns off the transistor T3, and so the OLED voltage is discharged through the OLED Dl until the OLED turns off (creating the OLED on voltage threshold).
• the OFF voltage of the OLED is transferred to an external readout circuit (e.g., using a charge amplifier) via the Monitor line.
• the 14 is a flow chart illustrating the reading of the pixel status by initializing the nodes externally.
• the internal nodes are reset so that at least one pixel component is ON.
• the second step provides time for the internal/external nodes to settle to a desired state, e.g., the OFF state.
• the third step reads the OFF state values of the internal nodes.
• FIG. 15 is a timing diagram that illustrates a modified operation of the circuit of FIG. 12, still initializing the nodes internally.
• the drive transistor Tl is programmed with an ON voltage VI .
• the OLED voltage rises to a voltage higher than its ON voltage threshold.
• the drive transistor Tl is programmed with an OFF voltage V0, and so the OLED voltage is discharged through the OLED Dl until the OLED turns off (creating the OLED ON voltage threshold).
• the OLED ON voltage threshold is transferred to an external readout circuit (e.g., using a charge amplifier).
• FIG. 16 is a flow chart illustrating the reading of the pixel status by initializing the nodes internally.
• the first step turns on the selected pixels for measurement so that the internal/external nodes settle to the ON state.
• the second step turns off the selected pixels so that the internal/external nodes settle to the OFF state.
• the third step reads the OFF state values of the internal nodes.
• FIG. 17 is a circuit diagram illustrating two of the pixel circuits shown in FIG. 12 connected to a common Monitor line via the respective read transistors T3 of the two circuits
• FIG. 18 is a timing diagram illustrating the operation of the combined circuits for reading the pixel charges with the shared Monitor line.
• the pixels are programmed with OFF voltages V01 and V03, and the OLED voltage is reset to VB0.
• the read signal RD is OFF, and the pixel intended for measurement is programmed with an ON voltage VI while the other pixel stays in an OFF state.
• the OLED voltage of the pixel selected for measurement is higher than its ON threshold voltage, while the other pixel connected to the Monitor line stays in the reset state.
• the pixel programmed with an ON voltage is also turned off by being programmed with an OFF voltage V02.
• the OLED voltage of the selected pixel discharges to its ON threshold voltage.
• the OLED voltage is read back.
• FIG. 19 is a flow chart illustrating the reading of the pixel status with a shared Monitor line.
• the first step turns off all the pixels and resets the internal/external nodes.
• the second step turns on the selected pixels for measurement so that the internal/external nodes are set to an ON state.
• the third step turns off the selected pixels so that the internal/external nodes settle to an OFF state.
• the fourth step reads the OFF state values of the internal nodes.
• FIG. 20A illustrates a pixel circuit in which a line Vdata (programming voltage) is coupled to a node A via a switching transistor T2, and a line Monitor/Vref (Vref is a reference voltage) is coupled to a node B via a readout transistor T3.
• Node A is connected to the gate of a drive transistor Tl and to one side of a storage capacitor Cs.
• FIG. 20B is a timing diagram for operation of the circuit of FIG. 20A using charge-based compensation.
• Node B is connected to the source of the drive transistor Tl and to the other side of the capacitor Cs, as well as the drain of a switching transistor T4 connected between the source of the drive transistor and a supply voltage source Vdd.
• the operation in this case is as follows:
• the pixel is programmed with a programming voltage V P supplied to node A from the line Vdata via the transistor T2, and node B is connected to a reference voltage Vref from line VMonitor/Vref via the transistor T3.
• a read signal RD turns off the transistor T3, and so the voltage at node B is adjusted to partially compensate for variation (e.g., aging) of the drive transistor Tl .
• a write signal WR turns off the transistor T2
• a signal EM turns on the transistor T4 to connect the supply voltage Vdd to the drive transistor Tl .
• the current of the drive transistor Tl is controlled by the voltage stored in a capacitor Cs , and the same current goes to the OLED.
• a reference voltage Vref is supplied to node A from the line Vdata via the switching transistor T2, and node B is supplied with a programming voltage Vp from the Monitor/Vdata line via the read transistor T3.
• the node A is charged to the reference voltage Vref supplied from the line Vdata via the transistor T2, and node B is supplied with a programming voltage Vp from the line monitor/Vref via the transistor T3.
• the read signal RD turns off the transistor T3, and so the voltage at node B is adjusted to partially compensate for variation (or aging) of the drive transistor Tl .
• the write signal WR turns off the transistor T2, and after a delay (that can be zero), the signal EM turns on the transistor T4 to connect the supply voltage Vdd to the drive transistor Tl .
• the current of the drive transistor Tl is controlled by the voltage stored in the storage capacitor Cs , and the same current goes to the OLED.
• FIG. 21 is a timing diagram for operation of the circuit of FIG. 20A to produce a readout of the current and/or the voltage of the drive transistor Tl .
• the pixel is programmed either with or without a discharge period. If there is a discharge period, it can be a short time to partially discharge the capacitor Cs, or it can be long enough to discharge the capacitor Cs until the drive transistor Tl is off.
• the current of the drive transistor Tl can be read by applying a fixed voltage during the readout time, or the voltage created by the drive transistor Tl acting as an amplifier can be read by applying a fixed current from the line Monitor/Vref through the read transistor T3.
• the voltage created at the node B as a result of discharge can be read back. This voltage is representative of the threshold voltage of the drive transistor Tl .
• FIG. 22 is a timing diagram for operation of the circuit of FIG. 20A to produce a readout of the OLED voltage.
• the pixel circuit is programmed so that the drive transistor Tl acts as a switch (with a high ON voltage), and the current or voltage of the OLED is measured through the transistors Tl and T3.
• several current/voltage points are measured by changing the voltage at node A and node B, and from the equation between the currents and voltages, the voltage of the OLED can be extracted.
• the OLED voltage affects the current of the drive transistor Tl more if that transistor is operating in the linear regime; thus, by having current points in the linear and saturation operation regimes of the drive transistor Tl, one can extract the OLED voltage from the voltage-current relationship of the transistor Tl .
• the pixels that are not selected for OLED measurement are turned OFF by applying an OFF voltage to their drive transistors Tl .
• FIG. 23 is a timing diagram for a modified operation of the circuit of FIG. 20A to produce a readout of the OLED voltage, as follows:
• the OLED is charged with an ON voltage during a reset phase.
• the signal Vdata turns off the drive transistor Tl during a discharge phase, and so the OLED voltage is discharged through the OLED to an OFF voltage.
• FIG. 24 illustrates a circuit for extracting the parasitic capacitance from a pixel circuit using external compensation.
• the internal nodes of the pixels are different during the measurement and driving cycles. Therefore, the effect of parasitic capacitance will not be extracted properly.
• Another technique is to extract the parasitic effect experimentally. For example, one can subtract the two set of measurements, and add the difference to other measurements by a gain. The gain can be extracted experimentally. For example, the scaled difference can be added to a measurement set done for a panel for a specific gray scale. The scaling factor can be adjusted experimentally until the image on the panel meets the specifications. This scaling factor can be used as a fixed parameter for all the other panels after that.
• FIG. 24 shows a pixel with a readout line for measuring the pixel current.
• the voltage of the readout line is controlled by a measurement unit bias voltage (VB).
• FIG. 25 illustrates a pixel circuit that can be used for current measurement.
• the pixel is programmed with a calibrated programming voltage V cal , and a monitor line is set to a reference voltage V re f. Then the current of a drive transistor Tl is measured by turning on a transistor T3 with a control signal RD.
• the voltage at node B is at V 0 i ed
• the voltage at node A changes from V ca i to V ca i + (V oled - V ref )Cs/(Cp+Cs), where V ca i is the calibrated programming voltage, C P is the total parasitic capacitance at node A, and V ref is the monitor voltage during programming.
• the gate-source voltage VGS of the drive transistor is different during the programming cycle (Vp-V ref ) and the driving cycle [(Vp-V ref )Cs/(C P +Cs) - V oled Cp/(Cp+Cs)]. Therefore, the current during programming and measurement is different from the driving current due to parasitic capacitance which will affect the compensation, especially if there is significant mobility variation in the drive transistor Tl .
• V B the gate-source voltage VQS during measurement will be [(V P -V ref ) C s /(Cp+C s ) - V B Cp/(Cp+C s )].
• V B i and V B2 Two different V B 's can be used to extract the value of the parasitic capacitance Cp.
• the voltage Vp is the same and the current for the two cases will be different.
• V B i-V B2 V B i-V B2
• Cp Cp/(Cp+Cs).
• FIG. 26 A pixel with charge readout capability is illustrated in FIG. 26. Here, either an internal capacitor is charged and then the charge is transferred to a charge integrator, or a current is integrated by a charge readout circuit. In the case of integrating the current, the method described above can be used to extract the parasitic capacitance.
• two different integration times may be used to extract the parasitic capacitance, in addition to adjusting voltages directly.
• the OLED capacitance can be used to integrate the pixel current internally, and then a charge-pump amplifier can be used to transfer it externally.
• the method described above can be used to change voltages.
• each pixel can be shared or replaced by other signals and achieve the same functionality.
• the pixel circuit of FIG. 26 is merely exemplary. Also one can easily modify the position of the load (e.g., a light emitting diode). In addition, one can change each of the TFTs to n-type TFT based on complementary circuit concept. Pixel circuits like the one shown in FIG.
• a charge-based in-pixel compensation by establishing a charge at an internal node of the pixel circuit (typically stored in a storage capacitor Cs), and allowing at least some of that charge to be removed or to discharge as a function of Tl and/or the OLED so that a parameter like the threshold voltage of Tl can be developed inside the pixel circuit.
• an internal node of the pixel circuit typically stored in a storage capacitor Cs
• switch transistor Tb2 eliminates the unwanted emission during the programming/compensation cycle because it redirects the current to through to Vb2.
• This circuit also allows reading the pixel or OLED current/voltage as described elsewhere herein.
• This pixel also enables to read TFT or OLED current, voltage or charge through Tm.
• the pixel can be programmed with a predefined (or calculated voltage) and then turn the Tm ON.
• voltage of the monitor line can be smaller than the OLED voltage since Tern is ON. This will make sure the OLED is off.
• the pixel current can be read.
• the WR and RD are ON and EM is OFF, and a current or voltage is applied to the monitor and the current or voltage is read back.
• the applied current or voltage to monitor line can be any value including zero.
• the pixel can be programmed so that the drive TFT acts as switch (for one example, Vbl can be adjusted to turn Td to a switch). Then the OLED current or voltage can be read through monitor line.
• the EM signal can be off, and therefore no current is going through Td, and so the OLED current or voltage can be read.
• Vbl can be selected in a way that node D goes to VOLED during programming cycle. And then the effect of OLED voltage on TFT can be read back after TFT programming.
• EM signal is divided into two signals. This allows using Tb to reset node D for compensation voltage generation based on charging/discharging function as described by waveform in FIG. 27. As can be seen EM' can be the EM signal of the next row.
• This pixel also enables to read TFT or OLED current, voltage or charge through Tm.
• the pixel can be programmed with a predefined (or calculated voltage) and then turn the Tm ON.
• voltage of the monitor line can be smaller than the OLED voltage since Tern is ON. This will make sure the OLED is off.
• the pixel current can be read.
• the WR and RD are ON and EM is OFF, and a current or voltage is applied to the monitor and the current or voltage is read back.
• the applied current or voltage to monitor line can be any value including zero.
• the pixel For reading the OLED current or voltage, the pixel can be programmed so that the drive TFT acts as switch (for one example, Vbl can be adjusted to turn Td to a switch). Then the OLED current or voltage can be read through monitor line.
• the drive TFT acts as switch (for one example, Vbl can be adjusted to turn Td to a switch). Then the OLED current or voltage can be read through monitor line.
• the EM' signal can be off, and therefore no current is going through Td, and so the OLED current or voltage can be read.
• Vbl can be selected in a way that node D goes to VOLED during programming cycle. And then the effect of OLED voltage on TFT can be read back after TFT programming.
• EM signal is divided into two signals. This allows using Tb to reset node D for compensation voltage generation based on charging/discharging function as described by waveform in FIG. 28. Also, Tm and Tb2 are shared.
• EM' can be the EM signal of the next row.
• This pixel circuit 104 also allows TFT or OLED current, voltage, or charge to be read or extracted through Tm.
• the pixel can be programmed with a predefined (or calculated voltage), and then the Tm is turned ON.
• the voltage of the monitor line can be smaller than the OLED voltage because Tern is ON. This will make sure the OLED is off.
• the pixel current can be read.
• the WR and RD are ON and EM is OFF, and a current or voltage is applied to the monitor and the current or voltage is read back.
• the applied current or voltage to monitor line can be any value including zero.
• the pixel For reading OLED (current/voltage/charge), the pixel can be programmed so that the TFT provide zero current. Then the OLED current or voltage can be read through monitor line.
• the EM' signal can be off, and therefore no current is going through Td, and so the OLED current or voltage can be read.
• Vbl can be selected in a way that node D goes to VOLED during programming cycle. And then the effect of OLED voltage on TFT can be read back after TFT programming.
• node B is reset through Tm and monitor line and node C is charged to Vdata while EM is off.
• compensation cycle cycle 4
• node B is charged with drive TFT (Td) to a compensation voltage which is the function of Td characteristics.
• driving cycle (6) EM is on and so the gate of Td is defined by the programming voltage and compensation voltage stored in Cs.
• This pixel also enables to read TFT or OLED current, voltage or charge through Tm.
• the pixel For drive TFT readout of its current or voltage, the pixel can be programmed with a predefined (or calculated voltage), and then Tm is turned ON.
• voltage of the monitor line can be smaller than the OLED voltage since Tern is ON. This will make sure the OLED is off. At this point the pixel current can be read.
• the WR and RD are ON and EM is OFF, and a current or voltage is applied to the monitor and the current or voltage is read back.
• the applied current or voltage to monitor line can be any value including zero.
• the pixel For reading the OLED current or voltage, the pixel can be programmed so that the TFT provide zero current. Then the EM is ON and the OLED current or voltage can be read through monitor line.
• the line connected to T2 is the data voltage and the line connected to T3 is the Monitor/Vref voltage.
• the operation in this example can proceed as follows: [00197] During the first cycle, the pixel is programmed with programming voltage (VP) and node B is connected to a reference voltage.
• VP programming voltage
• RD signal turns off and so the voltage at node B is adjusted partially to compensate for Tl variation (or aging).
• the line connected to T2 is the reference voltage (Vref) and the line connected to T3 is Monitor/Vdata line.
• node A is charged to a reference voltage and node B is connected to a programming voltage (VP).
• VP programming voltage
• RD signal turns off and so the voltage at node B is adjusted partially to compensate for Tl variation (or aging).
• the pixel is programmed (either with discharge or without discharge period). If there is a discharge period, it can be a relatively short time to partially discharge the capacitor Cs or it can be long to discharge the capacitor until the drive Tl is off. In the case of a short discharge time, the current of Tl can be read by applying a fixed reference voltage during readout time or read the voltage created by the drive Tl acting as an amplifier by applying a fixed current through T3. In the case of a long discharge time, the voltage created at node B as a result of discharge can be read back. This voltage will be representative of the threshold voltage of Tl .
• WR signal can stay on during the whole process.
• Tl is programmed to act as a switch (with high ON voltage). And the current or voltage of OLED can be measured or extracted through T3 and Tl .
• a few current/voltage points are measured by changing the voltage and Node A and Node Bl, and from the equation between the currents and voltages, the voltage of OLED can be extracted.
• the OLED voltage can affect the current of Tl more if Tl is in its linear region, thus, by having current points in linear and saturation operation regime of Tl, the OLED voltage can be extracted from the Tl voltage-current relationship.
• the OLED readout of its current or voltage can proceed as follows:
• the OLED is charged with an ON voltage during the reset phase.
• Drive Tl turns off and so the OLED voltage is discharged through OLED to an OFF voltage.
• the off voltage is read back through Tl .
• the inverse of RD or WR can be used as the EM signal (so the EM signal can correspond to /RD or /WR).
• the signal can be inverted and passed to the pixel or a complimentary TFT can be used to create the inverse function.
• a complimentary TFT can be used to create the inverse function.
• PMOS switch is used for RD TFT
• NMOS switch can be used for EM TFT.
• the inverse of the next RD or WR signals can be used instead as an EM signal of the current row.
• the inverse function of RD and WR can be implemented outside the pixel circuit and pass to it or complementary TFT combination can be used.
• FIG. 34 demonstrates another way of implementing an emission EM function in a charge-based pixel circuit 104.
• the inverse of control signals RD and WR can be used to create the emission EM signal. As a result, if any of them is ON, the pixel circuit will be disconnected from the power source, VDD.
• the inverse function of RD and WR (/RD and /WR) can be implemented outside the pixel circuit 104 and passed to it, or complimentary TFT combinations can be used.
• NMOS TFT can work for T4 and T5, it is recommended to use (but not necessary) PMOS for these TFTS, and NMOS for WR and RD (e.g., S2 and S3).
• the pixel circuit 104 in FIG. 34 includes a drive transistor Tl connected to a light emitting device (OLED), a storage device (Cs) coupled to the drive transistor Tl and storing programming information to cause the OLED to emit light according to the programming information via Tl .
• Cs can be but does not have to be connected directly across a gate and a first terminal (source or drain depending on whether Tl is NMOS or PMOS) of Tl .
• a second terminal of Tl (the other of the source or drain) can be connected to the OLED.
• the pixel circuit 34 includes a first switch S2 connected between Tl and a first line (which can carry programming information Vdata or a reference voltage Vref) to connect Tl to the first line according to a first signal (e.g., WR).
• the pixel circuit 104 includes a second switch S3 connected between Tl and a second line (which has at least two functions) to connect the second line to Tl according to a second signal (e.g., RD).
• the second line can be used as a monitor line to monitor a current or voltage read from one or more components of the pixel circuit.
• the second line can also be used to provide a reference voltage Vref or programming information Vdata to an internal node B of the pixel circuit.
• the pixel circuit 104 of FIG. 34 includes a third switch (S4) and a fourth switch (S5) connected in line between Tl and a power supply Vdd.
• the third switch S4 and the fourth switch S5 and their respective control signals have an inverse function of the first switch S2 and the second switch S3 and their respective control signals.
• S2 and S3 can be n-type transistors, while S4 and S5 are p-type.
• S2 and S3 can be p-type transistors, while S4 and S5 are n-type.
• S2-S5 can be the same type of transistor, n-type or p-type, but S4 and S5 are controlled by signals that are the inverse of a signal that controls S2 or S3.
• S4 can be controlled by AYR or /RD
• S5 can be controlled by /RD or /WR
• S2 is controlled by WR
• S3 is controlled by RD.
• a single switch can be used with its own control signal.
• the inverse function is an opposite state. For example, when the first and second switches are on or are controlled by respective control signals to turn on, the third and fourth switches are off or controlled by respective control signals to turn off.
• RD and WR (and their inverses which can be derived directly from RD and WR, respectively) to achieve both in-pixel compensation and external compensation by reading out the pixel circuit current or voltage through the second line.
• the first line can supply a programming voltage (Vdata) or a reference voltage (Vref) to the storage device Cs when the first switch S2 is closed.
• the first line applies Vref through the closed S2 (WR is active) to charge internal node B to Vref.
• the stored charge in Cs is allowed to discharge for a discharge period until the charge is indicative of at least a threshold voltage of Tl .
• WR is the deactivated, at which time the voltage across Cs becomes a function of Vdata - Vdischarge, which is a function of Tl and the OLED.
• RD is active to close S3, allowing the current or voltage to be read from the second line (monitor function).
• the second line can also be used, during a programming cycle, the supply Vdata to Cs when S3 is closed.
• the pixel circuit can be compensated externally from the pixel circuit for variations or aging of the pixel circuit by extracting a circuit parameter using the second line and storing the circuit parameter externally to the pixel circuit.
• the circuit parameter can be a current or a voltage of at least To or at least the OLED or at least Tl and the OLED.
• a reference voltage Vref can be supplied from either the first line or the second line (but not simultaneously). The charge associated with the supplied Vref is held in Cs.
• a programming voltage Vdata can also be supplied from either the first line or the second line (but not simultaneously), and Vdata is stored at least initially in Cs.
• the OLED emits light according to at least some of the stored Vdata.
• Internal and external compensation can add or subtract from the programming voltage. This flexibility allows one or both lines to be shared among multiple columns in the pixel array.
• the control signals RD and WR can also be shared among multiple rows of pixel circuits.
• FIG. 34 also relates to a method of extracting a circuit parameter from a pixel circuit and providing in-pixel compensation for variation or aging of the pixel circuit.
• the method includes causing an in-pixel compensation to self-compensate for a variation or aging of the drive device (Tl) or the light emitting device (OLED) or both in the pixel circuit by applying a reference voltage (Vref) from a first line or a second line to a storage device (Cs) in the pixel circuit to charge the storage device (Cs) based on the reference voltage (Vref).
• Vref reference voltage
• the method includes extracting, using a circuit external to the pixel circuit, the circuit parameter from the pixel circuit by closing a switch (S2 or S3) in the pixel circuit to allow the circuit parameter (e.g., current or voltage through Tl, OLED, or Tl and OLED) to be read from the first line or from the second line.
• the method includes subsequently driving the pixel circuit using programming information (e.g., derived from Vdata) that has been compensated based on at least the extracted circuit parameter.
• the driving cycle is carried out while the pixel circuit is disconnected from both the first line and the second line and while two switches (S4 and S5) connected in line between the drive device (Tl) and a power supply (VDD) are closed.
• FG. 35 shows a prior-art pixel circuit. In operation, during programming, EM is off, and WR is on.
• a current is applied to the pixel through Iref and a programming voltage (VP) is applied to Vdata.
• VP programming voltage
• a bias voltage is developed at node A and B (VB) which is a function of Iref and Tl characteristics.
• the stored voltage in Cs is VP-VB.
• emission signal EM is on and write signal WR is off.
• Node C changes from programming voltage VP to supply voltage VDD.
• Node A is boot-strapped by capacitor Cs and moves with the same value (VDD-VP).
• VDD-VP the voltage at node A will be VB+VDD-VP.
• a current proportional to VP which is compensated with VB will pass through the drive transistor Tl and the OLED.
• the switches can be shared between columns and rows.
• Tc and Td can be shared with rows.
• Ta and Tb can be shared with rows and columns.
• SEM and SWR can be the same as EM and WR.
• the sharing condition in FIG. 37 is the same as the pixel circuit in FIG. 36, but the programming cycle is different.
• SEM/EM are off, SWR/WR are ON.
• RD is on at the beginning resetting node B and A to Vref.
• RD turns off after that and node B and A are charged with Tl .
• the charging amount is a function of Tl parameters.
• the voltage developed at node A is a function of Tl and will compensate for its non-uniformity/aging during driving/emission cycle.
• FIG. 38 shows a 3-transistor pixel circuit that can use charge-based compensation.
• Vdata includes a programming voltage, and Vref supplies a reference voltage via T3.
• FIGS. 39A-49B show various pixel circuits and corresponding timing diagrams for compensating for variations in a parameter of the pixel circuit (e.g., aging, process non-uniformity).
• Tl is typically the drive transistor used to drive the OLED according to a current commensurate with a charge stored in a capacitor Cs. This charge may or may not be self-compensated for effects like shifts in the threshold voltage of the drive transistor Tl .
• Other transistors are labeled T2, T3, T4, etc.
• Vdd is a supply voltage.
• Vdata is a signal line that carries programming information in the form of a corresponding voltage, which may or may not be externally compensated for variations in one or more parameters of the pixel circuit.
• a line labeled Monitor is a signal line that is used to read or extract a current or voltage from the pixel circuit (e.g., from Tl, the OLED, or both Tl and the OLED). This extracted current or voltage is used externally from the pixel circuit to compensate for variations in parameters, such as aging, including shifts in a threshold voltage of Tl or the OLED or both.
• Programming means a programming cycle where programming information (in the form of a voltage or current) is applied to the Vdata line and stored in Cs.
• Discharge refers to a discharge period where charge stored in Cs is allowed to at least partially discharge. During this discharge period, the final voltage of Cs typically settles at a value that is indicative of a threshold voltage of Tl, and is used to internally self-compensate the applied programming voltage Vdata for shifts in the threshold voltage of Tl .
• the Driving Scheme refers to emission, where the OLED is connected to the supply voltage VDD, and current flows to the OLED according to the remaining charge stored in the capacitor Cs.
• Programming/Comp refers to a hybrid cycle where both programming and internal or external compensation can occur.
• a Reset operation refers to resetting the pixel circuit, e.g., a charge stored in Cs.
• a Read operation refers to reading or extracting a current or voltage from the pixel circuit (e.g., Tl, the OLED, or both Tl and the OLED) using the Monitor line.

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• 2014
  • 2014-12-05 CN CN201711202814.3A patent/CN107967897B/zh active Active
  • 2014-12-05 WO PCT/IB2014/066655 patent/WO2015083136A1/en active Application Filing
  • 2014-12-05 CN CN201480074742.7A patent/CN105960670B/zh active Active
  • 2014-12-05 DE DE112014005546.8T patent/DE112014005546T8/de active Active

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