WO2015081416A1 - Transistor a couches minces a barriere source de schottky enfouie, et procede de fabrication - Google Patents

Transistor a couches minces a barriere source de schottky enfouie, et procede de fabrication Download PDF

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Publication number
WO2015081416A1
WO2015081416A1 PCT/CA2014/000863 CA2014000863W WO2015081416A1 WO 2015081416 A1 WO2015081416 A1 WO 2015081416A1 CA 2014000863 W CA2014000863 W CA 2014000863W WO 2015081416 A1 WO2015081416 A1 WO 2015081416A1
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WO
WIPO (PCT)
Prior art keywords
source
schottky
thin film
channel
film transistor
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Application number
PCT/CA2014/000863
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English (en)
Inventor
Douglas Barlage
Alex MA
Manisha Gupta
Kyle BOTHE
Kenneth Cadien
Amir Afshar
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The Governors Of The University Of Alberta
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Application filed by The Governors Of The University Of Alberta filed Critical The Governors Of The University Of Alberta
Priority to US15/101,913 priority Critical patent/US20160315196A1/en
Priority to CA2932446A priority patent/CA2932446A1/fr
Publication of WO2015081416A1 publication Critical patent/WO2015081416A1/fr
Priority to US15/597,020 priority patent/US20170250287A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present invention relates to transistors, and more particularly to thin film transistors.
  • TFTs thin film transistors
  • ZnO zinc oxide
  • an enhancement-mode transistor is preferable compared to a depletion-mode transistor because the enhancement-mode transistor does not require a gate voltage to switch the device off.
  • Pulse-width modulation (PWM) converters dominate the market primarily due to their circuit simplicity and ability to offer a voltage gain greater than unity. More specifically, the voltage gain is provided by the boost converter topology.
  • the most common method of dictating the switching behaviour of the boosting circuit's transistor is through an extrinsic source, usually in form of a digital microcontroller (MCU).
  • MCU digital microcontroller
  • the incompatibility between a digitally driven switch and the pursuit of circuits operational at higher frequencies lies in the latter's objective to minimize both the area employed by the circuit and its bulk costs.
  • the digital approach is rendered unfeasible given the size needed for the MCU.
  • Atomic layer deposition is a thin film deposition method that is capable of
  • ZnO TFTs are attractive techniques for the large-scale fabrication of ZnO TFTs.
  • high- ⁇ gate dielectrics e.g. hafnium oxide (Hf02) and zirconium oxide (Zr0 2 )
  • Hf02 hafnium oxide
  • Zr0 2 zirconium oxide
  • ZnO films grown by ALD have also shown some desirable characteristics for electronics applications such as moderately high mobilities at low processing temperatures (below 200°C), thus making them compatible with plastic and flexible substrates.
  • SGTFT Schottky source-gated TFT
  • a Schottky barrier contact is used for the source electrode while an ohmic contact is used for the drain electrode.
  • This transistor consequently, utilizes a different operating principle from conventional TFTs fabricated with ohmic source/drain contacts.
  • Current in the SGTFT is controlled by the carrier injection barrier at the source rather than by the conductance of the channel. Based on this operating principle, a device should be normally-off if a high quality gated Schottky barrier is used; "high quality” meaning a Schottky barrier with a large rectification ratio, which is attained at the source to restrict current flow at negative gate biases.
  • the source Schottky barrier makes the device performance less dependent on the material properties of the semiconductor used for the active channel.
  • the SGTFT is effective using ZnO active channels, grown by pulsed laser deposition (PLD) and sol-gel (with relatively poor electrical properties). In those devices, when conventional ohmic source/drain contacts were used, there was no transistor action. Thus, the SGTFT architecture is well suited for realizing an enhancement-mode, high performance TFT that exploits the properties of ALD grown ZnO.
  • the transistor according to the invention may include a top-gate ZnO SGTFT using a buried Schottky source barrier contact with a ZnO active channel film and insulating dielectric, both deposited via atomic layer deposition.
  • a ZnO source-gated TFT is provided.
  • the device includes a buried source Schottky barrier electrode with a top gate and drain ohmic electrode.
  • ZnO thin films deposited at 130°C using thermal ALD are used for the device's active channel.
  • a thin (- 10 nm) Hf02 high- ⁇ insulator layer grown at 100°C by ALD is used as the gate oxide.
  • the device ZnO SGTFT uses this low temperature process along with the SGTFT architecture to display enhancement-mode operation with a threshold voltage of 1.1 V, a Ion/Ioff ratio of 107, a field effect mobility of 0.7 cm2 V-l s-1 , and a subthreshold swing of 192 mV/decade at low operating voltages.
  • a Schottky source-gated thin film transistor including: a drain contact; an insulating substrate; a source contact made of a Schottky metal; a channel connecting the buried source contact to the drain, the channel made of ZnO; and a Schottky source barrier formed between the source contact and the channel; and a gate; wherein the source contact is positioned below the channel.
  • the saturation of the transistor may occur when the barrier induces full depletion around the channel.
  • the drain contact may be positioned in line with the channel.
  • the gate may be positioned above the channel, and is separated from the channel by a gate oxide.
  • the source contact may be made of a metal that forms a Schottky barrier with the channel, such as TiW.
  • the gate oxide may be made of Hf0 2 or Zr0 2 .
  • the gate and the drain contact may be made of an AL/Au stack.
  • a Schottky source-gated thin film transistor including a drain contact; an insulating substrate; a source contact made of a Schottky metal; a channel connecting the buried source contact to the drain, the channel made of a semiconducting material; and a Schottky source barrier formed between the source contact and the channel; and a gate; wherein the source contact is positioned below the channel.
  • a method of manufacture of a Schottky source-gated thin film transistor including the steps of: providing an insulating substrate; using lift-off patterning to form a Schottky metal source contact on the substrate; using a thin film deposition system to provide a layer of semiconducting material over the source contact; etching the semiconducting material; depositing a gate dielectric layer above the semiconducting material; patterning the gate dielectric material using a lift-off process; depositing a cap oxide layer on a portion of the semiconducting material; and depositing gate and drain electrodes made of an ohmic metal.
  • the Schottky metal may be TiW between 5 nm and 20 nm thick.
  • the deposition system may be an atomic layer deposition system using a recipe at less than 200°C.
  • the semiconducting material may be ZnO.
  • the etching may be done using ferric chloride.
  • a Schottky source-gated thin film transistor is provided, prepared by a process including the steps of: providing an insulating substrate; using lift-off patterning to form a Schottky metal source contact on the substrate; using a thin film deposition system to provide a layer of semiconducting material over the source contact; depositing a patterned semiconductor using a lift-off process; depositing a gate dielectric layer above the semiconducting material; patterning the gate dielectric material using a lift-off process; depositing a cap oxide layer on a portion of the semiconducting material; and depositing gate and drain electrodes made of an ohmic metal.
  • Figure 1 is a cross-sectional view of an embodiment of a top-gated ZnO TFT with a
  • Figure 2a is a confocal microscope image of an embodiment of a top-gated TFT with a buried Schottky source barrier according to the invention.
  • Figure 2b is a graph showing output characteristics of an embodiment of a ZnO SGTFT according to the invention.
  • Figure 3 is a graph showing the transfer characteristics of an embodiment of a ZnO
  • invention and the like mean "the one or more inventions disclosed in this application", unless expressly specified otherwise.
  • a reference to "another embodiment” or “another aspect” in describing an embodiment does not imply that the referenced embodiment is mutually exclusive with another embodiment (e.g., an embodiment described before the referenced embodiment), unless expressly specified otherwise.
  • the function of the first machine may or may not be the same as the function of the second machine.
  • top-gate SGTFT 10 also referred to as “device” according to the invention, as
  • Fig. 1 includes a buried Schottky source barrier contact 20 which functions as an electrode.
  • the depletion region from the Schottky junction at the source is responsible for controlling the current flow in the device rather than the channel conductance. For instance, in the conventional TFT, saturation occurs when the drain region is depleted of carriers; whereas in the SGTFT, saturation occurs when the semiconductor at the source is fully depleted from the Schottky barrier.
  • the SGTFT operates as a single carrier/unipolar n-channel transistor due to the intrinsic n-type behaviour of ZnO, which is unintentionally present in all types of deposition techniques.
  • Advantages of the SGTFT include a lower saturation voltage, higher output impedance, faster operating speeds (due to reduced minority carrier storage), and a reduction in short- channel effects. Conversely, the drive current of device 10 is noticeably reduced compared to a conventional TFT due to the impedance of the Schottky barrier. Buried source contact 20 is used to ensure that the interface between the Schottky metal and active channel 30 layer is protected from contaminants during other processing steps, making it easier to control the variables during the Schottky junction formation.
  • gate 50 may have a top drain contact 60 rather than a buried contact under the active channel 30 layer like source contact 20; this allows gate 50 and drain contact 60 to be fabricated at the same time. As a result, no alignment between the distance from drain contact 60 and gate 50 is predefined therefore ensuring more consistent breakdown voltages between devices.
  • This top gate design also allows for easy integration with traditional circuits.
  • Another aspect of device 10 is the extremely thin, for example less than 5nm, high- ⁇ gate oxide 70, which is possible using the ALD technique. This leads to enormous, for example, greater than lMV/cm electric fields in channel 30 consequently increasing device performance and reducing operating voltages.
  • a ZnO SGTFT 10 with characteristics such as high drive currents and low operating voltages can be fabricated at low processing temperatures (less than 150°C).
  • the device can be patterned using photolithography and lift-off processes.
  • Devices 10 can be built on a clean, highly doped (—1016 cm3) p-type silicon (Si) wafer covered with 50 nm thick thermal silicon oxide (Si0 2 ).
  • the SGTFT architecture is applicable with nearly any kind of insulating substrate 90, which includes flexible or plastic materials if low temperature deposition processes such as those disclosed herein are used.
  • titanium tungsten (TiW) (12 nm thick) is first sputtered and patterned using a lift-off process to form the source Schottky metal source contact 20.
  • TiW is a stable alloy that is resistant to acid etches and oxidation.
  • Other materials such as Platinum, Gold, Copper, Ruthenium, Silver, or Tungsten, that can form a Schottky barrier with ZnO are also compatible with the device architecture as the source contact electrode 20.
  • ZnO may be blanket deposited by the ALD method (for example, using a Kurt J. Lesker Company ALD-150LX system) using a thermal or plasma enhanced ALD process at 130°C.
  • the precursors used for the ZnO deposition may be diethylzinc (DEZ) and water.
  • ZnO films are grown with a thickness of approximately 15 nm, or in the range of 5 to 50 nm, which can be monitored in-situ utilizing a J. A. Woollam Co. Inc. M-2000DI spectroscopic ellipsometer.
  • the ZnO growth for device 10 is not limited to the ALD method; any thin film deposition technique for ZnO such as sol-gel, pulsed laser deposition (PLD), and radio frequency (rf) sputtering can also be used (a low temperature growth should be used for compatibility with flexible substrates). If the thickness of the source metal is kept below 15 nm, conformal thin film deposition techniques such as PLD can be used for the ZnO growth. Likewise, the device may include other materials, as any semiconducting material that can be deposited as a thin film at thicknesses less than 25 nm is suitable for use as active channel 30 (providing an appropriate Schottky metal is used for source contact 20).
  • the ZnO may be etched using ferric chloride (FeC13) to pattern channel 30 and form electrical isolation between devices 10 as needed.
  • FeC13 ferric chloride
  • Other wet or dry etch processes for ZnO can be substituted for the FeCl 3 .
  • the dimensions of the channel width (W) and length (LSD), the source-to-gate overlap (LSG) and gate-to-drain distance (LGD) of the devices 10 may be varied. Increasing LSG leads to higher output current due to increased lowering of the effective source barrier while LQD affects the device breakdown voltage.
  • hafnium dioxide Hf0 2
  • ROP remote oxygen plasma
  • the Hf0 2 deposition may be done using tetrakis(dimethylamino)hafnium (TDMAHf) as a precursor with ROP. Additionally, as a result of the low growth temperature, the gate oxide can be patterned using a lift-off process. In an experiment, a 10 cycle ( ⁇ 1.7 nm thick) Hf0 2 cap oxide layer 80 was first deposited after etching the ZnO (and before
  • any other insulating material e.g.
  • Zr0 2 or spin-on-dielectrics that can be deposited as a thin film is suitable for use as the gate oxide 70 (the gate dielectric layer) in device 10.
  • an ohmic metal is deposited and patterned with lift-off to form top gate 50 and drain contact 60 electrodes.
  • An Aluminum/gold (Al/Au) stack (of a large range, including 20 nm/60 nm) can be used without any post-deposition annealing as the ohmic contacts. Alternatively, different metals can be used so long as they secure to ZnO and Hf0 2 .
  • a schematic of device 10 is shown in Fig. 1 , and a confocal microscope image of a typical device is shown in the inset in Fig. 2a. In Fig. 2b, as shown in the graph, VGS is at 3.6 V for the top curve and decreases in - 0.2 V increments until pinch-off. Using Hall Effect measurements, the electron
  • concentration of the ALD ZnO is on the order of 1017 cm " .
  • the measurements of L $ D/W, LSG > and LGD indicated in Figure 2b are typical, but are scalable downwards by a factor of 100 and upwards by a factor of 10.
  • Fig. 2b The output characteristics (drain current (IDS) VS. drain voltage (VDS)) of a typical ZnO SGTFT 10 with a buried TiW source Schottky contact 20 (measured using the Keithley Instruments Inc. 4200 semiconductor characterization system) is shown in Fig. 2b.
  • the dimensions of the device 10 are also given in the figure. Similar to other ZnO TFTs that utilized high- ⁇ k dielectrics, there is high transconductance over a low operating voltage range. Also, n-channel behaviour is present as current density increased as V G s was increased.
  • the device 10 in Fig. 2b also showed good drive current, reaching 120 ⁇ at a gate voltage (VGS) of 3.6 V, despite the low temperature of the ALD ZnO growth.
  • VGS gate voltage
  • the saturation voltages in device 10 are much lower than prior devices that did not use the source Schottky barrier; however, they can be made even lower with a higher quality Schottky junction.
  • IV current-voltage
  • an experiment measured a current on/off ratio of 10 and an ideality factor of greater than 2 using thermionic emission theory. These results are characteristic of a highly non-ideal Schottky barrier and are poor compared to other-known Schottky metals on ZnO. Regardless of poorer Schottky barrier properties though, using TiW as the source barrier metal is attractive due to its relatively low cost and robustness. In the saturation regime, there is high series resistance being exhibited as seen by the noticeable positive slope in the family of curves. This is most likely the result of the high carrier concentration in the channel along with the non-ideal source Schottky barrier.
  • the transfer characteristics (IDS VS. VGS) of the ZnO SGTFT at a drain voltage of 10 V are shown in Fig. 3.
  • the method of extracting the threshold voltage (VTH) from the linear portion of (IDS) 1/2 vs. VGS is also shown. From fitting a straight line to the square root of IDS versus VGS (also shown in Fig. 3), the threshold voltage (VTH) was extracted to be 1.1 V.
  • the maximum current on/off ratio (ION/IOFF) reaches 107, and the off-current reaches low values of approximately 1 ⁇ 10-12 A at a pinch-off voltage of -1 V.
  • device 10 can nonetheless operate as an enhancement-mode transistor due to the positive VTH and the relatively low current at zero gate bias ( ⁇ 1 .5 x 10-8 A) compared to the on-current values (greater than 1 x 10-5 A).
  • Carriers in SGTFT 10 are controlled by the gated field at the source, so the turn-on
  • Vth of the SGTFT is mostly determined by the properties of the source Schottky barrier (e.g. barrier height), which is advantageous for improving the fault tolerance of fabricating enhancement-mode devices.
  • the field- effect mobility ( ⁇ ) of the transistor was extracted to be 0.7 cm2 V-l s-1 using Eq. (1) (which applies when device 10 is in the saturation region):
  • the SS of device 10 is among the lowest. This is due to the 10 nm thick high- ⁇ k gate oxide, which is the thinnest gate oxide reported for ZnO TFTs.
  • the thin gate oxide helps reduce fabrication costs, due to a shorter deposition time, while also allowing for higher electric fields in channel 30 leading to higher transconductance and better charge control. Measurements of the gate leakage current did not show any

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne un transistor à couches minces à source-grille de Schottky, qui comprend : un contact de drain ; un substrat isolant ; un contact de source fait d'un métal de Schottky ; un canal reliant le contact de source enfoui au drain, ledit canal étant fait de ZnO ; et une barrière source de Schottky, formée entre le contact de source et le canal ; et une grille. Le contact de source est positionné au-dessous du canal.
PCT/CA2014/000863 2012-04-13 2014-12-04 Transistor a couches minces a barriere source de schottky enfouie, et procede de fabrication WO2015081416A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US15/101,913 US20160315196A1 (en) 2012-04-13 2014-12-04 Buried source schottky barrier thin film transistor and method of manufacture
CA2932446A CA2932446A1 (fr) 2013-12-04 2014-12-04 Transistor a couches minces a barriere source de schottky enfouie, et procede de fabrication
US15/597,020 US20170250287A1 (en) 2012-04-13 2017-05-16 Buried source schottky barrier thin transistor and method of manufacture

Applications Claiming Priority (2)

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US201361911787P 2013-12-04 2013-12-04
US61/911,787 2013-12-04

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US15/101,913 A-371-Of-International US20160315196A1 (en) 2012-04-13 2014-12-04 Buried source schottky barrier thin film transistor and method of manufacture
US15/597,020 Division US20170250287A1 (en) 2012-04-13 2017-05-16 Buried source schottky barrier thin transistor and method of manufacture

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020128508A1 (fr) * 2018-12-21 2020-06-25 The University Of Manchester Transistor à couches minces à barrière de schottky et son procédé de fabrication
CN116207138A (zh) * 2021-12-08 2023-06-02 北京超弦存储器研究院 晶体管及其制作方法、半导体器件

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441047B2 (en) * 2009-04-10 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8530892B2 (en) * 2009-11-06 2013-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8557641B2 (en) * 2009-06-30 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8441047B2 (en) * 2009-04-10 2013-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8557641B2 (en) * 2009-06-30 2013-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8530892B2 (en) * 2009-11-06 2013-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020128508A1 (fr) * 2018-12-21 2020-06-25 The University Of Manchester Transistor à couches minces à barrière de schottky et son procédé de fabrication
CN116207138A (zh) * 2021-12-08 2023-06-02 北京超弦存储器研究院 晶体管及其制作方法、半导体器件

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