WO2015067767A1 - Arrangement and method for protecting an electronic circuit - Google Patents

Abstract

The invention relates to an arrangement and a method for protecting an electronic circuit. The aim of the invention is to provide a solution which provides a reduced voltage drop over the protection circuit itself, whereby a destruction of the electronic circuits is prevented upon omitting and/or exchanging connection lines on an IO link device and/or an IO link master. The aim of the invention is achieved by the arrangement in that a voltage sensor is provided for monitoring a drain-source voltage of an MOS transistor, said voltage sensor being connected to the drain and source connection of the MOS transistor in order to monitor the voltage and to the gate connection of the MOS transistor in order to output a control signal. The aim of the invention is achieved by the method in that a voltage (U_DS) applied via the semiconductor switching element is monitored by means of a voltage monitoring means such that in the event of a fault, the semiconductor switching element is blocked by a control voltage generated by the voltage monitoring means when the absolute value of the voltage (U_DS) exceeds a threshold.

Description

 Arrangement and method for protecting an electronic

 The invention relates to an arrangement for protecting an electronic circuit, in which a MOS transistor in a positive and / or negative branch of a

Voltage supply of the arrangement with a drain-source path, for interrupting a current flow in the

is concerned, wherein a gate terminal of the MOS transistor with a first terminal of a means for generating a high impedance gate voltage (U _G s) is connected, the second terminal at least indirectly with the negative or positive branch of

Voltage supply of the arrangement is connected.

The invention also relates to a method for protecting an electronic circuit in which a semiconductor switching element is provided in a positive and / or negative branch of a power supply of the device, and wherein the semiconductor switching element by means of a

Control voltage switched through during operation and in

Error is blocked.

In many areas of electronics it is necessary

Sensors and / or actuators with a central control unit, such as a microcontroller to connect.

For example, in the area of factory automation, the IO-Link communication system is used to connect so-called intelligent sensors and actuators. The associated standard describes the electronic

Connection data of the components as well as the digital

 Communication protocol via which the sensors and / or actuators communicate with the central control unit, which is referred to as IO-Link master. The actors and

Sensors in this system are also called IO-Link device or Called IO-Link device.

The architecture provides that an IO-Link master has several so-called ports, to each of which an IO-Link device is connected. Between an IO-Link device and the IO-Link master, a point-to-point communication is provided.

The IO-Link master forms an interface to a higher-level controller, such as a

programmable logic controller (PLC), and controls the communication with the connected IO-Link devices according to the underlying communication protocol.

As smart sensors and actuators will be in this

Description Devices understood, which at the request of the master measuring and / or control data with the master

change. Furthermore, these devices may have, for example, a serial number or parameter data. In this case, such parameters, for example, a

Sensitivity, a switching delay or a

Be characteristic curve, which over the

Communication protocol both read as well as in the ongoing operation can be changed.

The connection between a port of the IO-Link master and an IO-Link device is made via a maximum 20 m long, unshielded, 3-core cable. In this description, in the embodiments, a variant with a 4-wire cable routing

shown. In these cases, an extension has been made such that in addition to the usual IO-Link communication wire "Line COM" another auxiliary wire, for example, called "Line AUX" is used. About this auxiliary wire is a transfer of information, for example, a connected IO-Link device, such as a sensor or an actuator possible. Alternatively, control signals can also be transmitted to IO-Link devices via the auxiliary core. Another alternative is the

Connection of a sensor with binary and possibly mutually logically negated output signals between the lines "Line COM" and "Line AUX".

In many cases, the line of the IO-Link devices is equipped with a plug connection. But since this is not required, IO-Link devices are also without a

Plug connection supplied only with its connecting cable. In these cases, the wires of the line must be clamped or soldered in compliance with their proper affiliation. This can lead to the exchange of wires, which can lead not only to the inoperability of the system but also in particular by the system voltage U used by 24 volts in a reverse polarity of the connections to damage the connected electronic modules.

Since the use of the IO-Link communication system under operating conditions with an influence of interference, for example, coupled via the line, must be expected, to ensure a faultless operation protective measures are required.

For this purpose, it is known to provide a protection arrangement, also referred to as a line interface, between the IO-Link master and the transmission line as well as between this line and the connected IO-Link device.

This protection arrangement provides protection

short-term high voltage pulses, also as

Electrostatic discharge (ESD, engl.

electrostatic discharge), as well as a protection against low over the operating voltage Ucc or Us or slightly below the

Reference potential of zero volts reached voltages. For a reverse polarity of connections beyond a so-called Verpolschut switching is required. Such arrangements are known in which diodes, ie, standard silicon diodes or to reduce the disturbing flux voltage Schottky diodes, are used. The disadvantage of this solution is that the protection by the diodes is associated with an additional voltage loss, which is associated with a reduction of the supply voltage and thus with a reduction of the system performance. In addition, this solution leads to the generation of heat by the unwanted power loss of the diodes.

Another disadvantage of this Verpolschut zschaltung is that a distortion of the transmitted digital signal is possible by connected to the signal line protection diodes.

The invention is therefore based on the object, a

Arrangement and method for protecting an electronic circuit to create, which reduced

Has voltage drop across the protection circuit itself and what if omission and / or interchange of

 Connecting cables to an IO-Link device and / or a 10-link master prevents destruction of the electronic circuits. In addition, a disturbing

Rectifier effect can be avoided in normal operation.

According to the invention, the object is achieved in an arrangement for protecting an electronic circuit of the type mentioned above in that a voltage sensor for monitoring a drain-source voltage of a MOS transistor is arranged, which with the drain and source terminal of the MOS - Transistor for voltage monitoring and with the gate terminal of the MOS transistor to output a

Control signal is connected. According to the invention, a voltage sensor is arranged parallel to the drain-source path of a MOS transistor used as an electronic switch in a branch of the voltage supply of the arrangement. By means of this voltage sensor, the drain-source voltage of the MOS transistor is monitored. As the drain-source voltage rises above a predetermined threshold, the voltage monitoring unit generates a turn-off control signal for the electronic switch. The threshold may be, for example, 0.6 volts. To output this shutdown or control signal, the voltage monitoring unit is connected to the gate terminal or source terminal of the MOS transistor.

In one embodiment of the invention it is provided that in the voltage sensor, a bipolar transistor with a

 Base resistor is arranged such that a

Base terminal of the bipolar transistor via the

Base resistor in positive branch of

Power supply to the drain connection of an im

Operation case inversely operating P-channel MOS transistor and the negative branch of the power supply to the drain terminal of an inversely operating in case N-channel MOS transistor is connected, that an emitter terminal of the bipolar transistor in the positive branch of the

Power supply to the source terminal and in the

negative branch of the power supply is connected to the source terminal of the MOS transistor and that a collector terminal of the bipolar transistor is connected to the gate terminal of the MOS transistor. The voltage sensor can be realized by means of a bipolar transistor with an associated base resistor. It is intended to connect the base resistor to the drain terminal of the MOS transistor. Of the

Emitter terminal of the bipolar transistor is connected to the source Connection of the MOS transistor connected. Such is the drain-source path of the MOS transistor for

Voltage monitoring interconnected with the voltage sensor. The collector terminal of the bipolar transistor is connected to the gate terminal of the MOS transistor. In the case of detection of a voltage by the voltage sensor, which exceeds a fixed threshold in terms of magnitude, by driving through the bipolar transistor, the gate-source voltage of the MOS transistor is reduced and thus the MOS transistor is turned off. Thus, the invention prevents a current flow that direction which is opposite to the current direction that occurs in the operating case and thus possible destruction of components of the device to be protected. The described voltage sensor can alternatively or simultaneously be arranged in the negative branch of the voltage supply

In a further embodiment of the invention

provided that the bipolar transistor in the positive branch of the power supply is a PNP transistor and in the negative branch of the power supply is an NPN transistor.

It is envisaged to use a combination of an NPN bipolar transistor with an N-channel MOSFET in the positive branch and / or a PNP bipolar transistor in conjunction with a P-channel MOSFET in the negative branch.

Taking into account the polarity or the current flow directions, a bipolar transistor of the type PNP (layer sequence of the transistor) is used in the voltage sensor, which is arranged in the positive branch of the voltage supply. In the negative branch of the power supply is a

Used bipolar transistor NPN type.

According to the invention, the object is achieved in a method for Protection of an electronic circuit of the type mentioned in that a monitoring of a voltage applied across the semiconductor switching element voltage U _D s by means of a voltage monitoring means that at an increase or decrease in the voltage U _D s above or below a threshold, the semiconductor Switching element is blocked by a control voltage generated by the voltage monitoring means.

According to the invention, the voltage U _D s is monitored across the drain and source terminals of the MOS transistor. The

Method performs a comparison between the detected voltage U _DS and a specified threshold voltage. In the event that the absolute value of the voltage U _D s is less than the threshold, the operation of the MOS transistor is not affected. In the event that in

Blocking the absolute value of the voltage U _{DS is} equal to or greater than the absolute value of the threshold value, the MOS transistor is influenced by a corresponding control voltage such that it is disabled. Thus, erroneous unacceptably large currents are avoided, which can lead to the destruction of components of the system.

The magnitude of the threshold may be, for example, 0.6 volts. Alternative values are possible and have no influence on the overall function of the

Invention.

The invention will be explained in more detail with reference to an embodiment ^¬ example. In the associated

Drawings shows

1 shows an illustration of an IO-Link device or 10-link master with an associated line and a protection circuit from the prior art,

2 shows an exemplary coupling of an IO-Link master with an IO-Link device with associated protection circuits and IO-Link connection line according to the prior art, another prior art representation of any proprietary network solution with multiple devices which are connected to the network cable via protective devices, an exemplary embodiment of the protection circuit According to the prior art, a schematic diagram of the use of protection diodes in a two-wire system according to the prior art, a schematic diagram of the use of MOSFET devices in a two-wire system according to the prior art, a representation of the operation in limiting a beyond the operating voltage limits Voltage (overshoot voltage) with clamping diodes according to the prior art, a schematic diagram of a

 Three-wire protection system with used clamping diodes according to the prior art, a schematic diagram of a

 Three-wire protection system with MOSFET components, a representation of a simulation model of a protection circuit according to FIG. 9 (right) with additionally existing decoupling capacity "CLOAD" according to the prior art,

Fig. 11 is a representation of the signal waveform

selected points of Figure 10, an embodiment of an exemplary

Four-conductor protection system according to the prior art with clamping diodes, a representation of insufficient protection by MOS transistors in a four-wire protection system with clamping diodes, a representation of a simulation model of poorly working protection circuit according to the prior art in a first variant, a representation of signal waveforms

14 shows a representation of a simulation model of the defective protective circuit according to the prior art in a second variant, a representation of a known form of the

Control of MOS transistors in two

Examples, a tabular summary of

Differences between regular and inverse

Operating case of an N-channel and a P-channel transistor, a representation of the invention

 Schut z circuit in a variant in the positive branch (left) and a

 Variant in the negative branch (right) of the power supply, a representation of the invention

Protection circuit arranged in both branches with indicated voltages and a parasitic diode between drain and source terminal, 21a, b an embodiment for the use of the protection circuit according to the invention with further components,

Fig. 22 is an illustration of signal waveforms

 selected points of FIGS. 21a and 21b,

23 shows an exemplary representation of the protective circuit modified according to the invention,

Fig. 24a, b is a representation of a prior art

 Protection circuit in a first variant of

 Investigation of the protective effect,

Fig. 25 is an illustration of signal waveforms

 selected points of FIGS. 24a and 24b,

Fig. 26a, b is a representation of a prior art

 Schut z circuit in a second variant to investigate the protective effect and

Fig. 27 is an illustration of signal waveforms

 selected points of Figures 26a and 26b.

For the sake of representability of the figures, several drawing figures have been split into two sheets. This relates, for example, to FIGS. 21, 24 and 26.

FIG. 1 shows an IO-Link master 1, which can alternatively also be an IO-Link device 2, as a central one

Control unit of an IO-Link system, which is connected via a port, not shown, to the line 3 (IO-Link connection line). The line 3 consists in the example of the wires Line L + and Line L- for the transmission of an operating voltage and the signal lines Line COM and Line AUX.

In the figure 1, this line 3 is in one place

shown interrupted, on which a protection circuit. 4 is inserted. The protection circuit 4 can be arranged directly to the port of the IO-Link master 1 without the part of the line 3 shown on the left.

FIG. 2 shows a connection of an IO-Link master 1 with an IO-Link device 2 via the connecting line 3 as well as respectively associated protective circuits 4. Optionally, a power supply 5 is shown, which can also be arranged in another location of the connection of the IO-Link modules 1 and 2. Shown is also the disturbing influence of electrical and / or electromagnetic interference, which on the

Line 4 can act. In the example ESD stands for electrostatic discharges and RF / EMI for

electromagnetic interference, which may affect the transmission of the signals via the line 4. In addition, such problems can also affect the supply ^¬ or operating voltage.

FIG. 3 shows an interconnection, known from the prior art, of a proprietary data bus system with a master 1 and with a plurality of devices 2, which may be embodied as actuators or as sensors via which

Line 3, and in each case for the protection of the arrangements 1 and 2 arranged protective circuits 4. Optionally, in turn, a unit for power supply 5 is shown at possible positions in the system. The representation of the line 3 as dash-line line to illustrate the possibility of arranging other devices 2.

In Figure 4, the protection circuit 4 in conjunction with an IO-Link Master 1 or IO-Link device 2 and the

Line 3 shown. For protection, the protection circuit 4 includes a sub-assembly for protection against electrostatic discharges ESD protection 6, an arrangement for protection against reverse polarity of Operating voltage 7 and an arrangement for limiting the input voltage. 8

The prior art is for example a

Two-conductor system known in which only the

Operating voltage is connected via the cable, either in the positive or negative branch between a voltage source 9 and a load resistor 11 to be arranged as consumer diodes 10, as shown in Figure 5. In this way it can be ensured that the load resistor 11 can be connected with reverse polarity protection.

A major disadvantage of this protection system is an undesirable voltage drop across the diodes 10 due to the forward voltage V _{F of} the diode 10 itself

For example, voltage drops are between 0.6 and 0.8 volts for silicon diodes and between 0.1 and 0.3 volts for metal-semiconductor diodes (Schottky diodes).

Another known from the prior art

Protective measure is the use of MOS transistors

(MOSFETs), which compared to diodes a lower

Voltage drop, for example, from a few 10 mV depending on

Transistor type, can reach. This enhancement P-channel transistors in the positive branch (MOSFET is inversely operated) or enhancement N-channel transistors in the negative branch (MOSFET is operated inverse) are used. As shown in the figure 6, is in a

 Embodiment, the gate of the MOSFETs usually from ESD Schut zgründen connected via a resistor 13 and the gate-source voltage is limited by a Zener diode 14.

The Zener diode 14 and the resistor 13 can also be replaced by a means 26 for generating a high impedance gate voltage U _G s, for example, the implementation in integrated circuit solutions. Another problem with the transmission of (digital) signals is the occurrence of so-called overshoots, ie

Voltage peaks, which are outside the permissible

Supply voltage range of, for example, zero volts to the supply voltage U _s are. To limit this Overshoot voltage are usually clamping diodes

used. These clamping diodes are shown in the figure 7 with the designations Dp2 and Dp3 and must in

Be considered. In the event that no clamping diodes explicitly in the

Circuit are inserted, but these are in

equally effective parasitic diodes, for example as Di2 and Di3 in Figure 7 in the ZIOL24xx with

Designated circuit part shown in the interface IC available, or integrated into the interface IC, and thus in the same manner in the Verpolschut zkonzept to observe.

In the presence of clamping diodes 17 state of the art is in each case a diode 18 in the plus and a diode 18 in the minus branch between voltage source and load to switch, as shown schematically in Figure 8 to the

To realize reverse polarity protection.

A disadvantage of this solution lies in an undesirable voltage drop across two diodes and thus twice the forward voltage (2x U _F ). In the figure 7 is shown in a small voltage-time curve, the case of the occurrence of an overvoltage 15 and the case of the occurrence of an undervoltage 16.

The disturbing occurring as a result of the overvoltage 15

Current flow is shown with the arrows, which have a continuous line.

The current flow in the case of the undervoltage 16 is represented by the arrows, which are a dash-and-dash line exhibit .

In the case of an overshoot by overvoltage 15 or by undervoltage 16, a derivation of the signal energy to the supply voltage of the device takes place. The presence of inserted into the circuit clamping diodes or

 Presence of equally effective diode arrangements within the interface IC lead to the application of one diode in the plus and one diode in the minus branch

between the voltage source and the load, as shown schematically in FIG.

The current flow occurring in the event of a fault, as shown in Figure 8 right lead to the destruction of electronic components, if only a Verpolschut zdiode would be applied. To prevent this flow of current, as shown in Figure 8 right, two

Verpolschut zdioden 18 used.

A realization of this protection concept according to FIG. 8 by means of MOS transistors is shown in FIG. 9 in two

Versions. The right-hand circuit of FIG. 9 represents a simplification of the circuit design.

As shown in FIG. 9, the gate of the MOSFET 12 is usually connected (for protection reasons) via a resistor 13, or the gate-source voltage is limited by a Zener diode 14. The disadvantage of this solution is that a secure operation only with a 3-wire connection

is guaranteed, which has no significant capacitive load. Otherwise, the MOSFETs 12 can not be opened (lock) until the voltage at

Load capacitor is sufficiently degraded.

In a simulation of this Verpolschut zes with a

Voltage changing polarity at signal and ground connected, shows an acceptable protection behavior at CLOAD = 10nF. At a capacity of CLOAD = 10pF significant destructive currents occur, which here through the clamping diode 17 D4 and the MOS transistor 12 M2 flow. The simulation of the underlying circuit arrangement is shown in FIG. In this circuit are for

Simulation of test voltages of different polarity two voltage sources 5 used. The current through the diode 17 D4, the output voltage and the voltage of the

Test voltage source are shown in FIG.

The course with CLOAD = 10nF is indicated by a dash-line and the curve for CLOAD = 10pF by means of a

represented by a solid line. It can be seen that in the case CLOAD = 10pF a high and time-lasting

Current flow occurs in a range of more than 100 amps, which leads to the destruction of said components.

From this simulation result it can be deduced that for 3-wire protection circuits in which a buffer capacitor 19 Cload is connected in parallel with the load 11, as shown in FIG. 7 (this concerns almost all

electronic circuit solutions for actuators, sensors, ....), the conventionally known Verpolschut switching with MOSFETs is not applicable. The diode circuit already shown in FIG. 7 can in principle be extended to two or more signal lines. For each additional signal 2 more clamping diodes 17 are required.

A corresponding diode circuit is prescribed, for example, in the data sheet of the ZMDI IC ZIOL2401 (2-channel cable driver, suitable for IO-Link).

The prescribed in the figure 12 clamping diodes 17 (D4-D7) supply the IO-Link device 1 with it, too

 Operating voltage, if there is a faulty voltage of any polarity on the signals C / Q (COM) and AUX, although the IO-Link device 1 is not regular on the

Supply terminals L + and L- (hereinafter referred to as "signal supply"), whereby the diodes 17 (D4-D7) function as bridge rectifiers.

The result of the error described above has the consequence that the circuit according to FIG. 9 can not be used, as shown in FIG. H. no technical solution is available directly or by modification.

The fault case shown in FIG. 13 shows that, on the one hand, a residual voltage remains above the load resistor 11 and the load capacitor 19, which voltage is high enough to pass across the Zener diodes 14 (D5, D6) and the

Resistor 13 R4 (circuit for gate voltage generation) to cause a current flow.

This gives the MOSFETs 12 a sufficiently large one

Control voltage and therefore can not open, d. H. interrupt the flow of electricity. The result is that the current flowing back into the voltage source 11 via the clamping diodes 17 can become very large and in turn can thus destroy the clamping diodes 17. The circuit shown in FIG. 13 has another one

 Disadvantage that can occur in the following situation. When operating the connected device, a short circuit in the connecting cable between the supply voltages may occur. The ones still available in the IO-Link device 2

Supply voltage keeps the MOSFETs 12 closed, i. H. the capacitor 19 is discharged via the short circuit, in turn, a relatively large current can flow. This

Disadvantage is also based on the 3-wire protection Schut of MOSFETs 12 as shown in FIG.

FIG. 14 shows a circuit arrangement on which the following simulation is based. For the

In the test case, a voltage of alternating polarity was applied to the supply voltage terminals. The positive supply voltage terminal is shorted to signal 1 and the negative to signal 2. For both variants of CLOAD (CLOAD = 10nF and CLOAD = 10pF), no acceptable behavior exists; H. there are significant

destructive currents flowing through the clamping diodes 17 D4 / D5 and MOS transistors 12 M1 / M2.

The course of the currents through the clamping diodes 17 D4 and D5 with CLOAD = 10nF is shown by a dash-and-dash line and the curve for CLOAD = 10pF by means of a solid line in FIG. It can be seen that in both

If a high and temporally lasting current flow up to a range of more than 40 amps occurs, which leads to the destruction of said components.

As in a ladder system 3 with two or more

Signal lines always the case of a signal feed

can occur with the conventionally known

Basic circuits using MOSFETs 12 for reverse polarity protection are not given a reliable solution.

Also a placement of the gate voltage generation (Dl, Rl, D2) at the cable entrance, d. H. An alternative variant according to FIG. 16, which would normally not be implemented in this way for reasons of ESD protection, does not provide a solution either. In the case of reverse polarity of the supply voltage and the signal supply that has occurred due to a previously (!) occurring, d. H. now not working in inverse operation

MOSFETs 12, a sufficiently high control voltage UGS for the MOSFETs 12 is present so that they remain fully closed (ie remain conductive). The Verpolschut switching circuit 7 uses enhancement MOS transistors (MOSFETs) as a semiconductor switching element, which are connected in the current flow in the positive branch and / or in the negative branch of the connection between the supply voltage 9 and load 11, and which in undesirable operating states, hereinafter called blocking case , the

Can interrupt current flow. Normally (normal operating state) the voltage drop should exceed the

Semiconductor switching element should be as small as possible. To explain the protection circuit, first, the regular operation of MOSFETs will be explained with reference to two simple basic circuits to better illustrate the inverse state of operation of the MOSFETs used in the protection circuit.

FIG. 17 illustrates two common or simplest applications of semiconductor switching elements in which, in both cases, the MOSFETs 12 operate in normal operation. The two transistors 12 parallel to the channel

Plotted diodes represent parasitic or intentionally integrated into the device diodes, which always work in the reverse direction in the basic circuits shown here.

17 shows a so-called "low-side switch" by means of N-channel MOSFET 12. The drain-source voltage U _{DS of} the N-channel MOSFET 12 is always greater than zero or the MOSFET is switched through, if the

Function block "control" 26 generates a gate-source voltage U _G s, which is greater than the threshold voltage U _tn of

MOSFETs 12 is. In this case, U _{tn is} a positive voltage and may be, for example, 2... 3V. 17 below shows a so-called "high-side switch" by means of P-channel MOSFET 12. The drain-source voltage U _{DS of} the P-channel MOSFET 12 is always less than zero or the MOSFET 12 is switched through if the

Function block "control" 26 a gate-source voltage U _G s generated, which is smaller than the threshold voltage U _tp of

MOSFETs 12 is. Here, U _{tp is} a negative voltage and may be, for example, -3 ... -2V.

The gate-source voltage illustrated in FIG. 17 in the upper as well as in the lower part of the figure controls the MOSFET 12 and is called generalized control voltage U _s . In the regular operation of the transistor 12, the control voltage

Us_regular, ie: U _s = U _s _ _r eguiar = U _G s ·

Characteristic of the normal operating mode of the MOSFET 12 is 12 U _DS > 0 for the N-channel MOSFET and 12 U _DS <0 for the P-channel MOSFET.

In the case of a reverse polarity of the drain-source voltage one speaks of the inverse operation (inverse operation). In inverse operation, the control voltage U _s in the following U _s _invers is called. Physically speaking, that is

Definition of drain or source in a standard MOSFET 12 given by the polarity of the voltage between these terminals. Ie. In reverse operation, the control voltage between the gate and drain acts as the drain port has physically taken over the source function.

In summary, for the N-channel and P-channel type transitors in the table of Fig. 18, the differences between regular and inverse operation cases are one

MOSFETs 12 are shown. In the figure 19 is the invention

 Verpolschut zschaltung 20 in two different

Embodiments shown. The left illustration shows an arrangement of Verpolschut zschaltung 20 in the positive branch of the power supply. The right-hand illustration of Figure 19 shows the arrangement of Verpolschut zschaltung 20 in the negative branch of the power supply.

The invention is a Verpolschut circuit, which the Low-drop characteristics of a reverse polarity reversal with

MOSFETs with a diode usually reached

Valve effect (prevention of backflow) connects.

For this purpose, a voltage sensor 21 is introduced which controls the drain-source voltage of the respective MOSFET 12

supervised. The drain-source voltage U _DS has opposite polarity to the normal operating case. This case is called in the following case. In the blocking case, the MOSFET 12 operates regularly, ie, not in inverse operation. In the blocking case, the effectively acting control voltage of the MOSFET 12 (gate-source voltage) is significantly reduced, ie significantly below the threshold voltage U _T of

MOSFETs 12. Thus, a lock, ie an opening of the MOSFETs is achieved. The voltage sensor 21 is formed for example by a base-emitter diode of an inserted bipolar transistor 22, which, for example, in the case of a blocking at an amount of the drain-source voltage | U _DS I> 0.6V one

Significant increase in base current of

Bipolar transistor 22 learns. For base current limiting, the base resistor 23 is used, which may be omitted under some circumstances, i. the basis of

Bipolar transistor is connected directly to the drain of the MOSFET. The onset in this context

Collector current of the bipolar transistor 22 reduces the gate-source voltage of the MOSFET 12.

The circuit for generating the gate-source voltage of the MOSFETs 12 is designed with high impedance. In this way, relatively small collector currents of the bipolar transistor 22 can efficiently contribute to reducing the gate-source voltage of the MOSFET 12. In integrated solutions is used to generate the gate-source voltage of the MOSFETs 12th

For example, a high-impedance voltage source 26th used.

In the figure 20 is the use of Verpolschut zschaltung 20 in a variant of the arrangement in both branches

shown. The protection circuit 20 operates either in normal operation (normal case) in which the voltage drops across the

Semiconductor switching elements 12 (MOSFETs) are kept as small as possible or in the case of blocking in which the

Lock semiconductor switching elements and thus a

prevent unwanted current flow. FIG. 20 shows a protective circuit 20 with the addition according to the invention of a voltage sensor 21.

Normal case and blocking case differed with respect to the operating case of the MOSFETs 12 used. - Normal case (operating case) o The MOSFETs 12 operate in inverse operation, ie their drain-source voltage U _DS has opposite to regular operating case REVERSED polarity o Physically, the physical

(express) connections Drain (D) and Source (S) interchanged. Thus, the control voltage between the formal terminals gate and drain (U _G D) is effective. o The electrical parallel to the respective channel of

MOSFETs 12 existing diodes work in

Forward direction, d. H. the MOSFET 12 as

 Entire component can thus not completely lock, which in the case of operation anyway

 is provided, since in this case the channels of the MOSFETs 12 are conductive. The conductivity of the

Transistors 12 is characterized by the between gate and Drain occurring control voltage U _s _invers effected. Disconnect (error) o The polarity U _{DS of} the MOSFETs 12 is reversed at the transition to the blocking case, so that the

 MOSFETS 12 now in regular operation

work (physically, drain is at the drain and source is at the source). o The applied before the switchover of control voltage U _S = U _invers _DG is now the control voltage U _S _ _r eguiar = U _G s · D. h. the transistors 12 remain conductive as long as the control voltage remains unchanged (= prior art). o According to the invention causes the U _DS sensor 21 a

reduce and thus lock the MOSFETs 12 as soon as the absolute value (magnitude) of the drain-source voltage U _D s exceeds a threshold value. o Assuming that the voltage sensor 21 is a bipolar transistor 22 and there is a significant increase in the collector current at an absolute value of the base-emitter voltage U _BE of, for example, 0.6 V, the following relationships result:

^■ N-channel transistor 22: Threshold of the voltage sensor 21 is equal to 0.6V = U _{BE of} the NPN bipolar transistor 22, ie, blocking the MOSFET 12 when U _DS > 0.6V

^■ P-channel transistor 22: Threshold of the voltage sensor 21 is equal to -0.6V = U _{BE of} the PNP bipolar transistor 22, ie, blocking when U _DS <-0.6V invention advantageously takes advantage of the circuit characteristics MOS circuit technology (low-drop, bidirectional

Current flow in normal operation) with the valve effect of a diode circuit in case of error.

In normal operation, the Verpolschut circuit 7 in addition to the low-drop property has no rectifier effect. There are no operating voltage peaks due to permanent overshoots on the communication signals, because the signal energy concerned immediately on the

Supply line is guided back, and thus no additional electronic components for

 Operating voltage limitation are necessary. Within a tolerance range to the regular supply voltage, which can be for example 18V - 30V, is the

 Supply voltage of the connected device within a very small differential voltage range (low-drop property) equal to the supply voltage provided in the system.

In the event of a fault, ie in the so-called blocking case, a valve action occurs at relatively low voltages. The load capacitance lying parallel to the supply voltage in many IO-Link devices 2, which was charged either before the fault, or by signal feeding a still existing or just building up

Supply voltage has leads with the voltage sensor according to the invention to no inadmissibly high currents through the clamping diodes 17 and other components.

The principle of the invention Verpolschut circuit 7 with the use of the voltage sensor 21st

(MOSFET + Bipolartransitor) can be used in the positive and / or negative branch of the supply voltage.

The invention will be described below with reference to an embodiment of a digital IO-Link communication between a Link master 1 and an IO-Link device 2 described.

The reference to the IO-Link standard is to be considered in reference to this description only as a specific embodiment of the implementation. A use of the invention in other standards and arrangements is of course also possible.

With IO-Link the device, which is on the

 Requirements / requesting page (control) is called, 10 Link-Master 1. The device, which requests

answered, IO-Link device 2 is called (sensor / actuator).

The driver ICs used require an overshoot protection by means of (Schottky) diodes and can establish bidirectional digital communication between IO-Link master 1 and IO-Link device 2, ie. H. either via a 3-wire cable (with a communication signal) or via a 4-wire cable (with two communication signals)

communicate.

The embodiment relates to a 4-wire line. The standard reverse polarity switching with diodes 17 is shown in FIG. In case of 3-wire communication, either D4 / D5 or D6 / D7 can be omitted.

To test the protection circuit, practically interesting variants of a faulty connection of an IO-Link master 1 or IO-Link device 2 are tested. For this purpose, as part of a network simulation, a signal stimulator as

so-called test controller used. The test controller contains a 24V DC power source. Furthermore, the test controller contains an internal circuit node

(Short-circuit node), with which the individual cores of the line 3 depending on the test phase (test clock / clock cycle)

can be connected. Each cycle of the line 3 is connected per clock cycle via appropriate switches either o to the voltage source - positive pole or o to the voltage source - negative pole or o to the short-circuit point or o is not connected.

As a result, the test controller 25 has four possible working states per wire. This results in four wires in the line 3 total 4x4x4x4 = 256 test states, which in the test bench in succession, each lasting for one clock cycle,

be simulated. To control the time sequences in the test controller 25, the clock signal 27 is applied to this.

Here is a clock cycle and thus the duration of a

Test state, chosen arbitrarily for the sake of the simulation technique, has been set to 10 ms. Kick in the

 Simulation an inadmissibly high current (for example by a

Clamping diode), which lasts about 10 ms, then it can be assumed that under the in this test condition

If the connection conditions are too high, a permanent, impermissibly high current would be tiled and damage to the application circuit of the IO-Link master 1 or IO-Link device 2 would result. Peak currents in the ps range, however, are normal and are in practice by using appropriate electronic components of the

Application circuit tolerated without damage.

The diagrams of the following

Simulation results in Figure 22 include: o the currents through the clamping diodes 17 Dl to D4

(Generally hazardous components) represented by I (D1) to I (D4) o the currents through the terminals of the device, here as

Current through the series connected to the terminal

 Ferrite Bead 24 (EMC Throttle) presented Ix (ul: 10) to

Ix (u4: 10). The currents through the

 Supply voltage terminals correspond to the drain-to-source currents of the MOSFETs 12 and thus allow detection of destructive high currents through the

MOSFETs 12. o The clock signal V (test_clock) of the test controller.

 With each low-high transition becomes a new one

 Test condition taken. o The supply voltage Udd of the IO-Link device 2

 (Sensor)

The simulation is based on the circuit arrangement shown in Figures 21a and 21b with the invention

This includes the already described components Zener diodes 14, resistor 13 and MOS transistors 12 as shown in FIGS. 13 and 20.

FIG. 21b also shows that consisting of the bipolar transistor 22 (Q1 and Q2) and the basic series resistor 23

Voltage sensor 21, which in both branches of

Power supply are arranged.

The assemblies shown in Figures 21a and 21b with the designations I to V are explained below. (I) Modeling of a device (here sensor) including a detailed model of the interface IC

(II) clamping diodes and resistor network for generating a defined high-Z signal level

(III) reverse-circuit protection according to the invention (IV) ESD / EMC protective circuit and "cable Supply voltage test "for detection of signal feeds (ZIOL2401 feature).

(V) cable model (model of a 20m long

 Four-wire line) and test controller As shown in Figure 22, none occur

destructive continuous currents to the device terminals or the clamping diodes 17. The occurring current peaks can, assuming adequate dimensioning of the circuit, be tolerated. The current peaks result

Switching operations, which can be real, if between different faulty and the correct ones

Connection is changed.

The marked time range (box with dashed

Line) contains all test states in which the device is fed correctly, d. H. there is no signal feed.

A real constructed embodiment of a

Actuator module for an IO-Link master 1 or a 10-link device 2 working protection circuit 4 is in the

Figure 23 shown. To investigate the operation of the invention, those described in FIGS. 21a, 21b and 22 have been described

Test procedure two prior art variants

faced.

In a first variant were opposite to in the

Figure 21 a and b shown the circuit arrangement

 Components bipolar transistor 22 (Ql and Q2) and the associated resistors 23 (R5 and R6) omitted.

In the second variant, in addition to the first variant, a shift of the components for gate voltage generation of the MOS transistors 12, comprising the diodes 14 (D5 and D6) and the resistor 13, made. The circuit arrangement according to variant 1 is in the

Figures 24a and 24b shown. The associated voltage and current waveforms with the illustrated sizes already described for Figure 22 are shown in FIG. FIG. 25 shows the occurrence of impermissibly high levels

 Continuous currents which are countersigned by way of example in FIG. 25 by means of two respective arrows. The regular one

Work area is marked as shown in Figure 22 with a box with a dashed line. There are no critical currents in this area.

The circuit arrangement according to the variant 2 is in the

Figures 23a and 23b shown. The associated voltage and current waveforms with the sizes already described for Figure 22 are shown in FIG. There are inadmissibly high continuous currents, as in the

 FIG. 27 was again characterized by way of example by means of two arrows each. Also in this figure 27 is the regular work area again with a box with

Dashed line marked, and has no power peaks in comparison.

In evaluating both variants, it can be stated that in each case impermissibly high continuous currents occur which potentially lead to the destruction of the MOS transistors 12 (M1, M2), the clamping diodes 17 (D1, D2, D3, D4) or the ferrite beads (Ul, U2, U3 and U4).

The present invention thus provides a

Polarity reversal ready, which has the following advantages: relatively small voltage drop across the Verpolschut z- components, suitable for use as (cable) interface of Control devices such as controllers, actuators,

Sensors etc. - hereinafter generally called "Device" - in conjunction with a multipole (here

For example, four-pin) connection to protect the appropriate arrangement, at any

Omissions of connections, any

Polarity reversal of the connection lines and any short circuits between the conductors, with a protection of the arrangement means that no destruction may occur in the event of a fault, and where no

Impairment of the arrangement in normal operation occur. a disturbing rectifier effect in the normal

Operating case is prevented.

Support for connecting cables, consisting of 2 DC supply voltage lines (usually, in industrial automation 24V) and one, two or more signal lines. As a result, the

Signal lines can supply a low impedance signal, these may also be considered as a voltage source (e.g., 24V) in the event of a fault.

Protection of the components of the IO-Link master or IO-Link device against overcurrent, which in the case of a

Line short occurs.

List of Reference Numerals IO-Link Master

IO-Link device

Line (three- or four-wire)

protection circuit

power supply

ESD protection circuit

Reverse connection

voltage limitation

voltage source

diode

load resistance

MOS transistor

resistance

Zener diode

Overload

undervoltage

clamping diode

additional diode

Load capacitor

reverse polarity switch according to the invention voltage sensor

bipolar transistor

base series

Ferrite Bead

Test controller

Means for generating a high impedance gate voltage U _G s

clock signal

Claims

Arrangement for protecting an electronic

Circuit (1, 2), wherein a MOS transistor (12) in a positive and / or negative branch of a

Voltage supply of the arrangement with a drain-source path, for interrupting a current flow in the respective branch, is arranged, wherein a gate terminal of the MOS transistor (12) with a first terminal of a means for generating a

high-impedance gate voltage (26) (U _G s) is connected, the second terminal is at least indirectly connected to the negative or positive branch of the power supply of the arrangement, characterized

characterized in that a voltage sensor (21) for monitoring a drain-source voltage of a MOS transistor (12) is arranged, which with the drain and source terminal of the MOS transistor (12) for

Voltage monitoring and connected to the gate terminal of the MOS transistor (12) for outputting a control signal.

Arrangement according to claim 1, characterized

characterized in that a bipolar transistor (22) with a base resistor (23) is arranged in the voltage sensor (21) such that a base terminal of the bipolar transistor (22) via the base resistor (23) to the drain terminal of the positive and / or negative Branch of

Supply voltage inserted MOS transistor (12) is connected to an emitter terminal of the

Bipolar transistor (22) to the source terminal of the positive and / or negative branch of the

Supply voltage inserted MOS transistor (12) is connected and that a collector terminal of the Bipolar transistor (22) with the gate terminal of the positive and / or negative branch of the

Supply voltage inserted MOS transistor (12) is connected.

Arrangement according to claim 2, characterized

characterized in that the bipolar transistor (22) in the positive branch of the power supply, a PNP transistor and in the negative branch of the

Power supply is an NPN transistor.

Arrangement according to claim 2 or 3, characterized

characterized in that the MOS transistor (12) in the positive branch of the power supply, a P-channel MOS transistor and in the negative branch of the

Power supply is an N-channel MOS transistor.

Arrangement according to one of claims 1 to 4, characterized in that as a means for generating a high-impedance gate voltage (26) (U _G s), a Zener diode (14) with a resistor (13) is arranged.

A method of protecting an electronic circuit, wherein a semiconductor switching element in a positive and / or negative branch of a

Voltage supply of the arrangement is provided and wherein the semiconductor switching element is turned on by means of a control voltage in the case of operation and locked in the event of an error, characterized

in that a monitoring of a voltage U _D s applied across the semiconductor switching element takes place by means of a voltage monitoring means (21), that in the event of a fault, if the absolute value of the voltage U _DS rises above a threshold value, the semiconductor switching element is replaced by one of

Voltage monitoring means (21) generated

Control voltage is disabled.