WO2015066879A1 - Sigma-delta modulator - Google Patents
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- WO2015066879A1 WO2015066879A1 PCT/CN2013/086718 CN2013086718W WO2015066879A1 WO 2015066879 A1 WO2015066879 A1 WO 2015066879A1 CN 2013086718 W CN2013086718 W CN 2013086718W WO 2015066879 A1 WO2015066879 A1 WO 2015066879A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
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- the invention belongs to the technical field of signal processing, and in particular relates to a sigma-de lta modulator.
- Analog-to-digital converters play a very important role in signal processing.
- a large number of data converters are required in the fields of digital audio, digital television, image coding, and frequency synthesis.
- VLSIs As the size and bias of VLSIs continue to decrease, the accuracy and dynamic range of analog devices continue to decrease, posing a challenge for high resolution ADCs.
- High-order multi-sigma-delta Since the ADC does not require a sample-and-hold circuit, the circuit scale is small, and a high resolution can be realized, so that it is widely used in practice.
- Sigma-delta Since the birth of the modulation technology in the 1960s, after several years of development, it has become one of the mainstream technologies for implementing high-performance analog-to-digital conversion interface circuits in very large-scale integrated circuit systems.
- the Sigma-delta modulator is used to convert a continuous-time, continuous-amplitude input signal into a discrete-time, discrete-amplitude output sequence.
- Sigma-delta The ADC uses oversampling technology combined with noise shaping technology to double suppress quantization noise to achieve high-precision analog-to-digital conversion.
- Oversampling techniques and noise shaping techniques are introduced as follows:
- Noise shaping - noise shaping can further improve the signal to noise ratio of the converter.
- the quantization noise of the low-frequency portion is shifted to the high-frequency portion, and noise in the signal bandwidth is reduced.
- the higher the order and sampling frequency of the high pass filter the less noise there is in the signal bandwidth. But the higher the order, the more unstable the system becomes.
- a common way to achieve noise shaping is to use sigma-delta Modulator.
- the Sigma-delta modulator is mainly composed of an A/D converter and a D/A
- the converter consists of a series of integrators.
- the number of integrators determines the order of the sigma-delta modulator. For example, if there are three integrators connected in series in a single loop modulator, then this single loop
- the sigma-delta modulator is called a single-loop third-order sigma-delta modulator.
- the main performance indicators of the Sigma-delta modulator are: dynamic range (DR), signal-to-noise ratio (SNR), and signal-to-noise ratio (SNDR ), effective number of bits ( ENOB ), and overload ( OL ).
- DR dynamic range
- SNR signal-to-noise ratio
- SNDR signal-to-noise ratio
- ENOB effective number of bits
- OL overload
- the feedback loop requires the use of a multi-bit DAC due to The mismatch of internal components (such as capacitors) of the multi-bit DAC results in a decrease in linearity, and the DAC produces nonlinear noise, which degrades the performance of the entire sigma-delta modulator system.
- the multi-bit DAC nonlinear noise is not processed, which affects the modulator SNR and further improvement of SNDR.
- the modulator can be stable.
- the maximum passband gain of the empirically quantized noise transfer function must be less than 1.5 in a one-bit quantizer design, less than 2.5 in a two-bit quantizer design, and must be less than a three-bit quantizer design. 3.5, and must be less than 5 in a four-bit quantizer design.
- Figure 1 is a three-stage multi-bit sigma-delta modulator of the conventional embodiment.
- First input analog signal X Feeding to an input port of the first adder; the output port of the first adder is coupled to the input port of the first integrator.
- An output port of the first integrator is respectively connected to the second adder and an input port of the first analog to digital converter; the second adder
- the output port of 2 is connected to the input port of the third adder 3;
- the output port of the second integrator 2 is connected to one input port of the fourth adder 4;
- the output port of the fourth adder 4 is connected to the third integrator 3
- the input port is connected; the third integrator 3
- the output port is connected to the input port of the second analog-to-digital converter; one output of the first analog-to-digital converter and the second analog-to-digital converter is output as a digital signal, and the other output is respectively sent to the first digital-to-analog conversion And the second digital-to-ana
- Multi-bit digital-to-analog converter is used in each stage of the feedback loop. For process reasons, multi-bit DAC Non-linear noise is generated, which can seriously affect the performance of the entire sigma-Delta modulator when the nonlinear noise is large.
- the technical problem to be solved by the present invention is to provide a sigma-delta modulator It is designed to perform noise shaping on the nonlinear noise of a multi-bit DAC, thereby suppressing it so that the noise floor is as low as possible.
- a sigma-delta modulator includes:
- a first-order modulation unit for converting an input analog signal into a first-order digital signal;
- the first-order digital signal includes quantization noise and multi-bit DAC nonlinear noise;
- a secondary modulation unit cascading with the primary modulation unit for converting quantization noise and multi-bit DAC nonlinear noise in the primary digital signal into a secondary digital signal, and the secondary digital
- the signal is fed back to the first-level modulation unit, and the first-order modulation unit modulates and converts the input analog signal according to the feedback second-level digital signal;
- noise shaping unit coupled to the primary modulation unit and the secondary modulation unit for canceling the quantization noise in the secondary digital signal and the primary digital signal from a multi-bit DAC nonlinear noise, A digital signal after noise cancellation is obtained and output.
- the primary modulation unit includes: a first adder, a second adder, a third adder, a first integrator, a first analog to digital converter, and a second digital to analog converter; the first adder is in phase The input end is connected to an external analog signal, the output end of the first adder is connected to the input end of the first integrator, and the output end of the first integrator is connected to the non-inverting input end of the second adder, An output of the second adder is connected to an input end of the first analog to digital converter, and an output end of the first analog to digital converter is simultaneously connected to the input of the noise shaping unit and the first digital to analog converter The output end of the first digital-to-analog converter is connected to the inverting input end of the first adder, and the non-inverting input end of the third adder is connected to the output end of the first digital-to-analog converter.
- the inverting input terminal of the third adder is connected to the output end of the second adder;
- the second modulation unit includes: a fourth adder, a fifth adder, a sixth adder, a second integrator, a third integrator, a second analog to digital converter, a third analog to digital converter, and a second number And a non-inverting input of the fourth adder is connected to an output end of the third adder, an output end of the fourth adder is connected to an input end of the second integrator, the second integral
- the output of the fifth integrator is connected to the input of the third integrator
- the output of the fifth integrator is connected to the input of the third integrator
- the output of the third integrator is connected to the third An input end of the analog to digital converter
- an output of the third analog to digital converter is coupled to a first non-inverting input of the sixth adder
- an input of the second analog to digital converter is coupled to the second An output of the integrator, an output of the second analog-to-digital converter being coupled to a second non-inverting input of the sixth adder, an output of the sixth
- the second modulation unit further includes a first gain module, a second gain module, and a third gain module; an output end of the fifth integrator is connected to an input end of the third integrator through the first gain module; An input end of the second analog-to-digital converter is connected to an output end of the second integrator through the second gain module; an output end of the sixth adder is connected to an input end of the third gain module, where The output of the third gain module is simultaneously connected to the input of the noise shaping unit and the second digital to analog converter.
- the first gain module and the second gain module are both 2 times gain, and the third gain module is 1/2 times gain.
- the noise shaping unit includes: a first matching module, a second matching module, and a seventh adder;
- the first matching module and the second matching module are respectively connected to the output ends of the primary modulation unit and the second modulation unit, and the first matching module and the second matching module are used to cooperate with each other. And modulating the secondary digital signal and the quantization noise in the primary digital signal with the multi-bit DAC nonlinear noise into a size-matched noise; the outputs of the first matching module and the second matching module are respectively connected to the a first non-inverting input and a second non-inverting input of the seventh adder.
- this The invention uses interstage feedback combined with a double quantization structure to cancel out the last-order multi-bit DAC nonlinear error and the previous-level quantization noise in the cascade structure, and the final-stage quantization noise and the previous-stage multi-bit DAC nonlinearity.
- the error is also shaped by noise, which greatly improves the
- the sigma-delta modulator outputs the signal-to-noise ratio of the digital signal.
- the experimental results also show that when the internal capacitance of the multi-bit DAC does not match and the nonlinear noise is generated, the performance of the improved structure is significantly better than the conventional structure.
- FIG. 1 is a logical structural diagram of a three-stage multi-bit sigma-delta modulator provided by the prior art
- FIG. 2 is a schematic structural diagram of a sigma-delta modulator provided by the present invention.
- Figure 3 is a diagram showing an example of a specific logic of the sigma-delta modulator shown in Figure 2;
- Figure 4A is a sigma-delta modulator and a conventional sigma-delta provided by the present invention.
- Figure 4B is a sigma-delta modulator and a conventional sigma-delta modulator provided by the present invention.
- the input signal is added to each integrator output and input to the quantizer.
- the output signal is converted by the DAC and subtracted from the input signal. Since the actual circuit, these operations are completed in one cycle. Therefore, the subtracted signal is equivalent to the quantization error of the current period input signal.
- the integrator simply integrates the quantization error (ie, the integrator only processes the quantization noise), thus improving the modulator's structure to suppress multi-bit DAC nonlinear noise, thereby increasing the SNR and SNDR of the entire sigma-delta modulator.
- Fig. 2 shows the structural principle of the sigma-delta modulator provided by the present invention, and for the convenience of description, only the parts related to the present invention are made.
- the sigma-delta modulator provided by the present invention comprises a primary modulation unit 1, a secondary modulation unit 2, and a noise shaping unit 3, wherein the primary modulation unit 1 and the secondary modulation unit 2 are cascaded and form a closed loop structure.
- the noise shaping unit 3 is in turn connected to the primary modulation unit 1 and the secondary modulation unit 2.
- the primary modulation unit 1 is used to convert the input analog signal into a primary digital signal, as described in the background section above (ie, due to a mismatch of internal components (eg, capacitance) of the multi-bit DAC, its linearity is reduced, The DAC produces nonlinear noise, which degrades the performance of the entire delta-sigma modulator system.) Therefore, the first-order digital signal contains multi-bit DAC nonlinear noise, and the first-order digital signal also includes quantization noise.
- the second modulation unit 2 converts the quantization noise in the primary digital signal and the multi-bit DAC nonlinear noise into a secondary digital signal, and feeds the secondary digital signal back to the primary modulation unit,
- the primary modulation unit modulates and converts the input analog signal according to the feedback secondary digital signal.
- the noise shaping unit 3 cancels the quantization noise in the second-level digital signal and the first-order digital signal and the multi-bit DAC nonlinear noise to obtain a digital signal after noise cancellation and outputs the digital signal.
- the multi-bit DAC nonlinear error and the upper-level quantization noise of the last stage in the cascade structure are cancelled, and the final-stage quantization noise and the previous-stage multi-bit DAC nonlinearity are eliminated.
- the error is also shaped by noise, which greatly improves the signal-to-noise ratio of the digital signal output by the sigma-delta modulator.
- FIG. 3 is a specific structural example of the modulator shown in FIG. 2. It should be understood that the specific implementation is not limited to the structure described in FIG. 3, as long as the functions of the various units in FIG. 2 can be implemented.
- the primary modulation unit 1 includes a first adder 11, a second adder 13, a third adder 16, a first integrator 12, a first analog to digital converter 14, and a second digital to analog converter 15. .
- the non-inverting input of the first adder 11 is input to the external analog signal X, the output end is connected to the input end of the first integrator 12, and the output end of the first integrator 12 is connected to the non-inverting input end of the second adder 13, the second addition
- the output end of the first analog-to-digital converter 14 is connected to the input end of the first analog-to-digital converter 14, and the first digital-to-analog conversion is connected to the input end of the first analog-to-digital converter 15
- the output of the first adder 11 is connected to the inverting input of the first adder 11, the non-inverting input of the third adder 16 is connected to the output of the first digital-to-analog converter 15, and the inverting input is connected to the second adder 13. Output.
- the second modulation unit 2 includes: a fourth adder 21, a fifth adder 23, a sixth adder 27, a second integrator 22, a third integrator 24, a second analog to digital converter 25, and a third analog to digital conversion The second digital to analog converter 28.
- the non-inverting input of the fourth adder 21 is connected to the output of the third adder 16, the output of the fourth adder 21 is connected to the input of the second integrator 22, and the output of the second integrator 22 is connected to the fifth adder.
- the output of the fifth integrator 23 is connected to the input of the third integrator 24, and the output of the third integrator 24 is connected to the input of the third analog-to-digital converter 26, the third analog-to-digital converter
- the output of 26 is connected to the first non-inverting input of the sixth adder 27, the input of the second analog-to-digital converter 25 is connected to the output of the second integrator 22, and the output of the second analog-to-digital converter 25 is connected.
- the second non-inverting input of the sixth adder 27, the output of the sixth adder 27 is simultaneously connected to the input ends of the noise shaping unit 3 and the second digital-to-analog converter 28, and the output of the second digital-to-analog converter 28 is simultaneously connected.
- a first gain module 29, a second gain module 20, and a third gain module 211 are further disposed.
- the other connection relationship is that the output end of the fifth integrator 23 is connected through the first gain module 29.
- the input end of the third integrator 24; the input end of the second analog-to-digital converter 25 is connected to the output end of the second integrator 22 through the second gain module 20; the output end of the sixth adder 27 is connected to the third gain module
- the output of the third gain module 211 is simultaneously connected to the input of the noise shaping unit 3 and the second digital to analog converter 28.
- the present invention recommends that both the first gain module 29 and the second gain module 20 are preferably 2x gain, and the third gain module 211 preferably has 1/2 gain.
- the noise shaping unit 3 includes a first matching module 31, a second matching module 32, and a seventh adder 33.
- the first matching module 31 and the second matching module 32 are respectively connected to the output terminals 2 of the first-level modulation unit 1 and the second-level modulation unit.
- the first matching module 31 is connected to the output end of the first analog-to-digital converter, and the second matching is performed.
- Module 32 is coupled to the output of the third gain module.
- the first matching module 31 and the second matching module 32 are configured to modulate the quantization noise in the second-level digital signal and the first-level digital signal with the multi-bit DAC nonlinear noise into a matching noise by interworking; the first matching module 31 and The output ends of the second matching module 32 are respectively connected to the first non-inverting input and the second non-inverting input of the seventh adder 33.
- the digital output of the first stage and the second stage are respectively input to the digital circuit 1, the digital circuit 2, and the final digital output is obtained by the adder 7:
- Y 1 (z), Y 2 (z) are the first stage, the second stage digital output, E 1 (z), E 2 (z), E 3 (z) are quantizer 1, quantizer 2
- the quantization noise of the quantizer 3 E d1 (z), E d2 (z) are the first-order DAC1 and the second-stage DAC2 nonlinear noise, respectively.
- the second multi-bit non-linear noise is DAC2 second order noise shaping and quantization noise E 1 (z), E 2 (z) is also effectively suppressed (i.e., multiplied by a gain 1 / 2).
- Figure 4A compares the signal-to-noise distortion ratio of the sigma-delta modulator output digital signal with an input signal amplitude of 6 dB, where the dashed line represents the signal-to-noise distortion ratio curve of the present invention, and the solid line represents the conventional signal-to-noise distortion ratio curve. . It can be seen from the comparison of FIG. 4A that the conventional embodiment causes system distortion due to multi-bit DAC nonlinear noise, thereby degrading the performance of the modulator system; however, in the embodiment of the present invention, the nonlinear noise of the multi-bit DAC is effectively suppressed. Thereby improving the modulator signal-to-noise ratio.
- Figure 4B compares the signal-to-noise distortion ratio of the sigma-delta modulator output digital signal with different input signal amplitudes. It can be seen from the comparison of FIG. 4B that the input dynamic range of the embodiment of the present invention is not reduced under the same simulation conditions, wherein the above one curve (Improved) is the signal-to-noise distortion of the output digital signal of the sigma-delta modulator of the present invention.
- the following curve (Conventional) is the signal-to-noise ratio of the digital signal output by the conventional sigma-delta modulator.
- the present invention feeds back the second stage analog input signal back to the first stage on the basis of the conventional Sigma-delta modulator structure, and adds a multi-bit quantizer to the second stage, and the second stage two
- the digital outputs of the multi-bit quantizers are summed to obtain the final digital output of the second stage.
- This feedback double quantization structure helps to reduce the overall quantization noise value, thereby improving the system SNR, and performing second-order noise shaping on the nonlinear noise of the last-stage multi-bit DAC, thereby effectively suppressing the nonlinear noise of the multi-bit DAC.
- the invention relates to the field of analog signal to digital signal with high precision and high signal to noise ratio, which mainly improves the stability of the converter and reduces the power consumption of the converter, thereby improving the performance of the converter.
- Suitable for some portable products such as mobile phones, PDAs.
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Abstract
The present invention is suitable for use in the technical field of signal processing and provides a sigma-delta modulator, comprising a primary modulation unit, used for converting an inputted analog signal to a primary digital signal; the primary digital signal comprising quantization noise and multi-bit DAC nonlinear noise; a secondary modulation unit, cascaded with the primary modulation unit and used for converting the quantization noise in the primary digital signal and the multi-bit DAC nonlinear noise to a secondary signal, and feeding said secondary digital signal back to said primary modulation unit; a noise shaping unit, connected to the primary modulation unit and the secondary modulation unit and used for cancellation of the quantization noise in the primary digital signal and the multi-bit DAC nonlinear noise, to obtain a noise-cancelled digital signal and output same. The present invention uses a combined configuration of inter-stage feedback and dual quantization to offset the multi-bit DAC nonlinear error of the last stage and the quantization noise of the previous stage.
Description
本发明属于信号处理技术领域,尤其涉及一种 sigma-de lta 调制器。 The invention belongs to the technical field of signal processing, and in particular relates to a sigma-de lta modulator.
模数转换器(ADC)在信号处理中起了一个非常重要的作用。在数字音频、数字电视、图像编码及频率合成等领域需要大量的数据转换器。由于超大规模集成电路的尺寸和偏压不断减少,模拟器件的精度和动态范围也不断降低,对于实现高分辨率的ADC是一种挑战。高阶多位sigma-delta
ADC由于不需要采样保持电路,电路规模小,可以实现较高的分辨率,因此在实际中得到广泛的应用。
Analog-to-digital converters (ADCs) play a very important role in signal processing. A large number of data converters are required in the fields of digital audio, digital television, image coding, and frequency synthesis. As the size and bias of VLSIs continue to decrease, the accuracy and dynamic range of analog devices continue to decrease, posing a challenge for high resolution ADCs. High-order multi-sigma-delta
Since the ADC does not require a sample-and-hold circuit, the circuit scale is small, and a high resolution can be realized, so that it is widely used in practice.
Sigma-delta
调制技术自二十世纪六十年代诞生以来,经过若干年的发展,现已成为超大规模集成电路系统中实现高性能模数转换接口电路的主流技术之一。基于sigma-delta调制技术的sigma-delta数据转换器,结合应用过采样技术和噪声整形技术,能够把量化噪声推到高频端,从而显著的提高数据转换器的信噪比。简而言之,Sigma-delta调制器用以将一连续时间,连续幅度的输入信号转换成为一离散时间,离散幅度的输出序列。 Sigma-delta
Since the birth of the modulation technology in the 1960s, after several years of development, it has become one of the mainstream technologies for implementing high-performance analog-to-digital conversion interface circuits in very large-scale integrated circuit systems. The sigma-delta data converter based on sigma-delta modulation technology, combined with the application of oversampling technology and noise shaping technology, can push the quantization noise to the high frequency end, thereby significantly improving the signal to noise ratio of the data converter. In short, the Sigma-delta modulator is used to convert a continuous-time, continuous-amplitude input signal into a discrete-time, discrete-amplitude output sequence.
如上文所述,Sigma-delta
ADC采用过采样技术跟噪声整形技术相结合,对量化噪声进行双重抑制,从而实现高精度模数转换。过采样技术和噪声整形技术分别介绍如下: As mentioned above, Sigma-delta
The ADC uses oversampling technology combined with noise shaping technology to double suppress quantization noise to achieve high-precision analog-to-digital conversion. Oversampling techniques and noise shaping techniques are introduced as follows:
过采样---sigma-delta
ADC采用远远高于Nyquist频率的时钟对输入信号进行采样,使得量化噪声的功率分布在更宽的频带内,这样就减少了信号频带内的噪声。 Oversampling---sigma-delta
The ADC samples the input signal with a clock much higher than the Nyquist frequency, so that the power of the quantization noise is distributed over a wider frequency band, thus reducing noise in the signal band.
噪声整形---噪声整形可以进一步提高转换器的信噪比。利用高通滤波器的特性,将低频部分的量化噪声移到高频部分,减少了信号带宽内的噪声。高通滤波器的阶数和采样频率越高,信号带宽内的噪声就越小。但阶数越高,系统就会变得越不稳定。实现噪声整形的一种常见方法就是采用sigma-delta
调制器。
Noise shaping - noise shaping can further improve the signal to noise ratio of the converter. By using the characteristics of the high-pass filter, the quantization noise of the low-frequency portion is shifted to the high-frequency portion, and noise in the signal bandwidth is reduced. The higher the order and sampling frequency of the high pass filter, the less noise there is in the signal bandwidth. But the higher the order, the more unstable the system becomes. A common way to achieve noise shaping is to use sigma-delta
Modulator.
在实际的设计中,需要根据设计指标、稳定性和动态范围等进行折中考虑。对于单环路高阶(三阶以上)sigma-delta
ADC来说,最大的问题就是稳定性。为了保持高阶SDM(sigma-delta
modulator)的稳定性,我们可以使用多位量化器,但这会增加后续内部DAC的设计难度,如果处理不妥当会产生大量的谐波分量,反而使sigma-delta
ADC的性能下降。
In the actual design, compromises need to be made based on design specifications, stability, and dynamic range. For single-loop high-order (third-order or higher) sigma-delta
For ADC, the biggest problem is stability. In order to maintain high-order SDM (sigma-delta
Modulator), we can use multi-bit quantizer, but this will increase the design difficulty of the subsequent internal DAC, if it is not handled properly, it will generate a lot of harmonic components, but make sigma-delta
The performance of the ADC is degraded.
Sigma-delta 调制器主要由一个 A/D 转换器、一个 D/A
转换器和一系列的串联积分器组成。积分器的个数决定了 sigma-delta 调制器的阶数。如:单环路调制器中有三个积分器串联,则此单环路
sigma-delta 调制器就称为单环路三阶 sigma-delta 调制器。 The Sigma-delta modulator is mainly composed of an A/D converter and a D/A
The converter consists of a series of integrators. The number of integrators determines the order of the sigma-delta modulator. For example, if there are three integrators connected in series in a single loop modulator, then this single loop
The sigma-delta modulator is called a single-loop third-order sigma-delta modulator.
Sigma-delta 调制器的主要性能指标为:动态范围( DR )、信噪比( SNR )、信噪失真比(
SNDR )、有效位数( ENOB )、以及过载度( OL )。 The main performance indicators of the Sigma-delta modulator are: dynamic range (DR), signal-to-noise ratio (SNR), and signal-to-noise ratio (
SNDR ), effective number of bits ( ENOB ), and overload ( OL ).
在传统的多比特 sigma-delta ADC 结构中,反馈回路需要使用多比特 DAC ,由于
多比特DAC内部元件(如电容)的不匹配导致其线性度下降,DAC产生非线性噪声,使得整个 sigma-delta 调制器系统性能下降。在传统多比特
sigma-delta ADC 结构中,并没有对多比特 DAC 非线性噪声进行处理,进而影响调制器 SNR 以及 SNDR 的进一步提升。 In traditional multi-bit sigma-delta ADC architectures, the feedback loop requires the use of a multi-bit DAC due to
The mismatch of internal components (such as capacitors) of the multi-bit DAC results in a decrease in linearity, and the DAC produces nonlinear noise, which degrades the performance of the entire sigma-delta modulator system. In traditional multi-bit
In the sigma-delta ADC structure, the multi-bit DAC nonlinear noise is not processed, which affects the modulator SNR and further improvement of SNDR.
为了使单环 sigma-delta
调制器能够稳定,经验上量化噪声传输函数的最大通带增益在一位量化器设计下必须小于 1.5 ,在二位量化器设计下必须小于 2.5 ,在三位量化器设计下必须小于
3.5 ,以及在四位量化器设计下必须小于 5 。 In order to make a single ring sigma-delta
The modulator can be stable. The maximum passband gain of the empirically quantized noise transfer function must be less than 1.5 in a one-bit quantizer design, less than 2.5 in a two-bit quantizer design, and must be less than a three-bit quantizer design.
3.5, and must be less than 5 in a four-bit quantizer design.
图 1 为传统实施例的三阶级联多比特 sigma-delta 调制器。首先输入的模拟信号 X
馈送到第一加法器的一个输入端口;第一加法器的输出端口与第一积分器的输入端口进行相连。第一积分器的输出端口分别与第二加法器以及第一模数转换器的输入端口相连;第二加法器
2 的输出端口与第三加法器 3 的输入端口相连;第二积分器 2 的输出端口与第四加法器 4 的一个输入端口相连;第四加法器 4 的输出端口与第三积分器 3
的输入端口相连;第三积分器 3
的输出端口与第二模数转换器的输入端口相连;第一模数转换器、第二模数转换器的一路输出作为数字信号输出,而另一路输出则分别送入到第一数模转换器、第二数模转换器;上述两个数模转换器把转换后的模拟信号分为三路:第一路模拟信号反馈回输入端第一加法器的另一个输入端口;第二路模拟信号反馈回输入端第三加法器的另一个输入端口;第三路模拟信号通过增益系数
Gain1 反馈回第四加法器的另一个输入端口。第一模数转换器、第二模数转换器输出的数字信号分别通过第一数字电路 1 、第二数字电路得到最终的数字信号 Y
并输出。 Figure 1 is a three-stage multi-bit sigma-delta modulator of the conventional embodiment. First input analog signal X
Feeding to an input port of the first adder; the output port of the first adder is coupled to the input port of the first integrator. An output port of the first integrator is respectively connected to the second adder and an input port of the first analog to digital converter; the second adder
The output port of 2 is connected to the input port of the third adder 3; the output port of the second integrator 2 is connected to one input port of the fourth adder 4; the output port of the fourth adder 4 is connected to the third integrator 3
The input port is connected; the third integrator 3
The output port is connected to the input port of the second analog-to-digital converter; one output of the first analog-to-digital converter and the second analog-to-digital converter is output as a digital signal, and the other output is respectively sent to the first digital-to-analog conversion And the second digital-to-analog converter; the two digital-to-analog converters divide the converted analog signal into three paths: the first analog signal is fed back to the other input port of the first adder at the input end; the second analog The signal is fed back to the other input port of the third adder at the input; the third analog signal passes the gain coefficient
Gain1 feeds back to the other input port of the fourth adder. The digital signals output by the first analog-to-digital converter and the second analog-to-digital converter respectively obtain the final digital signal through the first digital circuit 1 and the second digital circuit.
And output.
传统的 sigma-delta 调制器具有以下缺点: Traditional sigma-delta modulators have the following disadvantages:
1 、在每一级反馈回路使用多比特数模转换器( DAC ),由于工艺原因,多比特 DAC
会产生非线性噪声,当非线性噪声较大时,会严重影响整个 sigma-Delta 调制器性能。 1. Multi-bit digital-to-analog converter (DAC) is used in each stage of the feedback loop. For process reasons, multi-bit DAC
Non-linear noise is generated, which can seriously affect the performance of the entire sigma-Delta modulator when the nonlinear noise is large.
2 、没有使用相关措施对多比特 DAC 非线性噪声进行处理,使得多比特 DAC
非线性噪声直接输出。 2, no relevant measures are used to deal with multi-bit DAC nonlinear noise, making multi-bit DAC
Direct output of nonlinear noise.
本发明所要解决的技术问题在于提供一种 sigma-delta 调制器
,旨在对多比特DAC的非线性噪声进行噪声整形,从而对其进行抑制,使其噪声底部尽可能的低。 The technical problem to be solved by the present invention is to provide a sigma-delta modulator
It is designed to perform noise shaping on the nonlinear noise of a multi-bit DAC, thereby suppressing it so that the noise floor is as low as possible.
本发明是这样实现的,一种 sigma-delta 调制器 ,包括: The present invention is implemented in such a manner that a sigma-delta modulator includes:
一级调制单元,用于将输入的模拟信号转换为一级数字信号;所述一级数字信号中包含有量化噪声与多比特DAC非线性噪声;
a first-order modulation unit for converting an input analog signal into a first-order digital signal; the first-order digital signal includes quantization noise and multi-bit DAC nonlinear noise;
二级调制单元,其与所述一级调制单元级联,用于将所述一级数字信号中的量化噪声与多比特DAC非线性噪声转换为二级数字信号,并将所述二级数字信号反馈至所述一级调制单元,由所述一级调制单元根据反馈的所述二级数字信号对输入的模拟信号进行调制和转换;
a secondary modulation unit cascading with the primary modulation unit for converting quantization noise and multi-bit DAC nonlinear noise in the primary digital signal into a secondary digital signal, and the secondary digital The signal is fed back to the first-level modulation unit, and the first-order modulation unit modulates and converts the input analog signal according to the feedback second-level digital signal;
噪声整形单元,与所述一级调制单元和所述二级调制单元连接,用于将所述二级数字信号与所述一级数字信号中的量化噪声与多比特DAC非线性噪声相消,得到消除噪声后的数字信号并输出。
a noise shaping unit coupled to the primary modulation unit and the secondary modulation unit for canceling the quantization noise in the secondary digital signal and the primary digital signal from a multi-bit DAC nonlinear noise, A digital signal after noise cancellation is obtained and output.
进一步地,
所述一级调制单元包括:第一加法器、第二加法器、第三加法器、第一积分器、第一模数转换器、第二数模转换器;所述第一加法器的同相输入端供外部模拟信号输入,所述第一加法器的输出端连接所述第一积分器的输入端,所述第一积分器的输出端连接所述第二加法器的同相输入端,所述第二加法器的输出端连接所述第一模数转换器的输入端,所述第一模数转换器的输出端同时连接所述噪声整形单元和所述第一数模转换器的输入端,所述第一数模转换器的输出端连接所述第一加法器的反相输入端,所述第三加法器的同相输入端连接所述第一数模转换器的输出端,所述第三加法器的反相输入端连接所述第二加法器的输出端; further,
The primary modulation unit includes: a first adder, a second adder, a third adder, a first integrator, a first analog to digital converter, and a second digital to analog converter; the first adder is in phase The input end is connected to an external analog signal, the output end of the first adder is connected to the input end of the first integrator, and the output end of the first integrator is connected to the non-inverting input end of the second adder, An output of the second adder is connected to an input end of the first analog to digital converter, and an output end of the first analog to digital converter is simultaneously connected to the input of the noise shaping unit and the first digital to analog converter The output end of the first digital-to-analog converter is connected to the inverting input end of the first adder, and the non-inverting input end of the third adder is connected to the output end of the first digital-to-analog converter. The inverting input terminal of the third adder is connected to the output end of the second adder;
所述二级调制单元包括:第四加法器、第五加法器、第六加法器、第二积分器、第三积分器、第二模数转换器、第三模数转换器、第二数模转换器;所述第四加法器的同相输入端连接所述第三加法器的输出端,所述第四加法器的输出端连接所述第二积分器的输入端,所述第二积分器的输出端连接所述第五加法器的同相输入端,所述第五积分器的输出端连接所述第三积分器的输入端,所述第三积分器的输出端连接所述第三模数转换器的输入端,所述第三模数转换器的输出端连接所述第六加法器的第一同相输入端,所述第二模数转换器的输入端连接所述第二积分器的输出端,所述第二模数转换器的输出端连接所述第六加法器的第二同相输入端,所述第六加法器的输出端同时连接所述噪声整形单元和所述第二数模转换器的输入端,所述第二数模转换器的输出端同时连接所述第四加法器的反相输入端、第五加法器的反相输入端、第二加法器的反相输入端。
The second modulation unit includes: a fourth adder, a fifth adder, a sixth adder, a second integrator, a third integrator, a second analog to digital converter, a third analog to digital converter, and a second number And a non-inverting input of the fourth adder is connected to an output end of the third adder, an output end of the fourth adder is connected to an input end of the second integrator, the second integral The output of the fifth integrator is connected to the input of the third integrator, the output of the fifth integrator is connected to the input of the third integrator, and the output of the third integrator is connected to the third An input end of the analog to digital converter, an output of the third analog to digital converter is coupled to a first non-inverting input of the sixth adder, and an input of the second analog to digital converter is coupled to the second An output of the integrator, an output of the second analog-to-digital converter being coupled to a second non-inverting input of the sixth adder, an output of the sixth adder simultaneously connecting the noise shaping unit and the An input of a second digital to analog converter, the second digital to analog converter The output terminal is simultaneously connected to the inverting input terminal of the fourth adder, the inverting input terminal of the fifth adder, and the inverting input terminal of the second adder.
进一步地,
所述二级调制单元还包括第一增益模块、第二增益模块、第三增益模块;所述第五积分器的输出端通过所述第一增益模块连接所述第三积分器的输入端;所述第二模数转换器的输入端通过所述第二增益模块连接所述第二积分器的输出端;所述第六加法器的输出端连接所述第三增益模块的输入端,所述第三增益模块的输出端同时连接所述噪声整形单元和所述第二数模转换器的输入端。 further,
The second modulation unit further includes a first gain module, a second gain module, and a third gain module; an output end of the fifth integrator is connected to an input end of the third integrator through the first gain module; An input end of the second analog-to-digital converter is connected to an output end of the second integrator through the second gain module; an output end of the sixth adder is connected to an input end of the third gain module, where The output of the third gain module is simultaneously connected to the input of the noise shaping unit and the second digital to analog converter.
进一步地,
所述第一增益模块和所述第二增益模块均为2倍增益,所述第三增益模块为1/2倍增益。 further,
The first gain module and the second gain module are both 2 times gain, and the third gain module is 1/2 times gain.
进一步地, 所述噪声整形单元包括:第一匹配模块、第二匹配模块、第七加法器; Further, the noise shaping unit includes: a first matching module, a second matching module, and a seventh adder;
所述第一匹配模块和所述第二匹配模块分别连接所述一级调制单元和所述二级调制单元的输出端,所述第一匹配模块和所述第二匹配模块用于通过互相配合将所述二级数字信号与所述一级数字信号中的量化噪声与多比特DAC非线性噪声调制成大小匹配的噪声;所述第一匹配模块和第二匹配模块的输出端分别连接所述第七加法器的第一同相输入端和第二同相输入端。
The first matching module and the second matching module are respectively connected to the output ends of the primary modulation unit and the second modulation unit, and the first matching module and the second matching module are used to cooperate with each other. And modulating the secondary digital signal and the quantization noise in the primary digital signal with the multi-bit DAC nonlinear noise into a size-matched noise; the outputs of the first matching module and the second matching module are respectively connected to the a first non-inverting input and a second non-inverting input of the seventh adder.
本
发明使用级间反馈与双量化结构相结合,抵消了级联结构中最后一级的多比特DAC非线性误差与上一级量化噪声,而最后一级量化噪声与上一级多比特DAC非线性误差也同样被噪声整形,这极大的提高了
sigma-delta 调制器输出数字信号的信噪失真比。实验结果也表明,当多比特DAC内部电容不匹配而产生非线性噪声时,改进结构的性能明显优于传统结构。
this
The invention uses interstage feedback combined with a double quantization structure to cancel out the last-order multi-bit DAC nonlinear error and the previous-level quantization noise in the cascade structure, and the final-stage quantization noise and the previous-stage multi-bit DAC nonlinearity. The error is also shaped by noise, which greatly improves the
The sigma-delta modulator outputs the signal-to-noise ratio of the digital signal. The experimental results also show that when the internal capacitance of the multi-bit DAC does not match and the nonlinear noise is generated, the performance of the improved structure is significantly better than the conventional structure.
图1是现有技术提供的 三阶级联多比特 sigma-delta 调制器的逻辑结构图; 1 is a logical structural diagram of a three-stage multi-bit sigma-delta modulator provided by the prior art;
图2是本发明 提供的 sigma-delta 调制器的结构原理图; 2 is a schematic structural diagram of a sigma-delta modulator provided by the present invention;
图3是图2所示 sigma-delta 调制器的一种具体的 逻辑结示例图; Figure 3 is a diagram showing an example of a specific logic of the sigma-delta modulator shown in Figure 2;
图4A是本发明 提供的 sigma-delta 调制器和传统的 sigma-delta
调制器在固定输入信号幅度的情况下的 输出数字信号的信噪失真比; Figure 4A is a sigma-delta modulator and a conventional sigma-delta provided by the present invention.
The signal-to-noise-distortion ratio of the output digital signal of the modulator with a fixed input signal amplitude;
图4B是本发明 提供的 sigma-delta 调制器和传统的 sigma-delta 调制器在
不同输入信号幅度的情况下的输出数字信号的信噪失真比。 Figure 4B is a sigma-delta modulator and a conventional sigma-delta modulator provided by the present invention.
The signal-to-noise distortion ratio of the output digital signal with different input signal amplitudes.
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
本发明中,输入信号与每个积分器输出相加后输入量化器,经过量化后,输出信号经过DAC转换后与输入信号进行相减,由于实际电路中,这些运算都是在一个周期内完成的,因此相减后的信号相当于当前周期输入信号的量化误差。积分器只是对量化误差进行积分(即积分器只处理量化噪声),因而改进调制器的结构对多比特DAC非线性噪声进行抑制,从而提高了整个Sigma-delta调制器的SNR以及SNDR。In the present invention, the input signal is added to each integrator output and input to the quantizer. After quantization, the output signal is converted by the DAC and subtracted from the input signal. Since the actual circuit, these operations are completed in one cycle. Therefore, the subtracted signal is equivalent to the quantization error of the current period input signal. The integrator simply integrates the quantization error (ie, the integrator only processes the quantization noise), thus improving the modulator's structure to suppress multi-bit DAC nonlinear noise, thereby increasing the SNR and SNDR of the entire sigma-delta modulator.
图2示出了本发明提供的sigma-delta调制器的结构原理,为了便于描述,仅使出了与本发明相关的部分。参照图2,本发明提供的sigma-delta调制器包括一级调制单元1、二级调制单元2、噪声整形单元3,其中一级调制单元1与二级调制单元2级联并形成一闭环结构,噪声整形单元3又同时连接一级调制单元1和二级调制单元2。Fig. 2 shows the structural principle of the sigma-delta modulator provided by the present invention, and for the convenience of description, only the parts related to the present invention are made. Referring to FIG. 2, the sigma-delta modulator provided by the present invention comprises a primary modulation unit 1, a secondary modulation unit 2, and a noise shaping unit 3, wherein the primary modulation unit 1 and the secondary modulation unit 2 are cascaded and form a closed loop structure. The noise shaping unit 3 is in turn connected to the primary modulation unit 1 and the secondary modulation unit 2.
一级调制单元1用于将输入的模拟信号转换为一级数字信号,如前文背景技术部分所述的原因(即,由于多比特DAC内部元件(如电容)的不匹配导致其线性度下降,DAC产生非线性噪声,使得整个Δ-Σ调制器系统性能下降。),因此一级数字信号中包含有多比特DAC非线性噪声,另外,该一级数字信号中也包含有量化噪声。The primary modulation unit 1 is used to convert the input analog signal into a primary digital signal, as described in the background section above (ie, due to a mismatch of internal components (eg, capacitance) of the multi-bit DAC, its linearity is reduced, The DAC produces nonlinear noise, which degrades the performance of the entire delta-sigma modulator system.) Therefore, the first-order digital signal contains multi-bit DAC nonlinear noise, and the first-order digital signal also includes quantization noise.
二级调制单元2将所述一级数字信号中的量化噪声与多比特DAC非线性噪声转换为二级数字信号,并将所述二级数字信号反馈至所述一级调制单元,由所述一级调制单元根据反馈的所述二级数字信号对输入的模拟信号进行调制和转换。最后由噪声整形单元3将所述二级数字信号与所述一级数字信号中的量化噪声与多比特DAC非线性噪声相消,得到消除噪声后的数字信号并输出。The second modulation unit 2 converts the quantization noise in the primary digital signal and the multi-bit DAC nonlinear noise into a secondary digital signal, and feeds the secondary digital signal back to the primary modulation unit, The primary modulation unit modulates and converts the input analog signal according to the feedback secondary digital signal. Finally, the noise shaping unit 3 cancels the quantization noise in the second-level digital signal and the first-order digital signal and the multi-bit DAC nonlinear noise to obtain a digital signal after noise cancellation and outputs the digital signal.
通过上述级间反馈与双量化结构相结合,抵消了级联结构中最后一级的多比特DAC非线性误差与上一级量化噪声,而最后一级量化噪声与上一级多比特DAC非线性误差也同样被噪声整形,这极大的提高了sigma-delta调制器输出数字信号的信噪失真比。Through the combination of the above-mentioned interstage feedback and the double quantization structure, the multi-bit DAC nonlinear error and the upper-level quantization noise of the last stage in the cascade structure are cancelled, and the final-stage quantization noise and the previous-stage multi-bit DAC nonlinearity are eliminated. The error is also shaped by noise, which greatly improves the signal-to-noise ratio of the digital signal output by the sigma-delta modulator.
图3为图2所示调制器的一种具体结构示例,应当理解,具体实施时不限于图3所述的结构,只要能实现图2中的各个单元的功能即可。FIG. 3 is a specific structural example of the modulator shown in FIG. 2. It should be understood that the specific implementation is not limited to the structure described in FIG. 3, as long as the functions of the various units in FIG. 2 can be implemented.
参照图3,一级调制单元1包括:第一加法器11、第二加法器13、第三加法器16、第一积分器12、第一模数转换器14、第二数模转换器15
。第一加法器11的同相输入端供外部模拟信号X输入,输出端连接第一积分器12的输入端,第一积分器12的输出端连接第二加法器13的同相输入端,第二加法器13的输出端连接第一模数转换器14的输入端,第一模数转换器14的输出端同时连接噪声整形单元3和第一数模转换器15的输入端,第一数模转换器15的输出端连接第一加法器11的反相输入端,第三加法器16的同相输入端连接第一数模转换器15的输出端,反相输入端则连接第二加法器13的输出端。Referring to FIG. 3, the primary modulation unit 1 includes a first adder 11, a second adder 13, a third adder 16, a first integrator 12, a first analog to digital converter 14, and a second digital to analog converter 15.
. The non-inverting input of the first adder 11 is input to the external analog signal X, the output end is connected to the input end of the first integrator 12, and the output end of the first integrator 12 is connected to the non-inverting input end of the second adder 13, the second addition The output end of the first analog-to-digital converter 14 is connected to the input end of the first analog-to-digital converter 14, and the first digital-to-analog conversion is connected to the input end of the first analog-to-digital converter 15 The output of the first adder 11 is connected to the inverting input of the first adder 11, the non-inverting input of the third adder 16 is connected to the output of the first digital-to-analog converter 15, and the inverting input is connected to the second adder 13. Output.
二级调制单元2包括:第四加法器21、第五加法器23、第六加法器27、第二积分器22、第三积分器24、第二模数转换器25、第三模数转换器26、第二数模转换器28。第四加法器21的同相输入端连接第三加法器16的输出端,第四加法器21的输出端连接第二积分器22的输入端,第二积分器22的输出端连接第五加法器23的同相输入端,第五积分器23的输出端连接第三积分器24的输入端,第三积分器24的输出端连接第三模数转换器26的输入端,第三模数转换器26的输出端连接第六加法器27的第一同相输入端,第二模数转换器25的输入端连接第二积分器22的输出端,第二模数转换器25的输出端连接第六加法器27的第二同相输入端,第六加法器27的输出端同时连接噪声整形单元3和第二数模转换器28的输入端,第二数模转换器28的输出端同时连接第四加法器21的反相输入端、第五加法器23的反相输入端、第二加法器13的反相输入端。The second modulation unit 2 includes: a fourth adder 21, a fifth adder 23, a sixth adder 27, a second integrator 22, a third integrator 24, a second analog to digital converter 25, and a third analog to digital conversion The second digital to analog converter 28. The non-inverting input of the fourth adder 21 is connected to the output of the third adder 16, the output of the fourth adder 21 is connected to the input of the second integrator 22, and the output of the second integrator 22 is connected to the fifth adder. At the non-inverting input of 23, the output of the fifth integrator 23 is connected to the input of the third integrator 24, and the output of the third integrator 24 is connected to the input of the third analog-to-digital converter 26, the third analog-to-digital converter The output of 26 is connected to the first non-inverting input of the sixth adder 27, the input of the second analog-to-digital converter 25 is connected to the output of the second integrator 22, and the output of the second analog-to-digital converter 25 is connected. The second non-inverting input of the sixth adder 27, the output of the sixth adder 27 is simultaneously connected to the input ends of the noise shaping unit 3 and the second digital-to-analog converter 28, and the output of the second digital-to-analog converter 28 is simultaneously connected. The inverting input terminal of the quad-adder 21, the inverting input terminal of the fifth adder 23, and the inverting input terminal of the second adder 13.
进一步地,为提高整体信噪比,还设置有第一增益模块29、第二增益模块20、第三增益模块211,其他连接关系为第五积分器23的输出端通过第一增益模块29连接所述第三积分器24的输入端;第二模数转换器25的输入端通过第二增益模块20连接第二积分器22的输出端;第六加法器27的输出端连接第三增益模块211的输入端,所述第三增益模块211的输出端同时连接噪声整形单元3和第二数模转换器28的输入端。Further, in order to improve the overall signal-to-noise ratio, a first gain module 29, a second gain module 20, and a third gain module 211 are further disposed. The other connection relationship is that the output end of the fifth integrator 23 is connected through the first gain module 29. The input end of the third integrator 24; the input end of the second analog-to-digital converter 25 is connected to the output end of the second integrator 22 through the second gain module 20; the output end of the sixth adder 27 is connected to the third gain module At the input of 211, the output of the third gain module 211 is simultaneously connected to the input of the noise shaping unit 3 and the second digital to analog converter 28.
本发明推荐第一增益模块29和第二增益模块20均优选为2倍增益,第三增益模块211优选1/2倍增益。The present invention recommends that both the first gain module 29 and the second gain module 20 are preferably 2x gain, and the third gain module 211 preferably has 1/2 gain.
噪声整形单元3包括:第一匹配模块31、第二匹配模块32、第七加法器33。第一匹配模块31和第二匹配模块32分别连接一级调制单元1和二级调制单元的输出端2,具体的,第一匹配模块31连接第一模数转换器的输出端,第二匹配模块32连接第三增益模块的输出端。第一匹配模块31和第二匹配模块32用于通过互相配合将二级数字信号与一级数字信号中的量化噪声与多比特DAC非线性噪声调制成大小匹配的噪声;第一匹配模块31和第二匹配模块32的输出端分别连接第七加法器33的第一同相输入端和第二同相输入端。The noise shaping unit 3 includes a first matching module 31, a second matching module 32, and a seventh adder 33. The first matching module 31 and the second matching module 32 are respectively connected to the output terminals 2 of the first-level modulation unit 1 and the second-level modulation unit. Specifically, the first matching module 31 is connected to the output end of the first analog-to-digital converter, and the second matching is performed. Module 32 is coupled to the output of the third gain module. The first matching module 31 and the second matching module 32 are configured to modulate the quantization noise in the second-level digital signal and the first-level digital signal with the multi-bit DAC nonlinear noise into a matching noise by interworking; the first matching module 31 and The output ends of the second matching module 32 are respectively connected to the first non-inverting input and the second non-inverting input of the seventh adder 33.
以第一级、第二级数字输出为例:Take the first-level and second-level digital outputs as an example:
分别将第一级,第二级的数字输出输入到数字电路1,数字电路2 ,通过加法器7得到最终的数字输出: The digital output of the first stage and the second stage are respectively input to the digital circuit 1, the digital circuit 2, and the final digital output is obtained by the adder 7:
其中Y1(z), Y2(z)
分别为第一级,第二级数字输出,E1(z), E2(z), E3(z)
分别为量化器1,量化器2,量化器3的量化噪声, Ed1(z), Ed2(z)
分别为第一级DAC1,第二级DAC2非线性噪声 。Where Y 1 (z), Y 2 (z) are the first stage, the second stage digital output, E 1 (z), E 2 (z), E 3 (z) are quantizer 1, quantizer 2 The quantization noise of the quantizer 3, E d1 (z), E d2 (z) are the first-order DAC1 and the second-stage DAC2 nonlinear noise, respectively.
从表达式中我们可以看出,第二级多比特DAC2的非线性噪声被二阶噪声整形,并且量化噪声E1(z),
E2(z) 也被有效抑制(即乘以增益1/2)。We can see from the expression, the second multi-bit non-linear noise is DAC2 second order noise shaping and quantization noise E 1 (z), E 2 (z) is also effectively suppressed (i.e., multiplied by a gain 1 / 2).
图4A比较了在输入信号幅度为6dB的情况下,sigma-delta调制器输出数字信号的信噪失真比,其中虚线表示本发明的信噪失真比曲线,实线表示传统的信噪失真比曲线。从图4A的比较可以看出:传统实施例由于多比特DAC非线性噪声,而导致系统失真,从而使调制器系统性能下降;然而在本发明实施例,有效抑制了多比特DAC非线性噪声,从而提升了调制器信噪失真比。Figure 4A compares the signal-to-noise distortion ratio of the sigma-delta modulator output digital signal with an input signal amplitude of 6 dB, where the dashed line represents the signal-to-noise distortion ratio curve of the present invention, and the solid line represents the conventional signal-to-noise distortion ratio curve. . It can be seen from the comparison of FIG. 4A that the conventional embodiment causes system distortion due to multi-bit DAC nonlinear noise, thereby degrading the performance of the modulator system; however, in the embodiment of the present invention, the nonlinear noise of the multi-bit DAC is effectively suppressed. Thereby improving the modulator signal-to-noise ratio.
图4B比较了在不同输入信号幅度的情况下,sigma-delta调制器输出数字信号的信噪失真比。从图4B的比较可以看出:在相同的仿真条件下,本发明实施例的输入动态范围并没有降低,其中上面一条曲线(Improved)为本发明sigma-delta调制器输出数字信号的信噪失真比,下面的曲线(Conventional)为传统sigma-delta调制器输出数字信号的信噪失真比。Figure 4B compares the signal-to-noise distortion ratio of the sigma-delta modulator output digital signal with different input signal amplitudes. It can be seen from the comparison of FIG. 4B that the input dynamic range of the embodiment of the present invention is not reduced under the same simulation conditions, wherein the above one curve (Improved) is the signal-to-noise distortion of the output digital signal of the sigma-delta modulator of the present invention. The following curve (Conventional) is the signal-to-noise ratio of the digital signal output by the conventional sigma-delta modulator.
综上所述,本发明在传统的Sigma-delta调制器结构的基础上,把第二级模拟输入信号反馈回第一级,同时在第二级增加一个多比特量化器,把第二级两个多比特量化器的数字输出相加,从而得到第二级的最终数字输出。这种反馈式双量化结构有助于降低总体的量化噪声值,从而提高系统SNR,对最后一级多比特DAC非线性噪声进行二阶的噪声整形,从而有效抑制多比特DAC非线性噪声。In summary, the present invention feeds back the second stage analog input signal back to the first stage on the basis of the conventional Sigma-delta modulator structure, and adds a multi-bit quantizer to the second stage, and the second stage two The digital outputs of the multi-bit quantizers are summed to obtain the final digital output of the second stage. This feedback double quantization structure helps to reduce the overall quantization noise value, thereby improving the system SNR, and performing second-order noise shaping on the nonlinear noise of the last-stage multi-bit DAC, thereby effectively suppressing the nonlinear noise of the multi-bit DAC.
本发明涉及高精度、高信噪比的模拟信号转数字信号领域,主要是改善转换器的稳定性、降低转换器功耗,从而提高转换器的性能。适用于一些便携式产品,如:移动电话、PDAs。The invention relates to the field of analog signal to digital signal with high precision and high signal to noise ratio, which mainly improves the stability of the converter and reduces the power consumption of the converter, thereby improving the performance of the converter. Suitable for some portable products such as mobile phones, PDAs.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.
Claims (5)
- 一种 sigma-delta 调制器 ,其特征在于,包括:A sigma-delta modulator characterized by comprising:一级调制单元,用于将输入的模拟信号转换为一级数字信号;所述一级数字信号中包含有量化噪声与多比特DAC非线性噪声;a first-order modulation unit for converting an input analog signal into a first-order digital signal; the first-order digital signal includes quantization noise and multi-bit DAC nonlinear noise;二级调制单元,其与所述一级调制单元级联,用于将所述一级数字信号中的量化噪声与多比特DAC非线性噪声转换为二级数字信号,并将所述二级数字信号反馈至所述一级调制单元,由所述一级调制单元根据反馈的所述二级数字信号对输入的模拟信号进行调制和转换;a secondary modulation unit cascading with the primary modulation unit for converting quantization noise and multi-bit DAC nonlinear noise in the primary digital signal into a secondary digital signal, and the secondary digital The signal is fed back to the first-level modulation unit, and the first-order modulation unit modulates and converts the input analog signal according to the feedback second-level digital signal;噪声整形单元,与所述一级调制单元和所述二级调制单元连接,用于将所述二级数字信号与所述一级数字信号中的量化噪声与多比特DAC非线性噪声相消,得到消除噪声后的数字信号并输出。a noise shaping unit coupled to the primary modulation unit and the secondary modulation unit for canceling the quantization noise in the secondary digital signal and the primary digital signal from a multi-bit DAC nonlinear noise, A digital signal after noise cancellation is obtained and output.
- 如权利要求1所述的 sigma-delta 调制器,其特征在于:The sigma-delta modulator of claim 1 wherein:所述一级调制单元包括:第一加法器、第二加法器、第三加法器、第一积分器、第一模数转换器、第二数模转换器;所述第一加法器的同相输入端供外部模拟信号输入,所述第一加法器的输出端连接所述第一积分器的输入端,所述第一积分器的输出端连接所述第二加法器的同相输入端,所述第二加法器的输出端连接所述第一模数转换器的输入端,所述第一模数转换器的输出端同时连接所述噪声整形单元和所述第一数模转换器的输入端,所述第一数模转换器的输出端连接所述第一加法器的反相输入端,所述第三加法器的同相输入端连接所述第一数模转换器的输出端,所述第三加法器的反相输入端连接所述第二加法器的输出端;The primary modulation unit includes: a first adder, a second adder, a third adder, a first integrator, a first analog to digital converter, and a second digital to analog converter; the first adder is in phase The input end is connected to an external analog signal, the output end of the first adder is connected to the input end of the first integrator, and the output end of the first integrator is connected to the non-inverting input end of the second adder, An output of the second adder is connected to an input end of the first analog to digital converter, and an output end of the first analog to digital converter is simultaneously connected to the input of the noise shaping unit and the first digital to analog converter The output end of the first digital-to-analog converter is connected to the inverting input end of the first adder, and the non-inverting input end of the third adder is connected to the output end of the first digital-to-analog converter. The inverting input terminal of the third adder is connected to the output end of the second adder;所述二级调制单元包括:第四加法器、第五加法器、第六加法器、第二积分器、第三积分器、第二模数转换器、第三模数转换器、第二数模转换器;所述第四加法器的同相输入端连接所述第三加法器的输出端,所述第四加法器的输出端连接所述第二积分器的输入端,所述第二积分器的输出端连接所述第五加法器的同相输入端,所述第五积分器的输出端连接所述第三积分器的输入端,所述第三积分器的输出端连接所述第三模数转换器的输入端,所述第三模数转换器的输出端连接所述第六加法器的第一同相输入端,所述第二模数转换器的输入端连接所述第二积分器的输出端,所述第二模数转换器的输出端连接所述第六加法器的第二同相输入端,所述第六加法器的输出端同时连接所述噪声整形单元和所述第二数模转换器的输入端,所述第二数模转换器的输出端同时连接所述第四加法器的反相输入端、第五加法器的反相输入端、第二加法器的反相输入端。The second modulation unit includes: a fourth adder, a fifth adder, a sixth adder, a second integrator, a third integrator, a second analog to digital converter, a third analog to digital converter, and a second number And a non-inverting input of the fourth adder is connected to an output end of the third adder, an output end of the fourth adder is connected to an input end of the second integrator, the second integral The output of the fifth integrator is connected to the input of the third integrator, the output of the fifth integrator is connected to the input of the third integrator, and the output of the third integrator is connected to the third An input end of the analog to digital converter, an output of the third analog to digital converter is coupled to a first non-inverting input of the sixth adder, and an input of the second analog to digital converter is coupled to the second An output of the integrator, an output of the second analog-to-digital converter being coupled to a second non-inverting input of the sixth adder, an output of the sixth adder simultaneously connecting the noise shaping unit and the An input of the second digital to analog converter, the second digital to analog converter The end of the inverting input terminal while connecting the fourth adder, the inverting input of a fifth adder, the inverting input of the second adder.
- 如权利要求2所述的 sigma-delta 调制器,其特征在于,所述二级调制单元还包括第一增益模块、第二增益模块、第三增益模块;所述第五积分器的输出端通过所述第一增益模块连接所述第三积分器的输入端;所述第二模数转换器的输入端通过所述第二增益模块连接所述第二积分器的输出端;所述第六加法器的输出端连接所述第三增益模块的输入端,所述第三增益模块的输出端同时连接所述噪声整形单元和所述第二数模转换器的输入端。The sigma-delta of claim 2 a modulator, wherein the second modulation unit further includes a first gain module, a second gain module, and a third gain module; and an output end of the fifth integrator is connected to the first through the first gain module An input end of the third integrator; an input end of the second analog to digital converter is connected to an output end of the second integrator through the second gain module; an output end of the sixth adder is connected to the third end An input end of the gain module, an output end of the third gain module is simultaneously connected to the input ends of the noise shaping unit and the second digital to analog converter.
- 如权利要求3所述的 sigma-delta 调制器,其特征在于,所述第一增益模块和所述第二增益模块均为2倍增益,所述第三增益模块为1/2倍增益。The sigma-delta of claim 3 The modulator is characterized in that the first gain module and the second gain module are both 2 times gain, and the third gain module is 1/2 times gain.
- 如权利要求1所述的 sigma-delta 调制器,其特征在于,所述噪声整形单元包括:第一匹配模块、第二匹配模块、第七加法器;The sigma-delta of claim 1 a modulator, wherein the noise shaping unit comprises: a first matching module, a second matching module, and a seventh adder;所述第一匹配模块和所述第二匹配模块分别连接所述一级调制单元和所述二级调制单元的输出端,所述第一匹配模块和所述第二匹配模块用于通过互相配合将所述二级数字信号与所述一级数字信号中的量化噪声与多比特DAC非线性噪声调制成大小匹配的噪声;所述第一匹配模块和第二匹配模块的输出端分别连接所述第七加法器的第一同相输入端和第二同相输入端。The first matching module and the second matching module are respectively connected to the output ends of the primary modulation unit and the second modulation unit, and the first matching module and the second matching module are used to cooperate with each other. And modulating the secondary digital signal and the quantization noise in the primary digital signal with the multi-bit DAC nonlinear noise into a size-matched noise; the outputs of the first matching module and the second matching module are respectively connected to the a first non-inverting input and a second non-inverting input of the seventh adder.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102882528A (en) * | 2012-07-05 | 2013-01-16 | 深圳大学 | Sigma-delta modulator |
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---|---|---|---|---|
US10824579B2 (en) | 2018-03-16 | 2020-11-03 | Neuralink Corp. | Network-on-chip for neurological data |
US11216400B2 (en) | 2018-03-16 | 2022-01-04 | Neuralink Corp. | Network-on-chip for neurological data |
US11663151B2 (en) | 2018-03-16 | 2023-05-30 | Neuralink Corp. | Network-on-chip for neurological data |
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