WO2015055009A9

WO2015055009A9 - Digital tube driving circuit and control method thereof

Info

Publication number: WO2015055009A9
Application number: PCT/CN2014/078368
Authority: WO
Inventors: 程龙飞; 丁福波
Original assignee: 华为技术有限公司
Priority date: 2013-10-16
Filing date: 2014-05-26
Publication date: 2015-08-20
Also published as: CN103531141B; CN103531141A; WO2015055009A1

Abstract

A digital tube driving circuit and a control method thereof comprise a serial-to-parallel conversion unit (11) for obtaining serial signals through a serial bus I2C and converting the serial signals into parallel signals, a control unit (14) for obtaining refreshing signals and power supply signals, and converting the refreshing signals into control signals; a switching switch unit (13) respectively connected with the serial-to-parallel conversion unit (11) and the control unit (14), for obtaining the parallel signals from the serial-to-parallel conversion unit (11) and the control signals from the control unit (14), and outputting the parallel signals according to the control signals; and a digital tube unit (12) respectively connected with the control unit (14) and the switching switch unit (13), for obtaining power supply signals from the control unit (14) and the parallel signal from the switching switch unit (13), and illuminating the digital tube unit (12) according to the parallel signals and the power supply signals. Through the above method, problems of unfavourable layout and troublesome program programming due to the adoption of a micro control unit (MCU) to control the digital tube can be avoided, and the low-cost design and maintenance can be conveniently carried out.

Description

Digital tube driving circuit and control method thereof

This application claims priority to Chinese Patent Application No. 201310486254.4, entitled "A Digital Tube Drive Circuit and Its Control Method", filed on October 16, 2013, the entire contents of In this application.

Technical field

The present invention relates to the field of digital tube control, and in particular to a digital tube driving circuit and a control method thereof. Background technique

The digital tube is mainly used in the diagnostic panel in the server field, and the diagnostic panel and the server main board are connected by cables. At present, the driving and control method of the digital tube is mainly controlled by the 10-pin of the MCU (Micro Control Unit). The commonly used MCU for controlling the digital tube has a single-chip microcomputer, CPLD (Complex Programmable Logic Device, complex programmable logic). Devices), FPGA (Field Programmable Gate Array) and ARM (Asynchronous Response Mode) processors. The MCU controls the pin of the digital tube through the 10-pin to control the digital tube. If the MCU and the digital tube are on one board, there is not enough space on the board to place the MCU when the layout space is limited, which is not conducive to the layout of the board. If the MCU and the digital tube are not connected to one board but connected by cables, the number of connecting lines is large. In addition, the MCU needs to have a separate program burning interface, which is troublesome for programming, which is not conducive to low-cost design and maintenance. Summary of the invention

The embodiment of the invention provides a digital tube driving circuit and a control method thereof, which can avoid the problem that the use of the MCU to control the digital tube is unfavorable for layout and programming troubles, and facilitates cost design and maintenance.

The first aspect provides a digital tube driving circuit, the circuit comprising: a serial to parallel conversion unit, obtaining a serial signal through a serial bus I2C, and converting the serial signal into a parallel signal; a control unit, For acquiring a refresh signal and a power signal, and converting the refresh signal into a control signal; switching the switching unit, respectively connected to the serial-to-parallel conversion unit and the control unit, for acquiring parallel signals from the serial-to-parallel conversion unit, and acquiring control signals from the control unit And controlling the output parallel signal according to the control signal; the digital tube unit is respectively connected with the control unit and the switch unit, and is used for acquiring the power signal from the control unit, acquiring the parallel signal from the switch unit, and lighting according to the parallel signal and the power signal Digital tube unit.

In a first possible implementation manner of the first aspect, the circuit is configured to connect to an external device, and the external device includes an I2C control unit, and the serial to parallel conversion unit is connected to the I2C control unit through the serial bus I2C to obtain a serial signal.

In a second possible implementation manner of the first aspect, the digital tube unit includes a first digital tube and a second digital tube, and the first digital tube and the second digital tube are a common digital tube, the first digital tube and the second The anode of the digital tube is connected to the control unit, and the cathodes of the first digital tube and the second digital tube are connected to the switch unit.

In a third possible implementation manner of the first aspect, the digital tube unit includes a first digital tube and a second digital tube, and the first digital tube and the second digital tube are a common digital tube, the first digital tube and the second The anode of the digital tube is connected to the switch unit, and the cathodes of the first digital tube and the second digital tube are connected to the control unit.

In a fourth possible implementation manner of the first aspect, the control signal includes the first control signal and the second control signal, and the control unit further acquires the refresh signal from the refresh signal generating unit of the external device, and converts the refresh signal into a first control signal and a second control signal.

In a fifth possible implementation manner of the first aspect, the switching switch unit includes a control end that acquires a control signal, and the control end is coupled to the control unit to acquire the first control signal and the second control signal from the control unit.

In a sixth possible implementation manner of the first aspect, the control unit includes a first resistor, a first switch tube, a second switch tube, and a third switch tube, wherein the first end of the first switch tube passes the first resistor Connecting the power supply unit, the second end of the first switch tube is connected to the refresh signal generating unit, the third end of the first switch tube is grounded, the first end of the second switch tube and the first end of the third switch tube are connected to the power supply unit, The second end of the second switch tube and the second end of the third switch tube are connected to the control end of the switch unit, and the second end of the third switch tube is further connected to the first end of the first switch tube, and the refresh signal is further connected to the switch unit a control end and a second end of the second switch tube, the second switch tube The three ends are connected to the anode of the second digital tube, and the third end of the third switching tube is connected to the anode of the first digital tube. In a seventh possible implementation manner of the first aspect, the first switch tube is configured to convert the refresh signal into the first control signal and the second control signal; the first switch tube is an N-type MOS tube, and the first switch tube is One end is a drain, the second end is a gate, the third end is a source, the second switch tube and the third switch tube are P-type MOS tubes, and the first end of the second switch tube is a drain, the second end The gate is the source, the third end is the source, the first end of the third switch is the drain, the second end is the gate, and the third end is the source.

In an eighth possible implementation manner of the first aspect, the first control signal and the second control signal are 180 degrees out of phase.

In a ninth possible implementation manner of the first aspect, when the refresh signal is at a high level, the first control signal controls the switch unit to illuminate the first digital tube, and simultaneously controls the third switch to be turned on to enable the first digital The anode of the tube is connected to the power signal; when the refresh signal is low, the second control signal controls the switch unit to illuminate the second digital tube, and at the same time controls the second switch to conduct the signal to connect the anode of the second digital tube to the power signal.

In a tenth possible implementation of the first aspect, the refresh signal is a low frequency pulse signal having a duty cycle of 50%.

In an eleventh possible implementation manner of the first aspect, the refresh signal generating unit comprises a CPLD, an ARM chip, an FPGA, or a low frequency crystal oscillator.

In a twelfth possible implementation manner of the first aspect, the external device is a server, the I2C control unit is a BMC of the server, and the circuit is configured to perform fault detection on the server.

The second aspect provides a digital tube driving control method, comprising: acquiring a serial signal, and converting the serial signal into a parallel signal; acquiring a refresh signal and a power signal, and converting the refresh signal into a control signal; controlling according to the control signal Outputting a parallel signal; acquiring a power signal, and illuminating the digital tube unit according to the control signal, the parallel signal, and the power signal.

In a first possible implementation manner of the second aspect, the control signal includes a first control signal and a second control signal, and illuminating the digital tube unit according to the control signal, the parallel signal, and the power signal includes: acquiring the first control signal and the first a second control signal; illuminating the first digital tube according to the first control signal, the parallel signal and the power signal; lighting the second digital tube according to the second control signal, the parallel signal and the power signal.

In a third possible implementation manner of the second aspect, the first control signal and the second control signal are 180 degrees out of phase. In a fourth possible implementation of the second aspect, the refresh signal is a low frequency pulse signal having a 50% duty cycle.

The digital tube driving circuit and the control method thereof provided by the embodiment of the present invention acquire a serial signal through a serial bus I2C through a serial-to-parallel conversion unit and convert it into a parallel signal, and the control unit is configured to acquire a refresh signal and a power signal, and refresh the signal Converted into a control signal, the switch unit is respectively connected with the serial-to-parallel conversion unit and the control unit, configured to acquire a parallel signal from the serial-to-parallel conversion unit, obtain a control signal from the control unit, and output a parallel signal according to the control signal; the digital tube unit, respectively It is connected with the control unit and the switch unit for obtaining a power signal from the control unit, acquiring a parallel signal from the switch unit, and illuminating the digital tube unit according to the parallel signal and the power signal, thereby avoiding the use of the MCU to control the digital tube Conducive to the layout and programming problems, easy to carry out low-cost design and maintenance. DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described. It is obvious that the drawings in the following description are only some embodiments of the present invention. Other drawings may also be obtained from those of ordinary skill in the art in view of the drawings. among them:

1 is a schematic structural view of a digital tube driving circuit according to a first embodiment of the present invention;

2 is a schematic structural view of a digital tube driving circuit according to a second embodiment of the present invention;

3 is a schematic diagram showing waveforms of signals of a digital tube driving circuit according to a second embodiment of the present invention; FIG. 4 is a schematic structural view of a digital tube driving circuit according to a third embodiment of the present invention;

FIG. 5 is a schematic diagram of a control method of the digital tube driving according to the first embodiment of the present invention; FIG.

Fig. 6 is a view showing a control method of the digital tube driving according to the second embodiment of the present invention. detailed description

The invention will now be described in detail in conjunction with the drawings and embodiments.

First, please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a digital tube driving circuit according to a first embodiment of the present invention. As shown in FIG. 1, the digital tube driving circuit 10 includes a serial to parallel conversion unit 11, a digital tube unit 12, a changeover switch unit 13, and a control unit 14. The serial to parallel conversion unit 11 acquires a serial signal through the serial bus I2C and converts the serial signal into a parallel signal. Control unit 14 is used to acquire refresh Signal and power signals, and convert the refresh signal into a control signal. The changeover switch unit 13 is connected to the serial to parallel conversion unit 11 and the control unit 14, respectively, for acquiring parallel signals from the serial to parallel conversion unit 11, acquiring control signals from the control unit 14, and outputting parallel signals in accordance with the control signals. The digital tube unit 12 is connected to the control unit 14 and the changeover switch unit 13, respectively, for acquiring a power supply signal from the control unit 14, acquiring a parallel signal from the changeover switch unit 13, and illuminating the digital tube unit 12 in accordance with the parallel signal and the power supply signal. In this embodiment, the serial signal is converted into a parallel signal to control the digital tube, and the transmission distance is further. At the same time, there is no need to add an MCU, and it is possible to avoid the problem of using the MCU to control the digital tube, which is disadvantageous to layout and programming troubles, and is convenient for low-cost design and maintenance.

2 is a schematic structural view of a digital tube driving circuit of a second embodiment of the present invention. As shown in Fig. 2, the digital tube driving circuit 20 includes a serial to parallel conversion unit 21, a digital tube unit 22, a changeover switch unit 23, and a control unit 24. The digital tube drive circuit 20 is connected to the external device 27. The switching switch unit 23 is connected between the serial-to-parallel conversion unit 21 and the digital tube unit 22, and the control unit 24 is connected to the changeover switch unit 23 and the digital tube unit 22. The serial to parallel conversion unit 21 is connected to the I2C control unit 271 of the external device 27 via the serial bus I2C to acquire a serial signal and convert it into a parallel signal. The changeover switch unit 23 further includes a control terminal 231 that acquires a control signal to receive the control signal. The switching unit 23 outputs a parallel signal in accordance with the control signal to illuminate the digital tube unit 22. The control signal includes a first control signal OE1 and a second control signal OE2, and the phases are 180 degrees out of phase. The control unit 24 connects the power supply unit 272 of the external device 27 to obtain the power supply signal VCC, and supplies power to the digital tube unit 22 in accordance with the power supply signal VCC. At the same time, the control unit 24 is also connected to the refresh signal generating unit 273 of the external device 27 to acquire the refresh signal REF_CLK. The control unit 24 converts the refresh signal REF_CLK into the first control signal OE1 and the second control signal OE2 and sends it to the control terminal 231 of the changeover switch unit 23. The refresh signal REF_CLK is a low frequency pulse signal with a duty ratio of 50%, the refresh signal generating unit 273 includes a CPLD, an ARM chip, an FPGA, or a low frequency crystal oscillator; the I2C control unit 271 can be any chip, as long as the I2C control unit 271 is included. Just fine.

In this embodiment, the digital tube unit 22 includes a first digital tube 25 and a second digital tube 26, and the first digital tube 25 and the second digital tube 26 are both common digital tubes. The anodes of the first digital tube 25 and the second digital tube 26 are connected to the control unit 24 to receive the power supply signal VCC, and the cathodes of the first digital tube 25 and the second digital tube 26 are connected to the changeover switch unit 23 to receive parallel signals. In the invention In other embodiments, the digital tube unit 22 may include three, four, or even more digital tubes; the first digital tube 25 and the second digital tube 26 may also be common cathode digital tubes, and the anode is connected to the switch unit 23 To receive the parallel signal, the cathodes of the first digital tube 25 and the second digital tube 26 are connected to the control unit 24. Hereinafter, the first digital tube 25 and the second digital tube 26 are both described in detail as a common digital tube.

The control unit 24 includes a first resistor R1, a first switching transistor Q1, a second switching transistor Q2, and a third switching transistor Q3. The first end of the first switch Q1 is connected to the power supply unit 272 through the first resistor R1 to receive the power signal VCC, and the second end of the first switch Q1 is connected to the refresh signal generating unit 273 to receive the refresh signal REF_CLK, the first switch The third end of the tube Q1 is grounded, the first end of the second switch tube Q2 and the first end of the third switch tube Q3 are connected to the power supply unit 272 to receive the power signal VCC, and the second end of the second switch tube Q2 and the third switch The second end of the third switch tube Q3 is connected to the first end of the first switch tube Q1, and the refresh signal REF_CLK is also connected to the switch unit 23. The control terminal 231 and the second end of the second switch tube Q2, the third end of the second switch tube Q2 is connected to the anode of the second digital tube 26, and the third end of the third switch tube Q3 is connected to the anode of the first digital tube 25. In the embodiment of the present invention, the first switching transistor Q1 is an N-type MOS transistor, the first terminal of the first switching transistor Q1 is a drain, the second terminal is a gate, and the third terminal is a source; the second switching transistor Q2 and the third switching transistor Q3 are P-type MOS transistors, the first terminal of the second switching transistor Q2 is a drain, the second terminal is a gate, the third terminal is a source, and the first end of the third switching transistor Q3 is The drain, the second end is the gate, and the third end is the source. In other embodiments of the present invention, the first switch transistor Q1, the second switch transistor Q2, and the third switch transistor Q3 may also be BJT (Bipolar Junction Transistor), FET (Field Effect Transistor), field effect. Transistor) or IGBT (Insulated Gate Bipolar Transistor). The first switching transistor Q1 is for converting the refresh signal REF_CLK into a first control signal 0E1 and a second control signal 0E2. When the refresh signal REF_CLK is at a high level, the first control signal OE1 controls the switch unit 23 to illuminate the first digital tube 25, and at the same time, the third switch tube Q3 is controlled to be turned on to connect the anode of the first digital tube 25 to the power signal. VCC. When the refresh signal REF CLK is low, the second control signal OE2 controls the switch unit 23 to illuminate the second digital tube 26, and at the same time, the second switch tube Q2 is controlled to be turned on to connect the anode of the second digital tube 26 to the power supply signal VCC. .

In this embodiment, the serial signal is converted into a parallel signal to control the digital tube, and the transmission distance is Farther away. At the same time, there is no need to add an MCU, and it is possible to avoid the problem of using the MCU to control the digital tube, which is disadvantageous to layout and programming troubles, and is convenient for low-cost design and maintenance.

3 is a waveform diagram showing signals of a digital tube driving circuit according to a second embodiment of the present invention. As shown in Fig. 3, the changeover switch unit 23 outputs a 16-bit parallel signal in which DATA[0:7] is a parallel signal of the lower 8 bits. DATA[8: 15] is a parallel signal of 8 bits high, VCC_OE1 is the anode potential of the first digital tube 25, and VCC_OE2 is the anode potential of the second digital tube 26. The refresh signal REF CLK is the reference clock, tl to t3 is one clock cycle, and the power supply signal VCC is always high.

2 and FIG. 3, in the first half of the clock period from t1 to t2, the refresh signal REF_CLK is at a high level, the first switching transistor Q1 is turned on, and the power signal VCC passes through the first resistor R1 and the first switching transistor Q1. Grounding, the first control signal OE1 is at a low level, and the second control signal OE2 is at a high level. The first control signal OE1 controls the parallel signal DATA[0:7] of the lower 8 bits to be transmitted to the cathode of the first digital tube 25; meanwhile, the third switching transistor Q3 is turned on, and the power signal VCC is transmitted to the third through the third switching transistor Q3. The anode of a digital tube 25, the anode potential VCC_OE1 of the first digital tube 25 is at a high level, and the first digital tube 25 is illuminated. At this time, the second switching transistor Q2 is turned off, the power signal VCC cannot be transmitted to the anode of the second digital tube 26, the anode potential VCC_OE2 of the second digital tube 26 is at a low level, and the second control signal OE2 is controlled to be high 8 The bit parallel signal DATA[8:15] cannot be transmitted to the cathode of the second digital tube 26, and the second digital tube 26 is not illuminated.

During the second half of the clock period from t2 to t3, the refresh signal REF_CLK is at a low level, the first switching transistor Q1 is turned off, and the power signal VCC is transmitted to the first control signal OE1 through the first resistor R1, so the first control signal OE1 is high and the second control signal is low. The second control signal OE1 controls to transmit the high 8-bit parallel signal DATA[7:15] to the cathode of the second digital tube 26; meanwhile, the second switch Q2 is turned on, and the power signal VCC is transmitted to the second switch Q2 to The anode of the second digital tube 26, the anode potential VCC_OE2 of the second digital tube 26 is at a high level, and the second digital tube 26 is illuminated. At this time, the third switch tube Q3 is turned off, the anode potential VCC_OE2 of the first digital tube 25 is at a low level, and the first control signal OE1 is controlled low so that the 8-bit parallel signal DATA[0:7] cannot be transmitted to the first The cathode of the digital tube 25, the first digital tube 25 is not illuminated.

When the time from t1 to t3 is one clock cycle, the first digital tube 25 and the second digital tube 26 are alternately illuminated. When the alternating frequency exceeds the frequency recognizable by the human eye, the two digital tubes seen by the human eye are simultaneously Is lit. According to this method, a plurality of digital tubes can be illuminated. Fig. 4 is a block diagram showing the structure of a digital tube driving circuit of a third embodiment of the present invention. As shown in FIG. 4, on the basis of the third embodiment, the digital tube driving circuit 20 can be applied to the server field, the external device 27 is the server 29, and the digital tube driving circuit 20 is disposed on the detecting panel 28, and the digital tube is driven. The circuit 20 is for performing fault detection on the server 29. The I2C control unit 271 is a BMC (Baseboard Management Controller) 291 of the server, the power supply unit 272 is the power interface 292 of the server 29, and the refresh signal generation unit 273 is the CPLD module 293 of the server 29. The serial to parallel conversion unit 21 acquires a serial signal from the BMC 291 of the server 29 via the serial bus I2C, the control unit 24 acquires the power supply signal VCC from the power supply interface 292 of the server 29, and acquires the refresh signal REF_CLK from the CPLD module 293 of the server 29. Thus, all the input signals of the digital tube driving circuit 20, the serial signal, the power signal VCC, and the refresh signal TEF_CLK are all coming from the server 29, so that the peripheral circuit is simple, and the use of the MCU to control the digital tube can be avoided. The layout and the trouble of programming the program are convenient for low-cost design and maintenance. Because if an MCU or other control circuit is added to the detection panel 28, the PCB layout cannot be realized, and when the detection panel is produced, the program programming interface needs to be added, which is very inconvenient and costly.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a control method of the digital tube driving according to the first embodiment of the present invention. As shown in Figure 5, the control method of the digital tube driver includes:

S31: The digital tube driving circuit 10 acquires a serial signal and converts the serial signal into a parallel signal.

S32: The digital tube driving circuit 10 acquires a refresh signal and a power signal, and converts the refresh signal into a control signal.

S33: The digital tube unit 12 is lit according to a control signal, a parallel signal, and a power signal. In S33, the digital tube unit 12 can be a stand-alone digital tube, or a two-digit digital tube, or three, four or even more.

Fig. 6 is a view showing a control method of the digital tube driving according to the second embodiment of the present invention. Referring to FIG. 2 and FIG. 5, as shown in FIG. 6, in the embodiment, the digital tube unit 22 includes a first digital tube 25 and a second digital tube 26, and S33 includes:

S330: The digital tube driving circuit acquires the first control signal and the second control signal. In S330, the digital tube driving circuit acquires a refresh signal, and converts the refresh signal into a first control signal and a second control signal. Wherein, the refresh signal is a low frequency pulse signal with a duty ratio of 50%, which can pass The CPLD, the ARM chip, the FPGA, or the low frequency crystal oscillator generate a refresh signal; the first control signal and the second control signal are 180 degrees out of phase.

S331: The digital tube driving circuit lights the first digital tube 25 according to the first control signal, the parallel signal, and the power signal. In S331, the first control signal controls the parallel signal to illuminate the first digital tube

25, meanwhile, the first control signal controls the anode of the first digital tube 25 to connect to the power signal.

S332: The digital tube driving circuit illuminates the second digital tube according to the second control signal and the parallel signal

26. In S332, the second control signal controls the parallel signal to illuminate the second digital tube 26, and at the same time, the second control signal controls the anode connection power signal of the second digital tube 26.

In this embodiment, the serial signal is converted into a parallel signal to control the digital tube, and the transmission distance is further, and the MCU does not need to be added, and the use of the MCU to control the digital tube can be avoided, which is disadvantageous for layout and programming. Problem, convenient for low cost design and maintenance.

In summary, the present invention acquires a serial signal through a serial bus I2C through a serial-to-parallel conversion unit and converts it into a parallel signal, and the control unit is configured to acquire a refresh signal and a power signal, and convert the refresh signal into a control signal, and switch the switch unit. Connected to the serial-to-parallel conversion unit and the control unit respectively, for acquiring parallel signals from the serial-to-parallel conversion unit, obtaining control signals from the control unit, and outputting parallel signals according to the control signals; the digital tube unit is respectively connected with the control unit and the switch unit , for obtaining a power signal from the control unit, acquiring a parallel signal from the switch unit, and illuminating the digital tube unit according to the parallel signal and the power signal, thereby avoiding the trouble of layout and programming trouble caused by using the MCU to control the digital tube. Problem, convenient for low cost design and maintenance.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformations made by the specification and the drawings of the present invention may be directly or indirectly applied to other related technologies. The scope of the invention is included in the scope of patent protection of the present invention.

Claims

Rights request

A digital tube driving circuit, characterized in that the circuit comprises:

a serial to parallel conversion unit that acquires a serial signal through the serial bus I2C and converts the serial signal into a parallel signal;

a control unit, configured to acquire a refresh signal and a power signal, and convert the refresh signal into a control signal;

a switching switch unit respectively connected to the serial to parallel conversion unit and the control unit, configured to acquire the parallel signal from the serial to parallel conversion unit, acquire the control signal from the control unit, and according to the control Signaling the parallel signal;

a digital tube unit, respectively connected to the control unit and the switch unit, for acquiring the power signal from the control unit, acquiring the parallel signal from the switch unit, and according to the parallel signal and The power signal illuminates the digital tube unit.

2. The circuit according to claim 1, wherein the circuit is for connecting an external device, the external device comprises an I2C control unit, and the serial-to-parallel conversion unit passes the serial bus I2C and the I2C The control unit is connected to obtain the serial signal.

3. The circuit according to claim 2, wherein the digital tube unit comprises a first digital tube and a second digital tube, and the first digital tube and the second digital tube are a common digital tube. The anodes of the first digital tube and the second digital tube are connected to the control unit, and the cathodes of the first digital tube and the second digital tube are connected to the switch unit.

The circuit according to claim 2, wherein the digital tube unit comprises a first digital tube and a second digital tube, and the first digital tube and the second digital tube are common cathode digital tubes. The anodes of the first digital tube and the second digital tube are connected to the switch unit, and the cathodes of the first digital tube and the second digital tube are connected to the control unit.

The circuit according to claim 2, wherein the control signal comprises a first control signal and a second control signal, and the control unit further acquires the refresh signal from a refresh signal generating unit of the external device And converting the refresh signal into the first control signal and the second control signal.

The circuit according to claim 5, wherein the switching switch unit includes a control end that acquires the control signal, and the control end is connected to the control unit to acquire the a first control signal and the second control signal.

The circuit according to claim 6, wherein the control unit comprises a first resistor, a first switch tube, a second switch tube, and a third switch tube, wherein the first switch tube is first The second end of the first switch tube is connected to the refresh signal generating unit, the third end of the first switch tube is grounded, and the second switch tube is connected to the power supply unit. The first end and the first end of the third switch tube are connected to the power supply unit, and the second end of the second switch tube and the second end of the third switch tube are connected to the switch switch unit a second end of the third switch tube is further connected to the first end of the first switch tube, and the refresh signal is further connected to the control end of the switch switch unit and the second switch tube The second end of the second switch tube is connected to the anode of the second digital tube, and the third end of the third switch tube is connected to the anode of the first digital tube.

The circuit according to claim 7, wherein the first switch tube is configured to convert the refresh signal into the first control signal and the second control signal; An N-type MOS transistor, the first end of the first switch is a drain, the second end is a gate, the third end is a source, and the second switch and the third switch are P-type MOS The first switch of the second switch is a drain, the second end is a gate, the third end is a source, the first end of the third switch is a drain, and the second end is a gate The third end is the source.

9. The circuit of claim 6, wherein the first control signal and the second control signal are 180 degrees out of phase.

10. The circuit according to claim 9, wherein, when the refresh signal is at a high level, the first control signal controls the switch unit to illuminate the first digital tube while controlling the The third switch tube is turned on to connect the anode of the first digital tube to the power signal; when the refresh signal is low, the second control signal controls the switch unit to illuminate the second digital And controlling the second switch tube to conduct the anode of the second digital tube to connect the power signal.

The circuit according to claim 6, wherein the refresh signal is a low frequency pulse signal having a duty ratio of 50%.

12. The circuit according to claim 6, wherein the refresh signal generating unit comprises a CPLD, an ARM chip, an FPGA or a low frequency crystal oscillator.

The circuit according to claim 2, wherein the external device is a server, the I2C control unit is a BMC of the server, and the circuit is configured to perform the server Fault detection.

A digital tube driving control method, the method comprising: acquiring a serial signal, and converting the serial signal into a parallel signal;

Acquiring a refresh signal and a power signal, and converting the refresh signal into a control signal; lighting the digital tube unit according to the control signal, the parallel signal, and the power signal.

The method according to claim 14, wherein the control signal comprises a first control signal and a second control signal, wherein the control signal, the parallel signal, and the power signal are illuminated according to the control signal The digital tube unit includes:

Obtaining a first control signal and a second control signal;

Illuminating the first digital tube according to the first control signal, the parallel signal, and the power signal;

The second digital tube is illuminated according to the second control signal, the parallel signal, and the power signal.

16. The method according to claim 15, wherein the first control signal and the second control signal are 180 degrees out of phase.

17. The method according to claim 14, wherein the refresh signal is a low frequency pulse signal having a duty ratio of 50%.