WO2015045894A1 - Data processing device and data processing method - Google Patents
Data processing device and data processing method Download PDFInfo
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- WO2015045894A1 WO2015045894A1 PCT/JP2014/074193 JP2014074193W WO2015045894A1 WO 2015045894 A1 WO2015045894 A1 WO 2015045894A1 JP 2014074193 W JP2014074193 W JP 2014074193W WO 2015045894 A1 WO2015045894 A1 WO 2015045894A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
Definitions
- the present technology relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method capable of ensuring good communication quality in data transmission using, for example, an LDPC code. .
- the LDPC code is used as a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and the symbol is used as a signal point for quadrature modulation. Mapped and sent.
- quadrature modulation digital modulation
- QPSK Quadrature Phase Shift Keying
- bit groups 0 to 179 of the 64800-bit LDPC code are arranged in bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126,
- the second data processing apparatus / data processing method of the present technology uses an LDPC code having a code length of 64,800 bits and a coding rate of 10/15, 11/15, 12/15, or 13/15, 360 bits.
- a group-wise interleaving unit that performs group-wise interleaving for interleaving in units of bit groups of the 64800-bit LDPC code, the bit group i as the bit group i, and the group-wise interleaving includes the 64800
- the arrangement of bit groups 0 to 179 of the LDPC code of bits is represented by bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4,
- FIG. 3 is a block diagram illustrating a configuration example of a transmission device 11.
- FIG. 3 is a block diagram illustrating a configuration example of a bit interleaver 116.
- FIG. It is a figure which shows a check matrix.
- FIG. 3 is a block diagram illustrating a configuration example of an LDPC encoder 115.
- FIG. 5 is a flowchart for explaining processing of an LDPC encoder 115.
- Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 16200. It is a figure explaining the method of calculating
- FIG. 10 is a diagram illustrating a parity check matrix initial value table of a first new LDPC code having a code length N of 64k bits and a coding rate r of 7/15.
- LDPC code is a linear code and does not necessarily need to be binary, but here it will be described as being binary.
- the weight of each column (column weight) (the number of “1”) (weight) is “3”, and the weight of each row (row weight) is “6”. .
- FIG. 2 is a flowchart showing a procedure for decoding an LDPC code.
- a real value (reception LLR) expressing the “0” likelihood of the value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio as appropriate. ) Is also referred to as a received value u 0i . Further, a message output from the check node is u j and a message output from the variable node is v i .
- the branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node.
- sign (x) is 1 when x ⁇ 0, and ⁇ 1 when x ⁇ 0.
- one or more input streams (Input Streams) as target data are supplied to a Mode Adaptation / Multiplexer 111.
- the mapper 117 converts the LDPC code from the bit interleaver 116 into an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier.
- the quadrature modulation is performed by mapping to signal points determined by the modulation method for performing the quadrature modulation of the LDPC code.
- the mapper 117 uses the bit interleaver 116. Are mapped to signal points representing symbols out of 2 m signal points in symbol units.
- the OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder / resource allocation unit 131, and transmits the OFDM signal via the communication path 13 (FIG. 7).
- the error rate can be improved compared to when not performing groupwise interleaving, and as a result, good communication quality can be ensured in data transmission.
- the block interleaver 25 performs block interleaving for demultiplexing the LDPC code from the group-wise interleaver 24, thereby converting the LDPC code for one code into a m-bit symbol that is a unit of mapping, It is supplied to the mapper 117 (FIG. 8).
- KX + K3 + M-1 + 1 is equal to the code length N.
- the column weight on the head side (left side) tends to be large.
- the LDPC code corresponding to H the first code bit tends to be more resistant to errors (tolerant to errors), and the last code bit tends to be weaker to errors.
- FIG. 15 is a diagram illustrating an example of a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T as illustrated in FIG.
- LDPC codes having a code length N of 64800 bits and 16200 bits as LDPC codes defined in the DVB-T.2 standard.
- N 64800 bits
- 16200 bits 16200 bits
- the number P of columns in the unit of the cyclic structure is defined as 360, which is one of the divisors excluding 1 and M among the divisors of the parity length M.
- variable nodes connected to the same check node are separated by the number of columns P of the cyclic structure unit, that is, 360 bits here, so the burst length is In the case of less than 360 bits, it is possible to avoid a situation in which a plurality of variable nodes connected to the same check node cause an error at the same time, and as a result, it is possible to improve resistance to burst errors.
- the pseudo cyclic structure means a structure in which a part except for a part has a cyclic structure.
- FIG. 17 is a flowchart for explaining processing performed by the LDPC encoder 115, the bit interleaver 116, and the mapper 117 of FIG.
- the parity interleaver 23 performs parity interleaving for the LDPC code from the LDPC encoder 115, and converts the LDPC code after the parity interleaving to the group-wise interleave. Supplied to Lever 24.
- both parity interleaving and group-wise interleaving can be performed by writing and reading code bits to and from the memory, and an address (write address) for writing code bits is an address for reading code bits. It can be represented by a matrix to be converted into (read address).
- FIG. 18 is a block diagram illustrating a configuration example of the LDPC encoder 115 of FIG.
- the encoded parity calculation unit 615 reads the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602, and uses the parity check matrix H to calculate a parity bit for the information bits read by the information bit reading unit 614, A codeword (LDPC code) is generated by calculating based on the formula.
- LDPC code LDPC code
- the control unit 616 controls each block constituting the encoding processing unit 601.
- FIG. 19 is a flowchart for explaining an example of processing of the LDPC encoder 115 of FIG.
- FIG. 20 is a diagram illustrating an example of a parity check matrix initial value table.
- the parity check matrix initial value table indicates the position of one element of the information matrix H A (FIG. 10) corresponding to the information length K corresponding to the code length N of the LDPC code and the coding rate r, as 360 columns.
- This is a table expressed for each (number of columns P of the unit of the cyclic structure), and in the i-th row, the row number of the 1 element of the 1 + 360 ⁇ (i ⁇ 1) -th column of the check matrix H (check matrix H (The row number where the row number of the first row is 0) is arranged by the number of column weights of the 1 + 360 ⁇ (i ⁇ 1) th column.
- the numerical value of the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h i, j and j items in the w-th column of the parity check matrix H. If the row number of the first element is represented as H wj , the row number H of the first element in the w column, which is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H wj can be obtained by Expression (10).
- FIG. 34 shows a parity check matrix of a first new LDPC code having a code length N of 16k bits and a coding rate r of 6/15 (hereinafter also referred to as a first new LDPC code of (16k, 6/15)).
- 6 is a diagram illustrating a parity check matrix initial value table for H.
- FIG. 35 shows a parity check matrix of a first new LDPC code having a code length N of 16k bits and a coding rate r of 8/15 (hereinafter also referred to as a first new LDPC code of (16k, 8/15)).
- 6 is a diagram illustrating a parity check matrix initial value table for H.
- FIG. 36 shows a parity check matrix of a first new LDPC code having a code length N of 16k bits and a coding rate r of 10/15 (hereinafter also referred to as a first new LDPC code of (16k, 10/15)).
- 6 is a diagram illustrating a parity check matrix initial value table for H.
- FIG. 40 and 41 show a second new LDPC code having a code length N of 64k bits and a coding rate r of 6/15 (hereinafter referred to as a second new LDPC code of (64k, 6/15)).
- 2 is a diagram illustrating a parity check matrix initial value table for a parity check matrix H of FIG.
- Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ⁇ characterized by a degree sequence described later. It is.
- the expected value of the error probability is not zero, and the threshold of noise variance (hereinafter also referred to as performance threshold) is compared to determine whether the ensemble performance (appropriateness of the check matrix) is good or bad. Can be decided.
- performance threshold the threshold of noise variance
- each check node is connected with 6 branches equal to the row weight, and therefore there are only 3N branches connected to N / 2 check nodes.
- the interleaver through which the branch connected to the variable node and the branch connected to the check node pass is divided into multiple (multi edge), which makes it possible to further characterize the ensemble. Strictly done.
- the Tanner graph of FIG. 56 there are two branches connected to the first interleaver, only 0 check nodes with 0 branches connected to the second interleaver, and two branches connected to the first interleaver.
- the number of branches connected to the second interleaver is c2 check nodes, the number of branches connected to the first interleaver is 0, and the number of branches connected to the second interleaver is c3. Exists.
- KX1 + KX2 + KY1 + KY2 + M-1 + 1 is (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15).
- N 64800 bits.
- FIG. 61 is a diagram showing a simulation result of a simulation for measuring BER / FER performed by adopting QPSK as a modulation method for the first new LDPC code of (64k, 9/15).
- FIG. 63 is a diagram showing a simulation result of a simulation for measuring BER / FER performed by adopting QPSK as a modulation method for the first new LDPC code of (64k, 13/15).
- the first new LDPC codes of (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15) are used.
- BER / FER is obtained, and therefore the first of (64k, 7/15), (64k, 9/15), (64k, 11/15), and (64k, 13/15)
- the performance threshold of the other first new LDPC code (16k, 12/15) is 4.237556.
- FIG. 78 shows a simulation of measuring BER / FER (Bit Error Rate / Frame Error Rate) performed by adopting QPSK as a modulation method for another first new LDPC code of (16k, 12/15). It is a figure which shows a simulation result.
- FIG. 79 shows the second new LDPC codes of (64k, 6/15), (64k, 8/15), (64k, 10/15), and (64k, 12/15) of FIGS. It is a figure explaining the check matrix H.
- FIG. 87 is a diagram showing a simulation result of a simulation for measuring BER / FER performed by adopting QPSK as a modulation method for the second new LDPC code of (16k, 7/15).
- FIG. 90 is a diagram illustrating a simulation result of a simulation for measuring BER / FER, which is performed by adopting QPSK as a modulation method for the second new LDPC code of (16k, 13/15).
- NUC — 16 — 6/15 represents a constellation used in MODCOD where the modulation scheme is 16QAM and the coding rate r of the LDPC code is 6/15.
- UC is adopted as the constellation of QPSK. Further, as the constellation of 16QAM, 64QAM, and 256QAM, for example, 2D NUC is adopted. As a 1024QAM constellation, for example, 1D NUC is adopted.
- FIG. 94 is a diagram showing an example of constellation for each of the eight types of coding rates r of the LDPC code when the modulation scheme is 256QAM.
- the horizontal axis and the vertical axis are the I axis and the Q axis, respectively, and Re ⁇ x l ⁇ and Im ⁇ x l ⁇ are the signal points as the coordinates of the signal point x l , respectively.
- x represents the real part and imaginary part of l .
- FIG. 96 is a diagram showing a simulation result of a simulation for measuring BER when each of UC, 1DUCNUC, and 2D NUC is used as a constellation when the modulation method is 16QAM.
- FIG. 98 is a diagram showing a simulation result of a simulation for measuring BER when each of UC, 1D NUC, and 2D NUC is used as a constellation when the modulation method is 256QAM.
- FIG. 102 is a diagram showing the coordinates of 2D NUC signal points used for eight types of coding rates r of the LDPC code when the modulation scheme is 64QAM.
- NUC_2 m — r represents the coordinates of 2D NUC signal points used when the modulation scheme is 2 m QAM and the coding rate of the LDPC code is r.
- w # k represents the coordinates of signal points in the first quadrant of the constellation.
- the coding rate r of the LDPC code is, for example, 9/15
- the modulation scheme is 16QAM and the coding rate r is 9/15 (NUC_16_9 / 15) Since w0 is 0.4909 + 1.2007i, the coordinates -w0 of the signal point corresponding to the symbol y (12) is-(0.4909 + 1.2007i).
- a column of NUC_1k_r represents a value taken by u # k representing the coordinates of a 1D NUC signal point used when the modulation scheme is 1024QAM and the coding rate of the LDPC code is r.
- u # k represents a real part Re (z q ) and an imaginary part Im (z q ) of complex numbers as coordinates of a signal point z q of 1D NUC.
- FIG. 105 shows a symbol y and u # k as a complex real part Re (z q ) and imaginary part Im (z q ) representing the coordinates of a signal point z q of 1D NUC corresponding to the symbol y. It is a figure which shows a relationship.
- 105A shows an odd-numbered five bits y 0, q , y 2, q , y 4, q , y 6, q , y 8, q of the symbol y and a signal point z q corresponding to the symbol y. This represents the correspondence relationship with u # k representing the real part Re (z q ).
- FIG. 105 shows even-numbered 5 bits y 1, q , y 3, q , y 5, q , y 7, q , y 9, q of the symbol y and a signal point z q corresponding to the symbol y.
- u # k representing the imaginary part Im (z q ).
- 1024QAM 10-bit symbol y (y 0, q , y 1, q , y 2, q , y 3, q , y 4, q , y 5, q , y 6, q , y 7, q , y 8, q , y 9, q ) is, for example, (0,0,1,0,0,1,1,0,0), and the odd-numbered 5 bits (y 0, q , y 2, q , y 4, q , y 6, q , y 8, q ) is (0,1,0,1,0) and the even-numbered 5 bits (y 1, q , y 3, q , Y 5, q , y 7, q , y 9, q ) is (0,0,1,1,0).
- the coding rate r of the LDPC code is 7/15, for example, according to FIG. 104 described above, it is used when the modulation scheme is 1024QAM and the coding rate r7 / 15 of the LDPC code.
- u3 is 1.04 and u11 is 6.28.
- FIG. 106 is a block diagram showing a configuration example of the block interleaver 25 of FIG.
- the part column length R1 is equal to a multiple of 360 bits, which is the number of columns P of the cyclic structure unit
- the part column length R2 is the sum of the part column length R1 of part 1 and the part column length R2 of part 2 ( R1 + R2 (hereinafter also referred to as the column length) is equal to the remainder when dividing by 360 bits, which is the number of columns P in the cyclic structure unit.
- FIG. 107 is a diagram showing the number of columns C of parts 1 and 2 and the part column length (number of rows) R1 and R2 for a combination of the code length N and the modulation scheme.
- FIG. 108 is a diagram for explaining block interleaving performed by the block interleaver 25 in FIG.
- FIG. 109 is a diagram for explaining group-wise interleaving performed by the group-wise interleaver 24 in FIG.
- bit group i 1-th bit group from the beginning when the LDPC code of one codeword is divided into bit groups.
- the GW pattern is represented by a sequence of numbers representing bit groups.
- N code length 1800 bits
- the GW pattern 4, 2, 0, 3, 1 includes an arrangement of bit groups 0, 1, 2, 3, 4 , 3, and 1 are interleaved (reordered).
- GW pattern can be set at least for each code length N of LDPC code.
- the GW pattern is set separately for each combination of the code length N, the coding rate r, and the modulation method of the LDPC code, the LDPC code and the modulation method adopted by the transmission device 11 GW pattern has to be changed every time, the process becomes complicated.
- the GW pattern of FIG. 110 is a combination (64k, high rate, 16QAM)
- the GW pattern of FIG. 111 is a combination (64k, low rate, 64QAM)
- the GW pattern of FIG. 112 is a combination (64k, high).
- the rate GW pattern of FIG. 113 can be applied to the combination (64k, low rate, 1024QAM), respectively.
- FIG. 118 is a block diagram illustrating a configuration example of the receiving device 12 of FIG.
- the bit deinterleaver 165 performs bit deinterleaving on the data from the demapper 164 and supplies the LDPC code (the likelihood) that is the data after the bit deinterleaving to the LDPC decoder 166.
- the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 and supplies the LDPC target data (in this case, BCH code) obtained as a result to the BCH decoder 167.
- the null deletion unit 169 deletes the null inserted by the padder 112 in FIG. 8 from the data from the BB descrambler 168 and supplies the null to the demultiplexer 170.
- the receiving device 12 can be configured without providing a part of the blocks shown in FIG. That is, for example, when the transmission apparatus 11 (FIG. 8) is configured without the time interleaver 118, the SISO / MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the reception apparatus 12 A time deinterleaver 163, a SISO / MISO decoder 162, and a frequency deinterleaver 161, which are blocks corresponding to the time interleaver 118, SISO / MISO encoder 119, frequency interleaver 120, and frequency interleaver 124, respectively, of the transmission apparatus 11. And it can comprise without providing the frequency deinterleaver 153.
- the bit deinterleaver 165 includes a block deinterleaver 54 and a groupwise deinterleaver 55, and performs symbol bit deinterleaving of symbols as data from the demapper 164 (FIG. 118).
- the bit deinterleaver 165 uses the parity corresponding to the parity interleaving.
- Deinterleaving reverse processing of parity interleaving, that is, parity deinterleaving for returning the code bits of the LDPC code whose sequence has been changed by parity interleaving
- block deinterleaving corresponding to block interleaving and groupwise interleaving All of the groupwise deinterleaves corresponding to can be performed.
- bit deinterleaver 165 groupwise deinterleaver 55
- LDPC decoder 166 an LDPC code subjected to block deinterleaving and groupwise deinterleaving and not subjected to parity deinterleaving. Is supplied.
- FIG. 120 is a flowchart for explaining processing performed by the demapper 164, the bit deinterleaver 165, and the LDPC decoder 166 of FIG.
- step S111 the demapper 164 demaps and orthogonally demodulates the data from the time deinterleaver 163 (data on the constellation mapped to the signal points), supplies it to the bit deinterleaver 165, and performs the processing.
- the process proceeds to step S112.
- step S112 the bit deinterleaver 165 performs deinterleaving (bit deinterleaving) of data from the demapper 164, and the process proceeds to step S113.
- step S112 in the bit deinterleaver 165, the block deinterleaver 54 performs block deinterleaving on the data (symbol) from the demapper 164, and the code bits of the LDPC code obtained as a result are grouped. Supplied to the wise deinterleaver 55.
- the groupwise deinterleaver 55 performs groupwise deinterleaving on the LDPC code from the block deinterleaver 54 and supplies the resulting LDPC code (its likelihood) to the LDPC decoder 166.
- step S113 the LDPC decoder 166 performs LDPC decoding of the LDPC code from the group-wise deinterleaver 55 using the parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.
- a conversion check matrix obtained by performing at least column replacement corresponding to parity interleaving is used, and data obtained as a result is output to the BCH decoder 167 as a decoding result of LDPC target data.
- the block deinterleaver 54 that performs block deinterleaving and the groupwise deinterleaver 55 that performs groupwise deinterleaving are configured separately for convenience of explanation.
- the block deinterleaver 54 and the groupwise deinterleaver 55 can be configured integrally.
- the LDPC decoding performed by the LDPC decoder 166 in FIG. 118 will be further described.
- 0 is represented by a period (.).
- the first, seventh, thirteenth, nineteenth and twenty-fifth rows which are divided by six and the remainder is 1, the first, second, third, fourth, and fifth rows respectively.
- the second, eighth, eighth, ninth, and tenth lines that are divided by the remainder of 2 are replaced with the sixth, seventh, eighth, ninth, and tenth lines, respectively.
- the 61st column, the 61st column (parity matrix) and the 61st column, the 67th column, the 73rd column, the 79th column, and the 85th column whose remainder is 1 are divided by 61, respectively.
- 62, 63, 64, and 65, the 62, 68, 74, 80, and 86 columns, which are divided by 6 and have a remainder of 2 are called 66, 67, 68, 69, and 70 columns, respectively.
- the replacement is performed accordingly.
- FIG. 123 is a diagram showing the conversion check matrix H ′ of FIG. 122 with an interval in units of 5 ⁇ 5 matrices.
- these 5 ⁇ 5 matrices (unit matrix, quasi-unit matrix, shift matrix, sum matrix, 0 matrix) constituting the conversion check matrix H ′ are hereinafter appropriately referred to as constituent matrices.
- FIG. 124 is a block diagram illustrating a configuration example of a decoding device that performs such decoding.
- Decoding apparatus six FIFO 300 1 to the edge data storage memory 300 consisting of 300 6, FIFO 300 1 to the selector 301 for selecting 300 6, a check node calculation section 302,2 one cyclic shift circuit 303 and 308 in FIG. 124, 18 FIFOs 304 1 to 304 18 the edge data storage memory 304 consisting of, FIFOs 304 1 to 304 18 to select the selector 305, the reception data memory 306 for storing received data, a variable node calculation section 307, a decoded word calculation section 309
- the constituent matrix is a P ⁇ P unit matrix having a weight of 1, a quasi-unit matrix in which one or more of the elements of the unit matrix are 0, or Data corresponding to the unit matrix, quasi-unit matrix, or 1 position of the shift matrix when the unit matrix or quasi-unit matrix is expressed in the form of a plurality of shift matrices obtained by cyclically shifting the unit matrix or quasi-unit matrix (Messages corresponding to branches belonging to the unit matrix, quasi-unit matrix, or shift matrix) are stored in the same address (the same FIFO among the FIFOs 300 1 to 300 6 ).
- the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′ (the first shift obtained by cyclically shifting one 5 ⁇ 5 unit matrix to the right by one)
- the data corresponding to the position of 1 of the first shift matrix constituting the matrix and the sum matrix that is the sum of the matrix and the second shift matrix cyclically shifted by two to the right is stored.
- the third storage area stores data corresponding to position 1 of the second shift matrix constituting the sum matrix of (6,1) to (10,5) of the conversion check matrix H ′.
- data is also stored in the storage areas of the fourth and fifth stages in association with the conversion parity check matrix H ′.
- the number of stages in the storage area of the FIFO 304 1 is 5, which is the maximum number of 1s (Hamming weights) in the row direction in the first to fifth columns of the conversion parity check matrix H ′.
- the branch data storage memory 300 includes six FIFOs 300 1 to 300 6 , and to which row of the conversion check matrix H ′ of FIG. 123 the five messages D311 supplied from the preceding cyclic shift circuit 308 belong. according to the information (Matrix data) D312, a FIFO to store the data, select from among the FIFO300 1 to 300 6, will be stored in the order together five messages D311 to the selected FIFO. Also, the edge data storage memory 300, when reading data, sequentially reads five messages D300 1 from FIFO 300 1, supplied to the next stage of the selector 301. The branch data storage memory 300 reads the messages in order from the FIFOs 300 2 to 300 6 after reading the messages from the FIFO 300 1 and supplies them to the selector 301.
- the selector 301 selects five messages from the FIFO from which the current data is read out of the FIFOs 300 1 to 300 6 according to the select signal D301, and supplies the selected message to the check node calculation unit 302 as a message D302.
- the cyclic shift circuit 303 circulates the five messages D303 1 to D303 5 obtained by the check node calculation unit 302 using unit matrices (or quasi-unit matrices) whose corresponding branches are the original in the conversion check matrix H ′.
- a cyclic shift is performed based on the information (Matrix data) D305 indicating whether the data has been click-shifted, and the result is supplied to the branch data storage memory 304 as a message D304.
- the branch data storage memory 304 includes 18 FIFOs 304 1 to 304 18 , and according to information D 305 indicating which row of the conversion check matrix H ′ the five messages D 304 supplied from the preceding cyclic shift circuit 303 belong to.
- the FIFO for storing data is selected from the FIFOs 304 1 to 304 18 , and the five messages D 304 are collectively stored in the selected FIFO in order.
- the edge data storage memory 304 when reading data, sequentially reads five messages D306 1 from FIFOs 304 1, supplied to the next stage of the selector 305.
- Edge data storage memory 304 after completion of the data read from the FIFOs 304 1, from FIFOs 304 2 to 304 18, sequentially reads out a message, to the selector 305.
- the received data rearrangement unit 310 rearranges the LDPC code D313 corresponding to the parity check matrix H of FIG. 121 received through the communication path 13 by performing column replacement of Expression (12), and receives the received data D314 as The data is supplied to the reception data memory 306.
- the reception data memory 306 calculates and stores reception LLRs (log likelihood ratios) from the reception data D314 supplied from the reception data rearrangement unit 310, and collects the reception LLRs by five as reception values D309.
- the variable node calculation unit 307 and the decoded word calculation unit 309 are supplied.
- the variable node calculation unit 307 includes five variable node calculators 307 1 to 307 5 , a message D308 (D308 1 to D308 5 ) (message u j in Expression (1)) supplied through the selector 305, and received data. using five reception values supplied from use memory 306 D309 (formula (reception values u 0i 1)), the variable node operation according to equation (1), to the message D310 (D310 1 not obtained as a result of the calculation D310 5 ) (message v i in equation (1)) is supplied to the cyclic shift circuit 308.
- the cyclic shift circuit 308 cyclically shifts the message D310 1 to D310 5 calculated by the variable node calculation unit 307 by a number of unit matrices (or quasi-unit matrices) whose corresponding branches are the original in the transformation check matrix H ′. A cyclic shift is performed based on the information as to whether or not the data has been obtained, and the result is supplied to the branch data storage memory 300 as a message D311.
- the LDPC code can be decoded once (variable node calculation and check node calculation) by performing the above operation once.
- the decoding apparatus in FIG. 124 decodes the LDPC code a predetermined number of times, and then obtains and outputs a final decoding result in the decoded word calculation unit 309 and the decoded data rearranging unit 311.
- the decoded word calculation unit 309 includes five decoded word calculators 309 1 to 309 5 , and five messages D308 (D308 1 to D308 5 ) (message u j in Expression (5)) output from the selector 305 and Using the five reception values D309 (the reception value u 0i in equation (5)) supplied from the reception data memory 306, the decoding result (decoding) based on equation (5) is used as the final stage of multiple times of decoding. And the decoded data D315 obtained as a result is supplied to the decoded data rearranging unit 311.
- the LDPC decoder 166 constituting the receiving device 12 performs LDPC decoding by simultaneously performing P check node operations and P variable node operations, for example, as in the decoding device of FIG.
- the LDPC decoder 166 is configured in the same manner as the decoding device of FIG. 124 except that the received data rearrangement unit 310 of FIG. 124 is not provided, and column replacement of equation (12) is performed. Except for the above, the same processing as that of the decoding device of FIG. 124 is performed, and thus the description thereof is omitted.
- the scale can be reduced as compared with the decoding apparatus of FIG.
- the number P is 360 and the divisor q is M / P.
- the LDPC decoder 166 in FIG. 125 performs P check node operations and variable node operations for such LDPC codes. It is applicable when performing LDPC decoding by carrying out simultaneously.
- FIG. 126 is a block diagram showing a configuration example of the block deinterleaver 54 of FIG.
- the block deinterleaver 54 performs block deinterleaving by writing and reading LDPC codes for parts 1 and 2.
- LDPC codes (which are symbols) are written in the order in which the block interleaver 25 in FIG. 106 reads the LDPC codes.
- LDPC codes are read in the order in which the block interleaver 25 in FIG. 106 writes LDPC codes.
- FIG. 127 is a block diagram showing another configuration example of the bit deinterleaver 165 of FIG.
- bit deinterleaver 165 in FIG. 127 has the same configuration as that in FIG. 119 except that a parity deinterleaver 1011 is newly provided.
- the bit deinterleaver 165 includes a block deinterleaver 54, a groupwise deinterleaver 55, and a parity deinterleaver 1011.
- the bit deinterleaver 165 performs bit deinterleaving of code bits of the LDPC code from the demapper 164. .
- the block deinterleaver 54 targets the LDPC code from the demapper 164, and performs block deinterleave corresponding to the block interleave performed by the block interleaver 25 of the transmission apparatus 11 (block inverse interleaving process), that is, block interleave.
- Block deinterleaving is performed to return the position of the code bit replaced by the original position to the original position, and the resulting LDPC code is supplied to the groupwise deinterleaver 55.
- the groupwise deinterleaver 55 performs groupwise deinterleaving corresponding to the groupwise interleaving as the rearrangement process performed by the groupwise interleaver 24 of the transmission device 11 on the LDPC code from the block deinterleaver 54.
- the LDPC code obtained as a result of groupwise deinterleaving is supplied from the groupwise deinterleaver 55 to the parity deinterleaver 1011.
- the LDPC code obtained as a result of parity deinterleaving is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.
- the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H used by the LDPC encoder 115 of the transmission device 11 for LDPC encoding. That is, the LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165 using the parity check matrix H itself used for the LDPC encoding by the LDPC encoder 115 of the transmission device 11 or to the parity check matrix H. On the other hand, the conversion check matrix obtained by performing at least column replacement corresponding to parity interleaving is used.
- LDPC decoder 166 performs LDPC decoding of an LDPC code, and a transform check obtained by performing at least column replacement corresponding to parity interleaving on parity check matrix H used by LDPC encoder 115 of transmitting apparatus 11 for LDPC encoding
- the LDPC decoder 166 is an architecture decoding device that simultaneously performs P (or a divisor other than 1 of P) check node operations and variable node operations.
- the decoding apparatus (FIG. 124) having the received data rearrangement unit 310 that rearranges the code bits of the LDPC code by performing column replacement similar to the column replacement for obtaining the check matrix on the LDPC code. it can.
- FIG. 127 for convenience of explanation, a block deinterleaver 54 that performs block deinterleaving, a groupwise deinterleaver 55 that performs groupwise deinterleaving, and a parity deinterleaver 1011 that performs parity deinterleaving are illustrated. However, two or more of the block deinterleaver 54, the groupwise deinterleaver 55, and the parity deinterleaver 1011 are included in the parity interleaver 23, the groupwise interleaver 24, And like the block interleaver 25, it can comprise integrally.
- 128 is a block diagram illustrating a first configuration example of a receiving system to which the receiving device 12 can be applied.
- the reception system includes an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.
- the acquisition unit 1101 obtains a signal including an LDPC code obtained by LDPC encoding at least LDPC target data such as program image data and audio data, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, the Internet, and the like. Obtained via a transmission path (communication path) (not shown) such as a network of the network, and supplied to the transmission path decoding processing unit 1102.
- a transmission path communication path
- the transmission path decoding processing unit 1102 corresponds to the receiving device 12.
- the transmission path decoding processing unit 1102 performs a transmission path decoding process including at least processing for correcting an error occurring in the transmission path on the signal acquired by the acquisition unit 1101 via the transmission path, and obtains a signal obtained as a result thereof.
- the information is supplied to the information source decoding processing unit 1103.
- the transmission path decoding process may include demodulation of the modulation signal.
- the information source decoding processing unit 1103 performs an information source decoding process including at least a process of expanding the compressed information into the original information on the signal subjected to the transmission path decoding process.
- the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding for compressing information in order to reduce the amount of data such as images and sounds as information.
- the information source decoding processing unit 1103 performs information source decoding processing such as processing (decompression processing) for expanding the compressed information to the original information on the signal subjected to the transmission path decoding processing.
- examples of the decompression process include MPEG decoding.
- the transmission path decoding process may include descrambling and the like in addition to the decompression process.
- the acquisition unit 1101 for example, compression coding such as MPEG coding is performed on data such as images and sound, and further error correction codes such as LDPC coding are performed.
- the processed signal is acquired via the transmission path and supplied to the transmission path decoding processing unit 1102.
- transmission path decoding processing unit 1102 for example, processing similar to that performed by the reception device 12 is performed on the signal from the acquisition unit 1101 as transmission path decoding processing. This is supplied to the decryption processing unit 1103.
- the reception system of FIG. 128 as described above can be applied to, for example, a television tuner that receives a television broadcast as a digital broadcast.
- the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 are each configured as one independent device (hardware (IC (IntegratedIntegrCircuit) or the like) or software module)). It is possible.
- the set of the unit 1103, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device.
- FIG. 129 is a block diagram illustrating a second configuration example of a receiving system to which the receiving device 12 can be applied.
- the reception system of FIG. 129 is common to the case of FIG. 128 in that an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103 are included, and an output unit 1111 is newly provided. This is different from the case of FIG.
- the output unit 1111 is, for example, a display device that displays an image or a speaker that outputs audio, and outputs an image, audio, or the like as a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays an image or outputs sound.
- the reception system of FIG. 129 as described above can be applied to, for example, a TV (television receiver) that receives a television broadcast as a digital broadcast, a radio receiver that receives a radio broadcast, or the like.
- a TV television receiver
- a radio receiver that receives a radio broadcast
- the signal output from the transmission path decoding processing unit 1102 is supplied to the output unit 1111.
- the reception system in FIG. 130 is common to the case in FIG. 128 in that it includes an acquisition unit 1101 and a transmission path decoding processing unit 1102.
- the receiving system of FIG. 130 is different from the case of FIG. 128 in that the information source decoding processing unit 1103 is not provided and the recording unit 1121 is newly provided.
- the reception system of FIG. 130 as described above can be applied to a recorder or the like that records a television broadcast.
- FIG. 131 shows a configuration example of an embodiment of a computer in which a program for executing the series of processes described above is installed.
- the program is installed in the computer from the removable recording medium 711 as described above, or transferred from the download site to the computer wirelessly via a digital satellite broadcasting artificial satellite, LAN (Local Area Network),
- the program can be transferred to a computer via a network such as the Internet.
- the computer can receive the program transferred in this way by the communication unit 708 and install it in the built-in hard disk 705.
- the computer has a CPU (Central Processing Unit) 702 built-in.
- An input / output interface 710 is connected to the CPU 702 via a bus 701, and the CPU 702 operates an input unit 707 including a keyboard, a mouse, a microphone, and the like by the user via the input / output interface 710.
- a program stored in a ROM (Read Only Memory) 703 is executed accordingly.
- the CPU 702 may be a program stored in the hard disk 705, a program transferred from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or a removable recording medium 711 installed in the drive 709.
- processing steps for describing a program for causing a computer to perform various types of processing do not necessarily have to be processed in time series according to the order described in the flowchart, but in parallel or individually. This includes processing to be executed (for example, parallel processing or processing by an object).
- the program may be processed by one computer, or may be processed in a distributed manner by a plurality of computers. Furthermore, the program may be transferred to a remote computer and executed.
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Abstract
Description
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブするデータ処理装置/データ処理方法である。 The first data processing apparatus / data processing method of the present technology is an LDPC code having a code length of 64,800 bits and a coding rate of 10/15, 11/15, 12/15, or 13/15, 360 bits. A group-wise interleaving unit / step for performing group-wise interleaving for interleaving in units of bit groups, the i + 1-th bit group from the top of the 64800-bit LDPC code as bit group i, and in the group-wise interleaving, The sequence of
A data processing apparatus / data processing method for interleaving.
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブされる。 In the first data processing device / data processing method of the present technology, an LDPC code having a code length of 64,800 bits and an encoding rate of 10/15, 11/15, 12/15, or 13/15 Group-wise interleaving is performed in which bits are interleaved in bit group units. In the group-wise interleaving, the
Are interleaved.
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする送信装置から送信されてくるデータから得られる、グループワイズインターリーブ後の前記LDPC符号の並びを元の並びに戻すグループワイズデインターリーブ部/ステップを備えるデータ処理装置/データ処理方法である。 The second data processing apparatus / data processing method of the present technology uses an LDPC code having a code length of 64,800 bits and a coding rate of 10/15, 11/15, 12/15, or 13/15, 360 bits. A group-wise interleaving unit that performs group-wise interleaving for interleaving in units of bit groups of the 64800-bit LDPC code, the bit group i as the bit group i, and the group-wise interleaving includes the 64800 The arrangement of
A data processing apparatus / data processing method comprising a group-wise deinterleaving unit / step for returning the arrangement of the LDPC codes after group-wise interleaving obtained from data transmitted from the interleaving transmitting apparatus.
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする送信装置から送信されてくるデータから得られる、グループワイズインターリーブ後の前記LDPC符号の並びが元の並びに戻される。 In the second data processing apparatus / data processing method of the present technology, an LDPC code having a code length of 64,800 bits and an encoding rate of 10/15, 11/15, 12/15, or 13/15 is obtained. A group-wise interleaving unit that performs group-wise interleaving that performs interleaving in units of bit groups of bits. The sequence of
The sequence of the LDPC codes after group-wise interleaving obtained from the data transmitted from the interleaving transmitter is returned to the original sequence.
・・・(8) Hc T = 0
... (8)
・・・(9) K = (k + 1) × 360
... (9)
・・・(10) H wj = mod {h i, j + mod ((w-1), P) × q, M)
(10)
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブされる。 According to the GW pattern of FIG. 110, the sequence of bit groups 0 to 179 of the 64-kbit LDPC code is represented by bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87, 159, 146, 34, 57, 145, 143, 101, 53, 123, 48, 79, 13, 134, 71, 135, 81, 125, 30, 131, 139, 46, 12, 157, 23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73, 152, 72, 25, 83, 80, 149, 142, 77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155, 129, 3, 9, 47, 50, 144, 114, 154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 141, 15, 147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16, 175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8
Are interleaved.
32,84,49,56,54,99,76,178,65,48,87,125,121,51,130,70,90,2,73,123,174,20,46,31,3,89,16,66,30,158,19,137,0,12,153,147,91,33,122,57,36,129,135,24,168,141,52,71,80,96,50,44,10,93,81,22,152,29,41,95,172,107,173,42,144,63,163,43,150,60,69,58,101,68,62,9,166,78,177,146,118,82,6,21,161,4,169,18,106,176,162,175,117,8,128,97,100,111,23,114,45,34,165,28,59,131,143,83,25,61,105,35,104,156,38,102,85,142,164,26,17,160,109,40,11,47,72,124,79,7,136,159,67,1,5,14,94,110,98,145,75,149,119,74,55,155,115,113,53,151,39,92,171,154,179,139,148,103,86,37,27,77,157,108,167,13,127,126,120,133,138,134,140,116,64,88,170,132,15,112
の並びにインターリーブされる。 According to the GW pattern of FIG. 111, the sequence of bit groups 0 to 179 of the 64-kbit LDPC code is represented by bit groups 32, 84, 49, 56, 54, 99, 76, 178, 65, 48, 87, 125, 121, 51, 130, 70, 90, 2, 73, 123, 174, 20, 46, 31, 3, 89, 16, 66, 30, 158, 19, 137, 0, 12, 153, 147, 91, 33, 122, 57, 36, 129, 135, 24, 168, 141, 52, 71, 80, 96, 50, 44, 10, 93, 81, 22, 152, 29, 41, 95, 172, 107, 173, 42, 144, 63, 163, 43, 150, 60, 69, 58, 101, 68, 62, 9, 166, 78, 177, 146, 118, 82, 6, 21, 161, 4, 169, 18, 106, 176, 162, 175, 117, 8, 128, 97, 100, 111, 23, 114, 45, 34, 165, 28, 59, 131, 143, 83, 25, 61, 105, 35, 104, 156, 38, 102, 85, 142, 164, 26, 17, 160, 109, 40, 11, 47, 72, 124, 79, 7, 136, 159, 67, 1, 5, 14, 94, 110, 98, 145, 75, 149, 119, 74, 55, 155, 115, 113, 53, 151, 39, 92, 171, 154, 179, 139, 148, 103, 86, 37, 2 7, 77, 157, 108, 167, 13, 127, 126, 120, 133, 138, 134, 140, 116, 64, 88, 170, 132, 15, 112
Are interleaved.
90,64,100,166,105,61,29,56,66,40,52,21,23,69,31,34,10,136,94,4,123,39,72,129,106,16,14,134,152,142,164,37,67,17,48,99,135,54,2,0,146,115,20,76,111,83,145,177,156,174,28,25,139,33,128,1,179,45,153,38,62,110,151,32,70,101,143,77,130,50,84,127,103,109,5,63,92,124,87,160,108,26,60,98,172,102,88,170,6,13,171,97,95,91,81,137,119,148,86,35,30,140,65,82,49,46,133,71,42,43,175,141,55,93,79,107,173,78,176,96,73,57,36,44,154,19,11,165,58,18,53,126,138,117,51,113,114,162,178,3,150,8,22,131,157,118,116,85,41,27,80,12,112,144,68,167,59,75,122,132,149,24,120,47,104,147,121,74,155,125,15,7,89,161,163,9,159,168,169,158
の並びにインターリーブされる。 According to the GW pattern of FIG. 112, the bit groups 0 to 179 of the 64 kbit LDPC code are arranged in bit groups 90, 64, 100, 166, 105, 61, 29, 56, 66, 40, 52, 21, 23, 69, 31, 34, 10, 136, 94, 4, 123, 39, 72, 129, 106, 16, 14, 134, 152, 142, 164, 37, 67, 17, 48, 99, 135, 54, 2, 0, 146, 115, 20, 76, 111, 83, 145, 177, 156, 174, 28, 25, 139, 33, 128, 1, 179, 45, 153, 38, 62, 110, 151, 32, 70, 101, 143, 77, 130, 50, 84, 127, 103, 109, 5, 63, 92, 124, 87, 160, 108, 26, 60, 98, 172, 102, 88, 170, 6, 13, 171, 97, 95, 91, 81, 137, 119, 148, 86, 35, 30, 140, 65, 82, 49, 46, 133, 71, 42, 43, 175, 141, 55, 93, 79, 107, 173, 78, 176, 96, 73, 57, 36, 44, 154, 19, 11, 165, 58, 18, 53, 126, 138, 117, 51, 113, 114, 162,178,3,150,8,22,131,157,118,116,85,41,27,80,12,112,144,68,167,59,75,122,132 149,24,120,47,104,147,121,74,155,125,15,7,89,161,163,9,159,168,169,158
Are interleaved.
0,154,6,53,30,97,105,121,12,156,94,77,47,78,13,19,82,60,85,162,62,58,116,127,48,177,80,138,8,145,132,134,90,28,83,170,87,59,49,11,39,101,31,139,148,22,37,15,166,1,42,120,106,119,35,70,122,56,24,140,136,126,144,167,29,163,112,175,10,73,41,99,98,107,117,66,17,57,7,151,51,33,158,141,150,110,137,123,9,18,14,71,147,52,164,45,111,108,21,91,109,160,74,169,88,63,174,89,2,130,124,146,84,176,149,159,155,44,43,173,179,86,168,165,95,135,27,69,23,65,125,104,178,171,46,55,26,75,129,54,153,114,152,61,68,103,16,40,128,3,38,72,92,81,93,100,34,79,115,133,102,76,131,36,32,5,64,143,20,172,50,157,25,113,118,161,142,96,4,67
の並びにインターリーブされる。 According to the GW pattern of FIG. 113, the arrangement of bit groups 0 to 179 of the 64-kbit LDPC code is represented by bit groups 0, 154, 6, 53, 30, 97, 105, 121, 12, 156, 94, 77, 47, 78, 13, 19, 82, 60, 85, 162, 62, 58, 116, 127, 48, 177, 80, 138, 8, 145, 132, 134, 90, 28, 83, 170, 87, 59, 49, 11, 39, 101, 31, 139, 148, 22, 37, 15, 166, 1, 42, 120, 106, 119, 35, 70, 122, 56, 24, 140, 136, 126, 144, 167, 29, 163, 112, 175, 10, 73, 41, 99, 98, 107, 117, 66, 17, 57, 7, 151, 51, 33, 158, 141, 150, 110, 137, 123, 9, 18, 14, 71, 147, 52, 164, 45, 111, 108, 21, 91, 109, 160, 74, 169, 88, 63, 174, 89, 2, 130, 124, 146, 84,176,149,159,155,44,43,173,179,86,168,165,95,135,27,69,23,65,125,104,178,171,46,55,26, 75,129,54,153,114,152,61,68,103,16,40,128,3,38,72,92,81,93,100,34,79,115, 133, 102, 76, 131, 36, 32, 5, 64, 143, 20, 172, 50, 157, 25, 113, 118, 161, 142, 96, 4, 67
Are interleaved.
15,23,9,19,5,29,4,25,8,41,13,2,22,12,26,6,37,17,38,7,20,1,39,34,18,31,10,44,32,24,14,42,11,30,27,3,36,40,33,21,28,43,0,16,35
の並びにインターリーブされる。 According to the GW pattern of FIG. 114, the arrangement of the
Are interleaved.
6,14,24,36,30,12,33,16,37,20,21,3,11,26,34,5,7,0,1,18,2,22,19,9,32,28,27,23,42,15,13,17,35,25,8,29,38,40,10,44,31,4,43,39,41
の並びにインターリーブされる。 According to the GW pattern of FIG. 115, the arrangement of the
Are interleaved.
21,0,34,5,16,7,1,25,9,24,19,11,6,15,39,38,42,30,18,14,13,23,20,33,3,10,4,8,26,27,41,40,31,2,35,37,43,22,17,12,29,36,28,32,44
の並びにインターリーブされる。 According to the GW pattern of FIG. 116, the arrangement of the
Are interleaved.
15,25,9,27,5,38,13,10,19,16,28,1,36,0,11,17,32,35,7,26,14,21,6,4,23,22,3,18,20,24,30,12,37,2,40,8,33,29,31,34,41,42,43,44,39
の並びにインターリーブされる。 According to the GW pattern of FIG. 117, the arrangement of
Are interleaved.
・・・(11) Line replacement: 6s + t + 1 line → 5t + s + 1 line (11)
・・・(12) Column replacement: 6x + y + 61st column → 5y + x + 61th column ... (12)
Claims (14)
- 符号長が64800ビットであり符号化率が10/15,11/15,12/15、又は、13/15のLDPC符号を、360ビットのビットグループ単位でインターリーブするグループワイズインターリーブを行うグループワイズインターリーブ部を備え、
前記64800ビットのLDPC符号の先頭からi+1番目のビットグループを、ビットグループiとして、
前記グループワイズインターリーブでは、前記64800ビットのLDPC符号のビットグループ0ないし179の並びを、ビットグループ
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする
データ処理装置。 Group-wise interleaving that performs group-wise interleaving that interleaves LDPC codes with a code length of 64,800 bits and coding rates of 10/15, 11/15, 12/15, or 13/15 in 360-bit bit group units Part
The bit group i is the i + 1th bit group from the beginning of the 64800-bit LDPC code.
In the group-wise interleaving, the bit groups 0 to 179 of the 64800-bit LDPC code are arranged in bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73, 152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173, 153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174, 88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114, 154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 14 1, 15, 147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16, 175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8
Data processing device for interleaving. - 前記LDPC符号を、4ビット単位で、変調方式で定める16個の信号点のうちのいずれかにマッピングするマッピング部をさらに備える
請求項1に記載のデータ処理装置。 The data processing apparatus according to claim 1, further comprising a mapping unit that maps the LDPC code to any one of 16 signal points determined by a modulation method in units of 4 bits. - 符号長が64800ビットであり符号化率が10/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
979 1423 4166 4609 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721
である
請求項1に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and an encoding rate of 10/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
979 1423 4166 4609 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721
The data processing apparatus according to claim 1. - 符号長が64800ビットであり符号化率が11/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157 10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195 15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027 12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917 13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009 15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109 16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633 14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082 14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974 16619 16961 17033 17237
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806 15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297 16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432 17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061 16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983 16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808 16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805 16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127 14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859 16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837 15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099 16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686 16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960 17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262 15795 16476 17084 17193 17220
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255
である
請求項1に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 11/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157 10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195 15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027 12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917 13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009 15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109 16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633 14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082 14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974 16619 16961 17033 17237
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806 15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297 16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432 17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061 16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983 16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808 16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805 16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127 14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859 16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837 15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099 16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686 16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960 17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262 15795 16476 17084 17193 17220
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255
The data processing apparatus according to claim 1. - 符号長が64800ビットであり符号化率が12/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920 11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904
である
請求項1に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 12/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920 11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904
The data processing apparatus according to claim 1. - 符号長が64800ビットであり符号化率が13/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
請求項1に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 13/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
The data processing apparatus according to claim 1. - 符号長が64800ビットであり符号化率が10/15,11/15,12/15、又は、13/15のLDPC符号を、360ビットのビットグループ単位でインターリーブするグループワイズインターリーブを行うグループワイズインターリーブステップを備え、
前記64800ビットのLDPC符号の先頭からi+1番目のビットグループを、ビットグループiとして、
前記グループワイズインターリーブでは、前記64800ビットのLDPC符号のビットグループ0ないし179の並びを、ビットグループ
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする
データ処理方法。 Group-wise interleaving that performs group-wise interleaving that interleaves LDPC codes with a code length of 64,800 bits and coding rates of 10/15, 11/15, 12/15, or 13/15 in 360-bit bit group units With steps,
The bit group i is the i + 1th bit group from the beginning of the 64800-bit LDPC code.
In the group-wise interleaving, the bit groups 0 to 179 of the 64800-bit LDPC code are arranged in bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73, 152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173, 153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174, 88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114, 154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 14 1, 15, 147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16, 175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8
Data processing method for interleaving. - 符号長が64800ビットであり符号化率が10/15,11/15,12/15、又は、13/15のLDPC符号を、360ビットのビットグループ単位でインターリーブするグループワイズインターリーブを行うグループワイズインターリーブ部を備え、
前記64800ビットのLDPC符号の先頭からi+1番目のビットグループを、ビットグループiとして、
前記グループワイズインターリーブでは、前記64800ビットのLDPC符号のビットグループ0ないし179の並びを、ビットグループ
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする
送信装置
から送信されてくるデータから得られる、グループワイズインターリーブ後の前記LDPC符号の並びを元の並びに戻すグループワイズデインターリーブ部を備える
データ処理装置。 Group-wise interleaving that performs group-wise interleaving that interleaves LDPC codes with a code length of 64,800 bits and coding rates of 10/15, 11/15, 12/15, or 13/15 in 360-bit bit group units Part
The bit group i is the i + 1th bit group from the beginning of the 64800-bit LDPC code.
In the group-wise interleaving, the bit groups 0 to 179 of the 64800-bit LDPC code are arranged in bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73, 152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173, 153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174, 88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114, 154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 14 1, 15, 147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16, 175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8
A data processing apparatus comprising: a groupwise deinterleaving unit that returns the arrangement of the LDPC codes after groupwise interleaving obtained from data transmitted from a transmitting apparatus that interleaves the originals. - 前記LDPC符号を、4ビット単位で、変調方式で定める16個の信号点のうちのいずれかにマッピングするマッピング部をさらに備える
前記送信装置
から送信されてくるデータから得られる前記マッピングされたデータをデマッピングするデマッピング部をさらに備える
請求項8に記載のデータ処理装置。 The mapping data obtained from the data transmitted from the transmitter is further provided with a mapping unit that maps the LDPC code to any one of 16 signal points determined by a modulation method in units of 4 bits. The data processing apparatus according to claim 8, further comprising a demapping unit that performs demapping. - 符号長が64800ビットであり符号化率が10/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
979 1423 4166 4609 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721
である
前記送信装置
から送信されてくるデータから得られる前記LDPC符号を復号する復号部をさらに備える
請求項8に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and an encoding rate of 10/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
979 1423 4166 4609 6341 8258 10334 10548 14098 14514 17051 17333 17653 17830 17990
2559 4025 6344 6510 9167 9728 11312 14856 17104 17721 18600 18791 19079 19697 19840
3243 6894 7950 10539 12042 13233 13938 14752 16449 16727 17025 18297 18796 19400 21577
3272 3574 6341 6722 9191 10807 10957 12531 14036 15580 16651 17007 17309 19415 19845
155 4598 10201 10975 11086 11296 12713 15364 15978 16395 17542 18164 18451 18612 20617
1128 1999 3926 4069 5558 6085 6337 8386 10693 12450 15438 16223 16370 17308 18634
2408 2929 3630 4357 5852 7329 8536 8695 10603 11003 14304 14937 15767 18402 21502
199 3066 6446 6849 8973 9536 10452 12857 13675 15913 16717 17654 19802 20115 21579
312 870 2095 2586 5517 6196 6757 7311 7368 13046 15384 18576 20349 21424 21587
985 1591 3248 3509 3706 3847 6174 6276 7864 9033 13618 15675 16446 18355 18843
975 3774 4083 5825 6166 7218 7633 9657 10103 13052 14240 17320 18126 19544 20208
1795 2005 2544 3418 6148 8051 9066 9725 10676 10752 11512 15171 17523 20481 21059
167 315 1824 2325 2640 2868 6070 6597 7016 8109 9815 11608 16142 17912 19625
1298 1896 3039 4303 4690 8787 12241 13600 14478 15492 16602 17115 17913 19466 20597
568 3695 6045 6624 8131 8404 8590 9059 9246 11570 14336 18657 18941 19218 21506
228 1889 1967 2299 3011 5074 7044 7596 7689 9534 10244 10697 11691 17902 21410
1330 1579 1739 2234 3701 3865 5713 6677 7263 11172 12143 12765 17121 20011 21436
303 1668 2501 4925 5778 5985 9635 10140 10820 11779 11849 12058 15650 20426 20527
698 2484 3071 3219 4054 4125 5663 5939 6928 7086 8054 12173 16280 17945 19302
232 1619 3040 4901 7438 8135 9117 9233 10131 13321 17347 17436 18193 18586 19929
12 3721 6254 6609 7880 8139 10437 12262 13928 14065 14149 15032 15694 16264 18883
482 915 1548 1637 6687 9338 10163 11768 11970 15524 15695 17386 18787 19210 19340
1291 2500 4109 4511 5099 5194 10014 13165 13256 13972 15409 16113 16214 18584 20998
1761 4778 7444 7740 8129 8341 8931 9136 9207 10003 10678 13959 17673 18194 20990
3060 3522 5361 5692 6833 8342 8792 11023 11211 11548 11914 13987 15442 15541 19707
1322 2348 2970 5632 6349 7577 8782 9113 9267 9376 12042 12943 16680 16970 21321
6785 11960 21455
1223 15672 19550
5976 11335 20385
2818 9387 15317
2763 3554 18102
5230 11489 18997
5809 15779 20674
2620 17838 18533
3025 9342 9931
3728 5337 12142
2520 6666 9164
12892 15307 20912
10736 12393 16539
1075 2407 12853
4921 5411 18206
5955 15647 16838
6384 10336 19266
429 10421 17266
4880 10431 12208
2910 11895 12442
7366 18362 18772
4341 7903 14994
4564 6714 7378
4639 8652 18871
15787 18048 20246
3241 11079 13640
1559 2936 15881
2737 6349 10881
10394 16107 17073
8207 9043 12874
7805 16058 17905
11189 15767 17764
5823 12923 14316
11080 20390 20924
568 8263 17411
1845 3557 6562
2890 10936 14756
9031 14220 21517
3529 12955 15902
413 6750 8735
6784 12092 16421
12019 13794 15308
12588 15378 17676
8067 14589 19304
1244 5877 6085
15897 19349 19993
1426 2394 12264
3456 8931 12075
13342 15273 20351
9138 13352 20798
7031 7626 14081
4280 4507 15617
4170 10569 14335
3839 7514 16578
4688 12815 18782
4861 7858 9435
605 5445 12912
2280 4734 7311
6668 8128 12638
3733 10621 19534
13933 18316 19341
1786 3037 21566
2202 13239 16432
4882 5808 9300
4580 8484 16754
14630 17502 18269
6889 11119 12447
8162 9078 16330
6538 17851 18100
17763 19793 20816
2183 11907 17567
6640 14428 15175
877 12035 14081
1336 6468 12328
5948 9146 12003
3782 5699 12445
1770 7946 8244
7384 12639 14989
1469 11586 20959
7943 10450 15907
5005 8153 10035
17750 18826 21513
4725 8041 10112
3837 16266 17376
11340 17361 17512
1269 4611 4774
2322 10813 16157
16752 16843 18959
70 4325 18753
3165 8153 15384
160 8045 16823
14112 16724 16792
4291 7667 18176
5943 19879 20721
The data processing apparatus according to claim 8, further comprising: a decoding unit that decodes the LDPC code obtained from data transmitted from the transmission apparatus. - 符号長が64800ビットであり符号化率が11/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157 10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195 15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027 12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917 13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009 15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109 16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633 14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082 14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974 16619 16961 17033 17237
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806 15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297 16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432 17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061 16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983 16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808 16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805 16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127 14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859 16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837 15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099 16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686 16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960 17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262 15795 16476 17084 17193 17220
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255
である
前記送信装置
から送信されてくるデータから得られる前記LDPC符号を復号する復号部をさらに備える
請求項8に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 11/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
696 989 1238 3091 3116 3738 4269 6406 7033 8048 9157 10254 12033 16456 16912
444 1488 6541 8626 10735 12447 13111 13706 14135 15195 15947 16453 16916 17137 17268
401 460 992 1145 1576 1678 2238 2320 4280 6770 10027 12486 15363 16714 17157
1161 3108 3727 4508 5092 5348 5582 7727 11793 12515 12917 13362 14247 16717 17205
542 1190 6883 7911 8349 8835 10489 11631 14195 15009 15454 15482 16632 17040 17063
17 487 776 880 5077 6172 9771 11446 12798 16016 16109 16171 17087 17132 17226
1337 3275 3462 4229 9246 10180 10845 10866 12250 13633 14482 16024 16812 17186 17241
15 980 2305 3674 5971 8224 11499 11752 11770 12897 14082 14836 15311 16391 17209
0 3926 5869 8696 9351 9391 11371 14052 14172 14636 14974 16619 16961 17033 17237
3033 5317 6501 8579 10698 12168 12966 14019 15392 15806 15991 16493 16690 17062 17090
981 1205 4400 6410 11003 13319 13405 14695 15846 16297 16492 16563 16616 16862 16953
1725 4276 8869 9588 14062 14486 15474 15548 16300 16432 17042 17050 17060 17175 17273
1807 5921 9960 10011 14305 14490 14872 15852 16054 16061 16306 16799 16833 17136 17262
2826 4752 6017 6540 7016 8201 14245 14419 14716 15983 16569 16652 17171 17179 17247
1662 2516 3345 5229 8086 9686 11456 12210 14595 15808 16011 16421 16825 17112 17195
2890 4821 5987 7226 8823 9869 12468 14694 15352 15805 16075 16462 17102 17251 17263
3751 3890 4382 5720 10281 10411 11350 12721 13121 14127 14980 15202 15335 16735 17123
26 30 2805 5457 6630 7188 7477 7556 11065 16608 16859 16909 16943 17030 17103
40 4524 5043 5566 9645 10204 10282 11696 13080 14837 15607 16274 17034 17225 17266
904 3157 6284 7151 7984 11712 12887 13767 15547 16099 16753 16829 17044 17250 17259
7 311 4876 8334 9249 11267 14072 14559 15003 15235 15686 16331 17177 17238 17253
4410 8066 8596 9631 10369 11249 12610 15769 16791 16960 17018 17037 17062 17165 17204
24 8261 9691 10138 11607 12782 12786 13424 13933 15262 15795 16476 17084 17193 17220
88 11622 14705 15890
304 2026 2638 6018
1163 4268 11620 17232
9701 11785 14463 17260
4118 10952 12224 17006
3647 10823 11521 12060
1717 3753 9199 11642
2187 14280 17220
14787 16903 17061
381 3534 4294
3149 6947 8323
12562 16724 16881
7289 9997 15306
5615 13152 17260
5666 16926 17027
4190 7798 16831
4778 10629 17180
10001 13884 15453
6 2237 8203
7831 15144 15160
9186 17204 17243
9435 17168 17237
42 5701 17159
7812 14259 15715
39 4513 6658
38 9368 11273
1119 4785 17182
5620 16521 16729
16 6685 17242
210 3452 12383
466 14462 16250
10548 12633 13962
1452 6005 16453
22 4120 13684
5195 11563 16522
5518 16705 17201
12233 14552 15471
6067 13440 17248
8660 8967 17061
8673 12176 15051
5959 15767 16541
3244 12109 12414
31 15913 16323
3270 15686 16653
24 7346 14675
12 1531 8740
6228 7565 16667
16936 17122 17162
4868 8451 13183
3714 4451 16919
11313 13801 17132
17070 17191 17242
1911 11201 17186
14 17190 17254
11760 16008 16832
14543 17033 17278
16129 16765 17155
6891 15561 17007
12741 14744 17116
8992 16661 17277
1861 11130 16742
4822 13331 16192
13281 14027 14989
38 14887 17141
10698 13452 15674
4 2539 16877
857 17170 17249
11449 11906 12867
285 14118 16831
15191 17214 17242
39 728 16915
2469 12969 15579
16644 17151 17164
2592 8280 10448
9236 12431 17173
9064 16892 17233
4526 16146 17038
31 2116 16083
15837 16951 17031
5362 8382 16618
6137 13199 17221
2841 15068 17068
24 3620 17003
9880 15718 16764
1784 10240 17209
2731 10293 10846
3121 8723 16598
8563 15662 17088
13 1167 14676
29 13850 15963
3654 7553 8114
23 4362 14865
4434 14741 16688
8362 13901 17244
13687 16736 17232
46 4229 13394
13169 16383 16972
16031 16681 16952
3384 9894 12580
9841 14414 16165
5013 17099 17115
2130 8941 17266
6907 15428 17241
16 1860 17235
2151 16014 16643
14954 15958 17222
3969 8419 15116
31 15593 16984
11514 16605 17255
The data processing apparatus according to claim 8, further comprising: a decoding unit that decodes the LDPC code obtained from data transmitted from the transmission apparatus. - 符号長が64800ビットであり符号化率が12/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920 11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904
である
前記送信装置
から送信されてくるデータから得られる前記LDPC符号を復号する復号部をさらに備える
請求項8に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 12/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
584 1472 1621 1867 3338 3568 3723 4185 5126 5889 7737 8632 8940 9725
221 445 590 3779 3835 6939 7743 8280 8448 8491 9367 10042 11242 12917
4662 4837 4900 5029 6449 6687 6751 8684 9936 11681 11811 11886 12089 12909
2418 3018 3647 4210 4473 7447 7502 9490 10067 11092 11139 11256 12201 12383
2591 2947 3349 3406 4417 4519 5176 6672 8498 8863 9201 11294 11376 12184
27 101 197 290 871 1727 3911 5411 6676 8701 9350 10310 10798 12439
1765 1897 2923 3584 3901 4048 6963 7054 7132 9165 10184 10824 11278 12669
2183 3740 4808 5217 5660 6375 6787 8219 8466 9037 10353 10583 11118 12762
73 1594 2146 2715 3501 3572 3639 3725 6959 7187 8406 10120 10507 10691
240 732 1215 2185 2788 2830 3499 3881 4197 4991 6425 7061 9756 10491
831 1568 1828 3424 4319 4516 4639 6018 9702 10203 10417 11240 11518 12458
2024 2970 3048 3638 3676 4152 5284 5779 5926 9426 9945 10873 11787 11837
1049 1218 1651 2328 3493 4363 5750 6483 7613 8782 9738 9803 11744 11937
1193 2060 2289 2964 3478 4592 4756 6709 7162 8231 8326 11140 11908 12243
978 2120 2439 3338 3850 4589 6567 8745 9656 9708 10161 10542 10711 12639
2403 2938 3117 3247 3711 5593 5844 5932 7801 10152 10226 11498 12162 12941
1781 2229 2276 2533 3582 3951 5279 5774 7930 9824 10920 11038 12340 12440
289 384 1980 2230 3464 3873 5958 8656 8942 9006 10175 11425 11745 12530
155 354 1090 1330 2002 2236 3559 3705 4922 5958 6576 8564 9972 12760
303 876 2059 2142 5244 5330 6644 7576 8614 9598 10410 10718 11033 12957
3449 3617 4408 4602 4727 6182 8835 8928 9372 9644 10237 10747 11655 12747
811 2565 2820 8677 8974 9632 11069 11548 11839 12107 12411 12695 12812 12890
972 4123 4943 6385 6449 7339 7477 8379 9177 9359 10074 11709 12552 12831
842 973 1541 2262 2905 5276 6758 7099 7894 8128 8325 8663 8875 10050
474 791 968 3902 4924 4965 5085 5908 6109 6329 7931 9038 9401 10568
1397 4461 4658 5911 6037 7127 7318 8678 8924 9000 9473 9602 10446 12692
1334 7571 12881
1393 1447 7972
633 1257 10597
4843 5102 11056
3294 8015 10513
1108 10374 10546
5353 7824 10111
3398 7674 8569
7719 9478 10503
2997 9418 9581
5777 6519 11229
1966 5214 9899
6 4088 5827
836 9248 9612
483 7229 7548
7865 8289 9804
2915 11098 11900
6180 7096 9481
1431 6786 8924
748 6757 8625
3312 4475 7204
1852 8958 11020
1915 2903 4006
6776 10886 12531
2594 9998 12742
159 2002 12079
853 3281 3762
5201 5798 6413
3882 6062 12047
4133 6775 9657
228 6874 11183
7433 10728 10864
7735 8073 12734
2844 4621 11779
3909 7103 12804
6002 9704 11060
5864 6856 7681
3652 5869 7605
2546 2657 4461
2423 4203 9111
244 1855 4691
1106 2178 6371
391 1617 10126
250 9259 10603
3435 4614 6924
1742 8045 9529
7667 8875 11451
4023 6108 6911
8621 10184 11650
6726 10861 12348
3228 6302 7388
1 1137 5358
381 2424 8537
3256 7508 10044
1980 2219 4569
2468 5699 10319
2803 3314 12808
8578 9642 11533
829 4585 7923
59 329 5575
1067 5709 6867
1175 4744 12219
109 2518 6756
2105 10626 11153
5192 10696 10749
6260 7641 8233
2998 3094 11214
3398 6466 11494
6574 10448 12160
2734 10755 12780
1028 7958 10825
8545 8602 10793
392 3398 11417
6639 9291 12571
1067 7919 8934
1064 2848 12753
6076 8656 12690
5504 6193 10171
1951 7156 7356
4389 4780 7889
526 4804 9141
1238 3648 10464
2587 5624 12557
5560 5903 11963
1134 2570 3297
10041 11583 12157
1263 9585 12912
3744 7898 10646
45 9074 10315
1051 6188 10038
2242 8394 12712
3598 9025 12651
2295 3540 5610
1914 4378 12423
1766 3635 12759
5177 9586 11143
943 3590 11649
4864 6905 10454
5852 6042 10421
6095 8285 12349
2070 7171 8563
718 12234 12716
512 10667 11353
3629 6485 7040
2880 8865 11466
4490 10220 11796
5440 8819 9103
5262 7543 12411
516 7779 10940
2515 5843 9202
4684 5994 10586
573 2270 3324
7870 8317 10322
6856 7638 12909
1583 7669 10781
8141 9085 12555
3903 5485 9992
4467 11998 12904
The data processing apparatus according to claim 8, further comprising: a decoding unit that decodes the LDPC code obtained from data transmitted from the transmission apparatus. - 符号長が64800ビットであり符号化率が13/15のLDPC符号の検査行列に基づき、LDPC符号化を行う符号化部をさらに備え、
前記LDPC符号は、情報ビットとパリティビットを含み、
前記検査行列は、前記情報ビットに対応する情報行列部及び前記パリティビットに対応するパリティ行列部とを含み、
前記情報行列部は、検査行列初期値テーブルによって表され、
前記検査行列初期値テーブルは、前記情報行列部の1の要素の位置を360列ごとに表すテーブルであって、
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
である
前記送信装置
から送信されてくるデータから得られる前記LDPC符号を復号する復号部をさらに備える
請求項8に記載のデータ処理装置。 Based on a parity check matrix of an LDPC code having a code length of 64,800 bits and a coding rate of 13/15, further comprising an encoding unit that performs LDPC encoding,
The LDPC code includes information bits and parity bits,
The parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,
The information matrix part is represented by a parity check matrix initial value table,
The parity check matrix initial value table is a table that represents the position of one element of the information matrix part for every 360 columns,
142 2307 2598 2650 4028 4434 5781 5881 6016 6323 6681 6698 8125
2932 4928 5248 5256 5983 6773 6828 7789 8426 8494 8534 8539 8583
899 3295 3833 5399 6820 7400 7753 7890 8109 8451 8529 8564 8602
21 3060 4720 5429 5636 5927 6966 8110 8170 8247 8355 8365 8616
20 1745 2838 3799 4380 4418 4646 5059 7343 8161 8302 8456 8631
9 6274 6725 6792 7195 7333 8027 8186 8209 8273 8442 8548 8632
494 1365 2405 3799 5188 5291 7644 7926 8139 8458 8504 8594 8625
192 574 1179 4387 4695 5089 5831 7673 7789 8298 8301 8612 8632
11 20 1406 6111 6176 6256 6708 6834 7828 8232 8457 8495 8602
6 2654 3554 4483 4966 5866 6795 8069 8249 8301 8497 8509 8623
21 1144 2355 3124 6773 6805 6887 7742 7994 8358 8374 8580 8611
335 4473 4883 5528 6096 7543 7586 7921 8197 8319 8394 8489 8636
2919 4331 4419 4735 6366 6393 6844 7193 8165 8205 8544 8586 8617
12 19 742 930 3009 4330 6213 6224 7292 7430 7792 7922 8137
710 1439 1588 2434 3516 5239 6248 6827 8230 8448 8515 8581 8619
200 1075 1868 5581 7349 7642 7698 8037 8201 8210 8320 8391 8526
3 2501 4252 5256 5292 5567 6136 6321 6430 6486 7571 8521 8636
3062 4599 5885 6529 6616 7314 7319 7567 8024 8153 8302 8372 8598
105 381 1574 4351 5452 5603 5943 7467 7788 7933 8362 8513 8587
787 1857 3386 3659 6550 7131 7965 8015 8040 8312 8484 8525 8537
15 1118 4226 5197 5575 5761 6762 7038 8260 8338 8444 8512 8568
36 5216 5368 5616 6029 6591 8038 8067 8299 8351 8565 8578 8585
1 23 4300 4530 5426 5532 5817 6967 7124 7979 8022 8270 8437
629 2133 4828 5475 5875 5890 7194 8042 8345 8385 8518 8598 8612
11 1065 3782 4237 4993 7104 7863 7904 8104 8228 8321 8383 8565
2131 2274 3168 3215 3220 5597 6347 7812 8238 8354 8527 8557 8614
5600 6591 7491 7696
1766 8281 8626
1725 2280 5120
1650 3445 7652
4312 6911 8626
15 1013 5892
2263 2546 2979
1545 5873 7406
67 726 3697
2860 6443 8542
17 911 2820
1561 4580 6052
79 5269 7134
22 2410 2424
3501 5642 8627
808 6950 8571
4099 6389 7482
4023 5000 7833
5476 5765 7917
1008 3194 7207
20 495 5411
1703 8388 8635
6 4395 4921
200 2053 8206
1089 5126 5562
10 4193 7720
1967 2151 4608
22 738 3513
3385 5066 8152
440 1118 8537
3429 6058 7716
5213 7519 8382
5564 8365 8620
43 3219 8603
4 5409 5815
5 6376 7654
4091 5724 5953
5348 6754 8613
1634 6398 6632
72 2058 8605
3497 5811 7579
3846 6743 8559
15 5933 8629
2133 5859 7068
4151 4617 8566
2960 8270 8410
2059 3617 8210
544 1441 6895
4043 7482 8592
294 2180 8524
3058 8227 8373
364 5756 8617
5383 8555 8619
1704 2480 4181
7338 7929 7990
2615 3905 7981
4298 4548 8296
8262 8319 8630
892 1893 8028
5694 7237 8595
1487 5012 5810
4335 8593 8624
3509 4531 5273
10 22 830
4161 5208 6280
275 7063 8634
4 2725 3113
2279 7403 8174
1637 3328 3930
2810 4939 5624
3 1234 7687
2799 7740 8616
22 7701 8636
4302 7857 7993
7477 7794 8592
9 6111 8591
5 8606 8628
347 3497 4033
1747 2613 8636
1827 5600 7042
580 1822 6842
232 7134 7783
4629 5000 7231
951 2806 4947
571 3474 8577
2437 2496 7945
23 5873 8162
12 1168 7686
8315 8540 8596
1766 2506 4733
929 1516 3338
21 1216 6555
782 1452 8617
8 6083 6087
667 3240 4583
4030 4661 5790
559 7122 8553
3202 4388 4909
2533 3673 8594
1991 3954 6206
6835 7900 7980
189 5722 8573
2680 4928 4998
243 2579 7735
4281 8132 8566
7656 7671 8609
1116 2291 4166
21 388 8021
6 1123 8369
311 4918 8511
0 3248 6290
13 6762 7172
4209 5632 7563
49 127 8074
581 1735 4075
0 2235 5470
2178 5820 6179
16 3575 6054
1095 4564 6458
9 1581 5953
2537 6469 8552
14 3874 4844
0 3269 3551
2114 7372 7926
1875 2388 4057
3232 4042 6663
9 401 583
13 4100 6584
2299 4190 4410
21 3670 4979
The data processing apparatus according to claim 8, further comprising: a decoding unit that decodes the LDPC code obtained from data transmitted from the transmission apparatus. - 符号長が64800ビットであり符号化率が10/15,11/15,12/15、又は、13/15のLDPC符号を、360ビットのビットグループ単位でインターリーブするグループワイズインターリーブを行うグループワイズインターリーブ部を備え、
前記64800ビットのLDPC符号の先頭からi+1番目のビットグループを、ビットグループiとして、
前記グループワイズインターリーブでは、前記64800ビットのLDPC符号のビットグループ0ないし179の並びを、ビットグループ
178,140,44,100,107,89,169,166,36,52,33,160,14,165,109,35,74,136,99,97,28,59,7,29,164,119,41,55,17,115,138,93,96,24,31,179,120,91,98,43,6,56,148,68,45,103,5,4,10,58,1,76,112,124,110,66,0,85,64,163,75,105,117,87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23,127,61,82,84,32,22,94,170,167,126,176,51,102,171,18,104,73,152,72,25,83,80,149,142,77,137,177,19,20,173,153,54,69,49,11,156,133,162,63,122,106,42,174,88,62,78,86,116,155,129,3,9,47,50,144,114,154,121,161,92,37,38,39,108,95,70,113,141,15,147,151,111,2,118,158,60,132,168,150,21,16,175,27,90,128,130,67,172,65,26,40,8
の並びにインターリーブする
送信装置
から送信されてくるデータから得られる、グループワイズインターリーブ後の前記LDPC符号の並びを元の並びに戻すグループワイズデインターリーブステップを備える
データ処理方法。 Group-wise interleaving that performs group-wise interleaving that interleaves LDPC codes with a code length of 64,800 bits and coding rates of 10/15, 11/15, 12/15, or 13/15 in 360-bit bit group units Part
The bit group i is the i + 1th bit group from the beginning of the 64800-bit LDPC code.
In the group-wise interleaving, the bit groups 0 to 179 of the 64800-bit LDPC code are arranged in bit groups 178, 140, 44, 100, 107, 89, 169, 166, 36, 52, 33, 160, 14, 165, 109, 35, 74, 136, 99, 97, 28, 59, 7, 29, 164, 119, 41, 55, 17, 115, 138, 93, 96, 24, 31, 179, 120, 91, 98, 43, 6, 56, 148, 68, 45, 103, 5, 4, 10, 58, 1, 76, 112, 124, 110, 66, 0, 85, 64, 163, 75, 105, 117, 87,159,146,34,57,145,143,101,53,123,48,79,13,134,71,135,81,125,30,131,139,46,12,157,23, 127, 61, 82, 84, 32, 22, 94, 170, 167, 126, 176, 51, 102, 171, 18, 104, 73, 152, 72, 25, 83, 80, 149, 142, 77, 137, 177, 19, 20, 173, 153, 54, 69, 49, 11, 156, 133, 162, 63, 122, 106, 42, 174, 88, 62, 78, 86, 116, 155, 129, 3, 9, 47, 50, 144, 114, 154, 121, 161, 92, 37, 38, 39, 108, 95, 70, 113, 14 1, 15, 147, 151, 111, 2, 118, 158, 60, 132, 168, 150, 21, 16, 175, 27, 90, 128, 130, 67, 172, 65, 26, 40, 8
A data processing method comprising: a groupwise deinterleaving step for returning the arrangement of the LDPC codes after groupwise interleaving obtained from data transmitted from a transmitting device that performs interleaving to the original sequence.
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007006494A (en) * | 2005-06-21 | 2007-01-11 | Samsung Electronics Co Ltd | Device and method for data transmission/reception in communications system using structural low-density parity check code |
JP2011523318A (en) * | 2008-06-13 | 2011-08-04 | トムソン ライセンシング | Adaptive QAM transmission scheme for improving performance on AWGN channel |
JP2013005124A (en) * | 2011-06-15 | 2013-01-07 | Sony Corp | Data processor and data-processing method |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3875693B2 (en) * | 2004-03-24 | 2007-01-31 | 株式会社東芝 | Coded bit mapping method and transmission apparatus using LPC code |
US7543197B2 (en) * | 2004-12-22 | 2009-06-02 | Qualcomm Incorporated | Pruned bit-reversal interleaver |
CN100589564C (en) * | 2006-04-18 | 2010-02-10 | 华为技术有限公司 | Channel interleaving method in a kind of hand TV system and system |
JP5630278B2 (en) * | 2010-12-28 | 2014-11-26 | ソニー株式会社 | Data processing apparatus and data processing method |
-
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007006494A (en) * | 2005-06-21 | 2007-01-11 | Samsung Electronics Co Ltd | Device and method for data transmission/reception in communications system using structural low-density parity check code |
JP2011523318A (en) * | 2008-06-13 | 2011-08-04 | トムソン ライセンシング | Adaptive QAM transmission scheme for improving performance on AWGN channel |
JP2013005124A (en) * | 2011-06-15 | 2013-01-07 | Sony Corp | Data processor and data-processing method |
Non-Patent Citations (2)
Title |
---|
BILL HAYES: "ATSC 3.0 Overview", Retrieved from the Internet <URL:http://btsgold2014.unitbv.ro/uploads/presentations/Bill_Hayes_BTSGOLD2014.pdf> [retrieved on 20141029] * |
GUARNERI COMMUNICATIONS: "ATSC 3.0 Physical Layer Proposal Rev. 01 ANNEX A", THE PERFORMANCE OF SINGLE CARRIER MULTI-TONE(SCMT) MODULATION, 17 November 2013 (2013-11-17), pages 1 - 17, Retrieved from the Internet <URL:http://www.guarneri-communications.com/wp-content/uploads/2014/04/ATSC-3-PROPOSAL_anex-A.pdf> [retrieved on 20141029] * |
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