MX2016003559A - Data processing device and data processing method. - Google Patents

Data processing device and data processing method.

Info

Publication number
MX2016003559A
MX2016003559A MX2016003559A MX2016003559A MX2016003559A MX 2016003559 A MX2016003559 A MX 2016003559A MX 2016003559 A MX2016003559 A MX 2016003559A MX 2016003559 A MX2016003559 A MX 2016003559A MX 2016003559 A MX2016003559 A MX 2016003559A
Authority
MX
Mexico
Prior art keywords
data processing
group
ldpc code
code
processing device
Prior art date
Application number
MX2016003559A
Other languages
Spanish (es)
Inventor
Yuji Shinohara
Makiko Yamamoto
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of MX2016003559A publication Critical patent/MX2016003559A/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices

Abstract

This technology pertains to a data processing device and a data processing method that make it possible to ensure good communication quality when using an LDPC code to transmit data. In group-wise interleaving, an LDPC code having a code length of 64,800 bits and a code rate of 10/15, 11/15, 12/15, or 13/15 is interleaved on a per-bit-group basis, each bit group being 360 bits long. In group-wise deinterleaving, the interleaved LDPC code is restored to the original ordering thereof. This technology can be applied, for example, to data transmission or the like using an LDPC code.
MX2016003559A 2013-09-26 2014-09-12 Data processing device and data processing method. MX2016003559A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013199082 2013-09-26
PCT/JP2014/074193 WO2015045894A1 (en) 2013-09-26 2014-09-12 Data processing device and data processing method

Publications (1)

Publication Number Publication Date
MX2016003559A true MX2016003559A (en) 2016-07-21

Family

ID=52743036

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2016003559A MX2016003559A (en) 2013-09-26 2014-09-12 Data processing device and data processing method.

Country Status (6)

Country Link
JP (1) JPWO2015045894A1 (en)
KR (1) KR20160064092A (en)
CN (1) CN105580280A (en)
CA (1) CA2924874A1 (en)
MX (1) MX2016003559A (en)
WO (1) WO2015045894A1 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3875693B2 (en) * 2004-03-24 2007-01-31 株式会社東芝 Coded bit mapping method and transmission apparatus using LPC code
US7543197B2 (en) * 2004-12-22 2009-06-02 Qualcomm Incorporated Pruned bit-reversal interleaver
US7673225B2 (en) * 2005-06-21 2010-03-02 Samsung Electronics Co., Ltd. Apparatus and method for transmitting/receiving data in a communication system using structured low density parity check code
CN100589564C (en) * 2006-04-18 2010-02-10 华为技术有限公司 Channel interleaving method in a kind of hand TV system and system
EP2134051A1 (en) * 2008-06-13 2009-12-16 THOMSON Licensing An adaptive QAM transmission scheme for improving performance on an AWGN channel
JP5630278B2 (en) * 2010-12-28 2014-11-26 ソニー株式会社 Data processing apparatus and data processing method
JP5664919B2 (en) * 2011-06-15 2015-02-04 ソニー株式会社 Data processing apparatus and data processing method

Also Published As

Publication number Publication date
JPWO2015045894A1 (en) 2017-03-09
KR20160064092A (en) 2016-06-07
CN105580280A (en) 2016-05-11
CA2924874A1 (en) 2015-04-02
WO2015045894A1 (en) 2015-04-02

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