WO2015043217A1

WO2015043217A1 - Single event transient-resistant cmos circuit

Info

Publication number: WO2015043217A1
Application number: PCT/CN2014/078713
Authority: WO
Inventors: 宿晓慧; 毕津顺; 罗家俊; 韩郑生; 郝乐
Original assignee: 中国科学院微电子研究所
Priority date: 2013-09-24
Filing date: 2014-05-28
Publication date: 2015-04-02
Also published as: CN103546146A; CN103546146B

Abstract

An single event transient (SET)-resistant CMOS circuit. The circuit consists of a first buffer (101), a second buffer (102), a gating PMOS transistor (103), a gating NMOS transistor (104) and a phase inverter (105); the first buffer is used for eliminating 'high-low-high' pulse, the input end of the first buffer is connected with the input end of an SET-resistant circuit, and the output end of the first buffer is connected with a grid of the gating PMOS transistor (103); the second buffer is used for eliminating 'low-high-low' pulse, the input end of the second buffer is connected with the input end of the SET-resistant circuit, and the output end of the second buffer is connected with a grid of the gating NMOS transistor (104). A drain of the gating PMOS transistor (103) is connected with a drain of the gating NMOS transistor (104) and serves as the input end of the phase inverter (105); and the output end of the phase inverter serves as the output end of the SET-resistant circuit.

Description

Anti-single-particle transient pulse CMOS circuit

[0001] The present application claims priority to Chinese Patent Application No. 201310438818.7, entitled "Single-Particle Transient Pulse CMOS Circuit", filed on September 24, 2013, the entire contents of In the application.

Technical field

The present invention relates to the field of radiation resistant circuit, and in particular to a single particle transient pulsed CMOS circuit. Background technique

[0003] Aerospace technology is an important indicator to measure a country's modernization level and comprehensive national strength. Integrated circuits are the core of spacecraft, and its performance and function have become one of the main indicators of various spacecraft performance. In order to meet the challenges of current and future aerospace technology development, countries are actively developing high-performance, high-radiation-resistant integrated circuits. In recent years, China's aerospace industry has developed rapidly, and there are urgent demands for major aerospace applications such as manned spaceflight engineering, lunar exploration engineering, "Beidou, navigation and positioning system, "Tiangong" and other anti-irradiation integrated circuits.

[0004] Single-event effect refers to the high-energy particles existing in the radiation environment such as aerospace and ground, and the radiation damage effect caused by ionizing radiation in the sensitive area inside the chip. Ionizing radiation creates dense electron/hole pairs on the particle motion trajectory. When these electron/hole pairs are collected by circuit nodes, it may change the normal working state of the circuit, resulting in data errors, malfunctions, chip burnout and other serious consequences.

[0005] Single particle effects can be divided into two main categories:

Hard error: It means permanent damage to the device itself, such as single-particle burnout, single-particle gate wear, etc. Soft error: It means that the logic level of the circuit changes, the data is stored incorrectly, but the device itself does not cause permanent damage. The two main types are single-event flip and single-event transients.

[0006] Single-event flipping refers to the fact that radiation causes the state of the storage circuit to be reversed, which usually occurs in large-scale storage arrays such as SRAM and DRAM. The error rate caused by single-event flipping is independent of the clock frequency.

[0007] Single Event Transient SET (Single Event Transient) refers to radiation causing circuit node voltage, The current produces a transient change, producing a single-event transient pulse that propagates in the circuit, causing a phase-locked loop, an analog circuit such as an operational amplifier to operate abnormally, or it can be transmitted to the input of the memory circuit, causing erroneous data to be written. The error rate produced by single-particle transients increases linearly with increasing clock frequency.

[0008] As process sizes shrink and clock frequencies increase, single-event effects cause integrated circuit failures to become more severe, and single-event transient pulses have surpassed single-event flipping as a major source of soft errors. Therefore, designing a circuit to filter out single-event transient pulse signals can effectively prevent the transient propagation of transient pulses and avoid the influence on the subsequent circuits, which will significantly improve the single-particle level of the circuit.

[0009] At present, there are mainly two main types of anti-single-particle transient pulse circuits: time redundancy method and space redundancy method. The delay-arbitration circuit is a common time redundancy method. The method refers to the output of the combinational logic passing through two different delay paths, and the original signal and the two delayed signals are input to the arbitration circuit, and the decision circuit is determined by majority voting. The final output. The common method of spatial redundancy is to triple the redundant circuit, that is, to make three identical combination circuits, and the three outputs to the arbitration circuit. According to the majority vote, the correct result is required, and the original circuit needs more than 3 times the area. The improved double redundant structure also requires more than 2 times the original area. The time redundancy method also requires a large area to implement two delay paths. Clocks of different phases latch the output of the combinational logic at multiple points in time, and filter the SET pulses by comparing the results.该This method also requires two stages of phase delay, as well as three latches and arbitration circuits, which consume a lot of hardware. Summary of the invention

[0011] It is an object of the present invention to provide an anti-single-particle transient pulse circuit that solves the above problems.

[0012] In one aspect, the present invention provides a single-event transient pulsed CMOS circuit comprising:

[0013] a first buffer for eliminating "high, low, high" type pulses, the input end of which receives an input signal, and the output end of which outputs a first buffered signal;

a second buffer for canceling a "low high and low" type pulse, an input terminal receiving an input signal, and an output terminal outputting a second buffer signal;

[0015] gate PMOS transistor and gate NMOS transistor, wherein the gate of the PMOS transistor is connected to the substrate The power supply, the NMOS transistor source and the substrate ground are connected, the gate of the PMOS transistor is connected to the drain of the NMOS transistor, the gate of the PMOS transistor is connected to the first buffer signal, and the gate of the NMOS transistor is gated. Second buffer signal;

[0016] The output inverter has an input connected to the drain of the gate of the PMOS transistor, and an output terminal of the output of the single-particle transient pulse CMOS circuit.

[0017] In one embodiment, the first buffer is composed of an even number of inverters, and the input is connected to the inverter of the input of the single-element transient pulse circuit as the first-stage inverter, wherein, the odd number The ratio of the width to length ratio of the PMOS transistor to the NMOS transistor in the inverter is smaller than the ratio of electron mobility to hole mobility. The ratio of the width to length ratio of the PMOS transistor to the NMOS transistor in the even-numbered inverter is greater than the electron mobility and the hole. The ratio of mobility.

[0018] In one embodiment, the second buffer is formed by an even number of inverter cascades, and the input terminal is connected to the inverter of the input of the single-element transient pulse circuit as the first-stage inverter, wherein, the odd number The ratio of PMOS tube to NMOS width to length ratio in the inverter is greater than the ratio of electron mobility to hole mobility. The ratio of PMOS tube to NMOS tube width to length ratio in even stage inverter is smaller than electron mobility and hole migration. Rate ratio.

[0019] The present invention utilizes the inverter PMOS tube and the NMOS transistor width-to-length ratio mismatch in the buffer, resulting in an asymmetrical pull-up/pull-down driving capability of the inverter, so that the output signal rise/fall delay is different, thereby achieving an output. Pulse broadening/compression. And the difference between the ratio of the width to the length of the MOS tube and the ratio of the electron mobility to the hole mobility is larger. The more the number of inverter stages in the buffer, the larger the output pulse broadening/compression amplitude.

[0020] For the first buffer, when a "high, low, high" type pulse is input, the output pulse width will be compressed, and a "low, low" type pulse will be input, and the output pulse will be broadened. In the implementation process, according to the single-particle pulse width to be filtered, the appropriate inverter stage and MOS tube width-to-length ratio are selected through simulation, so that the input pulse width range is within the filtering range. When the particle is pulsed, the output pulse width will be compressed to 0, so that the output remains high, achieving the purpose of filtering out the "high and low" type single-event pulses.

[0021] Similarly, for the second buffer, when a "high-low" pulse is input, the output pulse is broadened, and when a "low-low" pulse is input, the output pulse is compressed. In the implementation process, according to the single-particle pulse width to be filtered, select the appropriate inverter stage and MOS tube width-to-length ratio, so that when inputting the "low high and low" type single particle pulse that needs to be filtered, the output pulse Width compressed to 0, output remains low Level, the purpose of filtering out "low and low" type single-particle pulses.

[0022] Therefore, when the input "high and low, type single particle pulse, the first buffer output signal is always high level, the second buffer output is widened by the "high and low" type pulse, when the first slow When the output of the punch and the output of the second buffer are both high, the connected PMOS transistor is turned off, and the NMOS transistor is turned on, so that the input signal of the inverter is low, and the output signal out is high. When the second buffer output goes low, the PMOS transistor is turned off, and the NMOS transistor is also turned off. Since the second buffer output low level time is short, the influence of the leakage on the level is negligible, so the inverter The input signal remains unchanged, maintaining a low level, and its output signal is high. After that, the output of the second buffer returns to a high level, the NMOS transistor is turned on, and the output of the inverter continues to remain high. The output signal filters out the purpose of "high and low" type single-event pulses.

[0023] Similarly, when a low-low, single-particle pulse is input, the first buffer outputs a widened "low-low" type single-event pulse, and the second buffer output is always at a low level. The tube is always off. When the first buffer outputs a low level, the PMOS transistor is turned on, the inverter input level is high, and the inverter output signal is low. When the first buffer outputs a high level. The PMOS transistor is turned off. Due to the short time, the leakage effect is small. At this time, the inverter input level remains unchanged, so that the inverter output remains low. Then the first buffer output returns to a low level. The input signal of the phaser is high level, and the output of the inverter is low level, which realizes the purpose of filtering out the "low high and low" type single particle pulse of the circuit output signal.

Therefore, the single-particle transient pulse signal is filtered by the invention, and has the advantages of strong anti-single-particle transient pulse capability, simple structure, small area, low power consumption and the like. By simply adjusting the circuit size difference and the number of inverter stages, it is easy to change the width range and output delay of the filterable single-particle pulse. For example, increasing the ratio of the width to length ratio of the PMOS tube to the NMOS transistor in the buffer is different from the ratio of the electron mobility to the hole mobility, or increasing the number of inverter stages in the buffer, and the filtering pulse can be enlarged. The width range, but the output delay increases, and conversely, the filter range becomes smaller, but the output delay also decreases. It can be selected according to the actual application requirements. DRAWINGS

1 is a schematic structural diagram of a single-particle transient pulse circuit according to an embodiment of the present invention;

2 is a schematic structural diagram of a circuit of a first buffer according to an embodiment of the present invention; FIG. 3 is a schematic structural diagram of a circuit of a second buffer according to an embodiment of the present invention; FIG.

4 is a schematic diagram of an operation waveform of a single-element transient pulse circuit according to an embodiment of the present invention. detailed description

The present invention will be further described in detail below with reference to the specific embodiments of the invention.

1 shows a schematic diagram of a structure of a single-element transient pulse circuit provided by an embodiment of the present invention, the circuit comprising:

[0031] The first buffer 101 is configured to eliminate "high and low" type pulses, the input terminal receives the input signal in, and the output terminal outputs the first buffer signal outl;

[0032] a second buffer 102, for eliminating "low high" pulse, its input receives the input signal in, and its output outputs a second buffer signal out2;

[0033] gate PMOS transistor 103 and gate NMOS transistor 104, wherein the source of the PMOS transistor 103 and the substrate are connected to the power supply, the source of the NMOS transistor 104 is gated and the substrate is grounded, and the drain of the PMOS transistor 103 is selected The NMOS transistor 104 is connected to the drain of the NMOS transistor 104, the gate of the PMOS transistor 103 is connected to the first buffer signal out1, and the gate of the NMOS transistor 104 is connected to the second buffer signal out2;

The output inverter 105 has an input connected to the drain of the gate PMOS transistor 103, and an output terminal thereof is an output terminal of the single-element transient pulse CMOS circuit.

[0035] In deep submicron circuits, the electron mobility is about 2 to 3 times the hole mobility. By changing the aspect ratio of the PMOS transistor of the inverter to the NMOS transistor in the buffer, the pull-up/pull-down driving capability of the inverter is asymmetrical, so that the rise and fall times of the output signal are different. When the inverter outputs a "low high" pulse, the inverter output signal width - input signal width = output signal fall time - output signal rise time. When the inverter outputs a "high-low" pulse, the inverter output signal width - input signal width = output signal rise time - output signal fall time. Therefore, when the inverter rise/fall times are inconsistent, the output pulse will be broadened or reduced.

[0036] In an embodiment of the invention, the type, number and size of the buffers are determined by the type and width range of single-event transient pulses that are filtered as needed. Embodiments of the present invention can be implemented in a 0.18 micron CMOS process due to electron mobility and hole mobility under deep submicron processes. The ratio is 2~3, and the difference between the width-to-length ratio of the MOS tube in the buffer is larger than this value, and the buffer broadening/compression ability is stronger. For this embodiment, the design requires that it be able to filter a single-particle pulse signal with a pulse width not exceeding Ins.

[0037] Since there are two different types of single-particle pulses, namely "low-low" pulses and "high-low" pulses, two different types of buffers are needed to filter separately.

The first buffer 101 is designed to eliminate "high and low, type pulses. To this end, the first buffer 101 can be formed by an even number of inverter cascades, and the input signal is connected to the first stage. The phase comparator, wherein the ratio of the width to length ratio of the PMOS tube to the NMOS transistor in the odd-numbered inverter is smaller than the ratio of the electron mobility to the hole mobility, and the ratio of the width to length ratio of the PMOS tube to the NMOS tube in the even-numbered inverter is greater than The ratio of electron mobility to hole mobility. In order to reduce the output pulse width to 0 when the Ins pulse is input, in one embodiment, considering the ratio of the width to length ratio of the MOS tube and the number of buffer stages, it is determined by simulation. The first buffer 101 is composed of four inverter cascades. As shown in FIG. 2, the PMOS transistors 201 and 205 and the NMOS transistors 204 and 208 are both set to have a width to length ratio of 0.5 μm / 0.18 μm, and PMOS transistors 203 and 207. The width-to-length ratio of the NMOS transistors 202 and 206 is set to 10 μm / 0.18 μm.

[0039] The second buffer 102 is designed to eliminate "low and low, type pulses. To this end, the second buffer 102 can be formed by a cascade of inverters, and the input signal is connected to the first stage. In the odd-numbered inverter, the ratio of the width to length ratio of the PMOS tube to the NMOS tube is greater than the ratio of electron mobility to hole mobility; the ratio of the width to length ratio of the PMOS tube to the NMOS tube in the even-numbered inverter is smaller than The ratio of electron mobility to hole mobility. In one embodiment, the second buffer 102 is composed of four inverter cascades, as shown in FIG. 3, PMOS transistors 303 and 307, NMOS transistors 302 and 306. The aspect ratio is 0.5 micrometers / 0.18 micrometers; the PMOS tubes 301 and 305, and the NMOS transistors 304 and 308 have a width to length ratio of 10 meters / 0.18 meters.

In this embodiment, the width-to-length ratio of the gate PMOS transistor 103 and the gate NMOS transistor 104 are both set to 10 μm/0.18 μm, and the width to length ratio of the PMOS transistor in the output inverter 105 is 9 μm/0.18 μm. The NMOS transistor has a width to length ratio of 3 μm / 0.18 μm.

4 is an operating waveform of a 1.8V voltage according to an embodiment of the present invention, wherein in is an input signal interfered by a single-event transient pulse signal, and out is an output signal of a single-particle transient pulse circuit, and outl is The first buffer output signal, out2 is the second buffer output signal.

[0042] In 0 ns, in is high level, outl is high level, out2 is high level, PMOS tube 103 is cut off The NMOS transistor 104 is turned on, the input signal of the inverter 105 is at a low level, and the output signal out of the inverter 105 is at a high level.

[0043] At 10 ns, in produces a "high and low" type interference pulse having a pulse width of Ins, and the first buffer 101 filters out the pulse, and outl is always at a high level. The second buffer 102 outputs a spread "high, low" pulse with an out2 pulse width of 2.1 ns. When out2 becomes low level, the PMOS transistor 103 is turned off, and the NMOS transistor 104 is turned off. Since the low level time of the out2 is 4 艮, the influence of the leakage current on the input signal voltage of the inverter 105 is negligible, so The phaser 105 input signal remains low and the output signal out is high. When out2 returns to a high level, the PMOS transistor 103 is turned off, the NMOS transistor 104 is turned on, and out is at a high level. Note that when the input signal in is disturbed by a single-event transient pulse of the Ins wide "high, low, high" type, the output signal out can filter it out without generating an interference pulse, and the output signal remains high.

[0044] At 20 ns, in becomes a low level, so that outl outputs a low level, out2 outputs a low level, PMOS transistor 103 is turned on, and NMOS transistor 104 is turned off, so the input signal of inverter 105 is a high level. , the output signal out is low.

[0045] At 30 ns, in input a "low high" interference pulse with a pulse width of Ins, buffer 102 filtering can filter the pulse, out2 remains low, buffer 101 outputs signal outl, resulting A "low high" pulse with a pulse width of 2.2 ns. When outl is high, the PMOS transistor 103 is turned off, and the NMOS transistor 104 is turned off. At this time, the input level of the inverter 105 remains unchanged, and is always at a high level, so that the inverter 105 always outputs a low level. When outl returns to a low level, the PMOS transistor 103 is turned on, the inverter 105 is turned off, the inverter 105 is input to a high level, and out is outputted to a low level. Explain that when the input signal in is disturbed by the Ins wide "low, low" type of single-event transient pulse, the output signal remains low and no interfering pulses are generated.

At 40 ns, in becomes a high level, so that outl outputs a high level, out2 outputs a high level, the PMOS transistor 103 is turned off, and the NMOS transistor 104 is turned on, so the input signal of the inverter 105 is a low level. , the output signal out is high.

[0047] The simulation shows that when the single-particle transient pulse width in in does not exceed Ins, this embodiment can filter it out. According to the waveform measurement, the delay of out with respect to in falling edge is 1.39 ns, and the rising edge delay is 1.19 ns.

[0048] In the design process, increasing the width-to-length ratio of the MOS tube in the buffer is the same as the electron mobility and the empty The difference in the ratio of hole mobility, or the number of inverters included in the buffer, the pulse width that the buffers 101 and 102 can filter out will become larger, but the delay of the output signal will be further increased. Therefore, in the actual design, the size of the NMOS tube and the PMOS tube can be designed according to the pulse width to be filtered. For example, if the filter is to be filtered for more than 2 ns, the size can be 20 μm / 0.18 μm and 0.5 μm / 0.18 μm. However, the falling edge delay will become 2.66 ns and the rising edge delay will be 2.32 ns.

[0049] Since the present invention uses different buffers 101 and 102 for up-and-down driving capability to filter pulses without a delay circuit, in the embodiment, only 20 MOS transistors are used, and the maximum size of the MOS transistors used is only 10 μm / 0.18 μm, if at least 30 MOS tubes with a maximum size of 10 μm / 0.18 μm are required by the Muller C method, the invention has a small area and low power consumption; and since the single-event transient pulse usually does not exceed lns, The present invention can be filtered out, and the output waveform is smooth and burr-free, indicating that the invention has strong anti-single-particle transient pulse capability and good filtering effect.

The above-described embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, modifications, and substitutions made without departing from the spirit and principles of the present invention. Combinations, simplifications, and equivalent replacements are all included in the scope of the present invention.

Claims

Rights request

1. A single-event transient pulsed CMOS circuit comprising:

a first buffer (101) for canceling a "high-low" pulse, an input terminal receiving an input signal (in), and an output terminal outputting a first buffer signal (outl);

a second buffer (102) for canceling a "low high" pulse, an input terminal receiving an input signal (in), and an output terminal outputting a second buffer signal (out2);

The PMOS transistor (103) and the strobe NMOS transistor (104) are gated, wherein the PMOS transistor (103) source and the substrate are connected to the power supply, the NMOS transistor (104) source and the substrate are grounded, and the PMOS transistor is gated. (103) the drain is connected to the drain of the strobe NMOS transistor (104), the gate of the PMOS transistor (103) is connected to the first buffer signal (outl), and the gate of the NMOS transistor (104) is connected to the second gate Buffer signal (out2); output inverter (105), whose input is connected to the drain of the strobe PMOS transistor (103), and its output terminal is the output of the anti-single-particle transient pulse CMOS circuit.

2. The circuit according to claim 1, wherein the first buffer (101) is composed of an even number of inverters cascaded, and the input terminal is connected to an inverter that is resistant to the input end of the single-event transient pulse circuit. The first-stage inverter, wherein the ratio of the width-to-length ratio of the PMOS transistor to the NMOS transistor in the odd-numbered inverter is smaller than the ratio of electron mobility to hole mobility, and the PMOS transistor and the NMOS transistor are wider in the even-numbered inverter The ratio of the length ratio is greater than the ratio of the electron mobility to the hole mobility.

3. The circuit according to claim 1, wherein the second buffer (102) is formed by an even number of inverter cascades, and the input terminal is connected to an inverter that is resistant to the input end of the single-event transient pulse circuit. The first-stage inverter, wherein the ratio of the PMOS tube to the NMOS width-to-length ratio in the odd-numbered inverter is greater than the ratio of the electron mobility to the hole mobility, and the PMOS tube is the same as the NMOS tube in the even-numbered inverter. The ratio is smaller than the electron mobility and hole mobility